修改端点

rk3588/.dr4-rk3588.dtb.cmd

@@ -33,14 +33,9 @@ deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := \
   arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
   arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
   arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi \
+  arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \
+  arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
   arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi \
-  arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi \
 
 arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb)
 

rk3588/.dr4-rk3588.dtb.d.pre.tmp

@@ -29,11 +29,6 @@ dr4-rk3588.o: arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts \
  arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
  arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
  arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi \
+ arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \
+ arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \
+ arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi
- arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi \
- arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi

rk3588/.dr4-rk3588.dtb.dts.tmp

@@ -1,6 +1,6 @@
-# 0 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
+# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
-# 0 "<built-in>"
+# 1 "<built-in>"
-# 0 "<command-line>"
+# 1 "<command-line>"
 # 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
 
 
@@ -10674,7 +10674,7 @@
   };
  };
 };
-# 6888 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
+# 6887 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
 # 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2
 # 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 1
 
@@ -14544,197 +14544,183 @@
 # 9 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
 
 
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi" 1
 
-/ {
+
-        vbus5v0_typec: vbus5v0-typec {
+
-                compatible = "regulator-fixed";
+
-                regulator-name = "vbus5v0_typec";
+# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi" 1
-                regulator-min-microvolt = <5000000>;
+
-                regulator-max-microvolt = <5000000>;
+
-                enable-active-high;
+
-                gpio = <&gpio1 2 0>;
+
-                vin-supply = <&vcc5v0_usb>;
+
-                pinctrl-names = "default";
+
-                pinctrl-0 = <&typec5v_pwren>;
+&mipi_dcphy0 {
-        };
+ status = "okay";
 };
 
+&csi2_dcphy0 {
+ status = "okay";
+
+ ports {
+  #address-cells = <1>;
+  #size-cells = <0>;
+  port@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipidcphy0_in_ucam0: endpoint@0 {
+    reg = <0>;
+    remote-endpoint = <&mvcam_out4>;
+
+    data-lanes = <1 2 3 4>;
+   };
+  };
+
+  port@1 {
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   csidcphy0_out: endpoint@0 {
+    reg = <0>;
+    remote-endpoint = <&mipi0_csi2_input>;
+   };
+  };
+ };
+};
+
+&i2c7 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7m0_xfer>;
+
+ mvcam_4: mvcam@3b{
+  status = "okay";
+  compatible = "veye,mvcam";
+  reg = <0x3b>;
+
+  pwdn-gpios = <&gpio1 5 0>;
+
+  reset-gpios = <&gpio1 3 1>;
+  rockchip,camera-module-index = <0>;
+  rockchip,camera-module-facing = "back";
+  rockchip,camera-module-name = "NC";
+  rockchip,camera-module-lens-name = "NC";
+  port {
+   mvcam_out4: endpoint {
+    remote-endpoint = <&mipidcphy0_in_ucam0>;
+
+    data-lanes = <1 2 3 4>;
+   };
+  };
+ };
+};
+
+&mipi0_csi2 {
+ status = "okay";
+
+ ports {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  port@0 {
+   reg = <0>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi0_csi2_input: endpoint@1 {
+    reg = <1>;
+    remote-endpoint = <&csidcphy0_out>;
+   };
+  };
+
+  port@1 {
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   mipi0_csi2_output: endpoint@0 {
+    reg = <0>;
+    remote-endpoint = <&cif_mipi_in0>;
+   };
+  };
+ };
+};
+
+&rkcif_mipi_lvds {
+ status = "okay";
+
+ port {
+  cif_mipi_in0: endpoint {
+   remote-endpoint = <&mipi0_csi2_output>;
+  };
+ };
+};
+
+&rkcif_mipi_lvds_sditf {
+ status = "disabled";
+
+ port {
+  mipi_lvds_sditf: endpoint {
+   remote-endpoint = <&isp1_in1>;
+  };
+ };
+};
+
+&rkisp1_vir0 {
+ status = "disabled";
+
+ port {
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  isp1_in1: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&mipi_lvds_sditf>;
+  };
+ };
+};
+# 16 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
 
 
-&i2c4 {
+
-    status = "okay";
+# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi" 1
+
+&mdio0 {
+    rgmii_phy0: phy@1 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x1>;
+    };
+};
+
+&gmac0 {
+
+    phy-mode = "rgmii-rxid";
+    clock_in_out = "input";
+
+    snps,reset-gpio = <&gpio3 15 1>;
+    snps,reset-active-low;
+
+    snps,reset-delays-us = <0 20000 100000>;
+
     pinctrl-names = "default";
-    pinctrl-0 = <&i2c4m1_xfer>;
+    pinctrl-0 = <&gmac0_miim
+             &gmac0_tx_bus2
+             &gmac0_rx_bus2
+             &gmac0_rgmii_clk
+             &gmac0_rgmii_bus
+            &gmac0_clkinout
+            &eth0_pins>;
 
-    usbc0: fusb302@22 {
+    tx_delay = <0x44>;
-        compatible = "fcs,fusb302";
-        reg = <0x22>;
-        interrupt-parent = <&gpio0>;
-        interrupts = <27 8>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&usbc0_int>;
-        vbus-supply = <&vbus5v0_typec>;
-        status = "okay";
-
-        ports {
-            #address-cells = <1>;
-            #size-cells = <0>;
-
-            port@0 {
-                reg = <0>;
-                usbc0_role_sw: endpoint@0 {
-                    remote-endpoint = <&dwc3_0_role_switch>;
-                };
-            };
-        };
-
-        usb_con: connector {
-            compatible = "usb-c-connector";
-            label = "USB-C";
-            data-role = "dual";
-            power-role = "dual";
-            try-power-role = "sink";
-            op-sink-microwatt = <1000000>;
-            sink-pdos =
-                <(((0) << 30) | ((1 << 26)) | ((((5000) / 50) & 0x3ff) << 10) | ((((1000) / 10) & 0x3ff) << 0))>;
-            source-pdos =
-                <(((0) << 30) | ((1 << 26)) | ((((5000) / 50) & 0x3ff) << 10) | ((((3000) / 10) & 0x3ff) << 0))>;
-
-            altmodes {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                altmode@0 {
-                    reg = <0>;
-                    svid = <0xff01>;
-                    vdo = <0xffffffff>;
-                };
-            };
-
-            ports {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                port@0 {
-                    reg = <0>;
-                    usbc0_orien_sw: endpoint {
-                        remote-endpoint = <&usbdp_phy0_orientation_switch>;
-                    };
-                };
-
-                port@1 {
-                    reg = <1>;
-                    dp_altmode_mux: endpoint {
-                        remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
-                    };
-                };
-            };
-        };
-    };
-};
 
 
-&usbdp_phy0 {
+    phy-handle = <&rgmii_phy0>;
-    orientation-switch;
-    svid = <0xff01>;
-    sbu1-dc-gpios = <&gpio3 28 0>;
-    sbu2-dc-gpios = <&gpio3 29 0>;
-
-    port {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        usbdp_phy0_orientation_switch: endpoint@0 {
-            reg = <0>;
-            remote-endpoint = <&usbc0_orien_sw>;
-        };
-
-        usbdp_phy0_dp_altmode_mux: endpoint@1 {
-            reg = <1>;
-            remote-endpoint = <&dp_altmode_mux>;
-        };
-    };
-};
-
-
-&usbdrd_dwc3_0 {
-    dr_mode = "otg";
-    usb-role-switch;
-    port {
-        #address-cells = <1>;
-        #size-cells = <0>;
-        dwc3_0_role_switch: endpoint@0 {
-            reg = <0>;
-            remote-endpoint = <&usbc0_role_sw>;
-        };
-    };
-};
-
-&pinctrl {
-        usb-typec {
-                usbc0_int: usbc0-int {
-                        rockchip,pins = <0 27 0 &pcfg_pull_up>;
-                };
-
-                typec5v_pwren: typec5v-pwren {
-                        rockchip,pins = <1 2 0 &pcfg_pull_none>;
-                };
-
-       };
-};
-# 12 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi" 1
-
-&u2phy2 {
     status = "okay";
 };
-
+# 20 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
-&u2phy3 {
-    status = "okay";
-};
-
-
-
-
-
-&u2phy2_host {
-    status = "okay";
-};
-
-&u2phy3_host {
-    status = "okay";
-};
-
-&usb_host0_ehci {
-    status = "okay";
-};
-
-&usb_host0_ohci {
-    status = "okay";
-};
-
-&usb_host1_ehci {
-    status = "okay";
-};
-
-&usb_host1_ohci {
-    status = "okay";
-};
-
-
-
-
-&usbhost3_0 {
-    status = "disabled";
-};
-
-&usbhost_dwc3_0 {
-    status = "disabled";
-};
-# 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
-
-
-
 # 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi" 1
 
 &mdio1 {
@@ -14750,7 +14736,7 @@
     phy-mode = "rgmii-rxid";
     clock_in_out = "input";
 
-    snps,reset-gpio = <&gpio3 15 1>;
+    snps,reset-gpio = <&gpio2 20 1>;
     snps,reset-active-low;
 
     snps,reset-delays-us = <0 20000 100000>;
@@ -14761,8 +14747,8 @@
              &gmac1_rx_bus2
              &gmac1_rgmii_clk
              &gmac1_rgmii_bus
-            &gmac1_clkinout
+            &gmac1_clkinout>;
-            &eth1_pins>;
+
 
     tx_delay = <0x44>;
 
@@ -14770,140 +14756,8 @@
     phy-handle = <&rgmii_phy1>;
     status = "okay";
 };
-# 17 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
+# 21 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
-# 30 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
+# 93 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi" 1
-
-/ {
-
-    reserved-memory {
-        #address-cells = <2>;
-        #size-cells = <2>;
-        ranges;
-
-
-        cma {
-            compatible = "shared-dma-pool";
-            reusable;
-            reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>;
-            linux,cma-default;
-        };
-    };
-
-  hdmiin-sound {
-    compatible = "simple-audio-card";
-    simple-audio-card,format = "i2s";
-    simple-audio-card,name = "rockchip,hdmiin";
-    simple-audio-card,bitclock-master = <&dailink0_master>;
-    simple-audio-card,frame-master = <&dailink0_master>;
-    status = "okay";
-    simple-audio-card,cpu {
-      sound-dai = <&i2s7_8ch>;
-    };
-    dailink0_master: simple-audio-card,codec {
-       sound-dai = <&hdmiin_dc>;
-   };
-  };
-
-  hdmiin_dc: hdmiin-dc {
-     compatible = "rockchip,dummy-codec";
-     #sound-dai-cells = <0>;
- };
-
-};
-
-&i2s7_8ch {
-  status = "okay";
-};
-
-
-&hdmirx_ctrler {
-    status = "okay";
-
-
-    hpd-trigger-level = <1>;
-    hdmirx-det-gpios = <&gpio1 29 1>;
-    pinctrl-0 = <&hdmim1_rx_cec &hdmim2_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda>;
-    pinctrl-names = "default";
-};
-# 31 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
-# 65 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 1
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi" 1
-&hdmi0 {
-        status = "okay";
-};
-
-&hdmi0_in_vp0 {
-        status = "okay";
-};
-
-&hdmi0_sound {
-        status = "okay";
-};
-
-&i2s5_8ch {
-        status = "okay";
-};
-
-&hdptxphy_hdmi0 {
-        status = "okay";
-};
-
-&route_hdmi0 {
-    status = "okay";
-    connect = <&vp0_out_hdmi0>;
-};
-# 2 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi" 1
-&hdmi1 {
-    status = "okay";
-    pinctrl-names = "default";
-    pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>;
-};
-
-&hdmi1_in_vp1 {
-    status = "okay";
-};
-
-&hdmi1_sound {
-    status = "okay";
-};
-
-&i2s6_8ch {
-        status = "okay";
-};
-
-
-&hdptxphy_hdmi1 {
-    status = "okay";
-};
-
-
-&route_hdmi1 {
-        status = "okay";
-        connect = <&vp1_out_hdmi1>;
-};
-# 3 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi" 1
-&dp0 {
-    status = "okay";
-};
-
-&dp0_in_vp2 {
-    status = "okay";
-};
-
-&dp0_sound{
-        status = "okay";
-};
-
-&spdif_tx2 {
-        status = "okay";
-};
-# 4 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2
-# 66 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
-# 89 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
 / {
     model = "dr4-rk3588";
 
@@ -14939,21 +14793,16 @@
                 status = "okay";
                 compatible = "rp_power";
                 rp_not_deep_sleep = <1>;
-# 136 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
+# 145 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
-                led {
-                        gpio_num = <&gpio4 6 0>;
-                        gpio_function = <3>;
-                };
-
                 usb-host-power {
                         gpio_num = <&gpio2 17 0>;
                         gpio_function = <4>;
                 };
 
-                usb-hub-reset {
+
-                        gpio_num = <&gpio3 10 0>;
+
-                        gpio_function = <4>;
+
-                };
+
     };
 
         rp_gpio{
@@ -14967,49 +14816,99 @@
         };
 };
 
-
+&uart1 {
-&uart3 {
+ status = "disabled";
-    status = "okay";
+ pinctrl-names = "default";
-    pinctrl-names = "default";
+ pinctrl-0 = <&uart1m1_xfer>;
-    pinctrl-0 = <&uart3m2_xfer>;
+ fifo-depth =<4096>;
+ rx-fifo-depth =<2048>;
+ tx-fifo-depth =<2048>;
+  dma-names = "tx", "rx";
 };
 
-&uart6 {
+&uart3 {
-    status = "okay";
+ status = "okay";
-    pinctrl-names = "default";
+ pinctrl-names = "default";
-    pinctrl-0 = <&uart6m2_xfer>;
+ pinctrl-0 = <&uart3m0_xfer>;
+ fifo-depth =<4096>;
+ rx-fifo-depth =<2048>;
+ tx-fifo-depth =<2048>;
+  dma-names = "tx", "rx";
 };
 
 &uart4 {
-    status = "okay";
+ status = "okay";
-    pinctrl-names = "default";
+ pinctrl-names = "default";
-    pinctrl-0 = <&uart4m2_xfer>;
+ pinctrl-0 = <&uart4m1_xfer>;
+ fifo-depth =<4096>;
+ rx-fifo-depth =<2048>;
+ tx-fifo-depth =<2048>;
+  dma-names = "tx", "rx";
+
+};
+
+&uart5 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m0_xfer>;
+ fifo-depth =<4096>;
+ rx-fifo-depth =<2048>;
+ tx-fifo-depth =<2048>;
+  dma-names = "tx", "rx";
+
+};
+
+&uart6 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart6m1_xfer>;
+ fifo-depth =<4096>;
+ rx-fifo-depth =<2048>;
+ tx-fifo-depth =<2048>;
+ dma-names = "tx", "rx";
 };
 
 &uart7 {
-    status = "okay";
+ status = "okay";
-    pinctrl-names = "default";
+ pinctrl-names = "default";
-    pinctrl-0 = <&uart7m2_xfer>;
+ pinctrl-0 = <&uart7m0_xfer>;
+ fifo-depth =<4096>;
+ rx-fifo-depth =<2048>;
+ tx-fifo-depth =<2048>;
+ dma-names = "tx", "rx";
 };
 
-
+&uart8 {
-
+ status = "disabled";
-&can0 {
+ pinctrl-names = "default";
-    assigned-clocks = <&cru 112>;
+ pinctrl-0 = <&uart8m0_xfer>;
-    assigned-clock-rates = <200000000>;
+ fifo-depth =<4096>;
-    status = "disabled";
+ rx-fifo-depth =<2048>;
-    pinctrl-names = "default";
+ tx-fifo-depth =<2048>;
-    pinctrl-0 = <&can0m0_pins>;
+ dma-names = "tx", "rx";
 };
 
 &can1 {
-    assigned-clocks = <&cru 114>;
+ assigned-clocks = <&cru 114>;
-    assigned-clock-rates = <200000000>;
+ assigned-clock-rates = <200000000>;
-    status = "disabled";
+ status = "disabled";
-    pinctrl-names = "default";
+ pinctrl-names = "default";
-    pinctrl-0 = <&can1m1_pins>;
+ pinctrl-0 = <&can1m1_pins>;
 };
 
+&spi3 {
+    status = "disabled";
+    pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
+
+    spi3_dev@0 {
+        compatible = "rockchip,spidev";
+        reg = <0>;
+        spi-max-frequency = <12000000>;
+        spi-lsb-first;
+    };
+};
+
+
 &i2c4 {
     status = "disabled";
     pinctrl-names = "default";
@@ -15030,9 +14929,8 @@
 
 };
 
-
 &sdmmc {
-    status = "okay";
+    status = "disabled";
 };
 
 &fiq_debugger {
@@ -15040,14 +14938,58 @@
 };
 
 &display_subsystem {
-clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
+    clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
-clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
+    clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
 };
 
 &hdptxphy_hdmi_clk0 {
-            status = "okay";
+            status = "disabled";
 };
 
 &hdptxphy_hdmi_clk1 {
-            status = "okay";
+            status = "disabled";
+};
+
+&pwm14 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm14m1_pins>;
+    #pwm-cells = <3>;
+};
+
+&pwm15 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm15m1_pins>;
+    #pwm-cells = <3>;
+};
+
+&pwm11 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm11m1_pins>;
+    #pwm-cells = <3>;
+};
+
+&pwm13 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm13m1_pins>;
+    #pwm-cells = <3>;
+};
+
+&i2c1 {
+  status = "okay";
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c1m2_xfer>;
+};
+
+&i2c2 {
+  status = "okay";
+  pinctrl-names = "default";
+  pinctrl-0 = <&i2c2m3_xfer>;
 };

rk3588/dr4-rk3588.dts

@@ -8,11 +8,15 @@
 #include "rpdzkj_config.dtsi"
 
 /* usb */
-#include "rp-usb-typec-rk3588.dtsi"
+// #include "rp-usb-typec-rk3588.dtsi"
-#include "rp-usb-host.dtsi"
+// #include "rp-usb-host.dtsi"
+
+/* mipi */
+#include "zkzg_mipi.dtsi"
 
 /* ethernet */
 // #include "rp-eth-pcie2gmac-rk3588.dtsi"
+#include "rp-eth-gmac0.dtsi"
 #include "rp-eth-gmac1.dtsi"
 
 /* pcie */
@@ -27,7 +31,7 @@
 // #include "rp-wifi-bt-ap6275p-rk3588.dtsi"
 
 /* hdmi rx */
-#include "rp-hdmirx.dtsi"
+// #include "rp-hdmirx.dtsi"
 
 /* camera */
 /***********all camera config********/
@@ -59,10 +63,10 @@
 //#include "rp-camera-dphy0-imx415.dtsi"
 /******************************************/
 
-//#include "rp-lcd-hdmi0.dtsi"        //batch ignore
+// #include "rp-lcd-hdmi0.dtsi"        //batch ignore
-//#include "rp-lcd-hdmi1.dtsi"        //batch ignore
+// #include "rp-lcd-hdmi1.dtsi"        //batch ignore
 //#include "rp-lcd-typec-dp0.dtsi"    //usb edp0, must be enable rp-usb-typec.dtsi, batch ignore 
-#include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi"
+// #include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi"
 
 /* lcd */
 // #include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi"
@@ -133,20 +137,20 @@
                 //        gpio_function = <4>;
                 //};
 
-                led {
+                // led {
-                        gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
+                //         gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
-                        gpio_function = <3>;
+                //         gpio_function = <3>;
-                };
+                // };
 
                 usb-host-power {
                         gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
                         gpio_function = <4>;
                 };
 
-                usb-hub-reset {
+                // usb-hub-reset {
-                        gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
+                //         gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
-                        gpio_function = <4>;
+                //         gpio_function = <4>;
-                };
+                // };
     };
 
         rp_gpio{
@@ -160,49 +164,99 @@
         };
 };
 
-
+&uart1 {
-&uart3 {
+	status = "disabled";
-    status = "okay";
+	pinctrl-names = "default";
-    pinctrl-names = "default";
+	pinctrl-0 = <&uart1m1_xfer>;
-    pinctrl-0 = <&uart3m2_xfer>;
+	fifo-depth =<4096>;	
+	rx-fifo-depth =<2048>;
+	tx-fifo-depth =<2048>;
+		dma-names = "tx", "rx";
 };
 
-&uart6 {
+&uart3 {
-    status = "okay";
+	status = "okay";
-    pinctrl-names = "default";
+	pinctrl-names = "default";
-    pinctrl-0 = <&uart6m2_xfer>;
+	pinctrl-0 = <&uart3m0_xfer>;
+	fifo-depth =<4096>;	
+	rx-fifo-depth =<2048>;
+	tx-fifo-depth =<2048>;
+		dma-names = "tx", "rx";
 };
 
 &uart4 {
-    status = "okay";
+	status = "okay";
-    pinctrl-names = "default";
+	pinctrl-names = "default";
-    pinctrl-0 = <&uart4m2_xfer>;
+	pinctrl-0 = <&uart4m1_xfer>;
+	fifo-depth =<4096>;	
+	rx-fifo-depth =<2048>;
+	tx-fifo-depth =<2048>;
+		dma-names = "tx", "rx";
+	
+};
+
+&uart5 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart5m0_xfer>;
+	fifo-depth =<4096>;	
+	rx-fifo-depth =<2048>;
+	tx-fifo-depth =<2048>;
+		dma-names = "tx", "rx";
+	
+};
+
+&uart6 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart6m1_xfer>;
+	fifo-depth =<4096>;	
+	rx-fifo-depth =<2048>;
+	tx-fifo-depth =<2048>;
+	dma-names = "tx", "rx";
 };
 
 &uart7 {
-    status = "okay";
+	status = "okay";
-    pinctrl-names = "default";
+	pinctrl-names = "default";
-    pinctrl-0 = <&uart7m2_xfer>;
+	pinctrl-0 = <&uart7m0_xfer>;
+	fifo-depth =<4096>;	
+	rx-fifo-depth =<2048>;
+	tx-fifo-depth =<2048>;
+	dma-names = "tx", "rx";
 };
 
-
+&uart8 {
-
+	status = "disabled";
-&can0 {
+	pinctrl-names = "default";
-    assigned-clocks = <&cru CLK_CAN0>;
+	pinctrl-0 = <&uart8m0_xfer>;
-    assigned-clock-rates = <200000000>;
+	fifo-depth =<4096>;	
-    status = "disabled";
+	rx-fifo-depth =<2048>;
-    pinctrl-names = "default";
+	tx-fifo-depth =<2048>;
-    pinctrl-0 = <&can0m0_pins>;
+	dma-names = "tx", "rx";
 };
 
 &can1 {
-    assigned-clocks = <&cru CLK_CAN1>;
+	assigned-clocks = <&cru CLK_CAN1>;
-    assigned-clock-rates = <200000000>;
+	assigned-clock-rates = <200000000>;
+	status = "disabled";
+	pinctrl-names = "default";
+	pinctrl-0 = <&can1m1_pins>;
+}; 
+
+&spi3 {
     status = "disabled";
-    pinctrl-names = "default";
+    pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
-    pinctrl-0 = <&can1m1_pins>;
+    
+    spi3_dev@0 {
+        compatible = "rockchip,spidev";
+        reg = <0>;
+        spi-max-frequency = <12000000>;
+        spi-lsb-first;
+    };
 };
 
+
 &i2c4 {
     status = "disabled";
     pinctrl-names = "default";
@@ -223,9 +277,8 @@
 
 };
 
-
 &sdmmc {
-    status = "okay";
+    status = "disabled";
 };
 
 &fiq_debugger {
@@ -233,14 +286,58 @@
 };
 
 &display_subsystem {
-clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
+    clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
-clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
+    clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
 };
 
 &hdptxphy_hdmi_clk0 {
-            status = "okay";
+            status = "disabled";
 };
 
 &hdptxphy_hdmi_clk1 {
-            status = "okay";
+            status = "disabled";
 };
+
+&pwm14 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm14m1_pins>;  // 选择 PWM1 的引脚复用
+    #pwm-cells = <3>;
+};
+
+&pwm15 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm15m1_pins>;  // 选择 PWM1 的引脚复用
+    #pwm-cells = <3>;
+};
+
+&pwm11 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm11m1_pins>; 
+    #pwm-cells = <3>;
+};
+
+&pwm13 {
+    status = "okay";
+    compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
+    pinctrl-names = "active";
+    pinctrl-0 = <&pwm13m1_pins>; 
+    #pwm-cells = <3>;
+};
+
+&i2c1 {
+  status = "okay";                    // 启用 I2C1 总线
+  pinctrl-names = "default";          // 引脚控制状态名称
+  pinctrl-0 = <&i2c1m2_xfer>;         // 使用 i2c1m2_xfer 引脚配置
+};
+
+&i2c2 {
+  status = "okay";                    // 启用 I2C2 总线
+  pinctrl-names = "default";          // 引脚控制状态名称
+  pinctrl-0 = <&i2c2m3_xfer>;         // 使用 i2c2m3_xfer 引脚配置
+};

rk3588/rp-eth-gmac0.dtsi

@@ -9,9 +9,9 @@
 &gmac0 {
     // Use rgmii-rxid mode to disable rx delay inside Soc
     phy-mode = "rgmii-rxid";
-    clock_in_out = "output";
+    clock_in_out = "input";
 
-    snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
+    snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
     snps,reset-active-low;
     // Reset time is 20ms, 100ms for rtl8211f 
     snps,reset-delays-us = <0 20000 100000>;
@@ -21,7 +21,9 @@
              &gmac0_tx_bus2
              &gmac0_rx_bus2
              &gmac0_rgmii_clk
-             &gmac0_rgmii_bus>;
+             &gmac0_rgmii_bus
+            &gmac0_clkinout
+            &eth0_pins>;
 
     tx_delay = <0x44>;
     // rx_delay = <0x4f>; 

rk3588/rp-eth-gmac1.dtsi

@@ -12,7 +12,7 @@
     phy-mode = "rgmii-rxid";
     clock_in_out = "input";
 
-    snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+    snps,reset-gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>;
     snps,reset-active-low;
     // Reset time is 20ms, 100ms for rtl8211f 
     snps,reset-delays-us = <0 20000 100000>;
@@ -23,8 +23,8 @@
              &gmac1_rx_bus2
              &gmac1_rgmii_clk
              &gmac1_rgmii_bus
-            &gmac1_clkinout
+            &gmac1_clkinout>;
-            &eth1_pins>;
+            // &eth1_pins>;
 
     tx_delay = <0x44>;
     // rx_delay = <0x4f>;

rk3588/rp-usb-host.dtsi

@@ -39,10 +39,27 @@
 
 
 &usbhost3_0 {
-    status = "disabled";
+    status = "okay";
 };
 
 &usbhost_dwc3_0 {
-    status = "disabled";
+    status = "okay";
 };
 
+&usbdrd_dwc3_0 {
+     extcon=<&u2phy0>;
+     status="okay";
+};
+  
+&u2phy0 {
+     status = "okay";
+};
+
+&usbdrd_dwc3_1 {
+     extcon=<&u2phy1>;
+     status="okay";
+};
+  
+&u2phy1 {
+     status = "okay";
+};

rk3588/zkzg-mipi.dtsi

@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+&mipi_dcphy0 {
+	status = "okay";
+};
+
+&csi2_dcphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipidcphy0_in_ucam0: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mvcam_out4>;
+				// 修改为 4 lane
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidcphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi0_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7m0_xfer>;
+
+	mvcam_4: mvcam@3b{
+		status = "okay";
+		compatible = "veye,mvcam";
+		reg = <0x3b>;
+		// 电源控制引脚
+		pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
+		// 新增复位引脚
+		reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "NC";
+		rockchip,camera-module-lens-name = "NC";
+		port {
+			mvcam_out4: endpoint {
+				remote-endpoint = <&mipidcphy0_in_ucam0>;
+				// 修改为 4 lane
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&mipi0_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_input: endpoint@1 {
+				reg = <1>;
+				remote-endpoint = <&csidcphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in0>;
+			};
+		};
+	};
+};
+
+&rkcif_mipi_lvds {
+	status = "okay";
+
+	port {
+		cif_mipi_in0: endpoint {
+			remote-endpoint = <&mipi0_csi2_output>;
+		};
+	};
+};
+
+&rkcif_mipi_lvds_sditf {
+	status = "disabled";
+
+	port {
+		mipi_lvds_sditf: endpoint {
+			remote-endpoint = <&isp1_in1>;
+		};
+	};
+};
+
+&rkisp1_vir0 {
+	status = "disabled";
+
+	port {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		isp1_in1: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&mipi_lvds_sditf>;
+		};
+	};
+};

rk3588/zkzg_mipi.dtsi

@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+&csi2_dcphy0 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipidcphy0_in_ucam0: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mvcam_out4>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			csidcphy0_out: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&mipi0_csi2_input>;
+			};
+		};
+	};
+};
+
+&i2c7 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c7m0_xfer>;
+
+	mvcam_4: mvcam@3b{
+		status = "okay";
+        compatible = "veye,mvcam";
+        reg = <0x3b>;
+		clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
+		clock-names = "xvclk";
+		power-domains = <&power RK3588_PD_VI>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&mipim0_camera2_clk>;
+		rockchip,grf = <&sys_grf>;
+		reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
+		pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
+		rockchip,camera-module-index = <0>;
+		rockchip,camera-module-facing = "back";
+		rockchip,camera-module-name = "NC";
+		rockchip,camera-module-lens-name = "NC";
+		port {
+			mvcam_out4: endpoint {
+				remote-endpoint = <&mipidcphy0_in_ucam0>;
+				data-lanes = <1 2 3 4>;
+			};
+		};
+	};
+};
+
+&mipi_dcphy0 {
+	status = "okay";
+};
+
+&mipi0_csi2 {
+	status = "okay";
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			// 修正这里：endpoint@0 和 reg = <0>
+			mipi0_csi2_input: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&csidcphy0_out>;
+			};
+		};
+
+		port@1 {
+			reg = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi0_csi2_output: endpoint@0 {
+				reg = <0>;
+				remote-endpoint = <&cif_mipi_in0>;
+			};
+		};
+	};
+};
+
+&rkcif {
+	status = "okay";
+};
+
+&rkcif_mmu {
+	status = "okay";
+};
+
+&rkcif_mipi_lvds {
+	status = "okay";
+
+	port {
+		cif_mipi_in0: endpoint {
+			remote-endpoint = <&mipi0_csi2_output>;
+		};
+	};
+};
+
+// 以下ISP相关配置可以保持disabled，先确保基础链路通
+&rkcif_mipi_lvds_sditf {
+	status = "disabled";
+};
+
+&rkisp1_vir0 {
+	status = "disabled";
+};