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更改dcphy控制器

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zhangpeng
2025-11-04 21:41:07 +08:00
parent 7a15762f4c
commit 8b1e982942
1 changed files with 101 additions and 53 deletions
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154
rk3588/zkzg_mipi.dtsi
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@@ -1,42 +1,24 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 www.veye.cc
*
*/
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
mvcam: mvcam@1a {
compatible = "veye,mvcam";
status = "okay";
reg = <0x3b>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
/ {
vcc_mipidcphy0: vcc-mipidcphy0-regulator {
status = "disabled";
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera2_clk>;
rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
mvcam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
data-lanes = <1 2 3 4>;
};
};
pinctrl-0 = <&mipidcphy0_pwr>;
regulator-name = "vcc_mipidcphy0";
enable-active-high;
};
};
&csi2_dphy0_hw {
&csi2_dcphy0 {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
@@ -44,7 +26,8 @@
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam2: endpoint@1 {
mipidcphy0_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&mvcam_out0>;
data-lanes = <1 2 3 4>;
@@ -54,77 +37,142 @@
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&mipi2_csi2 {
&csi2_dcphy0_hw {
status = "okay";
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
mvcam: mvcam@3b{
compatible = "veye,mvcam";
reg = <0x3b>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera2_clk>;
power-domains = <&power RK3588_PD_VI>;
//power-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
//avdd-supply = <&vcc_mipidcphy0>;
//firefly,clkout-enabled-index = <0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "NC";
rockchip,camera-module-lens-name = "NC";
port {
mvcam_out0: endpoint {
remote-endpoint = <&mipidcphy0_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
remote-endpoint = <&cif_mipi0_in0>;
};
};
};
};
&pinctrl {
cam {
mipidcphy0_pwr: mipidcphy0-pwr {
rockchip,pins =
/* camera power en */
<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkcif {
status = "okay";
// memory-region = <&cif_reserved>;
};
&rkcif_mipi_lvds2 {
status = "okay";
//firefly,yuv_camera;
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
cif_mipi0_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
status = "disabled";
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp1_vir1>;
mipi_lvds2_sditf: endpoint {
remote-endpoint = <&isp0_vir0>;
};
};
};
&rkisp1 {
&rkcif_mmu {
status = "okay";
};
&isp1_mmu {
status = "okay";
&rkisp0 {
status = "disabled";
};
&rkisp1_vir1 {
status = "okay";
&isp0_mmu {
status = "disabled";
};
&rkisp0_vir0 {
status = "disabled";
port {
#address-cells = <1>;
#size-cells = <0>;
isp1_vir1: endpoint@0 {
isp0_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
remote-endpoint = <&mipi_lvds2_sditf>;
};
};
};