Compare commits
14 Commits
03尺蠖机器人
...
智能控制模块_56m
| Author | SHA1 | Date | |
|---|---|---|---|
|
65ec98e142 | ||
|
|
13f99ce0e8 | ||
|
|
440be3e956 | ||
|
|
8b1e982942 | ||
|
|
7a15762f4c | ||
|
|
c6977360c3 | ||
|
|
aa4a8c801a | ||
|
|
b8465f59f4 | ||
|
|
0e3abc6330 | ||
|
|
5bdca9e967 | ||
|
|
d2ec2b532e | ||
|
|
3bbdf81bc5 | ||
|
|
92bc223ace | ||
|
|
f716b853db |
@@ -33,10 +33,9 @@ deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-power-rk3588.dtsi \
|
||||
|
||||
arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb)
|
||||
|
||||
|
||||
@@ -29,7 +29,6 @@ dr4-rk3588.o: arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-power-rk3588.dtsi
|
||||
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
# 0 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
# 0 "<built-in>"
|
||||
# 0 "<command-line>"
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
# 1 "<built-in>"
|
||||
# 1 "<command-line>"
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
|
||||
|
||||
@@ -10674,7 +10674,7 @@
|
||||
};
|
||||
};
|
||||
};
|
||||
# 6888 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
|
||||
# 6887 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
|
||||
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 1
|
||||
|
||||
@@ -14545,55 +14545,144 @@
|
||||
|
||||
|
||||
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi" 1
|
||||
|
||||
&u2phy2 {
|
||||
|
||||
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi" 1
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
&mipi_dcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3 {
|
||||
&csi2_dcphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipidcphy0_in_ucam0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mvcam_out4>;
|
||||
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
|
||||
|
||||
&u2phy2_host {
|
||||
status = "okay";
|
||||
csidcphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m0_xfer>;
|
||||
|
||||
mvcam_4: mvcam@3b{
|
||||
status = "okay";
|
||||
compatible = "veye,mvcam";
|
||||
reg = <0x3b>;
|
||||
|
||||
pwdn-gpios = <&gpio1 5 0>;
|
||||
|
||||
reset-gpios = <&gpio1 3 1>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "NC";
|
||||
rockchip,camera-module-lens-name = "NC";
|
||||
port {
|
||||
mvcam_out4: endpoint {
|
||||
remote-endpoint = <&mipidcphy0_in_ucam0>;
|
||||
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host0_ehci {
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidcphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
&usbhost3_0 {
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
mipi_lvds_sditf: endpoint {
|
||||
remote-endpoint = <&isp1_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbhost_dwc3_0 {
|
||||
&rkisp1_vir0 {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp1_in1: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi_lvds_sditf>;
|
||||
};
|
||||
# 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
};
|
||||
};
|
||||
# 16 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
|
||||
|
||||
|
||||
@@ -14611,7 +14700,7 @@
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "input";
|
||||
|
||||
snps,reset-gpio = <&gpio2 20 1>;
|
||||
snps,reset-gpio = <&gpio3 15 1>;
|
||||
snps,reset-active-low;
|
||||
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
@@ -14631,7 +14720,7 @@
|
||||
phy-handle = <&rgmii_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
# 17 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
# 20 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi" 1
|
||||
|
||||
&mdio1 {
|
||||
@@ -14647,7 +14736,7 @@
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "input";
|
||||
|
||||
snps,reset-gpio = <&gpio3 15 1>;
|
||||
snps,reset-gpio = <&gpio2 20 1>;
|
||||
snps,reset-active-low;
|
||||
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
@@ -14658,56 +14747,17 @@
|
||||
&gmac1_rx_bus2
|
||||
&gmac1_rgmii_clk
|
||||
&gmac1_rgmii_bus
|
||||
&gmac1_clkinout
|
||||
ð1_pins>;
|
||||
&gmac1_clkinout>;
|
||||
|
||||
|
||||
tx_delay = <0x44>;
|
||||
|
||||
|
||||
phy-handle = <&rgmii_phy1>;
|
||||
status = "okay";
|
||||
};
|
||||
# 18 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
|
||||
|
||||
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-power-rk3588.dtsi" 1
|
||||
|
||||
/ {
|
||||
pcie20_avdd0v85: pcie20-avdd0v85 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie20_avdd0v85";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <850000>;
|
||||
vin-supply = <&vdd_0v85_s0>;
|
||||
};
|
||||
|
||||
pcie20_avdd1v8: pcie20-avdd1v8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pcie20_avdd1v8";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
vin-supply = <&avcc_1v8_s0>;
|
||||
};
|
||||
|
||||
vcc3v3_pcie30: vcc3v3-pcie30 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio4 5 0>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
# 21 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
# 90 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
# 93 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
/ {
|
||||
model = "dr4-rk3588";
|
||||
|
||||
@@ -14736,14 +14786,14 @@
|
||||
thermal-zone = "soc-thermal";
|
||||
threshold-temp = <60000>;
|
||||
running-time = <10000>;
|
||||
status = "disable";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rp_power{
|
||||
status = "okay";
|
||||
compatible = "rp_power";
|
||||
rp_not_deep_sleep = <1>;
|
||||
# 142 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
# 145 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
usb-host-power {
|
||||
gpio_num = <&gpio2 17 0>;
|
||||
gpio_function = <4>;
|
||||
@@ -14754,13 +14804,74 @@
|
||||
|
||||
|
||||
};
|
||||
# 162 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
|
||||
rp_gpio{
|
||||
status = "disabled";
|
||||
compatible = "rp_gpio";
|
||||
|
||||
gpio3c7 {
|
||||
gpio_num = <&gpio3 23 0>;
|
||||
gpio_function = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
pinctrl-0 = <&uart7m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
@@ -14768,7 +14879,7 @@
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
@@ -14777,26 +14888,29 @@
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
||||
&can0 {
|
||||
assigned-clocks = <&cru 112>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0m0_pins>;
|
||||
|
||||
};
|
||||
|
||||
&can1 {
|
||||
assigned-clocks = <&cru 114>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
};
|
||||
# 225 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
|
||||
&spi3 {
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
|
||||
|
||||
spi3_dev@0 {
|
||||
compatible = "rockchip,spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>;
|
||||
spi-lsb-first;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&i2c4 {
|
||||
status = "disable";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4m1_xfer>;
|
||||
|
||||
@@ -14815,7 +14929,6 @@
|
||||
|
||||
};
|
||||
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -14823,3 +14936,60 @@
|
||||
&fiq_debugger {
|
||||
rockchip,baudrate = <115200>;
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi_clk0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi_clk1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm14 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm14m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm15 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm15m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm11 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm11m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm13 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm13m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1m2_xfer>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2m3_xfer>;
|
||||
};
|
||||
|
||||
Binary file not shown.
@@ -9,7 +9,10 @@
|
||||
|
||||
/* usb */
|
||||
// #include "rp-usb-typec-rk3588.dtsi"
|
||||
#include "rp-usb-host.dtsi"
|
||||
// #include "rp-usb-host.dtsi"
|
||||
|
||||
/* mipi */
|
||||
#include "zkzg_mipi.dtsi"
|
||||
|
||||
/* ethernet */
|
||||
// #include "rp-eth-pcie2gmac-rk3588.dtsi"
|
||||
@@ -17,7 +20,7 @@
|
||||
#include "rp-eth-gmac1.dtsi"
|
||||
|
||||
/* pcie */
|
||||
#include "rp-pcie-power-rk3588.dtsi"
|
||||
// #include "rp-pcie-power-rk3588.dtsi"
|
||||
// #include "rp-pcie3.dtsi" //need comment when use board of make it youself,and remove the pcie function
|
||||
// #include "rp-pcie-5g.dtsi"
|
||||
|
||||
@@ -115,7 +118,7 @@
|
||||
thermal-zone = "soc-thermal";
|
||||
threshold-temp = <60000>; //60C
|
||||
running-time = <10000>; //10s
|
||||
status = "disable";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rp_power{
|
||||
@@ -150,21 +153,73 @@
|
||||
// };
|
||||
};
|
||||
|
||||
// rp_gpio{
|
||||
// status = "okay";
|
||||
// compatible = "rp_gpio";
|
||||
rp_gpio{
|
||||
status = "disabled";
|
||||
compatible = "rp_gpio";
|
||||
|
||||
// gpio3c7 {
|
||||
// gpio_num = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
// gpio_function = <0>;
|
||||
// };
|
||||
// };
|
||||
gpio3c7 {
|
||||
gpio_num = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
|
||||
gpio_function = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
pinctrl-0 = <&uart7m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
@@ -172,7 +227,7 @@
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
@@ -181,49 +236,29 @@
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
||||
&can0 {
|
||||
assigned-clocks = <&cru CLK_CAN0>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0m0_pins>;
|
||||
|
||||
};
|
||||
|
||||
&can1 {
|
||||
assigned-clocks = <&cru CLK_CAN1>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
};
|
||||
|
||||
// &can2 {
|
||||
// assigned-clocks = <&cru CLK_CAN2>;
|
||||
// assigned-clock-rates = <200000000>;
|
||||
// status = "okay";
|
||||
// pinctrl-names = "default";
|
||||
// pinctrl-0 = <&can2m1_pins>;
|
||||
// };
|
||||
&spi3 {
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
|
||||
|
||||
// &spi3 {
|
||||
// // status = "disabled";
|
||||
// status = "okay";
|
||||
// max-freq = <48000000>;
|
||||
// dev-port = <1>;
|
||||
// pinctrl-0 = <&spi3m1_cs1 &spi3m1_pins>;
|
||||
// spidev0: spidev@00 {
|
||||
// status = "okay";
|
||||
// compatible = "rockchip,spidev";
|
||||
// reg = <0x00>;
|
||||
// spi-max-frequency = <48000000>;
|
||||
// };
|
||||
// };
|
||||
spi3_dev@0 {
|
||||
compatible = "rockchip,spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>;
|
||||
spi-lsb-first;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&i2c4 {
|
||||
status = "disable";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4m1_xfer>;
|
||||
|
||||
@@ -242,7 +277,6 @@
|
||||
|
||||
};
|
||||
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
};
|
||||
@@ -251,15 +285,59 @@
|
||||
rockchip,baudrate = <115200>;
|
||||
};
|
||||
|
||||
// &display_subsystem {
|
||||
// clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
// clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
// };
|
||||
&display_subsystem {
|
||||
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
};
|
||||
|
||||
// &hdptxphy_hdmi_clk0 {
|
||||
// status = "okay";
|
||||
// };
|
||||
&hdptxphy_hdmi_clk0 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
// &hdptxphy_hdmi_clk1 {
|
||||
// status = "okay";
|
||||
// };
|
||||
&hdptxphy_hdmi_clk1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm14 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm14m1_pins>; // 选择 PWM1 的引脚复用
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm15 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm15m1_pins>; // 选择 PWM1 的引脚复用
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm11 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm11m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm13 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm13m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay"; // 启用 I2C1 总线
|
||||
pinctrl-names = "default"; // 引脚控制状态名称
|
||||
pinctrl-0 = <&i2c1m2_xfer>; // 使用 i2c1m2_xfer 引脚配置
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay"; // 启用 I2C2 总线
|
||||
pinctrl-names = "default"; // 引脚控制状态名称
|
||||
pinctrl-0 = <&i2c2m3_xfer>; // 使用 i2c2m3_xfer 引脚配置
|
||||
};
|
||||
@@ -11,7 +11,7 @@
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "input";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
// Reset time is 20ms, 100ms for rtl8211f
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "input";
|
||||
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
// Reset time is 20ms, 100ms for rtl8211f
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
@@ -23,8 +23,8 @@
|
||||
&gmac1_rx_bus2
|
||||
&gmac1_rgmii_clk
|
||||
&gmac1_rgmii_bus
|
||||
&gmac1_clkinout
|
||||
ð1_pins>;
|
||||
&gmac1_clkinout>;
|
||||
// ð1_pins>;
|
||||
|
||||
tx_delay = <0x44>;
|
||||
// rx_delay = <0x4f>;
|
||||
|
||||
@@ -39,10 +39,27 @@
|
||||
|
||||
|
||||
&usbhost3_0 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbhost_dwc3_0 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
extcon=<&u2phy0>;
|
||||
status="okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
extcon=<&u2phy1>;
|
||||
status="okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
133
rk3588/zkzg-mipi.dtsi
Normal file
133
rk3588/zkzg-mipi.dtsi
Normal file
@@ -0,0 +1,133 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
&mipi_dcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dcphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipidcphy0_in_ucam0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mvcam_out4>;
|
||||
// 修改为 4 lane
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidcphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m0_xfer>;
|
||||
|
||||
mvcam_4: mvcam@3b{
|
||||
status = "okay";
|
||||
compatible = "veye,mvcam";
|
||||
reg = <0x3b>;
|
||||
// 电源控制引脚
|
||||
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
// 新增复位引脚
|
||||
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "NC";
|
||||
rockchip,camera-module-lens-name = "NC";
|
||||
port {
|
||||
mvcam_out4: endpoint {
|
||||
remote-endpoint = <&mipidcphy0_in_ucam0>;
|
||||
// 修改为 4 lane
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidcphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
mipi_lvds_sditf: endpoint {
|
||||
remote-endpoint = <&isp1_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkisp1_vir0 {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp1_in1: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi_lvds_sditf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
129
rk3588/zkzg_mipi.dtsi
Normal file
129
rk3588/zkzg_mipi.dtsi
Normal file
@@ -0,0 +1,129 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
&csi2_dcphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipidcphy0_in_ucam0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mvcam_out4>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidcphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m0_xfer>;
|
||||
|
||||
mvcam_4: mvcam@3b{
|
||||
status = "okay";
|
||||
compatible = "veye,mvcam";
|
||||
reg = <0x3b>;
|
||||
clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
|
||||
clock-names = "xvclk";
|
||||
power-domains = <&power RK3588_PD_VI>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mipim0_camera2_clk>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "NC";
|
||||
rockchip,camera-module-lens-name = "NC";
|
||||
port {
|
||||
mvcam_out4: endpoint {
|
||||
remote-endpoint = <&mipidcphy0_in_ucam0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
// 修正这里：endpoint@0 和 reg = <0>
|
||||
mipi0_csi2_input: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csidcphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
// 以下ISP相关配置可以保持disabled，先确保基础链路通
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rkisp1_vir0 {
|
||||
status = "disabled";
|
||||
};
|
||||
Reference in New Issue
Block a user