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更改dcphy控制器

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zhangpeng
2025-11-06 14:52:07 +08:00
parent 8b1e982942
commit 440be3e956
3 changed files with 113 additions and 148 deletions
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129
rk3588/.dr4-rk3588.dtb.dts.tmp
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@@ -14551,17 +14551,51 @@
# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg_mipi.dtsi" 1 # 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg_mipi.dtsi" 1
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipidcphy0_in_ucam0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mvcam_out4>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c7 { &i2c7 {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>; pinctrl-0 = <&i2c7m0_xfer>;
mvcam_4: mvcam@3b{
mvcam: mvcam@1a {
compatible = "veye,mvcam";
status = "okay"; status = "okay";
compatible = "veye,mvcam";
reg = <0x3b>; reg = <0x3b>;
clocks = <&cru 256>; clocks = <&cru 257>;
clock-names = "xvclk"; clock-names = "xvclk";
power-domains = <&power 27>; power-domains = <&power 27>;
pinctrl-names = "default"; pinctrl-names = "default";
@@ -14569,112 +14603,85 @@
rockchip,grf = <&sys_grf>; rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 3 0>; reset-gpios = <&gpio1 3 0>;
pwdn-gpios = <&gpio1 5 0>; pwdn-gpios = <&gpio1 5 0>;
rockchip,camera-module-index = <2>; rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "front"; rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2022-PX1"; rockchip,camera-module-name = "NC";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; rockchip,camera-module-lens-name = "NC";
port { port {
mvcam_out0: endpoint { mvcam_out4: endpoint {
remote-endpoint = <&mipi_in_ucam2>; remote-endpoint = <&mipidcphy0_in_ucam0>;
data-lanes = <1 2 3 4>; data-lanes = <1 2 3 4>;
}; };
}; };
}; };
}; };
&csi2_dphy0_hw { &mipi_dcphy0 {
status = "okay"; status = "okay";
}; };
&csi2_dphy0 { &mipi0_csi2 {
status = "okay"; status = "okay";
ports { ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { port@0 {
reg = <0>; reg = <0>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
mipi_in_ucam2: endpoint@1 {
mipi0_csi2_input: endpoint@1 {
reg = <1>; reg = <1>;
remote-endpoint = <&mvcam_out0>; remote-endpoint = <&csidcphy0_out>;
data-lanes = <1 2 3 4>;
}; };
}; };
port@1 { port@1 {
reg = <1>; reg = <1>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
csidphy0_out: endpoint@0 {
mipi0_csi2_output: endpoint@0 {
reg = <0>; reg = <0>;
remote-endpoint = <&mipi2_csi2_input>; remote-endpoint = <&cif_mipi_in0>;
}; };
}; };
}; };
}; };
&mipi2_csi2 { &rkcif_mipi_lvds {
status = "okay"; status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port { port {
cif_mipi_in2: endpoint { cif_mipi_in0: endpoint {
remote-endpoint = <&mipi2_csi2_output>; remote-endpoint = <&mipi0_csi2_output>;
}; };
}; };
}; };
&rkcif_mipi_lvds2_sditf { &rkcif_mipi_lvds_sditf {
status = "okay"; status = "disabled";
port { port {
mipi2_lvds_sditf: endpoint { mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp1_vir1>; remote-endpoint = <&isp1_in1>;
}; };
}; };
}; };
&rkisp1 { &rkisp1_vir0 {
status = "okay"; status = "disabled";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir1 {
status = "okay";
port { port {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
isp1_vir1: endpoint@0 { isp1_in1: endpoint@0 {
reg = <0>; reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>; remote-endpoint = <&mipi_lvds_sditf>;
}; };
}; };
}; };

BIN
rk3588/dr4-rk3588.dtb
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88
rk3588/zkzg_mipi.dtsi
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@@ -1,21 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/* /*
* Copyright (c) 2022 www.veye.cc * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
* *
*/ */
/ {
vcc_mipidcphy0: vcc-mipidcphy0-regulator {
status = "disabled";
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipidcphy0_pwr>;
regulator-name = "vcc_mipidcphy0";
enable-active-high;
};
};
&csi2_dcphy0 { &csi2_dcphy0 {
status = "okay"; status = "okay";
@@ -27,12 +15,13 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
mipidcphy0_in_ucam0: endpoint@1 { mipidcphy0_in_ucam0: endpoint@0 {
reg = <1>; reg = <0>;
remote-endpoint = <&mvcam_out0>; remote-endpoint = <&mvcam_out4>;
data-lanes = <1 2 3 4>; data-lanes = <1 2 3 4>;
}; };
}; };
port@1 { port@1 {
reg = <1>; reg = <1>;
#address-cells = <1>; #address-cells = <1>;
@@ -46,36 +35,29 @@
}; };
}; };
&csi2_dcphy0_hw {
status = "okay";
};
&i2c7 { &i2c7 {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>; pinctrl-0 = <&i2c7m0_xfer>;
mvcam: mvcam@3b{ mvcam_4: mvcam@3b{
status = "okay";
compatible = "veye,mvcam"; compatible = "veye,mvcam";
reg = <0x3b>; reg = <0x3b>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
clock-names = "xvclk"; clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera2_clk>; pinctrl-0 = <&mipim0_camera2_clk>;
power-domains = <&power RK3588_PD_VI>; rockchip,grf = <&sys_grf>;
//power-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
//avdd-supply = <&vcc_mipidcphy0>;
//firefly,clkout-enabled-index = <0>;
rockchip,camera-module-index = <0>; rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back"; rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "NC"; rockchip,camera-module-name = "NC";
rockchip,camera-module-lens-name = "NC"; rockchip,camera-module-lens-name = "NC";
port { port {
mvcam_out0: endpoint { mvcam_out4: endpoint {
remote-endpoint = <&mipidcphy0_in_ucam0>; remote-endpoint = <&mipidcphy0_in_ucam0>;
data-lanes = <1 2 3 4>; data-lanes = <1 2 3 4>;
}; };
@@ -84,6 +66,10 @@
}; };
&mipi_dcphy0 {
status = "okay";
};
&mipi0_csi2 { &mipi0_csi2 {
status = "okay"; status = "okay";
@@ -109,70 +95,42 @@
mipi0_csi2_output: endpoint@0 { mipi0_csi2_output: endpoint@0 {
reg = <0>; reg = <0>;
remote-endpoint = <&cif_mipi0_in0>; remote-endpoint = <&cif_mipi_in0>;
}; };
}; };
}; };
}; };
&pinctrl { &rkcif_mipi_lvds {
cam {
mipidcphy0_pwr: mipidcphy0-pwr {
rockchip,pins =
/* camera power en */
<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkcif {
status = "okay"; status = "okay";
// memory-region = <&cif_reserved>;
};
&rkcif_mipi_lvds2 {
status = "okay";
//firefly,yuv_camera;
port { port {
cif_mipi0_in0: endpoint { cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>; remote-endpoint = <&mipi0_csi2_output>;
}; };
}; };
}; };
&rkcif_mipi_lvds2_sditf { &rkcif_mipi_lvds_sditf {
status = "disabled"; status = "disabled";
port { port {
mipi_lvds2_sditf: endpoint { mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp0_vir0>; remote-endpoint = <&isp1_in1>;
}; };
}; };
}; };
&rkcif_mmu { &rkisp1_vir0 {
status = "okay";
};
&rkisp0 {
status = "disabled";
};
&isp0_mmu {
status = "disabled";
};
&rkisp0_vir0 {
status = "disabled"; status = "disabled";
port { port {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
isp0_vir0: endpoint@0 { isp1_in1: endpoint@0 {
reg = <0>; reg = <0>;
remote-endpoint = <&mipi_lvds2_sditf>; remote-endpoint = <&mipi_lvds_sditf>;
}; };
}; };
}; };