更改dcphy控制器

This commit is contained in:
zhangpeng
2025-11-06 14:52:07 +08:00
parent 8b1e982942
commit 440be3e956
3 changed files with 113 additions and 148 deletions

View File

@@ -14551,17 +14551,51 @@
# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg_mipi.dtsi" 1
&csi2_dcphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipidcphy0_in_ucam0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mvcam_out4>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi0_csi2_input>;
};
};
};
};
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
mvcam: mvcam@1a {
compatible = "veye,mvcam";
mvcam_4: mvcam@3b{
status = "okay";
reg = <0x3b>;
clocks = <&cru 256>;
compatible = "veye,mvcam";
reg = <0x3b>;
clocks = <&cru 257>;
clock-names = "xvclk";
power-domains = <&power 27>;
pinctrl-names = "default";
@@ -14569,112 +14603,85 @@
rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 3 0>;
pwdn-gpios = <&gpio1 5 0>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "NC";
rockchip,camera-module-lens-name = "NC";
port {
mvcam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
mvcam_out4: endpoint {
remote-endpoint = <&mipidcphy0_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&csi2_dphy0_hw {
&mipi_dcphy0 {
status = "okay";
};
&csi2_dphy0 {
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam2: endpoint@1 {
mipi0_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&mvcam_out0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csidcphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
mipi0_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
remote-endpoint = <&cif_mipi_in0>;
};
};
};
};
&mipi2_csi2 {
&rkcif_mipi_lvds {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
cif_mipi_in0: endpoint {
remote-endpoint = <&mipi0_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
&rkcif_mipi_lvds_sditf {
status = "disabled";
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp1_vir1>;
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp1_in1>;
};
};
};
&rkisp1 {
status = "okay";
};
&rkisp1_vir0 {
status = "disabled";
&isp1_mmu {
status = "okay";
};
&rkisp1_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp1_vir1: endpoint@0 {
isp1_in1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};