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base: zhangpeng:37cc8084febd20a74e4f2a849a765a0fa596dae1
Branches Tags
zhangpeng:master zhangpeng:智能控制模块_56mm zhangpeng:SOH_AI zhangpeng:十四五航弹院 zhangpeng:SOH_DI zhangpeng:SOH_UART zhangpeng:SOH_3588 zhangpeng:耐辐照相机 zhangpeng:02哈工大项目 zhangpeng:03尺蠖机器人 zhangpeng:01智能控制模块 zhangpeng:04PAL
..
compare: zhangpeng:SOH_UART
Branches Tags
zhangpeng:智能控制模块_56mm zhangpeng:SOH_AI zhangpeng:十四五航弹院 zhangpeng:SOH_DI zhangpeng:SOH_UART zhangpeng:SOH_3588 zhangpeng:耐辐照相机 zhangpeng:02哈工大项目 zhangpeng:03尺蠖机器人 zhangpeng:master zhangpeng:01智能控制模块 zhangpeng:04PAL

5 Commits
37cc8084fe ... SOH_UART

Author SHA1 Message Date
zhangpeng
58da0ee3c8 优化gmac配置 2025-10-23 10:24:30 +08:00
zhangpeng
4b55c90c22 修改GMAC复位引脚 2025-10-20 13:46:17 +08:00
zhangpeng
d4232d0fe1 更改网口gmac配置 2025-10-20 13:42:33 +08:00
zhangpeng
dde492ee5f 增加地址分配 2025-10-17 11:08:02 +08:00
zhangpeng
d92c0f85df 配置PCIE 2025-10-09 14:34:41 +08:00
7 changed files with 105 additions and 57 deletions
Expand all files Collapse all files

1
rk356x/.dr4-rk3568.dtb.cmd
View File

@@ -27,6 +27,7 @@ deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb := \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi \

1
rk356x/.dr4-rk3568.dtb.d.pre.tmp
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@@ -23,5 +23,6 @@ dr4-rk3568.o: arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi

93
rk356x/.dr4-rk3568.dtb.dts.tmp
View File

@@ -1,6 +1,6 @@
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -7868,7 +7868,7 @@
};
};
};
# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 3892 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
/ {
@@ -8836,35 +8836,59 @@ dsi1_panel: panel@0 {
disable-win-move;
};
# 13 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie_dma: pcie-dma@40000000 {
reg = <0x0 0x40000000 0x0 0x10000000>;
no-map;
};
};
};
&pcie3x2 {
compatible = "rockchip,rk3568-pcie-ep";
reset-gpios = <&gpio0 22 0>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
memory-region = <&pcie_dma>;
};
# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low;
snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru 389>, <&cru 386>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>;
assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x2d>;
rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
status = "okay";
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
@@ -8872,10 +8896,9 @@ dsi1_panel: panel@0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru 183>;
};
};
# 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
@@ -8900,8 +8923,8 @@ dsi1_panel: panel@0 {
pinctrl-0 = <&can1m1_pins>;
status = "okay";
};
# 33 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 79 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 36 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 82 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
/{
model = "dr4-rk3568";
compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568";
@@ -8922,7 +8945,7 @@ dsi1_panel: panel@0 {
pinctrl-name = "default";
pinctrl-0 = <&rp_power>;
# 122 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 125 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
otg_mode {
gpio_num = <&gpio1 4 1>;
gpio_function = <0>;
@@ -8931,13 +8954,13 @@ dsi1_panel: panel@0 {
gpio_num = <&gpio0 5 0>;
gpio_function = <4>;
};
# 170 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 173 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
};
rp_gpio{
status = "disabled";
compatible = "rp_gpio";
# 183 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 186 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
gpio0a0 {
gpio_num = <&gpio0 0 1>;
gpio_function = <0>;
@@ -9114,7 +9137,7 @@ dsi1_panel: panel@0 {
status = "disabled";
};
# 418 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 421 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&rk_headset {
pinctrl-0 = <&hp_det>;
headset_gpio = <&gpio2 27 0>;
@@ -9163,7 +9186,7 @@ dsi1_panel: panel@0 {
BT,wake_host_irq = <&gpio0 28 0>;
status = "disabled";
};
# 516 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 519 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&pinctrl {
rp_pins {
rp_power: rp-power {
@@ -9203,7 +9226,7 @@ dsi1_panel: panel@0 {
<3 2 0 &pcfg_pull_none>;
};
};
# 570 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 573 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
};

BIN
rk356x/dr4-rk3568.dtb
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Binary file not shown.

4
rk356x/dr4-rk3568.dts
View File

@@ -11,6 +11,9 @@
#include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi"
#include "../rk3568-linux.dtsi"
/**************************pcie***********************/
#include "zkzg-pcie-rk3568.dtsi"
/*************************camera***********************/
// #include "rp-camera-mipi-gc2093-single-2lane.dtsi"
/***************************************************/
@@ -579,3 +582,4 @@
BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "disabled";
};

43
rk356x/rp-gmac0-pro-rk3568.dtsi
View File

@@ -1,30 +1,30 @@
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x2d>;
rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
status = "okay";
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
@@ -32,6 +32,5 @@
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru CLK_MAC0_OUT>;
};
};

20
rk356x/zkzg-pcie-rk3568.dtsi Normal file
View File

@@ -0,0 +1,20 @@
/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie_dma: pcie-dma@40000000 {
reg = <0x0 0x40000000 0x0 0x10000000>;
no-map;
};
};
};
&pcie3x2 {
compatible = "rockchip,rk3568-pcie-ep";
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
memory-region = <&pcie_dma>;
};