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7 Commits
智能控制模块_56m
...
SOH_3588
| Author | SHA1 | Date | |
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10980d7306 | ||
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591fa0c3f9 | ||
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77d62eaa60 | ||
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29b4af2f0d | ||
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c58ccf6f9c | ||
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af654bb685 | ||
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0ae4e1e318 |
@@ -32,10 +32,13 @@ deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := \
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scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h \
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arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/zkzg-usb-host.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/zkzg-pcie.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb)
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@@ -28,7 +28,10 @@ dr4-rk3588.o: arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts \
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scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h \
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arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/zkzg-usb-host.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi
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arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/zkzg-pcie.dtsi \
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arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi
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@@ -1,6 +1,6 @@
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
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# 1 "<built-in>"
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# 1 "<command-line>"
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# 0 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
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# 0 "<built-in>"
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# 0 "<command-line>"
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
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@@ -10674,7 +10674,7 @@
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};
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};
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};
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# 6887 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
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# 6888 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
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# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 1
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@@ -14517,7 +14517,20 @@
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/delete-node/ &backlight;
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# 4 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi" 1
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&i2c6 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6m0_xfer>;
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goodix_ts:goodix_ts@5d {
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status = "okay";
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compatible = "goodix,gt9xx";
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reg = <0x5d>;
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};
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};
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# 6 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi" 1
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@@ -14546,143 +14559,32 @@
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg-mipi.dtsi" 1
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&mipi_dcphy0 {
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status = "okay";
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg-usb-host.dtsi" 1
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&u2phy2_host {
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status = "okay";
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};
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&csi2_dcphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipidcphy0_in_ucam0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mvcam_out4>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidcphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi0_csi2_input>;
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};
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};
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};
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&u2phy3_host {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7m0_xfer>;
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mvcam_4: mvcam@3b{
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status = "okay";
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compatible = "veye,mvcam";
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reg = <0x3b>;
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pwdn-gpios = <&gpio1 5 0>;
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reset-gpios = <&gpio1 3 1>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "NC";
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rockchip,camera-module-lens-name = "NC";
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port {
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mvcam_out4: endpoint {
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remote-endpoint = <&mipidcphy0_in_ucam0>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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&usb_host0_ehci {
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status = "okay";
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};
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&mipi0_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidcphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi0_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi_in0>;
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};
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};
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};
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&usb_host0_ohci {
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status = "okay";
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};
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&rkcif_mipi_lvds {
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status = "okay";
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port {
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cif_mipi_in0: endpoint {
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remote-endpoint = <&mipi0_csi2_output>;
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};
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};
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&usb_host1_ehci {
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status = "okay";
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};
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&rkcif_mipi_lvds_sditf {
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status = "disabled";
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port {
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mipi_lvds_sditf: endpoint {
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remote-endpoint = <&isp1_in1>;
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};
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};
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&usb_host1_ohci {
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status = "okay";
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};
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&rkisp1_vir0 {
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status = "disabled";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp1_in1: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi_lvds_sditf>;
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};
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};
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};
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# 16 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 14 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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@@ -14700,7 +14602,7 @@
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phy-mode = "rgmii-rxid";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio3 15 1>;
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snps,reset-gpio = <&gpio2 20 1>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 20000 100000>;
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@@ -14720,7 +14622,7 @@
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phy-handle = <&rgmii_phy0>;
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status = "okay";
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};
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# 20 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 18 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi" 1
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&mdio1 {
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@@ -14736,7 +14638,7 @@
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phy-mode = "rgmii-rxid";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio2 20 1>;
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snps,reset-gpio = <&gpio3 15 1>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 20000 100000>;
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@@ -14747,8 +14649,8 @@
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&gmac1_rx_bus2
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&gmac1_rgmii_clk
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&gmac1_rgmii_bus
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&gmac1_clkinout>;
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&gmac1_clkinout
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ð1_pins>;
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tx_delay = <0x44>;
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@@ -14756,8 +14658,105 @@
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phy-handle = <&rgmii_phy1>;
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status = "okay";
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};
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# 21 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 93 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
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# 19 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg-pcie.dtsi" 1
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/ {
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vcc3v3_pcie30: vcc3v3-pcie30 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie30";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpios = <&gpio3 19 0>;
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startup-delay-us = <5000>;
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vin-supply = <&vcc12v_dcin>;
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};
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};
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&combphy0_ps {
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status = "okay";
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};
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&combphy1_ps {
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status = "okay";
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};
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&combphy2_psu {
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status = "okay";
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};
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&pcie2x1l0 {
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phys = <&combphy1_ps 2>;
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reset-gpios = <&gpio4 5 0>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "disabled";
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};
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&pcie2x1l1 {
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phys = <&combphy2_psu 2>;
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reset-gpios = <&gpio4 2 0>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "disabled";
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};
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&pcie2x1l2 {
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reset-gpios = <&gpio4 17 0>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "disabled";
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};
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&pcie30phy {
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rockchip,pcie30-phymode = <0>;
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status = "okay";
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};
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&pcie3x2 {
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reset-gpios = <&gpio4 8 0>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "okay";
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};
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&pcie3x4 {
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num-lanes = <2>;
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reset-gpios = <&gpio4 14 0>;
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vpcie3v3-supply = <&vcc3v3_pcie30>;
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status = "okay";
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};
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# 22 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
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# 68 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
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# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi" 1
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&hdmi1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>;
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};
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&hdmi1_in_vp1 {
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status = "okay";
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};
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&hdmi1_sound {
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status = "okay";
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};
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&i2s6_8ch {
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status = "okay";
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};
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&hdptxphy_hdmi1 {
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status = "okay";
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};
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&route_hdmi1 {
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status = "okay";
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connect = <&vp1_out_hdmi1>;
|
||||
};
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# 69 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
|
||||
# 94 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
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/ {
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model = "dr4-rk3588";
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||||
@@ -14793,20 +14792,20 @@
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status = "okay";
|
||||
compatible = "rp_power";
|
||||
rp_not_deep_sleep = <1>;
|
||||
# 145 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
# 146 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
|
||||
usb-host-power {
|
||||
gpio_num = <&gpio2 17 0>;
|
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gpio_function = <4>;
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
usb-hub-reset {
|
||||
gpio_num = <&gpio3 10 0>;
|
||||
gpio_function = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
rp_gpio{
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
compatible = "rp_gpio";
|
||||
|
||||
gpio3c7 {
|
||||
@@ -14816,99 +14815,77 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&uart0 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0m0_xfer>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m1_xfer>;
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m2_xfer>;
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart9m2_xfer>;
|
||||
};
|
||||
|
||||
&can0 {
|
||||
assigned-clocks = <&cru 112>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0m0_pins>;
|
||||
};
|
||||
|
||||
&can1 {
|
||||
assigned-clocks = <&cru 114>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
assigned-clocks = <&cru 114>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
|
||||
|
||||
spi3_dev@0 {
|
||||
compatible = "rockchip,spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>;
|
||||
spi-lsb-first;
|
||||
};
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
};
|
||||
|
||||
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
@@ -14929,8 +14906,9 @@
|
||||
|
||||
};
|
||||
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fiq_debugger {
|
||||
@@ -14938,58 +14916,14 @@
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi_clk0 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi_clk1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pwm14 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm14m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm15 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm15m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm11 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm11m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm13 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm13m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1m2_xfer>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2m3_xfer>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
Binary file not shown.
@@ -2,7 +2,7 @@
|
||||
//#include "../rk3588-evb4-lp4-v10-linux.dts"
|
||||
#include "rp-rk3588-board.dtsi"
|
||||
|
||||
// #include "rp-tp-i2c6-gt911.dtsi"
|
||||
#include "rp-tp-i2c6-gt911.dtsi"
|
||||
// #include "rd-rk3588-lcd-gpio.dtsi"
|
||||
|
||||
#include "rpdzkj_config.dtsi"
|
||||
@@ -10,15 +10,16 @@
|
||||
/* usb */
|
||||
// #include "rp-usb-typec-rk3588.dtsi"
|
||||
// #include "rp-usb-host.dtsi"
|
||||
|
||||
/* mipi */
|
||||
#include "zkzg_mipi.dtsi"
|
||||
#include "zkzg-usb-host.dtsi"
|
||||
|
||||
/* ethernet */
|
||||
// #include "rp-eth-pcie2gmac-rk3588.dtsi"
|
||||
#include "rp-eth-gmac0.dtsi"
|
||||
#include "rp-eth-gmac1.dtsi"
|
||||
|
||||
/* pcie */
|
||||
#include "zkzg-pcie.dtsi"
|
||||
|
||||
/* pcie */
|
||||
// #include "rp-pcie-power-rk3588.dtsi"
|
||||
// #include "rp-pcie3.dtsi" //need comment when use board of make it youself,and remove the pcie function
|
||||
@@ -64,7 +65,7 @@
|
||||
/******************************************/
|
||||
|
||||
// #include "rp-lcd-hdmi0.dtsi" //batch ignore
|
||||
// #include "rp-lcd-hdmi1.dtsi" //batch ignore
|
||||
#include "rp-lcd-hdmi1.dtsi" //batch ignore
|
||||
//#include "rp-lcd-typec-dp0.dtsi" //usb edp0, must be enable rp-usb-typec.dtsi, batch ignore
|
||||
// #include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi"
|
||||
|
||||
@@ -147,14 +148,14 @@
|
||||
gpio_function = <4>;
|
||||
};
|
||||
|
||||
// usb-hub-reset {
|
||||
// gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
// gpio_function = <4>;
|
||||
// };
|
||||
usb-hub-reset {
|
||||
gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>;
|
||||
gpio_function = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
rp_gpio{
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
compatible = "rp_gpio";
|
||||
|
||||
gpio3c7 {
|
||||
@@ -164,99 +165,77 @@
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
&uart0 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0m0_xfer>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1m1_xfer>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m0_xfer>;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m1_xfer>;
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
};
|
||||
|
||||
&uart6 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m2_xfer>;
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
fifo-depth =<4096>;
|
||||
rx-fifo-depth =<2048>;
|
||||
tx-fifo-depth =<2048>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
};
|
||||
|
||||
&uart9 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart9m2_xfer>;
|
||||
};
|
||||
|
||||
&can0 {
|
||||
assigned-clocks = <&cru CLK_CAN0>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0m0_pins>;
|
||||
};
|
||||
|
||||
&can1 {
|
||||
assigned-clocks = <&cru CLK_CAN1>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
};
|
||||
|
||||
&spi3 {
|
||||
assigned-clocks = <&cru CLK_CAN1>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
status = "disabled";
|
||||
pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
|
||||
|
||||
spi3_dev@0 {
|
||||
compatible = "rockchip,spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>;
|
||||
spi-lsb-first;
|
||||
};
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
};
|
||||
|
||||
|
||||
&i2c4 {
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
@@ -277,8 +256,9 @@
|
||||
|
||||
};
|
||||
|
||||
|
||||
&sdmmc {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fiq_debugger {
|
||||
@@ -286,58 +266,14 @@
|
||||
};
|
||||
|
||||
&display_subsystem {
|
||||
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
|
||||
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi_clk0 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&hdptxphy_hdmi_clk1 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwm14 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm14m1_pins>; // 选择 PWM1 的引脚复用
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm15 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm15m1_pins>; // 选择 PWM1 的引脚复用
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm11 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm11m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&pwm13 {
|
||||
status = "okay";
|
||||
compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
|
||||
pinctrl-names = "active";
|
||||
pinctrl-0 = <&pwm13m1_pins>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay"; // 启用 I2C1 总线
|
||||
pinctrl-names = "default"; // 引脚控制状态名称
|
||||
pinctrl-0 = <&i2c1m2_xfer>; // 使用 i2c1m2_xfer 引脚配置
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
status = "okay"; // 启用 I2C2 总线
|
||||
pinctrl-names = "default"; // 引脚控制状态名称
|
||||
pinctrl-0 = <&i2c2m3_xfer>; // 使用 i2c2m3_xfer 引脚配置
|
||||
};
|
||||
@@ -11,7 +11,7 @@
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "input";
|
||||
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
// Reset time is 20ms, 100ms for rtl8211f
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
phy-mode = "rgmii-rxid";
|
||||
clock_in_out = "input";
|
||||
|
||||
snps,reset-gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
// Reset time is 20ms, 100ms for rtl8211f
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
@@ -23,8 +23,8 @@
|
||||
&gmac1_rx_bus2
|
||||
&gmac1_rgmii_clk
|
||||
&gmac1_rgmii_bus
|
||||
&gmac1_clkinout>;
|
||||
// ð1_pins>;
|
||||
&gmac1_clkinout
|
||||
ð1_pins>;
|
||||
|
||||
tx_delay = <0x44>;
|
||||
// rx_delay = <0x4f>;
|
||||
|
||||
@@ -39,27 +39,10 @@
|
||||
|
||||
|
||||
&usbhost3_0 {
|
||||
status = "okay";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&usbhost_dwc3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
extcon=<&u2phy0>;
|
||||
status="okay";
|
||||
};
|
||||
|
||||
&u2phy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbdrd_dwc3_1 {
|
||||
extcon=<&u2phy1>;
|
||||
status="okay";
|
||||
};
|
||||
|
||||
&u2phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -11,6 +11,20 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&typec5v_pwren>;
|
||||
};
|
||||
|
||||
vcc5v0_host: vcc5v0-host {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc5v0_host";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
vin-supply = <&vcc5v0_usb>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&vcc5v0_host_en>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@@ -111,7 +125,7 @@
|
||||
|
||||
|
||||
&usbdrd_dwc3_0 {
|
||||
dr_mode = "otg";
|
||||
dr_mode = "host";
|
||||
usb-role-switch;
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
@@ -123,6 +137,24 @@
|
||||
};
|
||||
};
|
||||
|
||||
&u2phy1_otg {
|
||||
phy-supply = <&vcc5v0_host>;
|
||||
};
|
||||
|
||||
// 使能USB3.1/SATA/PCIe Combo PHY
|
||||
&combphy2_psu {
|
||||
status = "okay";
|
||||
};
|
||||
// 配置USB3.1 HOST2 Controller
|
||||
&usbhost3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbhost_dwc3_0 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
usb-typec {
|
||||
usbc0_int: usbc0-int {
|
||||
@@ -134,4 +166,9 @@
|
||||
};
|
||||
|
||||
};
|
||||
usb {
|
||||
vcc5v0_host_en: vcc5v0-host-en {
|
||||
rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1,133 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
&mipi_dcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&csi2_dcphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipidcphy0_in_ucam0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mvcam_out4>;
|
||||
// 修改为 4 lane
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidcphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m0_xfer>;
|
||||
|
||||
mvcam_4: mvcam@3b{
|
||||
status = "okay";
|
||||
compatible = "veye,mvcam";
|
||||
reg = <0x3b>;
|
||||
// 电源控制引脚
|
||||
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
// 新增复位引脚
|
||||
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "NC";
|
||||
rockchip,camera-module-lens-name = "NC";
|
||||
port {
|
||||
mvcam_out4: endpoint {
|
||||
remote-endpoint = <&mipidcphy0_in_ucam0>;
|
||||
// 修改为 4 lane
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_input: endpoint@1 {
|
||||
reg = <1>;
|
||||
remote-endpoint = <&csidcphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
mipi_lvds_sditf: endpoint {
|
||||
remote-endpoint = <&isp1_in1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkisp1_vir0 {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
isp1_in1: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi_lvds_sditf>;
|
||||
};
|
||||
};
|
||||
};
|
||||
62
rk3588/zkzg-pcie.dtsi
Executable file
62
rk3588/zkzg-pcie.dtsi
Executable file
@@ -0,0 +1,62 @@
|
||||
/ {
|
||||
vcc3v3_pcie30: vcc3v3-pcie30 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc3v3_pcie30";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
|
||||
startup-delay-us = <5000>;
|
||||
vin-supply = <&vcc12v_dcin>;
|
||||
};
|
||||
};
|
||||
|
||||
&combphy0_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy1_ps {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&combphy2_psu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2x1l0 {
|
||||
phys = <&combphy1_ps PHY_TYPE_PCIE>;
|
||||
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie2x1l1 {
|
||||
phys = <&combphy2_psu PHY_TYPE_PCIE>;
|
||||
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie2x1l2 {
|
||||
reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&pcie30phy {
|
||||
rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x4 {
|
||||
num-lanes = <2>;
|
||||
reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
|
||||
vpcie3v3-supply = <&vcc3v3_pcie30>;
|
||||
status = "okay";
|
||||
};
|
||||
24
rk3588/zkzg-usb-host.dtsi
Executable file
24
rk3588/zkzg-usb-host.dtsi
Executable file
@@ -0,0 +1,24 @@
|
||||
&u2phy2_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&u2phy3_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
// USB2.0 HOST0/1 Controller
|
||||
&usb_host0_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host0_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ehci {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host1_ohci {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,129 +0,0 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
|
||||
*
|
||||
*/
|
||||
|
||||
&csi2_dcphy0 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipidcphy0_in_ucam0: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mvcam_out4>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
csidcphy0_out: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&mipi0_csi2_input>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c7 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c7m0_xfer>;
|
||||
|
||||
mvcam_4: mvcam@3b{
|
||||
status = "okay";
|
||||
compatible = "veye,mvcam";
|
||||
reg = <0x3b>;
|
||||
clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
|
||||
clock-names = "xvclk";
|
||||
power-domains = <&power RK3588_PD_VI>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mipim0_camera2_clk>;
|
||||
rockchip,grf = <&sys_grf>;
|
||||
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
||||
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
|
||||
rockchip,camera-module-index = <0>;
|
||||
rockchip,camera-module-facing = "back";
|
||||
rockchip,camera-module-name = "NC";
|
||||
rockchip,camera-module-lens-name = "NC";
|
||||
port {
|
||||
mvcam_out4: endpoint {
|
||||
remote-endpoint = <&mipidcphy0_in_ucam0>;
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mipi_dcphy0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi0_csi2 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
// 修正这里：endpoint@0 和 reg = <0>
|
||||
mipi0_csi2_input: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&csidcphy0_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mipi0_csi2_output: endpoint@0 {
|
||||
reg = <0>;
|
||||
remote-endpoint = <&cif_mipi_in0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rkcif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkcif_mmu {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&rkcif_mipi_lvds {
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
cif_mipi_in0: endpoint {
|
||||
remote-endpoint = <&mipi0_csi2_output>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
// 以下ISP相关配置可以保持disabled，先确保基础链路通
|
||||
&rkcif_mipi_lvds_sditf {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&rkisp1_vir0 {
|
||||
status = "disabled";
|
||||
};
|
||||
Reference in New Issue
Block a user