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base: zhangpeng:十四五航弹院
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zhangpeng:master zhangpeng:智能控制模块_56mm zhangpeng:SOH_AI zhangpeng:十四五航弹院 zhangpeng:SOH_DI zhangpeng:SOH_UART zhangpeng:SOH_3588 zhangpeng:耐辐照相机 zhangpeng:02哈工大项目 zhangpeng:03尺蠖机器人 zhangpeng:01智能控制模块 zhangpeng:04PAL
..
compare: zhangpeng:37cc8084febd20a74e4f2a849a765a0fa596dae1
Branches Tags
zhangpeng:智能控制模块_56mm zhangpeng:SOH_AI zhangpeng:十四五航弹院 zhangpeng:SOH_DI zhangpeng:SOH_UART zhangpeng:SOH_3588 zhangpeng:耐辐照相机 zhangpeng:02哈工大项目 zhangpeng:03尺蠖机器人 zhangpeng:master zhangpeng:01智能控制模块 zhangpeng:04PAL

2 Commits
十四五航弹院 ... 37cc8084fe

Author SHA1 Message Date
zhangpeng
37cc8084fe 配置UART、CAN和网络 2025-10-09 13:45:08 +08:00
zhangpeng
85a0f6e6ea 增加CPU频率区间 2025-09-18 10:43:09 +08:00
8 changed files with 140 additions and 96 deletions
Expand all files Collapse all files

19
rk3568.dtsi
View File

@@ -227,6 +227,25 @@
};
/* RK3568J cpu OPPs */
opp-j-408000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-j-600000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-j-816000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-j-1008000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <1008000000>;

2
rk356x/.dr4-rk3568.dtb.cmd
View File

@@ -27,8 +27,8 @@ deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb := \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb)

4
rk356x/.dr4-rk3568.dtb.d.pre.tmp
View File

@@ -23,5 +23,5 @@ dr4-rk3568.o: arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi
arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi

144
rk356x/.dr4-rk3568.dtb.dts.tmp
View File

@@ -1,6 +1,6 @@
# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -682,6 +682,25 @@
};
opp-j-408000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <408000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-j-600000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
};
opp-j-816000000 {
opp-supported-hw = <0xfb 0xffff>;
opp-hz = /bits/ 64 <816000000>;
opp-microvolt = <850000 850000 1150000>;
clock-latency-ns = <40000>;
opp-suspend;
};
opp-j-1008000000 {
opp-supported-hw = <0x04 0xffff>;
opp-hz = /bits/ 64 <1008000000>;
@@ -4166,7 +4185,7 @@
rockchip,grf = <&grf>;
status = "disabled";
};
# 3726 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
# 3745 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
csi2_dphy0: csi2-dphy0 {
compatible = "rockchip,rk3568-csi2-dphy";
rockchip,hw = <&csi2_dphy_hw>;
@@ -7849,7 +7868,7 @@
};
};
};
# 3873 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
/ {
@@ -8817,85 +8836,72 @@ dsi1_panel: panel@0 {
disable-win-move;
};
# 13 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 24 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi" 1
# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
&gmac1 {
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 3 1>;
snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru 393>, <&cru 390>, <&cru 198>;
assigned-clock-parents = <&cru 391>,<&gmac1_clkin>, <&cru 197>;
assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac1m1_miim
&gmac1m1_tx_bus2
&gmac1m1_rx_bus2
&gmac1m1_rgmii_clk
&gmac1m1_rgmii_bus
&eth1m0_pins
&gmac1m1_clkinout>;
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x3a>;
rx_delay = <0x29>;
phy-handle = <&rgmii_phy1>;
tx_delay = <0x2d>;
rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&mdio1 {
rgmii_phy1: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru 198>;
};
};
# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 4 1>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru 389>, <&cru 386>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
&mdio0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru 183>;
};
};
# 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 78 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi" 1
&can0 {
compatible = "rockchip,rk3568-can-2.0";
assigned-clocks = <&cru 321>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can0m1_pins>;
status = "okay";
};
&can1 {
compatible = "rockchip,rk3568-can-2.0";
assigned-clocks = <&cru 323>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can1m1_pins>;
status = "okay";
};
# 33 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 79 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
/{
model = "dr4-rk3568";
compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568";
@@ -8916,7 +8922,7 @@ dsi1_panel: panel@0 {
pinctrl-name = "default";
pinctrl-0 = <&rp_power>;
# 121 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 122 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
otg_mode {
gpio_num = <&gpio1 4 1>;
gpio_function = <0>;
@@ -8925,13 +8931,13 @@ dsi1_panel: panel@0 {
gpio_num = <&gpio0 5 0>;
gpio_function = <4>;
};
# 169 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 170 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
};
rp_gpio{
status = "disabled";
compatible = "rp_gpio";
# 182 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 183 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
gpio0a0 {
gpio_num = <&gpio0 0 1>;
gpio_function = <0>;
@@ -9061,13 +9067,13 @@ dsi1_panel: panel@0 {
};
&uart7 {
status = "okay";
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>;
};
&uart8 {
status = "okay";
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer>;
};
@@ -9108,7 +9114,7 @@ dsi1_panel: panel@0 {
status = "disabled";
};
# 417 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 418 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&rk_headset {
pinctrl-0 = <&hp_det>;
headset_gpio = <&gpio2 27 0>;
@@ -9157,7 +9163,7 @@ dsi1_panel: panel@0 {
BT,wake_host_irq = <&gpio0 28 0>;
status = "disabled";
};
# 515 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 516 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&pinctrl {
rp_pins {
rp_power: rp-power {
@@ -9197,7 +9203,7 @@ dsi1_panel: panel@0 {
<3 2 0 &pcfg_pull_none>;
};
};
# 569 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 570 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
};

BIN
rk356x/dr4-rk3568.dtb
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Binary file not shown.

7
rk356x/dr4-rk3568.dts
View File

@@ -21,7 +21,7 @@
/***************************************************/
/*************************gmac***********************/
#include "rp-gmac1-m1-pro-rk3568.dtsi"
// #include "rp-gmac1-m1-pro-rk3568.dtsi"
#include "rp-gmac0-pro-rk3568.dtsi"
/***************************************************/
@@ -29,6 +29,7 @@
// #include "rp-can0-m0-rk3568.dtsi"
// #include "rp-can1-m1-rk3568.dtsi"
// #include "rp-can2-m0-rk3568.dtsi"
#include "zkzg-can-rk3568.dtsi"
/**************************************************/
/*********************PCIE**************************/
@@ -308,13 +309,13 @@
};
&uart7 {
status = "okay";
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>;
};
&uart8 {
status = "okay";
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&uart8m0_xfer>;
};

43
rk356x/rp-gmac0-pro-rk3568.dtsi
View File

@@ -1,30 +1,30 @@
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
phy-mode = "rgmii";
clock_in_out = "input";
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>;
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
tx_delay = <0x2d>;
rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
@@ -32,5 +32,6 @@
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru CLK_MAC0_OUT>;
};
};

17
rk356x/zkzg-can-rk3568.dtsi Normal file
View File

@@ -0,0 +1,17 @@
&can0 {
compatible = "rockchip,rk3568-can-2.0";
assigned-clocks = <&cru CLK_CAN0>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can0m1_pins>;
status = "okay";
};
&can1 {
compatible = "rockchip,rk3568-can-2.0";
assigned-clocks = <&cru CLK_CAN1>;
assigned-clock-rates = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&can1m1_pins>;
status = "okay";
};