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配置GMAC

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zhangpeng
2025-10-24 11:27:59 +08:00
parent b934374df1
commit 9418df441d
3 changed files with 45 additions and 47 deletions
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49
rk356x/.dr4-rk3568.dtb.dts.tmp
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@@ -1,6 +1,6 @@
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -7849,7 +7849,7 @@
};
};
};
# 3872 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 3873 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
/ {
@@ -8860,31 +8860,31 @@ dsi1_panel: panel@0 {
# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
&gmac0 {
phy-mode = "rgmii";
clock_in_out = "input";
phy-mode = "rgmii";
clock_in_out = "input";
snps,reset-gpio = <&gpio3 4 1>;
snps,reset-active-low;
snps,reset-gpio = <&gpio3 4 1>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru 389>, <&cru 386>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>;
assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x2d>;
rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
status = "okay";
tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay";
};
@@ -8892,7 +8892,6 @@ dsi1_panel: panel@0 {
rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
clocks = <&cru 183>;
};
};
# 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2