diff --git a/rk356x/.dr4-rk3568.dtb.dts.tmp b/rk356x/.dr4-rk3568.dtb.dts.tmp index 2efe49c..77d0378 100644 --- a/rk356x/.dr4-rk3568.dtb.dts.tmp +++ b/rk356x/.dr4-rk3568.dtb.dts.tmp @@ -1,6 +1,6 @@ -# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" -# 1 "" -# 1 "" +# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" +# 0 "" +# 0 "" # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" @@ -7849,7 +7849,7 @@ }; }; }; -# 3872 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2 +# 3873 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2 / { @@ -8860,31 +8860,31 @@ dsi1_panel: panel@0 { # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1 &gmac0 { - phy-mode = "rgmii"; - clock_in_out = "input"; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 4 1>; + snps,reset-active-low; - snps,reset-gpio = <&gpio3 4 1>; - snps,reset-active-low; + snps,reset-delays-us = <0 20000 100000>; - snps,reset-delays-us = <0 20000 100000>; + assigned-clocks = <&cru 389>, <&cru 386>; + assigned-clock-parents = <&cru 387>, <&gmac0_clkin>; + assigned-clock-rates = <0>, <125000000>; - assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>; - assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>; - assigned-clock-rates = <0>, <125000000>, <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk_level2 + &gmac0_rgmii_bus + &gmac0_clkinout>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - ð0_pins - &gmac0_clkinout>; - tx_delay = <0x2d>; - rx_delay = <0x2c>; - phy-handle = <&rgmii_phy0>; - status = "okay"; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; }; @@ -8892,7 +8892,6 @@ dsi1_panel: panel@0 { rgmii_phy0: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; - clocks = <&cru 183>; }; }; # 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 diff --git a/rk356x/dr4-rk3568.dtb b/rk356x/dr4-rk3568.dtb index dad9856..ee9eac9 100644 Binary files a/rk356x/dr4-rk3568.dtb and b/rk356x/dr4-rk3568.dtb differ diff --git a/rk356x/rp-gmac0-pro-rk3568.dtsi b/rk356x/rp-gmac0-pro-rk3568.dtsi index a26a910..7c911d4 100755 --- a/rk356x/rp-gmac0-pro-rk3568.dtsi +++ b/rk356x/rp-gmac0-pro-rk3568.dtsi @@ -1,30 +1,30 @@ &gmac0 { - phy-mode = "rgmii"; - clock_in_out = "input"; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; - snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; + assigned-clock-rates = <0>, <125000000>; - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>; - assigned-clock-rates = <0>, <125000000>, <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk_level2 + &gmac0_rgmii_bus + &gmac0_clkinout>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus - ð0_pins - &gmac0_clkinout>; - tx_delay = <0x2d>; - rx_delay = <0x2c>; - phy-handle = <&rgmii_phy0>; - status = "okay"; + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; }; @@ -32,6 +32,5 @@ rgmii_phy0: phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; - clocks = <&cru CLK_MAC0_OUT>; }; }; \ No newline at end of file