rockchip
This commit is contained in:
zhangpeng
212
rk3588/rp-lcd-mipi0-8-1200-1920.dtsi
Executable file
212
rk3588/rp-lcd-mipi0-8-1200-1920.dtsi
Executable file
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&backlight_mipi {
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compatible = "pwm-backlight";
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//pwms = <&pwm1 0 25000 0>;
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status = "okay";
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brightness-levels = <
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0 20 20 21 21 22 22 23
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23 24 24 25 25 26 26 27
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27 28 28 29 29 30 30 31
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31 32 32 33 33 34 34 35
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35 36 36 37 37 38 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255
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>;
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default-brightness-level = <200>;
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};
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&vcc3v3_lcd_n {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_lcd0_n";
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regulator-boot-on;
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enable-active-high;
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//gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
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vin-supply = <&vcc_1v8_s3>;
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};
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&pwm1 {
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status = "okay";
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pinctrl-0 = <&pwm1m1_pins>;
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};
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&dsi0 {
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status = "okay";
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//rockchip,lane-rate = <480000>;
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dsi0_panel: panel@0 {
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status = "okay";
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compatible = "simple-panel-dsi";
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reg = <0>;
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power-supply = <&vcc3v3_lcd_n>;
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//reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>;
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//pinctrl-names = "default";
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//pinctrl-0 = <&lcd_rst_gpio>;
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backlight = <&backlight_mipi>;
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init-delay-ms = <60>;
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reset-delay-ms = <60>;
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enable-delay-ms = <60>;
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prepare-delay-ms = <60>;
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unprepare-delay-ms = <60>;
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disable-delay-ms = <60>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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dsi,lanes = <4>;
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panel-init-sequence = [
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05 78 01 11 //sleep out
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05 20 01 29 //display on
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];
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panel-exit-sequence = [
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05 78 01 28
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05 78 01 10
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];
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disp_timings0: display-timings {
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native-mode = <&dsi0_timing0>;
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dsi0_timing0: timing0 {
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clock-frequency = <148000000>;
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hactive = <1200>;
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vactive = <1920>;
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hback-porch = <60>;
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hfront-porch = <80>;
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vback-porch = <25>;
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vfront-porch = <16>;
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hsync-len = <10>;
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vsync-len = <2>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_panel>;
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi_out_panel: endpoint {
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remote-endpoint = <&panel_in_dsi>;
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};
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};
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};
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};
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&dsi0_in_vp2 {
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status = "disabled";
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};
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&dsi0_in_vp3 {
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status = "okay";
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};
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&mipi_dcphy0 {
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status = "okay";
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};
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&route_dsi0 {
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status = "okay";
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connect = <&vp3_out_dsi0>;
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};
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&goodix_ts {
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gtp_resolution_x = <1200>;
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gtp_resolution_y = <1920>;
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gtp_int_tarigger = <1>;
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gtp_change_x2y = <0>;
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gtp_overturn_x = <0>;
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gtp_overturn_y = <0>;
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gtp_send_cfg = <1>;
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gtp_touch_back = <1>;
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gtp_touch_wakeup = <1>;
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goodix,cfg-group0 = [
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5E B0 04 80 07 05 05 00 01 0F 28 05
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50 32 03 05 00 00 00 00 00 00 00 00
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00 00 00 8C 2C 0E 52 54 31 0D 00 00
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01 80 04 1C 00 00 00 00 00 03 64 32
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00 00 00 52 66 94 C5 02 07 00 00 04
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83 53 00 82 57 00 80 5B 00 7F 5F 00
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7E 63 00 7E 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 1C 1A 18 16 14 12 10 0E
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0C 0A 08 06 04 02 FF FF FF FF FF FF
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FF FF FF FF FF FF FF FF FF FF 00 02
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04 06 08 0A 0C 0F 10 12 13 14 28 26
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24 22 21 20 1F 1E 1D 1C 18 16 FF FF
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FF FF FF FF FF FF FF FF FF FF FF FF
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FF FF FF FF 22 01
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];
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goodix,cfg-group2 = [
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00 20 03 00 05 0A 05 00 01 08 28
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05 50 32 03 05 00 00 00 00 00 00
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00 00 00 00 00 8C 2C 0E 17 15 31
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0D 00 00 01 BA 03 1D 00 00 00 00
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00 03 64 32 00 00 00 0F 41 94 C5
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02 07 00 00 04 99 11 00 77 17 00
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5F 1F 00 4C 2A 00 41 38 00 41 00
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00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00
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00 00 1C 1A 18 16 14 12 10 0E 0C
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0A 08 06 04 02 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 28
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26 24 22 21 20 1F 1E 1D 1C 18 16
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00 02 04 06 08 0A 0C 0F 10 12 13
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14 FF FF 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 FE 01
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];
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};
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