commit 5dd7a8972b7199a2b74a5e296040896c6569d1c6 Author: zhangpeng Date: Mon Apr 28 11:36:59 2025 +0800 rockchip diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..5163c44 --- /dev/null +++ b/Makefile @@ -0,0 +1,271 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-avb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-mini-evb-ddr3-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-mini-evb-ddr3-v11-avb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr3-v11-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-amic-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-amic-v13.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-amic-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-audio-v10-display-rgb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-dmic-pdm-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb-dmic-pdm-v13.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308b-evb-amic-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308b-evb-amic-v10-amp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-amic-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-ddr3-v20-rk618-rgb2dsi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-dmic-pdm-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-mcu-display-v20.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-mipi-display-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308bs-evb-rgb-display-v20.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-avb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v11-avb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-evb-lp3-v12-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10-avb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-863-lp3-v10-rkisp1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358-evb-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3358m-vehicle-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-firefly.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-bob.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-kevin.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-inx.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-gru-scarlet-kd.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-hugsun-x99.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-captain.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-khadas-edge-v.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-leez-p710.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopc-t4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-m4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-nanopi-neo4.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-orangepi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-pinebook-pro.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-puma-haikou.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-roc-pc-mezzanine.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock-pi-4c.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rock960.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64-v2.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-rockpro64.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator-edp-avb.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo1-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo4-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-demo6-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb1-ddr4-v10-spi-nand-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb2-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb3-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-evb4-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3528-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-dictpen-test3-v20.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-linux-amp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-mcu-k350c4516t.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb2lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-rgb-k350c4516t.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb1-lp4x-v10-spdif.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-dual-camera.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-image-reverse.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-linux-amp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-pdm-mic-array.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-iotest-lp3-v10-dsm.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-rk817-tablet-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test1-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562-test2-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3562j-core-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb-mipitest-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb1-ddr4-v10-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-edp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-eink.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-i2s-mic-array.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb2-lp4x-v10-pdm-mic-array.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb3-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-evb5-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w6.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-eink-w103.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-k108.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-rkg11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-rk817-tablet-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-dual-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-dual-camera.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-amp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-linux-spi-nor.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb4-lp3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb5-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb7-ddr4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb8-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-iotest-ddr3-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v10-linux-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nvr-demo-v12-linux-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-pcie-ep-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-sd0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-toybrick-x0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-csi-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-camera-dvp-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-ipc-6x-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-amp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-linux-ipc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-lt6911uxe.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-lt6911uxc-dual-mipi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-lp4-v10-rk628-hdmi2csi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-edp2dp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb2-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb3-lp5-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb3-lp5-v10-edp.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb3-lp5-v10-edp-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb3-lp5-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb4-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb4-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb5-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb5-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb6-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb6-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-lp4-v11-linux-ipc.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb7-v11-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-ipc-4x-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo-v10-spi-nand.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo1-v21.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo1-v21-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo3-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nvr-demo3-v10-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-pcie-ep-demo-v11.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-pcie-ep-demo-v11-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-android.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v20.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v21.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-evb-v22.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-vehicle-s66-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb1-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb2-lp5-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb2-lp5-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb4-lp4x-v10-linux.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-evb8-lp4x-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-rk806-single-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-tablet-v11.dtb diff --git a/px30-ad-d6-anx6345.dts b/px30-ad-d6-anx6345.dts new file mode 100644 index 0000000..99d8bf5 --- /dev/null +++ b/px30-ad-d6-anx6345.dts @@ -0,0 +1,759 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "px30.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip PX30 AD D6 board"; + compatible = "rockchip,px30-ad-d6", "rockchip,px30"; + + dvdd12_anx: dvdd12-anx { + compatible = "regulator-fixed"; + regulator-name = "dvdd12-anx"; + regulator-boot-on; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + enable-active-high; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + auto-freq-en = <0>; + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_soc"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc1v0_soc"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v0_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd1v5_dvp"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,sleep-debug-en = <1>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc1v8_soc>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + anx6345@38 { + compatible = "analogix,anx6345"; + reg = <0x38>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + panel-supply = <&vcc3v3_lcd>; + dvdd25-supply = <&vcc3v3_lcd>; + dvdd12-supply = <&dvdd12_anx>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + anx6345_in_rgb: endpoint { + remote-endpoint = <&rgb_out_anx6345>; + }; + }; + }; + }; +}; + +&rgb { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_rgb_pins>; + pinctrl-1 = <&lcdc_sleep_pins>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_anx6345: endpoint { + remote-endpoint = <&anx6345_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "okay"; +}; + +&rgb_in_vopl { + status = "disabled"; +}; + +&route_rgb { + connect = <&vopb_out_rgb>; + status = "okay"; +}; + +&pinctrl { + lcdc { + lcdc_rgb_pins: lcdc-rgb-pins { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ + <3 RK_PA1 1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ + <3 RK_PA2 1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ + <3 RK_PA3 1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ + <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* LCDC_D23 */ + <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ + <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ + <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ + <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ + <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ + <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ + <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ + <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ + <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ + <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ + <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ + <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ + <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ + <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ + <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ + <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ + <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ + <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ + <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ + <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ + <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ + <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ + <3 RK_PA4 1 &pcfg_pull_none_8ma>; /* LCDC_D0 */ + }; + + lcdc_sleep_pins: lcdc-sleep-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D0 */ + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + + fstab { + compatible = "android,fstab"; + + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30-ad-r35-mb-rk618-dual-lvds.dts b/px30-ad-r35-mb-rk618-dual-lvds.dts new file mode 100644 index 0000000..09fc265 --- /dev/null +++ b/px30-ad-r35-mb-rk618-dual-lvds.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "px30-ad-r35-mb.dtsi" + +/ { + panel { + compatible = "lg,lm215wf3", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + bus-format = ; + width-mm = <476>; + height-mm = <268>; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <144000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <64>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&dmc { + auto-freq-en = <0>; +}; + +&i2c0 { + status = "okay"; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S1_OUT>; + assigned-clock-rates = <11289600>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S1_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S1_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + lvds { + compatible = "rockchip,rk618-lvds"; + clocks = <&clock LVDS_CLK>; + clock-names = "lvds"; + dual-channel; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_rgb: endpoint { + remote-endpoint = <&rgb_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_lvds: endpoint { + remote-endpoint = <&lvds_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "disabled"; +}; + +&rgb_in_vopl { + status = "okay"; +}; + +&route_rgb { + connect = <&vopl_out_rgb>; + status = "okay"; +}; diff --git a/px30-ad-r35-mb-rk618-hdmi-lvds.dts b/px30-ad-r35-mb-rk618-hdmi-lvds.dts new file mode 100644 index 0000000..d4f2021 --- /dev/null +++ b/px30-ad-r35-mb-rk618-hdmi-lvds.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "px30-ad-r35-mb.dtsi" + +/ { + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + bus-format = ; + width-mm = <231>; + height-mm = <154>; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <40>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&dmc { + auto-freq-en = <0>; +}; + +&i2c0 { + status = "okay"; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S1_OUT>; + assigned-clock-rates = <11289600>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S1_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S1_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + hdmi { + compatible = "rockchip,rk618-hdmi"; + clocks = <&clock HDMI_CLK>; + clock-names = "hdmi"; + assigned-clocks = <&clock HDMI_CLK>; + assigned-clock-parents = <&clock VIF0_CLK>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_vif: endpoint { + remote-endpoint = <&vif_out_hdmi>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_out_scaler: endpoint { + remote-endpoint = <&scaler_in_hdmi>; + }; + }; + }; + }; + + lvds { + compatible = "rockchip,rk618-lvds"; + clocks = <&clock LVDS_CLK>; + clock-names = "lvds"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_scaler: endpoint { + remote-endpoint = <&scaler_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + + scaler { + compatible = "rockchip,rk618-scaler"; + clocks = <&clock SCALER_CLK>, <&clock VIF0_CLK>, + <&clock DITHER_CLK>; + clock-names = "scaler", "vif", "dither"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + scaler_in_hdmi: endpoint { + remote-endpoint = <&hdmi_out_scaler>; + }; + }; + + port@1 { + reg = <1>; + + scaler_out_lvds: endpoint { + remote-endpoint = <&lvds_in_scaler>; + }; + }; + }; + }; + + vif { + compatible = "rockchip,rk618-vif"; + clocks = <&clock VIF0_CLK>, <&clock VIF0_PRE_CLK>; + clock-names = "vif", "vif_pre"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vif_in_rgb: endpoint { + remote-endpoint = <&rgb_out_vif>; + }; + }; + + port@1 { + reg = <1>; + + vif_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_vif>; + }; + }; + }; + }; + }; +}; + +&vopl { + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1188000000>; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_vif: endpoint { + remote-endpoint = <&vif_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "disabled"; +}; + +&rgb_in_vopl { + status = "okay"; +}; + +&route_rgb { + connect = <&vopl_out_rgb>; + status = "okay"; +}; diff --git a/px30-ad-r35-mb-rk618-hdmi.dts b/px30-ad-r35-mb-rk618-hdmi.dts new file mode 100644 index 0000000..0ea0566 --- /dev/null +++ b/px30-ad-r35-mb-rk618-hdmi.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "px30-ad-r35-mb.dtsi" + +&dmc { + auto-freq-en = <0>; +}; + +&i2c0 { + status = "okay"; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S1_OUT>; + assigned-clock-rates = <11289600>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S1_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S1_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + hdmi { + compatible = "rockchip,rk618-hdmi"; + clocks = <&clock HDMI_CLK>; + clock-names = "hdmi"; + assigned-clocks = <&clock HDMI_CLK>; + assigned-clock-parents = <&clock VIF0_CLK>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_rgb: endpoint { + remote-endpoint = <&rgb_out_hdmi>; + }; + }; + }; + }; + }; +}; + +&vopl { + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1188000000>; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "disabled"; +}; + +&rgb_in_vopl { + status = "okay"; +}; + +&route_rgb { + connect = <&vopl_out_rgb>; + status = "okay"; +}; diff --git a/px30-ad-r35-mb-rk618-lvds.dts b/px30-ad-r35-mb-rk618-lvds.dts new file mode 100644 index 0000000..8b54a9a --- /dev/null +++ b/px30-ad-r35-mb-rk618-lvds.dts @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "px30-ad-r35-mb.dtsi" + +/ { + panel { + compatible = "chunghwa,claa101wh31-cw", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + bus-format = ; + width-mm = <231>; + height-mm = <154>; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <40>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&dmc { + auto-freq-en = <0>; +}; + +&i2c0 { + status = "okay"; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S1_OUT>; + assigned-clock-rates = <12000000>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S1_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S1_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + lvds { + compatible = "rockchip,rk618-lvds"; + clocks = <&clock LVDS_CLK>; + clock-names = "lvds"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_rgb: endpoint { + remote-endpoint = <&rgb_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_lvds: endpoint { + remote-endpoint = <&lvds_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "disabled"; +}; + +&rgb_in_vopl { + status = "okay"; +}; + +&route_rgb { + connect = <&vopl_out_rgb>; + status = "okay"; +}; diff --git a/px30-ad-r35-mb.dtsi b/px30-ad-r35-mb.dtsi new file mode 100644 index 0000000..870409d --- /dev/null +++ b/px30-ad-r35-mb.dtsi @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include "px30.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip PX30 AD R35 MB board"; + compatible = "rockchip,px30-ad-r35-mb", "rockchip,px30"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1270000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <602000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <952000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <290000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x1>; + regulator-name = "vdd_logic"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x1>; + regulator-name = "vdd_arm"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x1>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x1>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_soc"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc1v0_soc"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v0_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd1v5_dvp"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc1v8_soc>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "pvo,p101nwwbp-01g", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <135>; + height-mm = <216>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 80 03 + 15 00 02 E0 04 + 15 00 02 2B 2B + 15 00 02 2D 03 + 15 00 02 2E 44 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 6D + 15 00 02 0C 74 + 15 00 02 17 00 + 15 00 02 18 A7 + 15 00 02 19 01 + 15 00 02 1A 00 + 15 00 02 1B A7 + 15 00 02 1C 01 + 15 00 02 1F 6A + 15 00 02 20 23 + 15 00 02 21 23 + 15 00 02 22 0E + 15 00 02 35 28 + 15 00 02 37 59 + 15 00 02 38 05 + 15 00 02 39 04 + 15 00 02 3A 08 + 15 00 02 3B 08 + 15 00 02 3C 7C + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F FF + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 43 08 + 15 00 02 44 0B + 15 00 02 45 88 + 15 00 02 4B 04 + 15 00 02 55 01 + 15 00 02 56 01 + 15 00 02 57 8D + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 28 + 15 00 02 5B 1E + 15 00 02 5C 16 + 15 00 02 5D 76 + 15 00 02 5E 58 + 15 00 02 5F 46 + 15 00 02 60 39 + 15 00 02 61 37 + 15 00 02 62 2A + 15 00 02 63 2F + 15 00 02 64 18 + 15 00 02 65 39 + 15 00 02 66 38 + 15 00 02 67 3A + 15 00 02 68 5A + 15 00 02 69 46 + 15 00 02 6A 4C + 15 00 02 6B 3F + 15 00 02 6C 3D + 15 00 02 6D 2F + 15 00 02 6E 1E + 15 00 02 6F 00 + 15 00 02 70 76 + 15 00 02 71 58 + 15 00 02 72 46 + 15 00 02 73 39 + 15 00 02 74 33 + 15 00 02 75 22 + 15 00 02 76 27 + 15 00 02 77 14 + 15 00 02 78 29 + 15 00 02 79 2A + 15 00 02 7A 28 + 15 00 02 7B 46 + 15 00 02 7C 38 + 15 00 02 7D 3E + 15 00 02 7E 31 + 15 00 02 7F 29 + 15 00 02 80 1B + 15 00 02 81 0A + 15 00 02 82 00 + 15 00 02 E0 02 + 15 00 02 00 44 + 15 00 02 01 44 + 15 00 02 02 45 + 15 00 02 03 45 + 15 00 02 04 46 + 15 00 02 05 46 + 15 00 02 06 47 + 15 00 02 07 47 + 15 00 02 08 1D + 15 00 02 09 1D + 15 00 02 0A 1D + 15 00 02 0B 1D + 15 00 02 0C 1D + 15 00 02 0D 1D + 15 00 02 0E 1D + 15 00 02 0F 57 + 15 00 02 10 57 + 15 00 02 11 58 + 15 00 02 12 58 + 15 00 02 13 40 + 15 00 02 14 55 + 15 00 02 15 55 + 15 00 02 16 44 + 15 00 02 17 44 + 15 00 02 18 45 + 15 00 02 19 45 + 15 00 02 1A 46 + 15 00 02 1B 46 + 15 00 02 1C 47 + 15 00 02 1D 47 + 15 00 02 1E 1D + 15 00 02 1F 1D + 15 00 02 20 1D + 15 00 02 21 1D + 15 00 02 22 1D + 15 00 02 23 1D + 15 00 02 24 1D + 15 00 02 25 57 + 15 00 02 26 57 + 15 00 02 27 58 + 15 00 02 28 58 + 15 00 02 29 40 + 15 00 02 2A 55 + 15 00 02 2B 55 + 15 00 02 58 40 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 00 + 15 00 02 5C 0A + 15 00 02 5D 10 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 00 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 0B + 15 00 02 64 6A + 15 00 02 65 00 + 15 00 02 66 00 + 15 00 02 67 31 + 15 00 02 68 0B + 15 00 02 69 1E + 15 00 02 6A 6A + 15 00 02 6B 04 + 15 00 02 6C 00 + 15 00 02 6D 04 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 F8 + 15 00 02 76 00 + 15 00 02 77 0D + 15 00 02 78 14 + 15 00 02 79 00 + 15 00 02 7A 00 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 06 + 15 80 01 11 + 15 16 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <68500000>; + hactive = <800>; + hfront-porch = <16>; + hsync-len = <16>; + hback-porch = <48>; + vactive = <1280>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + + fstab { + compatible = "android,fstab"; + + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30-android.dtsi b/px30-android.dtsi new file mode 100644 index 0000000..017a170 --- /dev/null +++ b/px30-android.dtsi @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 init=/init kpti=0"; + }; + + debug: debug@ff690000 { + compatible = "rockchip,debug"; + reg = <0x0 0xff690000 0x0 0x1000>, + <0x0 0xff692000 0x0 0x1000>, + <0x0 0xff694000 0x0 0x1000>, + <0x0 0xff696000 0x0 0x1000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + firmware_android: android {}; + + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + + vendor_storage_rm: vendor-storage-rm@00000000 { + compatible = "rockchip,vendor-storage-rm"; + reg = <0x0 0x0 0x0 0x0>; + }; + }; + + vendor_storage: vendor-storage { + compatible = "rockchip,ram-vendor-storage"; + memory-region = <&vendor_storage_rm>; + status = "okay"; + }; +}; + +&cpu0_opp_table { + rockchip,avs = <1>; +}; + +&display_subsystem { + status = "disabled"; + logo-memory-region = <&drm_logo>; + + route { + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_lvds>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_rgb>; + }; + }; +}; + +&dsi { + panel@0 { + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&vopb { + support-multi-area; +}; diff --git a/px30-ddr4p416dd6-timing.dtsi b/px30-ddr4p416dd6-timing.dtsi new file mode 100644 index 0000000..fde5895 --- /dev/null +++ b/px30-ddr4p416dd6-timing.dtsi @@ -0,0 +1,216 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + +&ddr_timing { + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <0>; + ddr3a0_ddr4a10_de-skew = <5>; + ddr3a3_ddr4a6_de-skew = <2>; + ddr3a2_ddr4a4_de-skew = <4>; + ddr3a5_ddr4a8_de-skew = <2>; + ddr3a4_ddr4a5_de-skew = <1>; + ddr3a7_ddr4a11_de-skew = <2>; + ddr3a6_ddr4a7_de-skew = <0>; + ddr3a9_ddr4a0_de-skew = <4>; + ddr3a8_ddr4a13_de-skew = <0>; + ddr3a11_ddr4a3_de-skew = <4>; + ddr3a10_ddr4cs0_de-skew = <5>; + ddr3a13_ddr4a2_de-skew = <2>; + ddr3a12_ddr4ba1_de-skew = <2>; + ddr3a15_ddr4odt0_de-skew = <7>; + ddr3a14_ddr4a1_de-skew = <4>; + ddr3ba1_ddr4a15_de-skew = <3>; + ddr3ba0_ddr4bg0_de-skew = <4>; + ddr3ras_ddr4cke_de-skew = <6>; + ddr3ba2_ddr4ba0_de-skew = <3>; + ddr3we_ddr4bg1_de-skew = <3>; + ddr3cas_ddr4a12_de-skew = <6>; + ddr3ckn_ddr4ckn_de-skew = <8>; + ddr3ckp_ddr4ckp_de-skew = <8>; + ddr3cke_ddr4a16_de-skew = <4>; + ddr3odt0_ddr4a14_de-skew = <4>; + ddr3cs0_ddr4act_de-skew = <7>; + ddr3reset_ddr4reset_de-skew = <3>; + ddr3cs1_ddr4cs1_de-skew = <5>; + ddr3odt1_ddr4odt1_de-skew = <6>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <9>; + cs0_dq0_rx_de-skew = <10>; + cs0_dq0_tx_de-skew = <10>; + cs0_dq1_rx_de-skew = <11>; + cs0_dq1_tx_de-skew = <10>; + cs0_dq2_rx_de-skew = <8>; + cs0_dq2_tx_de-skew = <10>; + cs0_dq3_rx_de-skew = <9>; + cs0_dq3_tx_de-skew = <9>; + cs0_dq4_rx_de-skew = <10>; + cs0_dq4_tx_de-skew = <10>; + cs0_dq5_rx_de-skew = <10>; + cs0_dq5_tx_de-skew = <10>; + cs0_dq6_rx_de-skew = <10>; + cs0_dq6_tx_de-skew = <10>; + cs0_dq7_rx_de-skew = <10>; + cs0_dq7_tx_de-skew = <10>; + cs0_dqs0_rx_de-skew = <5>; + cs0_dqs0p_tx_de-skew = <11>; + cs0_dqs0n_tx_de-skew = <11>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <9>; + cs0_dq8_rx_de-skew = <8>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <10>; + cs0_dq9_tx_de-skew = <9>; + cs0_dq10_rx_de-skew = <8>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <9>; + cs0_dq11_tx_de-skew = <10>; + cs0_dq12_rx_de-skew = <9>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <8>; + cs0_dq13_tx_de-skew = <9>; + cs0_dq14_rx_de-skew = <9>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <9>; + cs0_dq15_tx_de-skew = <9>; + cs0_dqs1_rx_de-skew = <5>; + cs0_dqs1p_tx_de-skew = <11>; + cs0_dqs1n_tx_de-skew = <11>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <10>; + cs0_dq16_rx_de-skew = <10>; + cs0_dq16_tx_de-skew = <9>; + cs0_dq17_rx_de-skew = <10>; + cs0_dq17_tx_de-skew = <9>; + cs0_dq18_rx_de-skew = <9>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <10>; + cs0_dq19_tx_de-skew = <9>; + cs0_dq20_rx_de-skew = <10>; + cs0_dq20_tx_de-skew = <10>; + cs0_dq21_rx_de-skew = <10>; + cs0_dq21_tx_de-skew = <9>; + cs0_dq22_rx_de-skew = <9>; + cs0_dq22_tx_de-skew = <8>; + cs0_dq23_rx_de-skew = <10>; + cs0_dq23_tx_de-skew = <9>; + cs0_dqs2_rx_de-skew = <5>; + cs0_dqs2p_tx_de-skew = <10>; + cs0_dqs2n_tx_de-skew = <10>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <9>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <9>; + cs0_dq25_tx_de-skew = <8>; + cs0_dq26_rx_de-skew = <9>; + cs0_dq26_tx_de-skew = <8>; + cs0_dq27_rx_de-skew = <9>; + cs0_dq27_tx_de-skew = <9>; + cs0_dq28_rx_de-skew = <9>; + cs0_dq28_tx_de-skew = <9>; + cs0_dq29_rx_de-skew = <9>; + cs0_dq29_tx_de-skew = <9>; + cs0_dq30_rx_de-skew = <10>; + cs0_dq30_tx_de-skew = <9>; + cs0_dq31_rx_de-skew = <10>; + cs0_dq31_tx_de-skew = <9>; + cs0_dqs3_rx_de-skew = <6>; + cs0_dqs3p_tx_de-skew = <10>; + cs0_dqs3n_tx_de-skew = <10>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <9>; + cs1_dq0_rx_de-skew = <10>; + cs1_dq0_tx_de-skew = <10>; + cs1_dq1_rx_de-skew = <11>; + cs1_dq1_tx_de-skew = <10>; + cs1_dq2_rx_de-skew = <8>; + cs1_dq2_tx_de-skew = <10>; + cs1_dq3_rx_de-skew = <9>; + cs1_dq3_tx_de-skew = <9>; + cs1_dq4_rx_de-skew = <10>; + cs1_dq4_tx_de-skew = <10>; + cs1_dq5_rx_de-skew = <10>; + cs1_dq5_tx_de-skew = <10>; + cs1_dq6_rx_de-skew = <10>; + cs1_dq6_tx_de-skew = <10>; + cs1_dq7_rx_de-skew = <10>; + cs1_dq7_tx_de-skew = <10>; + cs1_dqs0_rx_de-skew = <5>; + cs1_dqs0p_tx_de-skew = <11>; + cs1_dqs0n_tx_de-skew = <11>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <9>; + cs1_dq8_rx_de-skew = <8>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <10>; + cs1_dq9_tx_de-skew = <9>; + cs1_dq10_rx_de-skew = <8>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <9>; + cs1_dq11_tx_de-skew = <10>; + cs1_dq12_rx_de-skew = <9>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <8>; + cs1_dq13_tx_de-skew = <9>; + cs1_dq14_rx_de-skew = <9>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <9>; + cs1_dq15_tx_de-skew = <9>; + cs1_dqs1_rx_de-skew = <5>; + cs1_dqs1p_tx_de-skew = <11>; + cs1_dqs1n_tx_de-skew = <11>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <10>; + cs1_dq16_rx_de-skew = <10>; + cs1_dq16_tx_de-skew = <9>; + cs1_dq17_rx_de-skew = <10>; + cs1_dq17_tx_de-skew = <9>; + cs1_dq18_rx_de-skew = <9>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <10>; + cs1_dq19_tx_de-skew = <9>; + cs1_dq20_rx_de-skew = <10>; + cs1_dq20_tx_de-skew = <10>; + cs1_dq21_rx_de-skew = <10>; + cs1_dq21_tx_de-skew = <9>; + cs1_dq22_rx_de-skew = <9>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <10>; + cs1_dq23_tx_de-skew = <9>; + cs1_dqs2_rx_de-skew = <5>; + cs1_dqs2p_tx_de-skew = <10>; + cs1_dqs2n_tx_de-skew = <10>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <9>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <9>; + cs1_dq25_tx_de-skew = <8>; + cs1_dq26_rx_de-skew = <9>; + cs1_dq26_tx_de-skew = <8>; + cs1_dq27_rx_de-skew = <9>; + cs1_dq27_tx_de-skew = <9>; + cs1_dq28_rx_de-skew = <9>; + cs1_dq28_tx_de-skew = <9>; + cs1_dq29_rx_de-skew = <9>; + cs1_dq29_tx_de-skew = <9>; + cs1_dq30_rx_de-skew = <10>; + cs1_dq30_tx_de-skew = <9>; + cs1_dq31_rx_de-skew = <10>; + cs1_dq31_tx_de-skew = <9>; + cs1_dqs3_rx_de-skew = <6>; + cs1_dqs3p_tx_de-skew = <10>; + cs1_dqs3n_tx_de-skew = <10>; +}; diff --git a/px30-dram-default-timing.dtsi b/px30-dram-default-timing.dtsi new file mode 100644 index 0000000..99fb020 --- /dev/null +++ b/px30-dram-default-timing.dtsi @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr2_speed_bin = ; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr2_dll_dis_freq = <300>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr2_odt_dis_freq = <100>; + phy_ddr2_odt_dis_freq = <100>; + ddr2_drv = ; + ddr2_odt = ; + phy_ddr2_ca_drv = ; + phy_ddr2_ck_drv = ; + phy_ddr2_dq_drv = ; + phy_ddr2_odt = ; + + ddr3_odt_dis_freq = <400>; + phy_ddr3_odt_dis_freq = <400>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + phy_lpddr2_odt_dis_freq = <666>; + lpddr2_drv = ; + phy_lpddr2_ca_drv = ; + phy_lpddr2_ck_drv = ; + phy_lpddr2_dq_drv = ; + phy_lpddr2_odt = ; + + lpddr3_odt_dis_freq = <400>; + phy_lpddr3_odt_dis_freq = <400>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <625>; + phy_ddr4_odt_dis_freq = <625>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <6>; + ddr3a0_ddr4a10_de-skew = <7>; + ddr3a3_ddr4a6_de-skew = <7>; + ddr3a2_ddr4a4_de-skew = <7>; + ddr3a5_ddr4a8_de-skew = <7>; + ddr3a4_ddr4a5_de-skew = <7>; + ddr3a7_ddr4a11_de-skew = <7>; + ddr3a6_ddr4a7_de-skew = <6>; + ddr3a9_ddr4a0_de-skew = <7>; + ddr3a8_ddr4a13_de-skew = <7>; + ddr3a11_ddr4a3_de-skew = <7>; + ddr3a10_ddr4cs0_de-skew = <7>; + ddr3a13_ddr4a2_de-skew = <7>; + ddr3a12_ddr4ba1_de-skew = <7>; + ddr3a15_ddr4odt0_de-skew = <7>; + ddr3a14_ddr4a1_de-skew = <7>; + ddr3ba1_ddr4a15_de-skew = <7>; + ddr3ba0_ddr4bg0_de-skew = <7>; + ddr3ras_ddr4cke_de-skew = <7>; + ddr3ba2_ddr4ba0_de-skew = <7>; + ddr3we_ddr4bg1_de-skew = <7>; + ddr3cas_ddr4a12_de-skew = <7>; + ddr3ckn_ddr4ckn_de-skew = <7>; + ddr3ckp_ddr4ckp_de-skew = <7>; + ddr3cke_ddr4a16_de-skew = <7>; + ddr3odt0_ddr4a14_de-skew = <7>; + ddr3cs0_ddr4act_de-skew = <6>; + ddr3reset_ddr4reset_de-skew = <7>; + ddr3cs1_ddr4cs1_de-skew = <6>; + ddr3odt1_ddr4odt1_de-skew = <7>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <7>; + cs0_dq0_rx_de-skew = <8>; + cs0_dq0_tx_de-skew = <8>; + cs0_dq1_rx_de-skew = <9>; + cs0_dq1_tx_de-skew = <8>; + cs0_dq2_rx_de-skew = <8>; + cs0_dq2_tx_de-skew = <8>; + cs0_dq3_rx_de-skew = <8>; + cs0_dq3_tx_de-skew = <8>; + cs0_dq4_rx_de-skew = <9>; + cs0_dq4_tx_de-skew = <8>; + cs0_dq5_rx_de-skew = <9>; + cs0_dq5_tx_de-skew = <8>; + cs0_dq6_rx_de-skew = <9>; + cs0_dq6_tx_de-skew = <8>; + cs0_dq7_rx_de-skew = <8>; + cs0_dq7_tx_de-skew = <8>; + cs0_dqs0_rx_de-skew = <6>; + cs0_dqs0p_tx_de-skew = <9>; + cs0_dqs0n_tx_de-skew = <9>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <6>; + cs0_dq8_rx_de-skew = <8>; + cs0_dq8_tx_de-skew = <7>; + cs0_dq9_rx_de-skew = <9>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_rx_de-skew = <8>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <8>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_rx_de-skew = <8>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <9>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_rx_de-skew = <9>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <9>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1_rx_de-skew = <7>; + cs0_dqs1p_tx_de-skew = <9>; + cs0_dqs1n_tx_de-skew = <9>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <7>; + cs0_dq16_rx_de-skew = <9>; + cs0_dq16_tx_de-skew = <9>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq17_tx_de-skew = <9>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq19_tx_de-skew = <9>; + cs0_dq20_rx_de-skew = <9>; + cs0_dq20_tx_de-skew = <9>; + cs0_dq21_rx_de-skew = <9>; + cs0_dq21_tx_de-skew = <9>; + cs0_dq22_rx_de-skew = <8>; + cs0_dq22_tx_de-skew = <9>; + cs0_dq23_rx_de-skew = <8>; + cs0_dq23_tx_de-skew = <9>; + cs0_dqs2_rx_de-skew = <6>; + cs0_dqs2p_tx_de-skew = <9>; + cs0_dqs2n_tx_de-skew = <9>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <8>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <9>; + cs0_dq25_tx_de-skew = <9>; + cs0_dq26_rx_de-skew = <9>; + cs0_dq26_tx_de-skew = <8>; + cs0_dq27_rx_de-skew = <9>; + cs0_dq27_tx_de-skew = <8>; + cs0_dq28_rx_de-skew = <9>; + cs0_dq28_tx_de-skew = <9>; + cs0_dq29_rx_de-skew = <9>; + cs0_dq29_tx_de-skew = <9>; + cs0_dq30_rx_de-skew = <8>; + cs0_dq30_tx_de-skew = <8>; + cs0_dq31_rx_de-skew = <8>; + cs0_dq31_tx_de-skew = <8>; + cs0_dqs3_rx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <9>; + cs0_dqs3n_tx_de-skew = <9>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <7>; + cs1_dq0_rx_de-skew = <8>; + cs1_dq0_tx_de-skew = <8>; + cs1_dq1_rx_de-skew = <9>; + cs1_dq1_tx_de-skew = <8>; + cs1_dq2_rx_de-skew = <8>; + cs1_dq2_tx_de-skew = <8>; + cs1_dq3_rx_de-skew = <8>; + cs1_dq3_tx_de-skew = <8>; + cs1_dq4_rx_de-skew = <8>; + cs1_dq4_tx_de-skew = <8>; + cs1_dq5_rx_de-skew = <9>; + cs1_dq5_tx_de-skew = <8>; + cs1_dq6_rx_de-skew = <9>; + cs1_dq6_tx_de-skew = <8>; + cs1_dq7_rx_de-skew = <8>; + cs1_dq7_tx_de-skew = <8>; + cs1_dqs0_rx_de-skew = <6>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <8>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <8>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <8>; + cs1_dq11_tx_de-skew = <8>; + cs1_dq12_rx_de-skew = <8>; + cs1_dq12_tx_de-skew = <7>; + cs1_dq13_rx_de-skew = <8>; + cs1_dq13_tx_de-skew = <8>; + cs1_dq14_rx_de-skew = <8>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <8>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1_rx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <8>; + cs1_dq16_tx_de-skew = <9>; + cs1_dq17_rx_de-skew = <8>; + cs1_dq17_tx_de-skew = <9>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <8>; + cs1_dq19_tx_de-skew = <9>; + cs1_dq20_rx_de-skew = <9>; + cs1_dq20_tx_de-skew = <9>; + cs1_dq21_rx_de-skew = <9>; + cs1_dq21_tx_de-skew = <9>; + cs1_dq22_rx_de-skew = <8>; + cs1_dq22_tx_de-skew = <9>; + cs1_dq23_rx_de-skew = <8>; + cs1_dq23_tx_de-skew = <9>; + cs1_dqs2_rx_de-skew = <6>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <8>; + cs1_dq24_tx_de-skew = <9>; + cs1_dq25_rx_de-skew = <9>; + cs1_dq25_tx_de-skew = <9>; + cs1_dq26_rx_de-skew = <9>; + cs1_dq26_tx_de-skew = <8>; + cs1_dq27_rx_de-skew = <8>; + cs1_dq27_tx_de-skew = <8>; + cs1_dq28_rx_de-skew = <9>; + cs1_dq28_tx_de-skew = <9>; + cs1_dq29_rx_de-skew = <9>; + cs1_dq29_tx_de-skew = <9>; + cs1_dq30_rx_de-skew = <9>; + cs1_dq30_tx_de-skew = <8>; + cs1_dq31_rx_de-skew = <8>; + cs1_dq31_tx_de-skew = <8>; + cs1_dqs3_rx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; + }; +}; diff --git a/px30-evb-ddr3-lvds-v10.dts b/px30-evb-ddr3-lvds-v10.dts new file mode 100644 index 0000000..931ca2d --- /dev/null +++ b/px30-evb-ddr3-lvds-v10.dts @@ -0,0 +1,689 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include +#include +#include +#include "px30.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip PX30 evb ddr3 lvds board"; + compatible = "rockchip,px30-evb-ddr3-lvds-v10", "rockchip,px30"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1270000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <602000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <952000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <290000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + panel { + compatible = "samsung,lsl070nl01", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <49500000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <90>; + hfront-porch = <90>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <90>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk809 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + /*clocks = <&rk809 1>;*/ + /*clock-names = "ext_clock";*/ + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x1>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x1>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x1>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x1>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + sensor@f { + status = "okay"; + compatible = "ak8963"; + reg = <0x0f>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <1>; + reprobe_en = <1>; + }; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + }; + + sensor@4c { + status = "okay"; + compatible = "gs_mma7660"; + reg = <0x4c>; + type = ; + irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <2>; + reprobe_en = <1>; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vopb { + status = "okay"; +}; + +&lvds_in_vopl { + status = "disabled"; +}; + +&route_lvds { + connect = <&vopb_out_lvds>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30-evb-ddr3-v10-avb.dts b/px30-evb-ddr3-v10-avb.dts new file mode 100644 index 0000000..fd9b6a2 --- /dev/null +++ b/px30-evb-ddr3-v10-avb.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017-2021 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-android.dtsi" +#include "px30-evb-ddr3-v10.dtsi" + +/ { + model = "Rockchip PX30 evb ddr3 board"; + compatible = "rockchip,px30-evb-ddr3-v10-avb", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/px30-evb-ddr3-v10-linux.dts b/px30-evb-ddr3-v10-linux.dts new file mode 100644 index 0000000..9edb04a --- /dev/null +++ b/px30-evb-ddr3-v10-linux.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30.dtsi" +#include "rk3326-linux.dtsi" +#include "px30-evb-ddr3-v10.dtsi" + +/ { + model = "Rockchip linux PX30 evb ddr3 board"; + compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30"; + + /delete-node/ test-power; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; diff --git a/px30-evb-ddr3-v10-robot-linux.dts b/px30-evb-ddr3-v10-robot-linux.dts new file mode 100644 index 0000000..6461ac3 --- /dev/null +++ b/px30-evb-ddr3-v10-robot-linux.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "px30-robot.dtsi" + +/ { + model = "Rockchip linux PX30 evb ddr3 board"; + compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk809 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + pinctrl-0 = <&i2c2_xfer>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_3v0>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/px30-evb-ddr3-v10-robot-no-gpu-linux.dts b/px30-evb-ddr3-v10-robot-no-gpu-linux.dts new file mode 100644 index 0000000..afbe299 --- /dev/null +++ b/px30-evb-ddr3-v10-robot-no-gpu-linux.dts @@ -0,0 +1,627 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "px30-robot-no-gpu.dtsi" + +/ { + model = "Rockchip linux PX30 evb ddr3 board"; + compatible = "rockchip,px30-evb-ddr3-v10-linux", "rockchip,px30"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk809 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + pinctrl-0 = <&i2c2_xfer>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_3v0>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/px30-evb-ddr3-v10.dts b/px30-evb-ddr3-v10.dts new file mode 100644 index 0000000..ac0836b --- /dev/null +++ b/px30-evb-ddr3-v10.dts @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-android.dtsi" +#include "px30-evb-ddr3-v10.dtsi" + +/ { + model = "Rockchip PX30 evb ddr3 board"; + compatible = "rockchip,px30-evb-ddr3-v10", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30-evb-ddr3-v10.dtsi b/px30-evb-ddr3-v10.dtsi new file mode 100644 index 0000000..75f624e --- /dev/null +++ b/px30-evb-ddr3-v10.dtsi @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017-2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +/ { + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "back"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "homepage"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <1>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 1>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk809 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + test-power { + status = "okay"; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + clock_in_out = "input"; + assigned-clocks = <&cru SCLK_GMAC>; + assigned-clock-parents = <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk>; + snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + sensor@f { + status = "okay"; + compatible = "ak8963"; + reg = <0x0f>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <1>; + reprobe_en = <1>; + }; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + power-supply = <&vcc3v3_lcd>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + }; + + sensor@4c { + status = "okay"; + compatible = "gs_mma7660"; + reg = <0x4c>; + type = ; + irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <8>; + reprobe_en = <1>; + }; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_pin>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; diff --git a/px30-evb-ddr3-v11-linux.dts b/px30-evb-ddr3-v11-linux.dts new file mode 100644 index 0000000..54a4c19 --- /dev/null +++ b/px30-evb-ddr3-v11-linux.dts @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30-evb-ddr3-v10-linux.dts" + +/ { + model = "Rockchip linux PX30 evb ddr3 board"; + compatible = "rockchip,px30-evb-ddr3-v11-linux", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; diff --git a/px30-evb-ddr4-v10-linux.dts b/px30-evb-ddr4-v10-linux.dts new file mode 100644 index 0000000..6877824 --- /dev/null +++ b/px30-evb-ddr4-v10-linux.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30-evb-ddr3-v10-linux.dts" +#include "px30-ddr4p416dd6-timing.dtsi" + +/ { + model = "Rockchip linux PX30 evb ddr4 board"; + compatible = "rockchip,px30-evb-ddr4-v10-linux", "rockchip,px30"; +}; diff --git a/px30-evb-ddr4-v10.dts b/px30-evb-ddr4-v10.dts new file mode 100644 index 0000000..f128872 --- /dev/null +++ b/px30-evb-ddr4-v10.dts @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017-2021 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-android.dtsi" +#include "px30-evb-ddr3-v10.dtsi" +#include "px30-ddr4p416dd6-timing.dtsi" + +/ { + model = "Rockchip PX30 evb ddr4 board"; + compatible = "rockchip,px30-evb-ddr4-v10", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/px30-evb-ext-rk618-avb.dts b/px30-evb-ext-rk618-avb.dts new file mode 100644 index 0000000..ea44da5 --- /dev/null +++ b/px30-evb-ext-rk618-avb.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "px30-evb-ext-rk618.dtsi" + +/ { + model = "Rockchip PX30 EVB EXT RK618 board"; + compatible = "rockchip,px30-evb-ext-rk618-avb", "rockchip,px30"; +}; diff --git a/px30-evb-ext-rk618.dts b/px30-evb-ext-rk618.dts new file mode 100644 index 0000000..69f44b4 --- /dev/null +++ b/px30-evb-ext-rk618.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30-evb-ext-rk618.dtsi" + +/ { + model = "Rockchip PX30 EVB EXT RK618 board"; + compatible = "rockchip,px30-evb-ext-rk618", "rockchip,px30"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30-evb-ext-rk618.dtsi b/px30-evb-ext-rk618.dtsi new file mode 100644 index 0000000..f076787 --- /dev/null +++ b/px30-evb-ext-rk618.dtsi @@ -0,0 +1,203 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "px30-evb-ddr3-v10.dtsi" +#include "px30-android.dtsi" + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&dmc { + auto-freq-en = <0>; +}; + +&vcc3v0_pmu { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-suspend-microvolt = <3300000>; + }; +}; + +&i2c1 { + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S1_OUT>; + assigned-clock-rates = <11289600>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S1_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S1_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + hdmi { + compatible = "rockchip,rk618-hdmi"; + clocks = <&clock HDMI_CLK>; + clock-names = "hdmi"; + assigned-clocks = <&clock HDMI_CLK>; + assigned-clock-parents = <&clock VIF0_CLK>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_rgb: endpoint { + remote-endpoint = <&rgb_out_hdmi>; + }; + }; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "disabled"; +}; + +&rgb_in_vopl { + status = "okay"; +}; + +&route_rgb { + connect = <&vopl_out_rgb>; + status = "disabled"; +}; diff --git a/px30-evb.dts b/px30-evb.dts new file mode 100644 index 0000000..5fe905f --- /dev/null +++ b/px30-evb.dts @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "px30.dtsi" + +/ { + model = "Rockchip PX30 EVB"; + compatible = "rockchip,px30-evb", "rockchip,px30"; + + chosen { + stdout-path = "serial5:115200n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + esc-key { + label = "esc"; + linux,code = ; + press-threshold-microvolt = <1310000>; + }; + + home-key { + label = "home"; + linux,code = ; + press-threshold-microvolt = <624000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + power-supply = <&vcc3v3_lcd>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "xinpeng,xpp055c272"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_1v8>; + vci-supply = <&vcc3v3_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + mmc-pwrseq = <&emmc_pwrseq>; + vmmc-supply = <&vcc_3v0>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&gmac { + clock_in_out = "output"; + phy-supply = <&vcc_rmii>; + snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_log>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <0>; + clock-output-names = "xin32k"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: vcc_rmii: DCDC_REG4 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-name = "vcc_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: vccio_flash: vccio_sdio: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-name = "vcc3v0_pmu"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-name = "vcc2v8_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v5_dvp: LDO_REG9 { + regulator-name = "vcc1v5_dvp"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_lcd: SWITCH_REG1 { + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + }; + + vcc5v0_host: SWITCH_REG2 { + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + sensor@d { + compatible = "asahi-kasei,ak8963"; + reg = <0x0d>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&vcc3v0_pmu>; + mount-matrix = "1", /* x0 */ + "0", /* y0 */ + "0", /* z0 */ + "0", /* x1 */ + "1", /* y1 */ + "0", /* z1 */ + "0", /* x2 */ + "0", /* y2 */ + "1"; /* z2 */ + }; + + touchscreen@14 { + compatible = "goodix,gt1151"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&vcc3v3_lcd>; + }; + + sensor@4c { + compatible = "fsl,mma7660"; + reg = <0x4c>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_sdio>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + vccio6-supply = <&vccio_flash>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + emmc { + emmc_reset: emmc-reset { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <800>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdio { + cap-sd-highspeed; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/px30-mini-evb-ddr3-v11-avb.dts b/px30-mini-evb-ddr3-v11-avb.dts new file mode 100644 index 0000000..822eb3b --- /dev/null +++ b/px30-mini-evb-ddr3-v11-avb.dts @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017-2020 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-android.dtsi" +#include "px30-evb-ddr3-v10.dtsi" +#include "px30-mini-evb-v11.dtsi" + +/ { + model = "Rockchip PX30 mini evb ddr3 board"; + compatible = "rockchip,px30-mini-evb-ddr3-v11-avb", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 78 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + +}; diff --git a/px30-mini-evb-ddr3-v11.dts b/px30-mini-evb-ddr3-v11.dts new file mode 100644 index 0000000..34d3d9c --- /dev/null +++ b/px30-mini-evb-ddr3-v11.dts @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "px30.dtsi" +#include "px30-android.dtsi" +#include "px30-evb-ddr3-v10.dtsi" +#include "px30-mini-evb-v11.dtsi" + +/ { + model = "Rockchip PX30 mini evb ddr3 board"; + compatible = "rockchip,px30-mini-evb-ddr3-v11", "rockchip,px30"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30-mini-evb-v11.dtsi b/px30-mini-evb-v11.dtsi new file mode 100644 index 0000000..ef6475c --- /dev/null +++ b/px30-mini-evb-v11.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd + */ + +&gmac { + clock_in_out = "output"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; +}; + +&rk809_sound { + hp-det-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; +}; + + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; +}; + diff --git a/px30-robot-no-gpu.dtsi b/px30-robot-no-gpu.dtsi new file mode 100644 index 0000000..e3f4274 --- /dev/null +++ b/px30-robot-no-gpu.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ +#include "px30-robot.dtsi" + +/ { + compatible = "rockchip,linux", "rockchip,px30-robot-no-gpu"; + + /* Remove gpu thermal and gpu cooling map */ + /delete-node/ thermal-zones; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <252>; + + thermal-sensors = <&tsadc 0>; + trips { + threshold: trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; +}; + +&gpu { + status = "disabled"; +}; diff --git a/px30-robot.dtsi b/px30-robot.dtsi new file mode 100644 index 0000000..6ddf360 --- /dev/null +++ b/px30-robot.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "px30.dtsi" + +/ { + compatible = "rockchip,linux", "rockchip,px30-robot"; + + chosen { + bootargs = "console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ramoops: ramoops@8000000 { + compatible = "ramoops"; + reg = <0x0 0x8000000 0x0 0xa0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x00000>; + }; + }; +}; + +&cpu0_opp_table { + /delete-node/ opp-1248000000; + /delete-node/ opp-1296000000; + /delete-node/ opp-1416000000; + /delete-node/ opp-1512000000; +}; + +&dmc_opp_table { + /delete-node/ opp-666000000; + /delete-node/ opp-768000000; +}; + +&i2s1_2ch { + rockchip,playback-only; +}; + +&rng { + status = "okay"; +}; + +&soc_thermal { + trips { + threshold: trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; diff --git a/px30-z7-a0-rk618-dsi.dts b/px30-z7-a0-rk618-dsi.dts new file mode 100644 index 0000000..ba30ab7 --- /dev/null +++ b/px30-z7-a0-rk618-dsi.dts @@ -0,0 +1,875 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "px30.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip PX30 Z7 A0 board"; + compatible = "rockchip,px30-z7-a0", "rockchip,px30"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + reset-gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <95>; + height-mm = <151>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 02 b0 00 + 15 00 02 d6 01 + 39 00 06 b3 14 08 00 22 00 + 15 00 02 b4 0c + 15 00 02 de 00 + 39 00 03 b6 3a d3 + 15 00 02 51 e0 + 15 00 02 53 04 + 15 00 02 3a 77 + 15 00 02 35 01 + 39 00 05 2a 00 00 04 af + 39 00 05 2b 00 00 07 7f + 05 96 01 29 + 05 14 01 11 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <156000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <4>; + vfront-porch = <4>; + hsync-len = <10>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + auto-freq-en = <0>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_soc"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc1v0_soc"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v0_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd1v5_dvp"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + }; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S1_OUT>; + assigned-clock-rates = <12000000>; + reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S1_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S1_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + dsi { + compatible = "rockchip,rk618-dsi"; + clocks = <&clock MIPI_CLK>; + clock-names = "dsi"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_in_rgb: endpoint { + remote-endpoint = <&rgb_out_dsi>; + }; + }; + }; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <95>; + height-mm = <151>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 02 b0 00 + 15 00 02 d6 01 + 39 00 06 b3 14 08 00 22 00 + 15 00 02 b4 0c + 15 00 02 DE 00 + 39 00 03 b6 3a d3 + 15 00 02 51 E0 + 15 00 02 53 04 + 15 00 02 3a 77 + 15 00 02 35 01 + 39 00 05 2A 00 00 04 AF + 39 00 05 2B 00 00 07 7F + 05 96 01 29 + 05 14 01 11 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <156000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <4>; + vfront-porch = <4>; + hsync-len = <10>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; +}; + +&io_domains { + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm0 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,sleep-debug-en = <1>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc1v8_soc>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_dsi: endpoint { + remote-endpoint = <&dsi_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopl { + status = "okay"; +}; + +&rgb_in_vopb { + status = "disabled"; +}; + +&route_rgb { + connect = <&vopl_out_rgb>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + + fstab { + compatible = "android,fstab"; + + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/px30.dtsi b/px30.dtsi new file mode 100644 index 0000000..ce921f6 --- /dev/null +++ b/px30.dtsi @@ -0,0 +1,3129 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "px30-dram-default-timing.dtsi" +#include "px30s-dram-default-timing.dtsi" + +/ { + compatible = "rockchip,px30"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + mmc0 = &sdmmc; + mmc1 = &sdio; + mmc2 = &emmc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &sfc; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + dynamic-power-coefficient = <90>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + dynamic-power-coefficient = <90>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + dynamic-power-coefficient = <90>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + dynamic-power-coefficient = <90>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <1000000>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1512 50000 + >; + + clocks = <&cru PLL_APLL>; + rockchip,avs-scale = <4>; + rockchip,max-volt = <1350000>; + rockchip,evb-irdrop = <25000>; + nvmem-cells = <&cpu_leakage>, <&performance>; + nvmem-cell-names = "cpu_leakage", "performance"; + rockchip,bin-scaling-sel = < + 0 13 + 1 15 + >; + + rockchip,pvtm-voltage-sel = < + 0 50000 0 + 50001 54000 1 + 54001 60000 2 + 60001 99999 3 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <1000000>; + rockchip,pvtm-ch = <0 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <(-56) (-56)>; + rockchip,thermal-zone = "soc-thermal"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + opp-microvolt-L0 = <950000 950000 1350000>; + opp-microvolt-L1 = <950000 950000 1350000>; + opp-microvolt-L2 = <950000 950000 1350000>; + opp-microvolt-L3 = <950000 950000 1350000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + opp-microvolt-L0 = <950000 950000 1350000>; + opp-microvolt-L1 = <950000 950000 1350000>; + opp-microvolt-L2 = <950000 950000 1350000>; + opp-microvolt-L3 = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1050000 1050000 1350000>; + opp-microvolt-L0 = <1050000 1050000 1350000>; + opp-microvolt-L1 = <1000000 1000000 1350000>; + opp-microvolt-L2 = <1000000 1000000 1350000>; + opp-microvolt-L3 = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1175000 1175000 1350000>; + opp-microvolt-L0 = <1175000 1175000 1350000>; + opp-microvolt-L1 = <1125000 1125000 1350000>; + opp-microvolt-L2 = <1125000 1125000 1350000>; + opp-microvolt-L3 = <1050000 1050000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1300000 1300000 1350000>; + opp-microvolt-L0 = <1300000 1300000 1350000>; + opp-microvolt-L1 = <1275000 1275000 1350000>; + opp-microvolt-L2 = <1250000 1250000 1350000>; + opp-microvolt-L3 = <1200000 1200000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-microvolt-L0 = <1350000 1350000 1350000>; + opp-microvolt-L1 = <1300000 1300000 1350000>; + opp-microvolt-L2 = <1275000 1275000 1350000>; + opp-microvolt-L3 = <1225000 1225000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-microvolt-L0 = <1350000 1350000 1350000>; + opp-microvolt-L1 = <1350000 1350000 1350000>; + opp-microvolt-L2 = <1300000 1300000 1350000>; + opp-microvolt-L3 = <1250000 1250000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-microvolt-L0 = <1350000 1350000 1350000>; + opp-microvolt-L1 = <1350000 1350000 1350000>; + opp-microvolt-L2 = <1300000 1300000 1350000>; + opp-microvolt-L3 = <1250000 1250000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-microvolt-L0 = <1350000 1350000 1350000>; + opp-microvolt-L1 = <1350000 1350000 1350000>; + opp-microvolt-L2 = <1300000 1300000 1350000>; + opp-microvolt-L3 = <1250000 1250000 1350000>; + clock-latency-ns = <40000>; + }; + }; + + px30s_cpu0_opp_table: px30s-cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; + + rockchip,pvtm-voltage-sel = < + 0 69850 0 + 69851 73800 1 + 73801 77750 2 + 77751 81700 3 + 81701 99999 4 + >; + + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ch = <0 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <0>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,thermal-zone = "soc-thermal"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <950000 950000 1150000>; + opp-microvolt-L0 = <950000 950000 1150000>; + opp-microvolt-L1 = <925000 925000 1150000>; + opp-microvolt-L2 = <900000 900000 1150000>; + opp-microvolt-L3 = <875000 875000 1150000>; + opp-microvolt-L4 = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1050000 1050000 1150000>; + opp-microvolt-L0 = <1050000 1050000 1150000>; + opp-microvolt-L1 = <1025000 1025000 1150000>; + opp-microvolt-L2 = <1000000 1000000 1150000>; + opp-microvolt-L3 = <975000 975000 1150000>; + opp-microvolt-L4 = <950000 950000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + opp-microvolt = <1075000 1075000 1150000>; + opp-microvolt-L0 = <1075000 1075000 1150000>; + opp-microvolt-L1 = <1050000 1050000 1150000>; + opp-microvolt-L2 = <1025000 1025000 1150000>; + opp-microvolt-L3 = <1000000 1000000 1150000>; + opp-microvolt-L4 = <975000 975000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1100000 1100000 1150000>; + opp-microvolt-L0 = <1100000 1100000 1150000>; + opp-microvolt-L1 = <1075000 1075000 1150000>; + opp-microvolt-L2 = <1050000 1050000 1150000>; + opp-microvolt-L3 = <1025000 1025000 1150000>; + opp-microvolt-L4 = <1000000 1000000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1150000 1150000 1150000>; + opp-microvolt-L0 = <1150000 1150000 1150000>; + opp-microvolt-L1 = <1125000 1125000 1150000>; + opp-microvolt-L2 = <1100000 1100000 1150000>; + opp-microvolt-L3 = <1075000 1075000 1150000>; + opp-microvolt-L4 = <1050000 1050000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000 1150000 1150000>; + opp-microvolt-L0 = <1150000 1150000 1150000>; + opp-microvolt-L1 = <1125000 1125000 1150000>; + opp-microvolt-L2 = <1100000 1100000 1150000>; + opp-microvolt-L3 = <1075000 1075000 1150000>; + opp-microvolt-L4 = <1050000 1050000 1150000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + bus_soc: bus-soc { + compatible = "rockchip,px30-bus"; + rockchip,busfreq-policy = "autocs"; + soc-bus0 { + bus-id = <0>; + timer-us = <20>; + enable-msk = <0x40f7>; + }; + soc-bus1 { + bus-id = <1>; + timer-us = <200>; + enable-msk = <0x40bf>; + status = "disabled"; + }; + soc-bus2 { + bus-id = <2>; + timer-us = <200>; + enable-msk = <0x4007>; + status = "disabled"; + }; + }; + + bus_apll: bus-apll { + compatible = "rockchip,px30-bus"; + rockchip,busfreq-policy = "clkfreq"; + clocks = <&cru PLL_APLL>; + clock-names = "bus"; + operating-points-v2 = <&bus_apll_opp_table>; + status = "disabled"; + }; + + bus_apll_opp_table: bus-apll-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1000000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <950000>; + }; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&cpu_id>; + nvmem-cell-names = "id"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopb_out>, <&vopl_out>; + status = "disabled"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + + sdei: sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-px30"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_HW_PLLS_PD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_PMIC_LP + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CLUSTER_WKUP_EN + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + ) + >; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <750>; + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point-0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit: soc-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + + map1 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 1>; + }; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + scmi_shmem: scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + }; + + pmu: power-management@ff000000 { + compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff000000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,px30-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_LOGIC */ + power-domain@PX30_PD_USB { + reg = ; + clocks = <&cru HCLK_HOST>, + <&cru HCLK_OTG>, + <&cru SCLK_OTG_ADP>; + pm_qos = <&qos_usb_host>, <&qos_usb_otg>; + }; + power-domain@PX30_PD_SDCARD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sdmmc>; + }; + power-domain@PX30_PD_GMAC { + reg = ; + clocks = <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>, + <&cru SCLK_MAC_REF>, + <&cru SCLK_GMAC_RX_TX>; + pm_qos = <&qos_gmac>; + }; + power-domain@PX30_PD_MMC_NAND { + reg = ; + clocks = <&cru HCLK_NANDC>, + <&cru HCLK_EMMC>, + <&cru HCLK_SDIO>, + <&cru HCLK_SFC>, + <&cru SCLK_EMMC>, + <&cru SCLK_NANDC>, + <&cru SCLK_SDIO>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, <&qos_nand>, + <&qos_sdio>, <&qos_sfc>; + }; + power-domain@PX30_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>, + <&cru SCLK_CORE_VPU>; + pm_qos = <&qos_vpu>, <&qos_vpu_r128>; + }; + power-domain@PX30_PD_VO { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru ACLK_VOPB>, + <&cru ACLK_VOPL>, + <&cru DCLK_VOPB>, + <&cru DCLK_VOPL>, + <&cru HCLK_RGA>, + <&cru HCLK_VOPB>, + <&cru HCLK_VOPL>, + <&cru PCLK_MIPI_DSI>, + <&cru SCLK_RGA_CORE>, + <&cru SCLK_VOPB_PWM>; + pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, + <&qos_vop_m0>, <&qos_vop_m1>; + }; + power-domain@PX30_PD_VI { + reg = ; + clocks = <&cru ACLK_CIF>, + <&cru ACLK_ISP>, + <&cru HCLK_CIF>, + <&cru HCLK_ISP>, + <&cru SCLK_ISP>; + pm_qos = <&qos_isp_128>, <&qos_isp_rd>, + <&qos_isp_wr>, <&qos_isp_m1>, + <&qos_vip>; + }; + power-domain@PX30_PD_GPU { + reg = ; + clocks = <&cru SCLK_GPU>; + pm_qos = <&qos_gpu>; + }; + }; + }; + + pmugrf: syscon@ff010000 { + compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xff010000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_io_domains: io-domains { + compatible = "rockchip,px30-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,px30-pmu-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pvtm@1 { + reg = <1>; + clocks = <&pmucru SCLK_PVTM_PMU>; + clock-names = "clk"; + }; + }; + }; + + uart0: serial@ff030000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff030000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 0>, <&dmac 1>; + /*You can add it to enable dma*/ + /*dma-names = "tx", "rx";*/ + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + i2s0_8ch: i2s@ff060000 { + compatible = "rockchip,px30-i2s-tdm"; + reg = <0x0 0xff060000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac 16>, <&dmac 17>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_sclktx + &i2s0_8ch_sclkrx + &i2s0_8ch_lrcktx + &i2s0_8ch_lrckrx + &i2s0_8ch_sdi0 + &i2s0_8ch_sdi1 + &i2s0_8ch_sdi2 + &i2s0_8ch_sdi3 + &i2s0_8ch_sdo0 + &i2s0_8ch_sdo1 + &i2s0_8ch_sdo2 + &i2s0_8ch_sdo3>; + status = "disabled"; + }; + + i2s1_2ch: i2s@ff070000 { + compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff070000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 18>, <&dmac 19>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck + &i2s1_2ch_sdi &i2s1_2ch_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@ff080000 { + compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff080000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 20>, <&dmac 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck + &i2s2_2ch_sdi &i2s2_2ch_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + crypto: crypto@ff0b0000 { + compatible = "rockchip,px30-crypto"; + reg = <0x0 0xff0b0000 0x0 0x400>, <0x0 0xff0b0480 0x0 0x3B80>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO >, <&cru HCLK_CRYPTO >, + <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>; + clock-names = "aclk", "hclk", "sclk", "apb_pclk"; + resets = <&cru SRST_CRYPTO>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@ff0b0000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff0b0400 0x0 0x80>; + clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + clock-names = "clk_crypto", "clk_crypto_apk", + "aclk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + assigned-clock-rates = <150000000>, <150000000>, + <200000000>, <200000000>; + resets = <&cru SRST_CRYPTO>; + reset-names = "reset"; + status = "disabled"; + }; + + gic: interrupt-controller@ff131000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xff131000 0 0x1000>, + <0x0 0xff132000 0 0x2000>, + <0x0 0xff134000 0 0x2000>, + <0x0 0xff136000 0 0x2000>; + interrupts = ; + }; + + grf: syscon@ff140000 { + compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff140000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,px30-io-voltage-domain"; + status = "disabled"; + }; + + lvds: lvds { + compatible = "rockchip,px30-lvds"; + phys = <&video_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_vopb_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_lvds>; + }; + + lvds_vopl_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_lvds>; + }; + }; + }; + }; + + rgb: rgb { + compatible = "rockchip,px30-rgb"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_m0_rgb_pins>; + pinctrl-1 = <&lcdc_m0_sleep_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_rgb>; + }; + + rgb_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_rgb>; + }; + }; + }; + }; + }; + + core_grf: syscon@ff148000 { + compatible = "syscon", "simple-mfd"; + reg = <0x0 0xff148000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pvtm: pvtm { + compatible = "rockchip,px30-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pvtm@0 { + reg = <0>; + clocks = <&cru SCLK_PVTM>; + clock-names = "clk"; + }; + }; + }; + + uart1: serial@ff158000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff158000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 2>, <&dmac 3>; + /*You can add it to enable dma*/ + /*dma-names = "tx", "rx";*/ + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + status = "disabled"; + }; + + uart2: serial@ff160000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff160000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 4>, <&dmac 5>; + /*You can add it to enable dma*/ + /*dma-names = "tx", "rx";*/ + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart3: serial@ff168000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff168000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 6>, <&dmac 7>; + /*You can add it to enable dma*/ + /*dma-names = "tx", "rx";*/ + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; + status = "disabled"; + }; + + uart4: serial@ff170000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff170000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 8>, <&dmac 9>; + /*You can add it to enable dma*/ + /*dma-names = "tx", "rx";*/ + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; + status = "disabled"; + }; + + uart5: serial@ff178000 { + compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff178000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 10>, <&dmac 11>; + /*You can add it to enable dma*/ + /*dma-names = "tx", "rx";*/ + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; + status = "disabled"; + }; + + i2c0: i2c@ff180000 { + compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff180000 0x0 0x1000>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ff190000 { + compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff190000 0x0 0x1000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff1a0000 { + compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff1a0000 0x0 0x1000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ff1b0000 { + compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff1b0000 0x0 0x1000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@ff1d0000 { + compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 12>, <&dmac 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff1d8000 { + compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 14>, <&dmac 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@ff1e0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff1e0000 0x0 0x100>; + clocks = <&cru PCLK_WDT_NS>; + interrupts = ; + status = "disabled"; + }; + + pwm0: pwm@ff200000 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200000 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@ff200010 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200010 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@ff200020 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200020 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ff200030 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff200030 0x0 0x10>; + interrupts = , + ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@ff208000 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208000 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@ff208010 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208010 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@ff208020 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208020 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@ff208030 { + compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff208030 0x0 0x10>; + interrupts = , + ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + rktimer: timer@ff210000 { + compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff210000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + amba: bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac: dmac@ff240000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff240000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,px30-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <50000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <120000>; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&tsadc_otp_pin>; + pinctrl-1 = <&tsadc_otp_out>; + pinctrl-2 = <&tsadc_otp_pin>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + saradc: saradc@ff288000 { + compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff288000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + otp: nvmem@ff290000 { + compatible = "rockchip,px30-otp"; + reg = <0x0 0xff290000 0x0 0x4000>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "phy"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + cpu_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + performance: performance@1e { + reg = <0x1e 0x1>; + bits = <4 3>; + }; + }; + + cru: clock-controller@ff2b0000 { + compatible = "rockchip,px30-cru"; + reg = <0x0 0xff2b0000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1188000000>; + }; + + pmucru: clock-controller@ff2bc000 { + compatible = "rockchip,px30-pmucru"; + reg = <0x0 0xff2bc000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, + <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; + assigned-clock-rates = + <1200000000>, <100000000>, + <26000000>, <600000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>; + }; + + usb2phy_grf: syscon@ff2c0000 { + compatible = "rockchip,px30-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xff2c0000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,px30-usb2phy"; + reg = <0x100 0x20>; + clocks = <&pmucru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>, <&cru SCLK_UART1_SRC>; + assigned-clock-parents = <&u2phy>, <&cru USB480M>; + clock-output-names = "usb480m_phy"; + status = "disabled"; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + }; + + video_phy: dsi_dphy: phy@ff2e0000 { + compatible = "rockchip,px30-dsi-dphy", "rockchip,px30-video-phy"; + reg = <0x0 0xff2e0000 0x0 0x10000>, + <0x0 0xff450000 0x0 0x10000>; + reg-names = "phy", "host"; + clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, + <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; + clock-names = "ref", "pclk", "pclk_host"; + resets = <&cru SRST_MIPIDSIPHY_P>; + reset-names = "apb"; + #phy-cells = <0>; + power-domains = <&power PX30_PD_VO>; + status = "disabled"; + }; + + mipi_dphy_rx0: mipi-dphy-rx0@ff2f0000 { + compatible = "rockchip,rk3326-mipi-dphy"; + reg = <0x0 0xff2f0000 0x0 0x4000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "dphy-ref"; + power-domains = <&power PX30_PD_VI>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + usb20_otg: usb@ff300000 { + compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff300000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + power-domains = <&power PX30_PD_USB>; + status = "disabled"; + }; + + usb_host0_ehci: usb@ff340000 { + compatible = "generic-ehci"; + reg = <0x0 0xff340000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&u2phy>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + power-domains = <&power PX30_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff350000 { + compatible = "generic-ohci"; + reg = <0x0 0xff350000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&u2phy>; + clock-names = "usbhost", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + power-domains = <&power PX30_PD_USB>; + status = "disabled"; + }; + + gmac: ethernet@ff360000 { + compatible = "rockchip,px30-gmac"; + reg = <0x0 0xff360000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, + <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac", "clk_mac_speed"; + rockchip,grf = <&grf>; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; + power-domains = <&power PX30_PD_GMAC>; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + status = "disabled"; + }; + + sdmmc: dwmmc@ff370000 { + compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff370000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; + fifo-depth = <0x100>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power PX30_PD_SDCARD>; + status = "disabled"; + }; + + sdio: dwmmc@ff380000 { + compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff380000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <4>; + fifo-depth = <0x100>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + + emmc: dwmmc@ff390000 { + compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff390000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + bus-width = <8>; + fifo-depth = <0x100>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + + sfc: spi@ff3a0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff3a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + nandc0: nandc@ff3b0000 { + compatible = "rockchip,rk-nandc"; + reg = <0x0 0xff3b0000 0x0 0x4000>; + interrupts = ; + nandc_id = <0>; + clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; + clock-names = "clk_nandc", "hclk_nandc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-parents = <&cru SCLK_NANDC_DIV50>; + power-domains = <&power PX30_PD_MMC_NAND>; + status = "disabled"; + }; + + gpu: gpu@ff400000 { + compatible = "rockchip,px30-mali", "arm,mali-bifrost"; + reg = <0x0 0xff400000 0x0 0x4000>; + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + clocks = <&cru SCLK_GPU>; + #cooling-cells = <2>; + power-domains = <&power PX30_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + upthreshold = <40>; + downdifferential = <10>; + status = "disabled"; + power_model { + compatible = "arm,mali-simple-power-model"; + static-coefficient = <411000>; + dynamic-coefficient = <733>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <1000000>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 480 50000 + >; + + rockchip,max-volt = <1175000>; + rockchip,evb-irdrop = <25000>; + + rockchip,pvtm-voltage-sel = < + 0 50000 0 + 50001 54000 1 + 54001 60000 2 + 60001 99999 3 + >; + rockchip,pvtm-ch = <0 0>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <950000>; + opp-microvolt-L2 = <950000>; + opp-microvolt-L3 = <950000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; + opp-microvolt-L2 = <950000>; + opp-microvolt-L3 = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-microvolt-L0 = <1050000>; + opp-microvolt-L1 = <1025000>; + opp-microvolt-L2 = <975000>; + opp-microvolt-L3 = <950000>; + }; + opp-480000000 { + opp-hz = /bits/ 64 <480000000>; + opp-microvolt = <1125000>; + opp-microvolt-L0 = <1125000>; + opp-microvolt-L1 = <1100000>; + opp-microvolt-L2 = <1050000>; + opp-microvolt-L3 = <1000000>; + }; + }; + + px30s_gpu_opp_table: px30s-gpu-opp-table { + compatible = "operating-points-v2"; + + rockchip,pvtm-voltage-sel = < + 0 69850 0 + 69851 73800 1 + 73801 77750 2 + 77751 81700 3 + 81701 99999 4 + >; + rockchip,pvtm-ch = <0 0>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + }; + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1000000>; + opp-microvolt-L0 = <1000000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <950000>; + opp-microvolt-L3 = <950000>; + opp-microvolt-L4 = <950000>; + }; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <1>; + rockchip,resetgroup-count = <1>; + rockchip,grf = <&grf>; + rockchip,grf-offset = <0x0410>; + rockchip,grf-values = <0x80008000>, <0x80000000>, <0x80000000>; + rockchip,grf-names = "grf_rkvdec", "grf_vdpu2", "grf_vepu2"; + status = "disabled"; + }; + + vdpu: vdpu@ff442400 { + compatible = "rockchip,vpu-decoder-px30"; + reg = <0x0 0xff442400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vpu_mmu>; + power-domains = <&power PX30_PD_VPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff442800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff442800 0x0 0x100>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power PX30_PD_VPU>; + rockchip,shootdown-entire; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu: vepu@ff442000 { + compatible = "rockchip,vpu-encoder-px30"; + reg = <0x0 0xff442000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_enc"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vpu_mmu>; + power-domains = <&power PX30_PD_VPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + hevc: hevc@ff440000 { + compatible = "rockchip,hevc-decoder-px30"; + reg = <0x0 0xff440000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>, + <&cru SRST_VPU_NIU_A>, <&cru SRST_VPU_NIU_H>, + <&cru SRST_VPU_CORE>; + reset-names = "shared_video_a", "shared_video_h", + "niu_a", "niu_h", + "video_core"; + iommus = <&hevc_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + power-domains = <&power PX30_PD_VPU>; + status = "disabled"; + }; + + hevc_mmu: iommu@ff440440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff440440 0x0 0x40>, <0x0 0xff440480 0x0 0x40>; + interrupts = ; + interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power PX30_PD_VPU>; + rockchip,shootdown-entire; + #iommu-cells = <0>; + status = "disabled"; + }; + + dsi: dsi@ff450000 { + compatible = "rockchip,px30-mipi-dsi"; + reg = <0x0 0xff450000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_MIPI_DSI>; + clock-names = "pclk"; + phys = <&video_phy>; + phy-names = "dphy"; + power-domains = <&power PX30_PD_VO>; + resets = <&cru SRST_MIPIDSI_HOST_P>; + reset-names = "apb"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dsi>; + }; + + dsi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dsi>; + }; + }; + }; + }; + + vopb: vop@ff460000 { + compatible = "rockchip,px30-vop-big"; + reg = <0x0 0xff460000 0x0 0x260>, <0x0 0xff460a00 0x0 0x400>; + rockchip,grf = <&grf>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, + <&cru HCLK_VOPB>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopb_mmu>; + power-domains = <&power PX30_PD_VO>; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopb_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vopb>; + }; + + vopb_out_lvds: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds_vopb_in>; + }; + + vopb_out_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&rgb_in_vopb>; + }; + }; + }; + + vopb_mmu: iommu@ff460f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff460f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; + clock-names = "aclk", "iface"; + power-domains = <&power PX30_PD_VO>; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + vopl: vop@ff470000 { + compatible = "rockchip,px30-vop-lit"; + reg = <0x0 0xff470000 0x0 0x1fc>, <0x0 0xff470a00 0x0 0x400>; + rockchip,grf = <&grf>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, + <&cru HCLK_VOPL>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vopl_mmu>; + power-domains = <&power PX30_PD_VO>; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopl_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vopl>; + }; + + vopl_out_lvds: endpoint@1 { + reg = <1>; + remote-endpoint = <&lvds_vopl_in>; + }; + + vopl_out_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&rgb_in_vopl>; + }; + }; + }; + + vopl_mmu: iommu@ff470f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff470f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; + clock-names = "aclk", "iface"; + power-domains = <&power PX30_PD_VO>; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + rk_rga: rk_rga@ff480000 { + compatible = "rockchip,rga2"; + //dev_mode = <1>; + reg = <0x0 0xff480000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power PX30_PD_VO>; + status = "disabled"; + }; + + cif: cif@ff490000 { + compatible = "rockchip,cif"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; + clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; + power-domains = <&power PX30_PD_VI>; + pinctrl-names = "cif_pin_all"; + pinctrl-0 = <&dvp_d2d9_m0>; + iommus = <&vip_mmu>; + status = "disabled"; + }; + + cif_new: cif-new@ff490000 { + compatible = "rockchip,px30-cif"; + reg = <0x0 0xff490000 0x0 0x200>; + interrupts = ; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>, <&cru SCLK_CIF_OUT>; + clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin"; + power-domains = <&power PX30_PD_VI>; + iommus = <&vip_mmu>; + status = "disabled"; + }; + + vip_mmu: iommu@ff490800{ + compatible = "rockchip,iommu"; + reg = <0x0 0xff490800 0x0 0x100>; + interrupts = ; + interrupt-names = "vip_mmu"; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; + clock-names = "aclk", "iface"; + power-domains = <&power PX30_PD_VI>; + rk_iommu,disable_reset_quirk; + #iommu-cells = <0>; + status = "disabled"; + }; + + rk_isp: rk_isp@ff4a0000 { + compatible = "rockchip,px30-isp", "rockchip,isp"; + reg = <0x0 0xff4a0000 0x0 0x8000>; + interrupts = ; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>, <&cru SCLK_ISP>, + <&cru PCLK_ISP>, <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, <&cru PCLK_MIPICSIPHY>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", + "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx"; + resets = <&cru SRST_ISP>, <&cru SRST_MIPICSIPHY_P>; + reset-names = "rst_isp", "rst_mipicsiphy"; + power-domains = <&power PX30_PD_VI>; + pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit"; + pinctrl-0 = <&cif_clkout_m0>; + pinctrl-1 = <&dvp_d2d9_m0>; + pinctrl-2 = <&dvp_d2d9_m0 &dvp_d10d11_m0>; + pinctrl-3 = <&dvp_d0d1_m0 &dvp_d2d9_m0 &dvp_d10d11_m0>; + rockchip,isp,mipiphy = <1>; + rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>; + rockchip,grf = <&grf>; + rockchip,cru = <&cru>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp_mmu>; + status = "disabled"; + }; + + rkisp1: rkisp1@ff4a0000 { + compatible = "rockchip,rk3326-rkisp1"; + reg = <0x0 0xff4a0000 0x0 0x8000>; + interrupts = , + , + ; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>, <&cru PCLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", + "clk_isp", "pclk_isp"; + devfreq = <&dmc>; + power-domains = <&power PX30_PD_VI>; + iommus = <&isp_mmu>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + isp_mmu: iommu@ff4a8000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff4a8000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + power-domains = <&power PX30_PD_VI>; + rk_iommu,disable_reset_quirk; + #iommu-cells = <0>; + status = "disabled"; + }; + + qos_gmac: qos@ff518000 { + compatible = "syscon"; + reg = <0x0 0xff518000 0x0 0x20>; + }; + + qos_gpu: qos@ff520000 { + compatible = "syscon"; + reg = <0x0 0xff520000 0x0 0x20>; + }; + + qos_sdmmc: qos@ff52c000 { + compatible = "syscon"; + reg = <0x0 0xff52c000 0x0 0x20>; + }; + + qos_emmc: qos@ff538000 { + compatible = "syscon"; + reg = <0x0 0xff538000 0x0 0x20>; + }; + + qos_nand: qos@ff538080 { + compatible = "syscon"; + reg = <0x0 0xff538080 0x0 0x20>; + }; + + qos_sdio: qos@ff538100 { + compatible = "syscon"; + reg = <0x0 0xff538100 0x0 0x20>; + }; + + qos_sfc: qos@ff538180 { + compatible = "syscon"; + reg = <0x0 0xff538180 0x0 0x20>; + }; + + qos_usb_host: qos@ff540000 { + compatible = "syscon"; + reg = <0x0 0xff540000 0x0 0x20>; + }; + + qos_usb_otg: qos@ff540080 { + compatible = "syscon"; + reg = <0x0 0xff540080 0x0 0x20>; + }; + + qos_isp_128: qos@ff548000 { + compatible = "syscon"; + reg = <0x0 0xff548000 0x0 0x20>; + }; + + qos_isp_rd: qos@ff548080 { + compatible = "syscon"; + reg = <0x0 0xff548080 0x0 0x20>; + }; + + qos_isp_wr: qos@ff548100 { + compatible = "syscon"; + reg = <0x0 0xff548100 0x0 0x20>; + }; + + qos_isp_m1: qos@ff548180 { + compatible = "syscon"; + reg = <0x0 0xff548180 0x0 0x20>; + }; + + qos_vip: qos@ff548200 { + compatible = "syscon"; + reg = <0x0 0xff548200 0x0 0x20>; + }; + + qos_rga_rd: qos@ff550000 { + compatible = "syscon"; + reg = <0x0 0xff550000 0x0 0x20>; + }; + + qos_rga_wr: qos@ff550080 { + compatible = "syscon"; + reg = <0x0 0xff550080 0x0 0x20>; + }; + + qos_vop_m0: qos@ff550100 { + compatible = "syscon"; + reg = <0x0 0xff550100 0x0 0x20>; + }; + + qos_vop_m1: qos@ff550180 { + compatible = "syscon"; + reg = <0x0 0xff550180 0x0 0x20>; + }; + + qos_vpu: qos@ff558000 { + compatible = "syscon"; + reg = <0x0 0xff558000 0x0 0x20>; + }; + + qos_vpu_r128: qos@ff558080 { + compatible = "syscon"; + reg = <0x0 0xff558080 0x0 0x20>; + }; + + dfi: dfi@ff610000 { + reg = <0x00 0xff610000 0x00 0x400>; + compatible = "rockchip,px30-dfi"; + rockchip,pmugrf = <&pmugrf>; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,px30-dmc"; + interrupts = ; + interrupt-names = "complete_irq"; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 666000 + SYS_STATUS_REBOOT 450000 + SYS_STATUS_SUSPEND 194000 + SYS_STATUS_VIDEO_1080P 450000 + SYS_STATUS_BOOST 666000 + SYS_STATUS_ISP 666000 + SYS_STATUS_PERFORMANCE 1056000 + >; + auto-min-freq = <328000>; + auto-freq-en = <1>; + #cooling-cells = <2>; + status = "disabled"; + + ddr_power_model: ddr_power_model { + compatible = "ddr_power_model"; + dynamic-power-coefficient = <120>; + static-power-coefficient = <200>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + dmc_fsp: dmc-fsp { + compatible = "rockchip,px30s-dmc-fsp"; + + debug_print_level = <0>; + phy_de_skew_en = <1>; + ddr3_params = <&ddr3_params>; + ddr4_params = <&ddr4_params>; + lpddr2_params = <&lpddr2_params>; + lpddr3_params = <&lpddr3_params>; + lpddr4_params = <&lpddr4_params>; + ddr_timing = <&ddr_timing>; + status = "okay"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,max-volt = <1150000>; + rockchip,evb-irdrop = <25000>; + + rockchip,pvtm-voltage-sel = < + 0 50000 0 + 50001 54000 1 + 54001 60000 2 + 60001 99999 3 + >; + rockchip,pvtm-ch = <0 0>; + + opp-194000000 { + opp-hz = /bits/ 64 <194000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <950000>; + opp-microvolt-L2 = <950000>; + opp-microvolt-L3 = <950000>; + }; + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <950000>; + opp-microvolt-L2 = <950000>; + opp-microvolt-L3 = <950000>; + }; + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <950000>; + opp-microvolt-L2 = <950000>; + opp-microvolt-L3 = <950000>; + }; + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <1050000>; + opp-microvolt-L0 = <1050000>; + opp-microvolt-L1 = <1000000>; + opp-microvolt-L2 = <975000>; + opp-microvolt-L3 = <950000>; + }; + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <1050000>; + opp-microvolt-L2 = <1025000>; + opp-microvolt-L3 = <1000000>; + status = "disabled"; + }; + }; + + px30s_dmc_opp_table: px30s-dmc-opp-table { + compatible = "operating-points-v2"; + + opp-194000000 { + opp-hz = /bits/ 64 <194000000>; + opp-microvolt = <950000>; + }; + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <950000>; + }; + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <950000>; + }; + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <950000>; + status = "disabled"; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <950000>; + status = "disabled"; + }; + /* 1056M only for LP4 */ + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <950000>; + status = "disabled"; + }; + }; + + dmcdbg: dmcdbg { + compatible = "rockchip,px30-dmcdbg"; + status = "okay"; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,polling-delay = <200>; /* milliseconds */ + }; + + pinctrl: pinctrl { + compatible = "rockchip,px30-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff040000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff040000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0_PMU>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff250000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff270000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff270000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_2ma: pcfg-pull-none-2ma { + bias-disable; + drive-strength = <2>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_4ma: pcfg-pull-up-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <0 RK_PB0 1 &pcfg_pull_none_smt>, + <0 RK_PB1 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <0 RK_PC2 1 &pcfg_pull_none_smt>, + <0 RK_PC3 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 RK_PB7 2 &pcfg_pull_none_smt>, + <2 RK_PC0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <1 RK_PB4 4 &pcfg_pull_none_smt>, + <1 RK_PB5 4 &pcfg_pull_none_smt>; + }; + }; + + tsadc { + tsadc_otp_gpio: tsadc_otp_pin: tsadc-otp-pin { + rockchip,pins = + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tsadc_otp_out: tsadc-otp-out { + rockchip,pins = + <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <0 RK_PB2 1 &pcfg_pull_up>, + <0 RK_PB3 1 &pcfg_pull_up>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <0 RK_PB4 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <0 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_up>, + <1 RK_PC0 1 &pcfg_pull_up>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = + <1 RK_PC2 1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = + <1 RK_PC3 1 &pcfg_pull_none>; + }; + + uart1_rts_gpio: uart1-rts-gpio { + rockchip,pins = + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart2-m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + <1 RK_PD2 2 &pcfg_pull_up>, + <1 RK_PD3 2 &pcfg_pull_up>; + }; + }; + + uart2-m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + <2 RK_PB4 2 &pcfg_pull_up>, + <2 RK_PB6 2 &pcfg_pull_up>; + }; + }; + + uart3-m0 { + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + <0 RK_PC0 2 &pcfg_pull_up>, + <0 RK_PC1 2 &pcfg_pull_up>; + }; + + uart3m0_cts: uart3m0-cts { + rockchip,pins = + <0 RK_PC2 2 &pcfg_pull_none>; + }; + + uart3m0_rts: uart3m0-rts { + rockchip,pins = + <0 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + uart3-m1 { + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + <1 RK_PB6 2 &pcfg_pull_up>, + <1 RK_PB7 2 &pcfg_pull_up>; + }; + + uart3m1_cts: uart3m1-cts { + rockchip,pins = + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + uart3m1_rts: uart3m1-rts { + rockchip,pins = + <1 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + <1 RK_PD4 2 &pcfg_pull_up>, + <1 RK_PD5 2 &pcfg_pull_up>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = + <1 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + uart5 { + uart5_xfer: uart5-xfer { + rockchip,pins = + <3 RK_PA2 4 &pcfg_pull_up>, + <3 RK_PA1 4 &pcfg_pull_up>; + }; + + uart5_cts: uart5-cts { + rockchip,pins = + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + uart5_rts: uart5-rts { + rockchip,pins = + <3 RK_PA5 4 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <1 RK_PB7 3 &pcfg_pull_up_4ma>; + }; + + spi0_csn: spi0-csn { + rockchip,pins = + <1 RK_PB6 3 &pcfg_pull_up_4ma>; + }; + + spi0_miso: spi0-miso { + rockchip,pins = + <1 RK_PB5 3 &pcfg_pull_up_4ma>; + }; + + spi0_mosi: spi0-mosi { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_up_4ma>; + }; + + spi0_clk_hs: spi0-clk-hs { + rockchip,pins = + <1 RK_PB7 3 &pcfg_pull_up_8ma>; + }; + + spi0_miso_hs: spi0-miso-hs { + rockchip,pins = + <1 RK_PB5 3 &pcfg_pull_up_8ma>; + }; + + spi0_mosi_hs: spi0-mosi-hs { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_up_8ma>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <3 RK_PB7 4 &pcfg_pull_up_4ma>; + }; + + spi1_csn0: spi1-csn0 { + rockchip,pins = + <3 RK_PB1 4 &pcfg_pull_up_4ma>; + }; + + spi1_csn1: spi1-csn1 { + rockchip,pins = + <3 RK_PB2 2 &pcfg_pull_up_4ma>; + }; + + spi1_miso: spi1-miso { + rockchip,pins = + <3 RK_PB6 4 &pcfg_pull_up_4ma>; + }; + + spi1_mosi: spi1-mosi { + rockchip,pins = + <3 RK_PB4 4 &pcfg_pull_up_4ma>; + }; + + spi1_clk_hs: spi1-clk-hs { + rockchip,pins = + <3 RK_PB7 4 &pcfg_pull_up_8ma>; + }; + + spi1_miso_hs: spi1-miso-hs { + rockchip,pins = + <3 RK_PB6 4 &pcfg_pull_up_8ma>; + }; + + spi1_mosi_hs: spi1-mosi-hs { + rockchip,pins = + <3 RK_PB4 4 &pcfg_pull_up_8ma>; + }; + }; + + pdm { + pdm_clk0m0: pdm-clk0m0 { + rockchip,pins = + <3 RK_PC6 2 &pcfg_pull_none>; + }; + + pdm_clk0m1: pdm-clk0m1 { + rockchip,pins = + <2 RK_PC6 1 &pcfg_pull_none>; + }; + + pdm_clk1: pdm-clk1 { + rockchip,pins = + <3 RK_PC7 2 &pcfg_pull_none>; + }; + + pdm_sdi0m0: pdm-sdi0m0 { + rockchip,pins = + <3 RK_PD3 2 &pcfg_pull_none>; + }; + + pdm_sdi0m1: pdm-sdi0m1 { + rockchip,pins = + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + <3 RK_PD0 2 &pcfg_pull_none>; + }; + + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + <3 RK_PD1 2 &pcfg_pull_none>; + }; + + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + <3 RK_PD2 2 &pcfg_pull_none>; + }; + + pdm_clk0m0_sleep: pdm-clk0m0-sleep { + rockchip,pins = + <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_clk0m_sleep1: pdm-clk0m1-sleep { + rockchip,pins = + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_clk1_sleep: pdm-clk1-sleep { + rockchip,pins = + <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { + rockchip,pins = + <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { + rockchip,pins = + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_sdi1_sleep: pdm-sdi1-sleep { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_sdi2_sleep: pdm-sdi2-sleep { + rockchip,pins = + <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdm_sdi3_sleep: pdm-sdi3-sleep { + rockchip,pins = + <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s0 { + i2s0_8ch_mclk: i2s0-8ch-mclk { + rockchip,pins = + <3 RK_PC1 2 &pcfg_pull_none_smt>; + }; + + i2s0_8ch_sclktx: i2s0-8ch-sclktx { + rockchip,pins = + <3 RK_PC3 2 &pcfg_pull_none_smt>; + }; + + i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { + rockchip,pins = + <3 RK_PB4 2 &pcfg_pull_none_smt>; + }; + + i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { + rockchip,pins = + <3 RK_PC2 2 &pcfg_pull_none_smt>; + }; + + i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { + rockchip,pins = + <3 RK_PB5 2 &pcfg_pull_none_smt>; + }; + + i2s0_8ch_sdo0: i2s0-8ch-sdo0 { + rockchip,pins = + <3 RK_PC4 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdo1: i2s0-8ch-sdo1 { + rockchip,pins = + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdo2: i2s0-8ch-sdo2 { + rockchip,pins = + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdo3: i2s0-8ch-sdo3 { + rockchip,pins = + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdi0: i2s0-8ch-sdi0 { + rockchip,pins = + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdi1: i2s0-8ch-sdi1 { + rockchip,pins = + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdi2: i2s0-8ch-sdi2 { + rockchip,pins = + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + i2s0_8ch_sdi3: i2s0-8ch-sdi3 { + rockchip,pins = + <3 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_2ch_mclk: i2s1-2ch-mclk { + rockchip,pins = + <2 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + i2s1_2ch_sclk: i2s1-2ch-sclk { + rockchip,pins = + <2 RK_PC2 1 &pcfg_pull_none_smt>; + }; + + i2s1_2ch_lrck: i2s1-2ch-lrck { + rockchip,pins = + <2 RK_PC1 1 &pcfg_pull_none_smt>; + }; + + i2s1_2ch_sdi: i2s1-2ch-sdi { + rockchip,pins = + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + i2s1_2ch_sdo: i2s1-2ch-sdo { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + i2s2_2ch_mclk: i2s2-2ch-mclk { + rockchip,pins = + <3 RK_PA1 2 &pcfg_pull_none_smt>; + }; + + i2s2_2ch_sclk: i2s2-2ch-sclk { + rockchip,pins = + <3 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + i2s2_2ch_lrck: i2s2-2ch-lrck { + rockchip,pins = + <3 RK_PA3 2 &pcfg_pull_none_smt>; + }; + + i2s2_2ch_sdi: i2s2-2ch-sdi { + rockchip,pins = + <3 RK_PA5 2 &pcfg_pull_none>; + }; + + i2s2_2ch_sdo: i2s2-2ch-sdo { + rockchip,pins = + <3 RK_PA7 2 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <1 RK_PD6 1 &pcfg_pull_none_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <1 RK_PD7 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_det: sdmmc-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <1 RK_PD2 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <1 RK_PD2 1 &pcfg_pull_up_8ma>, + <1 RK_PD3 1 &pcfg_pull_up_8ma>, + <1 RK_PD4 1 &pcfg_pull_up_8ma>, + <1 RK_PD5 1 &pcfg_pull_up_8ma>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = + <1 RK_PC5 1 &pcfg_pull_none>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = + <1 RK_PC4 1 &pcfg_pull_up>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = + <1 RK_PC6 1 &pcfg_pull_up>, + <1 RK_PC7 1 &pcfg_pull_up>, + <1 RK_PD0 1 &pcfg_pull_up>, + <1 RK_PD1 1 &pcfg_pull_up>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_none_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <1 RK_PB2 2 &pcfg_pull_up_8ma>; + }; + + emmc_rstnout: emmc-rstnout { + rockchip,pins = + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = + <1 RK_PA0 2 &pcfg_pull_up_8ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <1 RK_PA0 2 &pcfg_pull_up_8ma>, + <1 RK_PA1 2 &pcfg_pull_up_8ma>, + <1 RK_PA2 2 &pcfg_pull_up_8ma>, + <1 RK_PA3 2 &pcfg_pull_up_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <1 RK_PA0 2 &pcfg_pull_up_8ma>, + <1 RK_PA1 2 &pcfg_pull_up_8ma>, + <1 RK_PA2 2 &pcfg_pull_up_8ma>, + <1 RK_PA3 2 &pcfg_pull_up_8ma>, + <1 RK_PA4 2 &pcfg_pull_up_8ma>, + <1 RK_PA5 2 &pcfg_pull_up_8ma>, + <1 RK_PA6 2 &pcfg_pull_up_8ma>, + <1 RK_PA7 2 &pcfg_pull_up_8ma>; + }; + }; + + flash { + flash_cs0: flash-cs0 { + rockchip,pins = + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + flash_dqs: flash-dqs { + rockchip,pins = + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + flash_ale: flash-ale { + rockchip,pins = + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + flash_cle: flash-cle { + rockchip,pins = + <1 RK_PB4 1 &pcfg_pull_none>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = + <1 RK_PB5 1 &pcfg_pull_none>; + }; + + flash_csl: flash-csl { + rockchip,pins = + <1 RK_PB6 1 &pcfg_pull_none>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = + <1 RK_PB7 1 &pcfg_pull_none>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = + <1 RK_PA0 1 &pcfg_pull_up_12ma>, + <1 RK_PA1 1 &pcfg_pull_up_12ma>, + <1 RK_PA2 1 &pcfg_pull_up_12ma>, + <1 RK_PA3 1 &pcfg_pull_up_12ma>, + <1 RK_PA4 1 &pcfg_pull_up_12ma>, + <1 RK_PA5 1 &pcfg_pull_up_12ma>, + <1 RK_PA6 1 &pcfg_pull_up_12ma>, + <1 RK_PA7 1 &pcfg_pull_up_12ma>; + }; + }; + + lcdc { + lcdc_m0_rgb_pins: lcdc-m0-rgb-pins { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ + <3 RK_PA1 1 &pcfg_pull_none_8ma>, /* LCDC_HSYNC */ + <3 RK_PA2 1 &pcfg_pull_none_8ma>, /* LCDC_VSYNC */ + <3 RK_PA3 1 &pcfg_pull_none_8ma>, /* LCDC_DEN */ + <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ + <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* LCDC_D1 */ + <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ + <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* LCDC_D3 */ + <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* LCDC_D4 */ + <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* LCDC_D5 */ + <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ + <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ + <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* LCDC_D8 */ + <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ + <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* LCDC_D10 */ + <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* LCDC_D11 */ + <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ + <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ + <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ + <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ + <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ + <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ + <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ + <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ + <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ + <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ + <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ + <3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ + }; + + lcdc_m0_sleep_pins: lcdc-m0-sleep-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_HSYNC */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_VSYNC */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DEN */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D1 */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D3 */ + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D4 */ + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D5 */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ + <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D8 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ + <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */ + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <0 RK_PB7 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <2 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = + <0 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + pwm4_pin: pwm4-pin { + rockchip,pins = + <3 RK_PC2 3 &pcfg_pull_none>; + }; + }; + + pwm5 { + pwm5_pin: pwm5-pin { + rockchip,pins = + <3 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + pwm6 { + pwm6_pin: pwm6-pin { + rockchip,pins = + <3 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + pwm7 { + pwm7_pin: pwm7-pin { + rockchip,pins = + <3 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + gmac { + rmii_pins: rmii-pins { + rockchip,pins = + <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ + <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ + <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ + <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ + <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ + <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ + <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ + <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ + <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ + }; + + mac_refclk_12ma: mac-refclk-12ma { + rockchip,pins = + <2 RK_PB2 2 &pcfg_pull_none_12ma>; + }; + + mac_refclk: mac-refclk { + rockchip,pins = + <2 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + cif-m0 { + cif_clkout_m0: cif-clkout-m0 { + rockchip,pins = + <2 RK_PB3 1 &pcfg_pull_none_12ma>;/* cif_clkout */ + }; + + dvp_d2d9_m0: dvp-d2d9-m0 { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ + <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ + <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ + <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ + <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ + <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ + <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ + <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ + <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ + <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ + <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ + <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ + }; + + dvp_d0d1_m0: dvp-d0d1-m0 { + rockchip,pins = + <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ + <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ + }; + + dvp_d10d11_m0:d10-d11-m0 { + rockchip,pins = + <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ + <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ + }; + }; + + cif-m1 { + cif_clkout_m1: cif-clkout-m1 { + rockchip,pins = + <3 RK_PD0 3 &pcfg_pull_none>; + }; + + dvp_d2d9_m1: dvp-d2d9-m1 { + rockchip,pins = + <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ + <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ + <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ + <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ + <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ + <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ + <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ + <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ + <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ + <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ + <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ + <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ + }; + + dvp_d0d1_m1: dvp-d0d1-m1 { + rockchip,pins = + <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ + <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ + }; + + dvp_d10d11_m1:d10-d11-m1 { + rockchip,pins = + <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ + <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ + }; + }; + + isp { + isp_prelight: isp-prelight { + rockchip,pins = + <3 RK_PD1 4 &pcfg_pull_none>; + }; + }; + }; +}; +#include "px30s-pinctrl.dtsi" diff --git a/px30s-dram-default-timing.dtsi b/px30s-dram-default-timing.dtsi new file mode 100644 index 0000000..aefe70a --- /dev/null +++ b/px30s-dram-default-timing.dtsi @@ -0,0 +1,379 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/ { + ddr3_params: ddr3-params { + /* version information */ + version = <0x101>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <666>; + freq_1 = <194>; + freq_2 = <328>; + freq_3 = <666>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = <300>; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <33>; + phy_ca_drv_odten = <33>; + phy_clk_drv_odten = <33>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <33>; + phy_ca_drv_odtoff = <33>; + phy_clk_drv_odtoff = <33>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <120>; + phy_odt = <133>; + phy_odt_puup_en = <1>; + phy_odt_pudn_en = <1>; + /* odt enable freq */ + dram_dq_odt_en_freq = <333>; + phy_odt_en_freq = <333>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0xf>; + phy_ca_sr_odten = <0x3>; + phy_clk_sr_odten = <0x3>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0xf>; + phy_ca_sr_odtoff = <0x3>; + phy_clk_sr_odtoff = <0x3>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + }; + + ddr4_params: ddr4-params { + /* version information */ + version = <0x101>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <666>; + freq_1 = <194>; + freq_2 = <328>; + freq_3 = <666>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = <500>; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <33>; + phy_ca_drv_odten = <33>; + phy_clk_drv_odten = <33>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <33>; + phy_ca_drv_odtoff = <33>; + phy_clk_drv_odtoff = <33>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <120>; + phy_odt = <121>; + phy_odt_puup_en = <1>; + phy_odt_pudn_en = <1>; + /* odt enable freq */ + dram_dq_odt_en_freq = <500>; + phy_odt_en_freq = <500>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0xe>; + phy_ca_sr_odten = <0x1>; + phy_clk_sr_odten = <0x1>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0xe>; + phy_ca_sr_odtoff = <0x1>; + phy_clk_sr_odtoff = <0x1>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x2 << 6) | (0x3 << 4) | (0x0 << 2) | (0x1 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <(((3 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 0) | \ + ((2 << 0 | 0 << 2 | 2 << 4 | 1 << 6) << 8) | \ + ((3 << 0 | 2 << 2 | 1 << 4 | 2 << 6) << 16) | \ + ((3 << 0 | 0 << 2 | 1 << 4 | 0 << 6) << 24))>; + dq_map_cs0_dq_h = <(((2 << 0 | 0 << 2 | 0 << 4 | 1 << 6) << 0) | \ + ((3 << 0 | 3 << 2 | 2 << 4 | 1 << 6) << 8) | \ + ((1 << 0 | 3 << 2 | 2 << 4 | 0 << 6) << 16) | \ + ((3 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 24))>; + dq_map_cs1_dq_l = <(((2 << 0 | 1 << 2 | 2 << 4 | 0 << 6) << 0) | \ + ((3 << 0 | 1 << 2 | 3 << 4 | 0 << 6) << 8) | \ + ((2 << 0 | 3 << 2 | 0 << 4 | 3 << 6) << 16) | \ + ((2 << 0 | 1 << 2 | 0 << 4 | 1 << 6) << 24))>; + dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 1 << 4 | 0 << 6) << 0) | \ + ((2 << 0 | 2 << 2 | 3 << 4 | 0 << 6) << 8) | \ + ((0 << 0 | 2 << 2 | 3 << 4 | 1 << 6) << 16) | \ + ((2 << 0 | 0 << 2 | 3 << 4 | 1 << 6) << 24))>; + }; + + lpddr2_params: lpddr2-params { + /* version information */ + version = <0x101>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <528>; + freq_1 = <194>; + freq_2 = <328>; + freq_3 = <528>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = ; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <33>; + phy_ca_drv_odten = <33>; + phy_clk_drv_odten = <33>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <33>; + phy_ca_drv_odtoff = <33>; + phy_clk_drv_odtoff = <33>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <0>; + phy_odt = <0>; + phy_odt_puup_en = <0>; + phy_odt_pudn_en = <0>; + /* odt enable freq */ + dram_dq_odt_en_freq = <625>; + phy_odt_en_freq = <625>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0xe>; + phy_ca_sr_odten = <0x1>; + phy_clk_sr_odten = <0x1>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0xe>; + phy_ca_sr_odtoff = <0x1>; + phy_clk_sr_odtoff = <0x1>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + }; + + lpddr3_params: lpddr3-params { + /* version information */ + version = <0x101>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <666>; + freq_1 = <194>; + freq_2 = <328>; + freq_3 = <666>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = ; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <33>; + phy_ca_drv_odten = <33>; + phy_clk_drv_odten = <33>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <33>; + phy_ca_drv_odtoff = <33>; + phy_clk_drv_odtoff = <33>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <240>; + phy_odt = <121>; + phy_odt_puup_en = <1>; + phy_odt_pudn_en = <1>; + /* odt enable freq */ + dram_dq_odt_en_freq = <333>; + phy_odt_en_freq = <333>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0x0>; + phy_ca_sr_odten = <0x0>; + phy_clk_sr_odten = <0x0>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0x0>; + phy_ca_sr_odtoff = <0x0>; + phy_clk_sr_odtoff = <0x0>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + }; + + lpddr4_params: lpddr4-params { + /* version information */ + version = <0x101>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <666>; + freq_1 = <194>; + freq_2 = <328>; + freq_3 = <666>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = ; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <44>; + phy_ca_drv_odten = <38>; + phy_clk_drv_odten = <47>; + dram_dq_drv_odten = <40>; + /* drv when odt off */ + phy_dq_drv_odtoff = <44>; + phy_ca_drv_odtoff = <38>; + phy_clk_drv_odtoff = <47>; + dram_dq_drv_odtoff = <40>; + /* odt info */ + dram_odt = <60>; + phy_odt = <80>; + phy_odt_puup_en = ; + phy_odt_pudn_en = ; + /* odt enable freq */ + dram_dq_odt_en_freq = <800>; + phy_odt_en_freq = <800>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0x7>; + phy_ca_sr_odten = <0x1>; + phy_clk_sr_odten = <0x1>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0x7>; + phy_ca_sr_odtoff = <0x1>; + phy_clk_sr_odtoff = <0x1>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + /* lp4 odt info */ + lp4_ca_odt = <120>; + lp4_drv_pu_cal_odten = ; + lp4_drv_pu_cal_odtoff = ; + phy_lp4_drv_pulldown_en_odten = <0>; + phy_lp4_drv_pulldown_en_odtoff = <0>; + /* lp4 odt enable freq */ + lp4_ca_odt_en_freq = <800>; + /* lp4 cs drv info and ca odt info */ + phy_lp4_cs_drv_odten = <0>; + phy_lp4_cs_drv_odtoff = <0>; + lp4_odte_ck_en = <1>; + lp4_odte_cs_en = <1>; + lp4_odtd_ca_en = <0>; + /* lp4 vref info when odt enable */ + phy_lp4_dq_vref_odten = <200>; + lp4_dq_vref_odten = <276>; + lp4_ca_vref_odten = <380>; + /* lp4 vref info when odt disable */ + phy_lp4_dq_vref_odtoff = <420>; + lp4_dq_vref_odtoff = <420>; + lp4_ca_vref_odtoff = <420>; + }; +}; + diff --git a/px30s-pinctrl.dtsi b/px30s-pinctrl.dtsi new file mode 100644 index 0000000..5d8869a --- /dev/null +++ b/px30s-pinctrl.dtsi @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + */ + +&pinctrl { + /* default for px30 and 4ma for px30s */ + pcfg_pull_none_n_4ma: pcfg-pull-none-n-4ma { + bias-disable; + drive-strength-s = <4>; + }; + pcfg_pull_up_n_4ma: pcfg-pull-up-n-4ma { + bias-pull-up; + drive-strength-s = <4>; + }; + pcfg_pull_down_n_4ma: pcfg-pull-down-n-4ma { + bias-pull-down; + drive-strength-s = <4>; + }; + + /* default for px30 and 6ma for px30s */ + pcfg_pull_none_0_6ma: pcfg-pull-none-0-6ma { + bias-disable; + drive-strength-s = <6>; + }; + pcfg_pull_up_0_6ma: pcfg-pull-up-0-6ma { + bias-pull-up; + drive-strength-s = <6>; + }; + pcfg_pull_down_0_6ma: pcfg-pull-down-0-6ma { + bias-pull-down; + drive-strength-s = <6>; + }; + + /* 4ma for px30 and 6ma for px30s */ + pcfg_pull_none_4_6ma: pcfg-pull-none-4-6ma { + bias-disable; + drive-strength = <4>; + drive-strength-s = <6>; + }; + pcfg_pull_up_4_6ma: pcfg-pull-up-4-6ma { + bias-pull-up; + drive-strength = <4>; + drive-strength-s = <6>; + }; + pcfg_pull_down_4_6ma: pcfg-pull-down-4-6ma { + bias-pull-down; + drive-strength = <4>; + drive-strength-s = <6>; + }; + + /* 8ma for px30 and 6ma for px30s */ + pcfg_pull_none_8_6ma: pcfg-pull-none-8-6ma { + bias-disable; + drive-strength = <8>; + drive-strength-s = <6>; + }; + pcfg_pull_up_8_6ma: pcfg-pull-up-8-6ma { + bias-pull-up; + drive-strength = <8>; + drive-strength-s = <6>; + }; + pcfg_pull_down_8_6ma: pcfg-pull-down-8-6ma { + bias-pull-down; + drive-strength = <8>; + drive-strength-s = <6>; + }; + + /* 8ma for px30 and 4ma for px30s */ + pcfg_pull_none_8_4ma: pcfg-pull-none-8-4ma { + bias-disable; + drive-strength = <8>; + drive-strength-s = <4>; + }; + pcfg_pull_up_8_4ma: pcfg-pull-up-8-4ma { + bias-pull-up; + drive-strength = <8>; + drive-strength-s = <4>; + }; + pcfg_pull_down_8_4ma: pcfg-pull-down-8-4ma { + bias-pull-down; + drive-strength = <8>; + drive-strength-s = <4>; + }; + + /* 12ma for px30 and 4ma for px30s */ + pcfg_pull_none_12_4ma: pcfg-pull-none-12-4ma { + bias-disable; + drive-strength = <12>; + drive-strength-s = <4>; + }; + pcfg_pull_up_12_4ma: pcfg-pull-up-12-4ma { + bias-pull-up; + drive-strength = <12>; + drive-strength-s = <4>; + }; + pcfg_pull_down_12_4ma: pcfg-pull-down-12-4ma { + bias-pull-down; + drive-strength = <12>; + drive-strength-s = <4>; + }; + + /* 12ma for px30 and 6ma for px30s */ + pcfg_pull_none_12_6ma: pcfg-pull-none-12-6ma { + bias-disable; + drive-strength = <12>; + drive-strength-s = <6>; + }; + pcfg_pull_up_12_6ma: pcfg-pull-up-12-6ma { + bias-pull-up; + drive-strength = <12>; + drive-strength-s = <6>; + }; + pcfg_pull_down_12_6ma: pcfg-pull-down-12-6ma { + bias-pull-down; + drive-strength = <12>; + drive-strength-s = <6>; + }; +}; + +&pinctrl { + /delete-node/ emmc; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_none_8_6ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <1 RK_PB2 2 &pcfg_pull_up_8_6ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + emmc_rstnout: emmc-rstnout { + rockchip,pins = + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = + <1 RK_PA0 2 &pcfg_pull_up_8_6ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <1 RK_PA0 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA1 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA2 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA3 2 &pcfg_pull_up_8_6ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <1 RK_PA0 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA1 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA2 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA3 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA4 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA5 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA6 2 &pcfg_pull_up_8_6ma>, + <1 RK_PA7 2 &pcfg_pull_up_8_6ma>; + }; + }; +}; diff --git a/rk-stb-ir-keymap.dtsi b/rk-stb-ir-keymap.dtsi new file mode 100644 index 0000000..0c0d923 --- /dev/null +++ b/rk-stb-ir-keymap.dtsi @@ -0,0 +1,394 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ +#include + +&pwm3 { + ir_key1 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + /*for IPTV ltjc*/ + ir_key2 { + rockchip,usercode = <0xc43b>; + rockchip,key_table = + <0x7e KEY_REPLY>, + <0x7f KEY_BACK>, + <0x7a KEY_UP>, + <0x78 KEY_DOWN>, + <0x7b KEY_LEFT>, + <0x79 KEY_RIGHT>, + <0x66 KEY_VOLUMEUP>, + <0x65 KEY_VOLUMEDOWN>, + <0x69 KEY_POWER>, + <0x64 KEY_MUTE>, + <0x76 KEY_1>, + <0x75 KEY_2>, + <0x74 KEY_3>, + <0x73 KEY_4>, + <0x72 KEY_5>, + <0x71 KEY_6>, + <0x70 KEY_7>, + <0x6f KEY_8>, + <0x6e KEY_9>, + <0x77 KEY_0>, + <0x7c KEY_PAGEDOWN>, + <0x7d KEY_PAGEUP>, + <0x6a KEY_SETUP>, + <0x68 KEY_CHANNEL_UP>, + <0x67 KEY_CHANNEL_DN>, + <0x39 KEY_PORTAL>, + <0x29 KEY_HOME_PAGE>, + <0x33 KEY_CH_CUT_BACK>, + <0x34 KEY_LOCAL>, + <0x2d KEY_REVIEW>, + <0x2c KEY_ON_DEMAND>, + <0x2b KEY_INFO1>, + <0x2e KEY_DIRECT_SEEDING>, + <0x2d KEY_REVIEW>, + <0x2c KEY_ON_DEMAND>, + <0x2b KEY_INFO1>, + <0x63 KEY_SOUND1>, + <0x6c KEY_X1>, + <0x6d KEY_X2>, + <0x62 KEY_PLAYPAUSE>, + <0x6b KEY_EQUAL>, + <0x61 KEY_FASTFORWARD>, + <0x60 KEY_REWIND>, + <0x3b KEY_STOP>, + <0x35 KEY_BLUE>, + <0x36 KEY_YELLOW>, + <0x37 KEY_GREEN>, + <0x38 KEY_RED>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; + + /* for IPTV */ + ir_key4 { + rockchip,usercode = <0x4db2>; + rockchip,key_table = + <0x31 KEY_REPLY>, + <0x3a KEY_BACK>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x7f KEY_VOLUMEUP>, + <0xfe KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x6d KEY_1>, + <0x6c KEY_2>, + <0x33 KEY_3>, + <0x71 KEY_4>, + <0x70 KEY_5>, + <0x37 KEY_6>, + <0x75 KEY_7>, + <0x74 KEY_8>, + <0x3b KEY_9>, + <0x78 KEY_0>, + <0x73 KEY_PAGEDOWN>, + <0x22 KEY_PAGEUP>, + <0x72 KEY_SETUP>, + <0x7a KEY_CHANNEL_UP>, + <0x79 KEY_CHANNEL_DN>, + <0x77 KEY_HOME_PAGE>, + <0x29 KEY_CH_CUT_BACK>, + <0x32 KEY_DIRECT_SEEDING>, + <0x6e KEY_REVIEW>, + <0x7c KEY_ON_DEMAND>, + <0x3c KEY_INFO1>, + <0x67 KEY_SOUND1>, + <0x25 KEY_X1>, + <0x2f KEY_X2>, + <0x7d KEY_LOCAL>, + <0x6a KEY_PLAYPAUSE>, + <0x0b KEY_EQUAL>; + }; + + /* for CMCC */ + ir_key5 { + rockchip,usercode = <0x1608>; + rockchip,key_table = + <0x4c KEY_REPLY>, + <0x4d KEY_BACK>, + <0x4b KEY_UP>, + <0x4a KEY_DOWN>, + <0x49 KEY_LEFT>, + <0x48 KEY_RIGHT>, + <0x4e KEY_HOME>, + <0x0b KEY_VOLUMEUP>, + <0x0c KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x45 KEY_MUTE>, + <0x44 KEY_MENU>, + <0x78 KEY_1>, + <0x77 KEY_2>, + <0x76 KEY_3>, + <0x75 KEY_4>, + <0x74 KEY_5>, + <0x73 KEY_6>, + <0x72 KEY_7>, + <0x71 KEY_8>, + <0x70 KEY_9>, + <0x79 KEY_0>, + <0x43 KEY_EQUAL>, + <0x72 KEY_X1>, + <0x5f KEY_SETUP>, + <0x25 KEY_DIRECT_SEEDING>, + <0x24 KEY_REVIEW>, + <0x21 KEY_ON_DEMAND>, + <0x20 KEY_INFO1>; + }; + + /* rk new remote */ + ir_key6 { + rockchip,usercode = <0xfe01>; + rockchip,key_table = + <0xec KEY_REPLY>, + <0xe6 KEY_BACK>, + <0xe9 KEY_UP>, + <0xe5 KEY_DOWN>, + <0xae KEY_LEFT>, + <0xaf KEY_RIGHT>, + <0xee KEY_HOME>, + <0xe7 KEY_VOLUMEUP>, + <0xef KEY_VOLUMEDOWN>, + <0xbf KEY_POWER>, + <0xbe KEY_MUTE>, + <0xb3 KEY_MENU>, + <0xff 388>, + <0xb1 KEY_1>, + <0xf2 KEY_2>, + <0xf3 KEY_3>, + <0xb5 KEY_4>, + <0xf6 KEY_5>, + <0xf7 KEY_6>, + <0xb9 KEY_7>, + <0xfa KEY_8>, + <0xfb KEY_9>, + <0xfe KEY_0>, + <0xbd KEY_EQUAL>, + <0xbc KEY_SETUP>, + <0xf0 KEY_LOCAL>, + <0x0d KEY_DIRECT_SEEDING>, + <0x0c KEY_REVIEW>, + <0x0b KEY_ON_DEMAND>, + <0x0a KEY_INFO1>, + <0x0e KEY_CH_CUT_BACK>; + }; + + /* for IPTV gd */ + ir_key7 { + rockchip,usercode = <0x4cb3>; + rockchip,key_table = + <0x31 KEY_REPLY>, + <0x3a KEY_BACK>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x7f KEY_VOLUMEUP>, + <0x7e KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x6d KEY_1>, + <0x6c KEY_2>, + <0x33 KEY_3>, + <0x71 KEY_4>, + <0x70 KEY_5>, + <0x37 KEY_6>, + <0x75 KEY_7>, + <0x74 KEY_8>, + <0x3b KEY_9>, + <0x78 KEY_0>, + <0x73 KEY_PAGEDOWN>, + <0x22 KEY_PAGEUP>, + <0x72 KEY_SETUP>, + <0x7a KEY_CHANNEL_UP>, + <0x79 KEY_CHANNEL_DN>, + <0x77 KEY_HOME_PAGE>, + <0x29 KEY_CH_CUT_BACK>, + <0x32 KEY_DIRECT_SEEDING>, + <0x6e KEY_REVIEW>, + <0x7c KEY_ON_DEMAND>, + <0x3c KEY_INFO1>, + <0x67 KEY_SOUND1>, + <0x25 KEY_X1>, + <0x2f KEY_X2>, + <0x7d KEY_LOCAL>, + <0x6a KEY_PLAYPAUSE>, + <0x0b KEY_EQUAL>; + }; + + /* for CMCC */ + ir_key8 { + rockchip,usercode = <0xdd22>; + rockchip,key_table = + <0x31 KEY_REPLY>, + <0x6a KEY_BACK>, + <0x35 KEY_UP>, + <0x2d KEY_DOWN>, + <0x66 KEY_LEFT>, + <0x3e KEY_RIGHT>, + <0x7f KEY_VOLUMEUP>, + <0x7e KEY_VOLUMEDOWN>, + <0x23 KEY_POWER>, + <0x63 KEY_MUTE>, + <0x6d KEY_1>, + <0x6c KEY_2>, + <0x33 KEY_3>, + <0x71 KEY_4>, + <0x70 KEY_5>, + <0x37 KEY_6>, + <0x75 KEY_7>, + <0x74 KEY_8>, + <0x3b KEY_9>, + <0x78 KEY_0>, + <0x73 KEY_PAGEDOWN>, + <0x22 KEY_PAGEUP>, + <0x72 KEY_SETUP>, + <0x7a KEY_CHANNEL_UP>, + <0x79 KEY_CHANNEL_DN>, + <0x77 KEY_HOME_PAGE>, + <0x2f KEY_CH_CUT_BACK>, + <0x32 KEY_DIRECT_SEEDING>, + <0x6e KEY_REVIEW>, + <0x7c KEY_ON_DEMAND>, + <0x3c KEY_INFO1>, + <0x3a KEY_HELP>, + <0x67 KEY_SOUND1>, + <0x25 KEY_X2>, + <0x7d KEY_MENU>, + <0x3f KEY_EQUAL>, + <0x29 388>, + <0x26 KEY_PLAYPAUSE>, + <0x76 401>, + <0x7b 400>, + <0x69 66>; + }; + + /* for BJLT IPTV */ + ir_key9 { + rockchip,usercode = <0x3bc4>; + rockchip,key_table = + <0x81 KEY_REPLY>, + <0x80 KEY_BACK>, + <0x85 KEY_UP>, + <0x87 KEY_DOWN>, + <0x84 KEY_LEFT>, + <0x86 KEY_RIGHT>, + <0x99 KEY_VOLUMEUP>, + <0x9a KEY_VOLUMEDOWN>, + <0x96 KEY_POWER>, + <0x9b KEY_MUTE>, + <0x89 KEY_1>, + <0x8a KEY_2>, + <0x8b KEY_3>, + <0x8c KEY_4>, + <0x8d KEY_5>, + <0x8e KEY_6>, + <0x8f KEY_7>, + <0x90 KEY_8>, + <0x91 KEY_9>, + <0x88 KEY_0>, + <0x83 KEY_PAGEDOWN>, + <0x82 KEY_PAGEUP>, + <0x95 KEY_SETUP>, + <0x97 KEY_CHANNEL_UP>, + <0x98 KEY_CHANNEL_DN>, + <0xc6 KEY_LOCAL>, + <0xd6 KEY_HOME_PAGE>, + <0xd7 KEY_TRACK>, + <0xcc KEY_CH_CUT_BACK>, + <0xc3 KEY_INTERX>, + <0xd1 KEY_DIRECT_SEEDING>, + <0xd2 KEY_REVIEW>, + <0xd3 KEY_ON_DEMAND>, + <0xd4 KEY_INFO1>, + <0xc7 KEY_DIRECT_SEEDING>, + <0xc8 KEY_REVIEW>, + <0xc9 KEY_ON_DEMAND>, + <0xca KEY_INFO1>, + <0xcd KEY_FAVORITE>, + <0xce KEY_CHANNEL_POS>, + <0xcf KEY_HELP>, + <0xd0 KEY_EVENT>, + <0x9c KEY_SOUND1>, + <0x93 KEY_X1>, + <0x92 KEY_X2>, + <0xc0 KEY_END>, + <0xc1 KEY_GO_BEGINNING>, + <0x9d KEY_PLAYPAUSE>, + <0xc4 KEY_STOP>, + <0x94 KEY_EQUAL>, + <0x9e KEY_YELLOW>, + <0x9f KEY_BLUE>, + <0xcb KEY_APPLICATION>, + <0xc5 KEY_POS>; + }; +}; diff --git a/rk1808-dram-default-timing.dtsi b/rk1808-dram-default-timing.dtsi new file mode 100644 index 0000000..0fa79e2 --- /dev/null +++ b/rk1808-dram-default-timing.dtsi @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr2_speed_bin = ; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr2_dll_dis_freq = <300>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr2_odt_dis_freq = <100>; + phy_ddr2_odt_dis_freq = <100>; + ddr2_drv = ; + ddr2_odt = ; + phy_ddr2_ca_drv = ; + phy_ddr2_ck_drv = ; + phy_ddr2_dq_drv = ; + phy_ddr2_odt = ; + + ddr3_odt_dis_freq = <400>; + phy_ddr3_odt_dis_freq = <400>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + phy_lpddr2_odt_dis_freq = <666>; + lpddr2_drv = ; + phy_lpddr2_ca_drv = ; + phy_lpddr2_ck_drv = ; + phy_lpddr2_dq_drv = ; + phy_lpddr2_odt = ; + + lpddr3_odt_dis_freq = <400>; + phy_lpddr3_odt_dis_freq = <400>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <666>; + phy_ddr4_odt_dis_freq = <666>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* + * CA de-skew, one step is 15ps, range 0-31 + * DDR3 CA define is different from others(DDR4/LPDDR2/LPDDR3). + */ + a0_ddr3a9_de-skew = <7>; + a1_ddr3a14_de-skew = <7>; + a2_ddr3a13_de-skew = <7>; + a3_ddr3a11_de-skew = <7>; + a4_ddr3a2_de-skew = <7>; + a5_ddr3a4_de-skew = <7>; + a6_ddr3a3_de-skew = <7>; + a7_ddr3a6_de-skew = <7>; + a8_ddr3a5_de-skew = <7>; + a9_ddr3a1_de-skew = <7>; + a10_ddr3a0_de-skew = <7>; + a11_ddr3a7_de-skew = <7>; + a12_ddr3casb_de-skew = <7>; + a13_ddr3a8_de-skew = <7>; + a14_ddr3odt0_de-skew = <7>; + a15_ddr3ba1_de-skew = <7>; + a16_ddr3rasb_de-skew = <7>; + a17_ddr3null_de-skew = <7>; + ba0_ddr3ba2_de-skew = <7>; + ba1_ddr3a12_de-skew = <7>; + bg0_ddr3ba0_de-skew = <7>; + bg1_ddr3web_de-skew = <7>; + cke_ddr3cke_de-skew = <7>; + ck_ddr3ck_de-skew = <7>; + ckb_ddr3ckb_de-skew = <7>; + csb0_ddr3a10_de-skew = <7>; + odt0_ddr3a15_de-skew = <7>; + resetn_ddr3resetn_de-skew = <7>; + actn_ddr3csb0_de-skew = <7>; + csb1_ddr3csb1_de-skew = <7>; + odt1_ddr3odt1_de-skew = <7>; + + /* DATA de-skew, one step is 15ps, range 0-31 */ + /* cs0_skew_a */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <7>; + cs0_dq0_rx_de-skew = <7>; + cs0_dq0_tx_de-skew = <7>; + cs0_dq1_rx_de-skew = <7>; + cs0_dq1_tx_de-skew = <7>; + cs0_dq2_rx_de-skew = <7>; + cs0_dq2_tx_de-skew = <7>; + cs0_dq3_rx_de-skew = <7>; + cs0_dq3_tx_de-skew = <7>; + cs0_dq4_rx_de-skew = <7>; + cs0_dq4_tx_de-skew = <7>; + cs0_dq5_rx_de-skew = <7>; + cs0_dq5_tx_de-skew = <7>; + cs0_dq6_rx_de-skew = <7>; + cs0_dq6_tx_de-skew = <7>; + cs0_dq7_rx_de-skew = <7>; + cs0_dq7_tx_de-skew = <7>; + cs0_dqs0p_rx_de-skew = <14>; + cs0_dqs0p_tx_de-skew = <9>; + cs0_dqs0n_tx_de-skew = <9>; + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <7>; + cs0_dq8_rx_de-skew = <7>; + cs0_dq8_tx_de-skew = <7>; + cs0_dq9_rx_de-skew = <7>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_rx_de-skew = <7>; + cs0_dq10_tx_de-skew = <7>; + cs0_dq11_rx_de-skew = <7>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_rx_de-skew = <7>; + cs0_dq12_tx_de-skew = <7>; + cs0_dq13_rx_de-skew = <7>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_rx_de-skew = <7>; + cs0_dq14_tx_de-skew = <7>; + cs0_dq15_rx_de-skew = <7>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1p_rx_de-skew = <14>; + cs0_dqs1p_tx_de-skew = <9>; + cs0_dqs1n_tx_de-skew = <9>; + cs0_dqs0n_rx_de-skew = <14>; + cs0_dqs1n_rx_de-skew = <14>; + + /* cs0_skew_b */ + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <7>; + cs0_dq16_rx_de-skew = <7>; + cs0_dq16_tx_de-skew = <7>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq17_tx_de-skew = <7>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq18_tx_de-skew = <7>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq19_tx_de-skew = <7>; + cs0_dq20_rx_de-skew = <7>; + cs0_dq20_tx_de-skew = <7>; + cs0_dq21_rx_de-skew = <7>; + cs0_dq21_tx_de-skew = <7>; + cs0_dq22_rx_de-skew = <7>; + cs0_dq22_tx_de-skew = <7>; + cs0_dq23_rx_de-skew = <7>; + cs0_dq23_tx_de-skew = <7>; + cs0_dqs2p_rx_de-skew = <14>; + cs0_dqs2p_tx_de-skew = <9>; + cs0_dqs2n_tx_de-skew = <9>; + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq24_tx_de-skew = <7>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3p_rx_de-skew = <14>; + cs0_dqs3p_tx_de-skew = <9>; + cs0_dqs3n_tx_de-skew = <9>; + cs0_dqs2n_rx_de-skew = <14>; + cs0_dqs3n_rx_de-skew = <14>; + + /* cs1_skew_a */ + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <7>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq0_tx_de-skew = <7>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq1_tx_de-skew = <7>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq2_tx_de-skew = <7>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq3_tx_de-skew = <7>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq4_tx_de-skew = <7>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq5_tx_de-skew = <7>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq6_tx_de-skew = <7>; + cs1_dq7_rx_de-skew = <7>; + cs1_dq7_tx_de-skew = <7>; + cs1_dqs0p_rx_de-skew = <14>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq8_tx_de-skew = <7>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <7>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq12_tx_de-skew = <7>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq14_tx_de-skew = <7>; + cs1_dq15_rx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1p_rx_de-skew = <14>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + cs1_dqs0n_rx_de-skew = <14>; + cs1_dqs1n_rx_de-skew = <14>; + + /* cs1_skew_b */ + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <7>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <7>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <7>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <7>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq19_tx_de-skew = <7>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq20_tx_de-skew = <7>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <7>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq22_tx_de-skew = <7>; + cs1_dq23_rx_de-skew = <7>; + cs1_dq23_tx_de-skew = <7>; + cs1_dqs2p_rx_de-skew = <14>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq24_tx_de-skew = <7>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3p_rx_de-skew = <14>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; + cs1_dqs2n_rx_de-skew = <14>; + cs1_dqs3n_rx_de-skew = <14>; + }; +}; diff --git a/rk1808-evb-v10.dts b/rk1808-evb-v10.dts new file mode 100644 index 0000000..a098248 --- /dev/null +++ b/rk1808-evb-v10.dts @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "rk1808-evb.dtsi" + +/ { + model = "Rockchip RK1808 EVB V10 Board"; + compatible = "rockchip,rk1808-evb-v10", "rockchip,rk1808"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait kpti=0 snd_aloop.index=7"; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk1808-vad"; + rockchip,cpu = <&i2s0>; + rockchip,codec = <&vad>; + }; +}; + +&adc_key { + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <18000>; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + power-supply = <&vcc5v0_sys>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + clock-frequency = <100000>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vdd1v5_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + pwdn-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s1 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy { + status = "okay"; +}; + +&mipi_dphy_rx { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rk809_sound { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_dsi { + status = "disabled"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s0>; + rockchip,buffer-time-ms = <200>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; + +&vop_lite { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vpu_service { + status = "okay"; +}; diff --git a/rk1808-evb-x4-second.dts b/rk1808-evb-x4-second.dts new file mode 100644 index 0000000..413d4f6 --- /dev/null +++ b/rk1808-evb-x4-second.dts @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "rk1808-evb.dtsi" + +/ { + model = "Rockchip RK1808 EVB X4 Board"; + compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 dump_initrd init=/init kpti=0"; + }; +}; + +&adc_key { + power-key { + linux,code = ; + label = "power key"; + press-threshold-microvolt = <18000>; + }; +}; + +/delete-node/ &backlight; +/delete-node/ &vcc1v8_dvp; +/delete-node/ &vdd1v5_dvp; +/delete-node/ &vcc2v8_dvp; + +&cif { + status = "okay"; + + port { + cif_in: endpoint@0 { + remote-endpoint = <&dphy_rx_out>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&cif_mmu { + status = "okay"; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_PPLL>, <&cru ARMCLK>, + <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, + <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, + <&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>; + assigned-clock-rates = + <1188000000>, <1000000000>, + <100000000>, <816000000>, + <200000000>, <100000000>, + <300000000>, <200000000>, + <100000000>, <80000000>; +}; + +&csi_tx { + status = "okay"; + csi-tx-bypass-mode = <1>; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing_1280x3_720>; + + timing_1280x3_720: timing-1280x3-720 { + clock-frequency = <80000000>; + hactive = <3840>; + vactive = <720>; + hfront-porch = <1200>; + hsync-len = <500>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing_4k: timing-4k { + clock-frequency = <250000000>; + hactive = <3840>; + vactive = <2160>; + hfront-porch = <1500>; + hsync-len = <500>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing_4096: timing-4096 { + clock-frequency = <100000000>; + hactive = <4096>; + vactive = <2048>; + hfront-porch = <1500>; + hsync-len = <500>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing_1920x3_1080: timing-1920x3-1080 { + clock-frequency = <250000000>; + hactive = <5760>; + vactive = <1080>; + hfront-porch = <1500>; + hsync-len = <70>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&emmc { + status = "disabled"; +}; + +&gmac { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vcamera@30 { + compatible = "rockchip,virtual-camera"; + reg = <0x30>; + width = <3840>; + height = <720>; + bus-format = ; + + port { + vcamera_out: endpoint { + remote-endpoint = <&dphy_rx_in>; + link-frequencies = /bits/ 64 <320000000>; + }; + }; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&mipi_dphy { + status = "okay"; +}; + +&mipi_dphy_rx { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vcamera_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_in>; + }; + }; + }; +}; + +&rk809_codec { + status = "disabled"; +}; + +&rk_rga { + status = "okay"; +}; + +&route_csi { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&sdio { + status = "disabled"; +}; + +&sfc { + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&vop_raw { + status = "okay"; +}; + +&vopr_mmu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; diff --git a/rk1808-evb-x4.dts b/rk1808-evb-x4.dts new file mode 100644 index 0000000..17993d1 --- /dev/null +++ b/rk1808-evb-x4.dts @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "rk1808-evb.dtsi" + +/ { + model = "Rockchip RK1808 EVB X4 Board"; + compatible = "rockchip,rk1808-evb-x4", "rockchip,rk1808"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 dump_initrd init=/init kpti=0"; + }; +}; + +&adc_key { + power-key { + linux,code = ; + label = "power key"; + press-threshold-microvolt = <18000>; + }; +}; + +/delete-node/ &backlight; +/delete-node/ &vcc1v8_dvp; +/delete-node/ &vdd1v5_dvp; +/delete-node/ &vcc2v8_dvp; + +&cif { + status = "okay"; + + port { + cif_in: endpoint@0 { + remote-endpoint = <&dphy_rx_out>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&cif_mmu { + status = "okay"; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_PPLL>, <&cru ARMCLK>, + <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, + <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, + <&cru LSCLK_BUS_PRE>, <&cru DCLK_VOPRAW>; + assigned-clock-rates = + <1188000000>, <1000000000>, + <100000000>, <816000000>, + <200000000>, <100000000>, + <300000000>, <200000000>, + <100000000>, <80000000>; +}; + +&csi_tx { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing_1280x3_720>; + + timing_1280x3_720: timing-1280x3-720 { + clock-frequency = <80000000>; + hactive = <3840>; + vactive = <720>; + hfront-porch = <1200>; + hsync-len = <500>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing_4k: timing-4k { + clock-frequency = <250000000>; + hactive = <3840>; + vactive = <2160>; + hfront-porch = <1500>; + hsync-len = <500>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing_4096: timing-4096 { + clock-frequency = <190000000>; + hactive = <4096>; + vactive = <2048>; + hfront-porch = <1500>; + hsync-len = <500>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing_1920x3_1080: timing-1920x3-1080 { + clock-frequency = <250000000>; + hactive = <5760>; + vactive = <1080>; + hfront-porch = <1500>; + hsync-len = <70>; + hback-porch = <30>; + vfront-porch = <40>; + vsync-len = <20>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&emmc { + status = "disabled"; +}; + +&gmac { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vcamera@30 { + compatible = "rockchip,virtual-camera"; + reg = <0x30>; + width = <1280>; + height = <720>; + bus-format = ; + + port { + vcamera_out: endpoint { + remote-endpoint = <&dphy_rx_in>; + link-frequencies = /bits/ 64 <320000000>; + }; + }; + }; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "disabled"; +}; + +&mipi_dphy { + status = "okay"; +}; + +&mipi_dphy_rx { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vcamera_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_in>; + }; + }; + }; +}; + +&rk809_codec { + status = "disabled"; +}; + +&rk_rga { + status = "okay"; +}; + +&route_csi { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&sdio { + status = "disabled"; +}; + +&sfc { + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&vop_raw { + status = "okay"; +}; + +&vopr_mmu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; diff --git a/rk1808-evb.dtsi b/rk1808-evb.dtsi new file mode 100644 index 0000000..bb57ae1 --- /dev/null +++ b/rk1808-evb.dtsi @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +#include +#include +#include +#include +#include +#include "rk1808.dtsi" + +/ { + model = "Rockchip RK1808 EVB"; + compatible = "rockchip,rk1808-evb", "rockchip,rk1808"; + + adc_key: adc-keys { + compatible = "adc-keys"; + autorepeat; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_lite_out>, <&vop_raw_out>; + logo-memory-region = <&drm_logo>; + status = "disabled"; + + route { + route_csi: route-csi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_raw_out_csi>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_lite_out_dsi>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_lite_out_rgb>; + }; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <0>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x30000>; + console-size = <0xc0000>; + ftrace-size = <0x00000>; + pmsg-size = <0x00000>; + }; + }; + + rk809_sound: rk809-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4_rts>; + pinctrl-1 = <&uart4_rts_gpio>; + BT,power_gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>; + wifi_chip_type = "ap6212"; + WIFI,host_wake_irq = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&combphy { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <200000000>; + mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio0 10 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + assigned-clocks = <&cru SCLK_GMAC>; + assigned-clock-parents = <&gmac_clkin>; + tx_delay = <0x50>; + rx_delay = <0x3a>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + vdd_npu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <0>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_null>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc_3v3>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_log: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_log"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdda_0v8: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdda_0v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v8: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + + regulator-name = "vdd_0v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + + }; + }; + + vcc1v8_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG6 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + }; + + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_2CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c4 { + status = "okay"; + + sensor@d { + status = "okay"; + compatible = "ak8963"; + reg = <0x0d>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <1>; + reprobe_en = <1>; + }; + + sensor@4c { + status = "okay"; + compatible = "gs_mma7660"; + reg = <0x4c>; + type = ; + irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <2>; + reprobe_en = <1>; + }; +}; + +&npu { + npu-supply = <&vdd_npu>; + status = "okay"; +}; + +&pcie0 { + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + /* Disable usbdrd_dwc3 and usbdrd3 if using pcie0 */ + status = "disabled"; +}; + +&power { + npu-supply = <&vdd_npu>; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sd; + no-mmc; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <300>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc_otg_vbus>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; + extcon = <&u2phy>; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + vsel_gpio: vsel-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart4_rts_gpio: uart4-rts-gpio { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_wake_host: wifi-wake-host { + rockchip,pins = + <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk1808-fpga.dts b/rk1808-fpga.dts new file mode 100644 index 0000000..d9aad0f --- /dev/null +++ b/rk1808-fpga.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + +/dts-v1/; +#include "rk1808.dtsi" + +/ { + model = "Rockchip rk1808 fpga board"; + compatible = "rockchip,fpga", "rockchip,rk1808"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 root=/dev/mmcblk1p8 rootfstype=ext4 rootwait clk_ignore_unused"; + }; + + memory@200000 { + device_type = "memory"; + reg = <0x0 0x00200000 0x0 0x0FE00000>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "okay"; + }; +}; + +&emmc { + max-frequency = <400000>; + clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + mmc-hs200-1_8v; + no-sdio; + no-sd; + num-slots = <1>; + status = "okay"; +}; + +&npu { + status = "okay"; +}; + +&sdmmc { + max-frequency = <400000>; + clocks = <&xin24m>, <&xin24m>, <&xin24m>, <&xin24m>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + no-sdio; + no-mmc; + status = "okay"; +}; + +/* If fiq_debugger set okay, need to define uart2 and to be disabled */ +&uart2 { + status = "disabled"; +}; diff --git a/rk1808.dtsi b/rk1808.dtsi new file mode 100644 index 0000000..ed23ddf --- /dev/null +++ b/rk1808.dtsi @@ -0,0 +1,3055 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk1808-dram-default-timing.dtsi" + +/ { + compatible = "rockchip,rk1808"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + dynamic-power-coefficient = <74>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + power-model { + compatible = "simple-power-model"; + ref-leakage = <31>; + static-coefficient = <100000>; + ts = <597400 241050 (-2450) 70>; + thermal-zone = "soc-thermal"; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + dynamic-power-coefficient = <74>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <800000>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1608 50000 + >; + + rockchip,max-volt = <950000>; + rockchip,evb-irdrop = <25000>; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + rockchip,pvtm-voltage-sel = < + 0 69000 0 + 69001 74000 1 + 74001 99999 2 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <800000>; + rockchip,pvtm-ch = <0 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <(-20) (-26)>; + rockchip,thermal-zone = "soc-thermal"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <800000 800000 950000>; + opp-microvolt-L0 = <800000 800000 950000>; + opp-microvolt-L1 = <750000 750000 950000>; + opp-microvolt-L2 = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <825000 825000 950000>; + opp-microvolt-L0 = <825000 825000 950000>; + opp-microvolt-L1 = <775000 775000 950000>; + opp-microvolt-L2 = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <850000 850000 950000>; + opp-microvolt-L0 = <850000 850000 950000>; + opp-microvolt-L1 = <800000 800000 950000>; + opp-microvolt-L2 = <775000 775000 950000>; + clock-latency-ns = <40000>; + }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <875000 875000 950000>; + opp-microvolt-L0 = <875000 875000 950000>; + opp-microvolt-L1 = <825000 825000 950000>; + opp-microvolt-L2 = <800000 800000 950000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <900000 900000 950000>; + opp-microvolt-L0 = <900000 900000 950000>; + opp-microvolt-L1 = <850000 850000 950000>; + opp-microvolt-L2 = <825000 825000 950000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + + bus_soc: bus-soc { + compatible = "rockchip,rk1808-bus"; + rockchip,busfreq-policy = "smc"; + soc-bus0 { + bus-id = <0>; + cfg-val = <0x1e0>; + enable-msk = <0x407f>; + status = "okay"; + }; + soc-bus1 { + bus-id = <1>; + cfg-val = <0x12c0>; + enable-msk = <0x41ff>; + status = "okay"; + }; + soc-bus2 { + bus-id = <2>; + cfg-val = <0x12c0>; + enable-msk = <0x4005>; + status = "okay"; + }; + soc-bus3 { + bus-id = <3>; + cfg-val = <0x12c0>; + enable-msk = <0x4001>; + status = "okay"; + }; + soc-bus4 { + bus-id = <4>; + cfg-val = <0x12c0>; + enable-msk = <0x4001>; + status = "disabled"; + }; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + mipi_csi2: mipi-csi2 { + compatible = "rockchip,rk1808-mipi-csi2"; + rockchip,hw = <&mipi_csi2_hw>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk1808"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_PMIC_LP + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&clkin_32k>; + }; + + pcie0: pcie@fc400000 { + compatible = "rockchip,rk1808-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0x1f>; + clocks = <&cru HSCLK_PCIE>, <&cru LSCLK_PCIE>, + <&cru ACLK_PCIE>, <&cru PCLK_PCIE>, + <&cru SCLK_PCIE_AUX>; + clock-names = "hsclk", "lsclk", + "aclk", "pclk", + "sclk-aux"; + interrupts = , + , + , + ; + interrupt-names = "sys", "legacy", "msg", "err"; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-ob-windows = <2>; + msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <2>; + phys = <&combphy PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreq>; + power-domains = <&power RK1808_PD_PCIE>; + ranges = <0x00000800 0x0 0xf8000000 0x0 0xf8000000 0x0 0x800000 + 0x83000000 0x0 0xf8800000 0x0 0xf8800000 0x0 0x3700000 + 0x81000000 0x0 0xfbf00000 0x0 0xfbf00000 0x0 0x100000>; + reg = <0x0 0xfc000000 0x0 0x400000>, + <0x0 0xfc400000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE_NIU_H>, <&cru SRST_PCIE_NIU_L>, + <&cru SRST_PCIEGRF_P>, <&cru SRST_PCIECTL_P>, + <&cru SRST_PCIECTL_POWERUP>, <&cru SRST_PCIECTL_MST_A>, + <&cru SRST_PCIECTL_SLV_A>, <&cru SRST_PCIECTL_DBI_A>, + <&cru SRST_PCIECTL_BUTTON>, <&cru SRST_PCIECTL_PE>, + <&cru SRST_PCIECTL_CORE>, <&cru SRST_PCIECTL_NSTICKY>, + <&cru SRST_PCIECTL_STICKY>, <&cru SRST_PCIECTL_PWR>, + <&cru SRST_PCIE_NIU_A>, <&cru SRST_PCIE_NIU_P>; + reset-names = "niu-h", "niu-l", "grf-p", "ctl-p", + "ctl-powerup", "ctl-mst-a", "ctl-slv-a", + "ctl-dbi-a", "ctl-button", "ctl-pe", + "ctl-core", "ctl-nsticky", "ctl-sticky", + "ctl-pwr", "ctl-niu-a", "ctl-niu-p"; + rockchip,usbpciegrf = <&usb_pcie_grf>; + rockchip,pmugrf = <&pmugrf>; + status = "disabled"; + }; + + usbdrd3: usb { + compatible = "rockchip,rk1808-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, + <&cru SCLK_USB3_OTG0_SUSPEND>; + clock-names = "ref_clk", "bus_clk", + "suspend_clk"; + assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>; + assigned-clock-rates = <24000000>; + power-domains = <&power RK1808_PD_PCIE>; + resets = <&cru SRST_USB3_OTG_A>; + reset-names = "usb3-otg"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@fd000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x200000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy_otg>, <&combphy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,tx-ipgap-linecheck-dis-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfe000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + npu_pvtm: npu-pvtm { + compatible = "rockchip,rk1808-npu-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pvtm@2 { + reg = <2>; + clocks = <&cru SCLK_PVTM_NPU>; + clock-names = "clk"; + }; + }; + + rgb: rgb { + compatible = "rockchip,rk1808-rgb"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + rgb_in_vop_lite: endpoint { + remote-endpoint = <&vop_lite_out_rgb>; + }; + }; + }; + }; + }; + + usb2phy_grf: syscon@fe010000 { + compatible = "rockchip,rk1808-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfe010000 0x0 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rk1808-usb2phy"; + reg = <0x100 0x10>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clock-output-names = "usb480m_phy"; + status = "disabled"; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + }; + + combphy_grf: syscon@fe018000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xfe018000 0x0 0x8000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfe020000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk1808-pmu-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pvtm@1 { + reg = <1>; + clocks = <&cru SCLK_PVTM_PMU>; + clock-names = "clk"; + }; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + }; + }; + + usb_pcie_grf: syscon@fe040000 { + compatible = "rockchip,usb-pcie-grf", "syscon"; + reg = <0x0 0xfe040000 0x0 0x1000>; + }; + + coregrf: syscon@fe050000 { + compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd"; + reg = <0x0 0xfe050000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pvtm: pvtm { + compatible = "rockchip,rk1808-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pvtm@0 { + reg = <0>; + clocks = <&cru SCLK_PVTM_CORE>; + clock-names = "clk"; + }; + }; + }; + + qos_npu: qos@fe850000 { + compatible = "syscon"; + reg = <0x0 0xfe850000 0x0 0x20>; + }; + + qos_pcie: qos@fe880000 { + compatible = "syscon"; + reg = <0x0 0xfe880000 0x0 0x20>; + status = "disabled"; + }; + + qos_usb2: qos@fe890000 { + compatible = "syscon"; + reg = <0x0 0xfe890000 0x0 0x20>; + status = "disabled"; + }; + + qos_usb3: qos@fe890080 { + compatible = "syscon"; + reg = <0x0 0xfe890080 0x0 0x20>; + status = "disabled"; + }; + + qos_isp: qos@fe8a0000 { + compatible = "syscon"; + reg = <0x0 0xfe8a0000 0x0 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "syscon"; + reg = <0x0 0xfe8a0080 0x0 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "syscon"; + reg = <0x0 0xfe8a0100 0x0 0x20>; + }; + + qos_cif: qos@fe8a0180 { + compatible = "syscon"; + reg = <0x0 0xfe8a0180 0x0 0x20>; + }; + + qos_vop_raw: qos@fe8b0000 { + compatible = "syscon"; + reg = <0x0 0xfe8b0000 0x0 0x20>; + }; + + qos_vop_lite: qos@fe8b0080 { + compatible = "syscon"; + reg = <0x0 0xfe8b0080 0x0 0x20>; + }; + + qos_vpu: qos@fe8c0000 { + compatible = "syscon"; + reg = <0x0 0xfe8c0000 0x0 0x20>; + }; + + sram: sram@fec00000 { + compatible = "mmio-sram"; + reg = <0x0 0xfec00000 0x0 0x200000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xfec00000 0x200000>; + /* reserved for ddr dvfs and system suspend/resume */ + ddr-sram@0 { + reg = <0x0 0x8000>; + }; + /* reserved for vad audio buffer */ + vad_sram: vad-sram@1c0000 { + reg = <0x1c0000 0x40000>; + }; + }; + + hwlock: hwspinlock@ff040000 { + compatible = "rockchip,hwspinlock"; + reg = <0 0xff040000 0 0x10000>; + #hwlock-cells = <1>; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xff100000 0 0x10000>, /* GICD */ + <0x0 0xff140000 0 0xc0000>, /* GICR */ + <0x0 0xff300000 0 0x10000>, /* GICC */ + <0x0 0xff310000 0 0x10000>, /* GICH */ + <0x0 0xff320000 0 0x10000>; /* GICV */ + interrupts = ; + its: interrupt-controller@ff120000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xff120000 0x0 0x20000>; + }; + }; + + efuse: efuse@ff260000 { + compatible = "rockchip,rk1808-efuse"; + reg = <0x0 0xff3b0000 0x0 0x50>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_EFUSE_NS>, <&cru PCLK_EFUSE>; + clock-names = "sclk_efuse", "pclk_efuse"; + assigned-clocks = <&cru SCLK_EFUSE_NS>; + assigned-clock-rates = <24000000>; + rockchip,efuse-size = <0x20>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@18 { + reg = <0x18 0x1>; + }; + npu_leakage: npu-leakage@19 { + reg = <0x19 0x1>; + }; + efuse_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + }; + + cru: clock-controller@ff350000 { + compatible = "rockchip,rk1808-cru"; + reg = <0x0 0xff350000 0x0 0x5000>; + rockchip,grf = <&grf>; + rockchip,pmugrf = <&pmugrf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru SCLK_32K_IOE>, + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_PPLL>, <&cru ARMCLK>, + <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, + <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, + <&cru LSCLK_BUS_PRE>; + assigned-clock-parents = <&xin32k>; + assigned-clock-rates = + <32768>, + <1188000000>, <1000000000>, + <100000000>, <816000000>, + <200000000>, <100000000>, + <300000000>, <200000000>, + <100000000>; + }; + + mipi_dphy_rx: mipi-dphy-rx@ff360000 { + compatible = "rockchip,rk1808-mipi-dphy-rx"; + reg = <0x0 0xff360000 0x0 0x4000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "pclk"; + power-domains = <&power RK1808_PD_VIO>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + mipi_dphy: mipi-dphy@ff370000 { + compatible = "rockchip,rk1808-mipi-dphy"; + reg = <0x0 0xff370000 0x0 0x500>; + clocks = <&cru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; + clock-names = "ref", "pclk"; + clock-output-names = "mipi_dphy_pll"; + #clock-cells = <0>; + resets = <&cru SRST_MIPIDSIPHY_P>; + reset-names = "apb"; + #phy-cells = <0>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + combphy: phy@ff380000 { + compatible = "rockchip,rk1808-combphy"; + reg = <0x0 0xff380000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-rates = <25000000>; + resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, + <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>, + <&cru SRST_USB3PHY_GRF_P>; + reset-names = "otg-rst", "combphy-por", + "combphy-apb", "combphy-pipe", + "usb3phy_grf_p"; + rockchip,combphygrf = <&combphy_grf>; + rockchip,usbpciegrf = <&usb_pcie_grf>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <977>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point-0 { + /* millicelsius */ + temperature = <75000>; + /* millicelsius */ + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + /* millicelsius */ + temperature = <85000>; + /* millicelsius */ + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&target>; + cooling-device = + <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + }; + + tsadc: tsadc@ff3a0000 { + compatible = "rockchip,rk1808-tsadc"; + reg = <0x0 0xff3a0000 0x0 0x100>; + interrupts = ; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <650000>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + status = "disabled"; + }; + + saradc: saradc@ff3c0000 { + compatible = "rockchip,rk1808-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff3c0000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + pwm0: pwm@ff3d0000 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@ff3d0010 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@ff3d0020 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@ff3d0030 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm4: pwm@ff3d8000 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d8000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@ff3d8010 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d8010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@ff3d8020 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d8020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@ff3d8030 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff3d8030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7_pin>; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff3e0000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk1808-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + pd_npu@RK1808_VD_NPU { + reg = ; + clocks = <&cru SCLK_NPU>, + <&cru ACLK_NPU>, + <&cru HCLK_NPU>; + pm_qos = <&qos_npu>; + }; + + /* These power domains are grouped by VD_LOGIC */ + pd_pcie@RK1808_PD_PCIE { + reg = ; + clocks = <&cru HSCLK_PCIE>, + <&cru LSCLK_PCIE>, + <&cru ACLK_PCIE>, + <&cru ACLK_PCIE_MST>, + <&cru ACLK_PCIE_SLV>, + <&cru PCLK_PCIE>, + <&cru SCLK_PCIE_AUX>, + <&cru SCLK_PCIE_AUX>, + <&cru ACLK_USB3OTG>, + <&cru HCLK_HOST>, + <&cru HCLK_HOST_ARB>, + <&cru SCLK_USB3_OTG0_REF>, + <&cru SCLK_USB3_OTG0_SUSPEND>; + pm_qos = <&qos_pcie>, + <&qos_usb2>, + <&qos_usb3>; + }; + pd_vpu@RK1808_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + }; + pd_vio@RK1808_PD_VIO { + reg = ; + clocks = <&cru HSCLK_VIO>, + <&cru LSCLK_VIO>, + <&cru ACLK_VOPRAW>, + <&cru HCLK_VOPRAW>, + <&cru ACLK_VOPLITE>, + <&cru HCLK_VOPLITE>, + <&cru PCLK_DSI_TX>, + <&cru PCLK_CSI_TX>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru ACLK_ISP>, + <&cru HCLK_ISP>, + <&cru ACLK_CIF>, + <&cru HCLK_CIF>, + <&cru PCLK_CSI2HOST>, + <&cru DCLK_VOPRAW>, + <&cru DCLK_VOPLITE>; + pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, + <&qos_isp>, <&qos_cif>, + <&qos_vop_raw>, <&qos_vop_lite>; + }; + }; + }; + + i2c0: i2c@ff410000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff410000 0x0 0x1000>; + clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac: dmac@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff4e0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + uart0: serial@ff430000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff430000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0_PMU>, <&cru PCLK_UART0_PMU>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 0>, <&dmac 1>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + i2c1: i2c@ff500000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff504000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff504000 0x0 0x1000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ff508000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff508000 0x0 0x1000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ff50c000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff50c000 0x0 0x1000>; + clocks = <&cru SCLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ff510000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff510000 0x0 0x1000>; + clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@ff520000 { + compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff520000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 10>, <&dmac 11>; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; + pinctrl-1 = <&spi0_clk_hs &spi0_csn &spi0_miso_hs &spi0_mosi_hs>; + status = "disabled"; + }; + + spi1: spi@ff530000 { + compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff530000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 12>, <&dmac 13>; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; + pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_csn1 &spi1_miso_hs &spi1_mosi_hs>; + status = "disabled"; + }; + + uart1: serial@ff540000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff540000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 2>, <&dmac 3>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1_cts &uart1_rts>; + status = "disabled"; + }; + + uart2: serial@ff550000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff550000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 4>, <&dmac 5>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart3: serial@ff560000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff560000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 6>, <&dmac 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer &uart3_ctsm0 &uart3_rtsm0>; + status = "disabled"; + }; + + uart4: serial@ff570000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff570000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 8>, <&dmac 9>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; + status = "disabled"; + }; + + spi2: spi@ff580000 { + compatible = "rockchip,rk1808-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff580000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 14>, <&dmac 15>; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi2m0_clk &spi2m0_csn &spi2m0_miso &spi2m0_mosi>; + pinctrl-1 = <&spi2m0_clk_hs &spi2m0_csn &spi2m0_miso_hs &spi2m0_mosi_hs>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff5a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 25>, <&dmac 26>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_xfer>; + status = "disabled"; + }; + + uart6: serial@ff5b0000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff5b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 27>, <&dmac 28>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6_xfer>; + status = "disabled"; + }; + + uart7: serial@ff5c0000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff5c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 29>, <&dmac 30>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7_xfer>; + status = "disabled"; + }; + + pwm8: pwm@ff5d0000 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff5d0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8_pin>; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@fff5d0010 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff5d0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9_pin>; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@ff5d0020 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff5d0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10_pin>; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@ff5d0030 { + compatible = "rockchip,rk1808-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff5d0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11_pin>; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + rng: rng@ff630000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff630000 0x0 0x4000>; + clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + clock-names = "clk_crypto", "clk_crypto_apk", + "aclk_crypto", "hclk_crypto"; + resets = <&cru SRST_CRYPTO_CORE>; + reset-names = "reset"; + status = "disabled"; + }; + + dcf: dcf@ff640000 { + compatible = "syscon"; + reg = <0x0 0xff640000 0x0 0x1000>; + }; + + rktimer: rktimer@ff700000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x0 0xff700000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@ff720000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff720000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "okay"; + }; + + i2s0: i2s@ff7e0000 { + compatible = "rockchip,rk1808-i2s-tdm"; + reg = <0x0 0xff7e0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac 16>, <&dmac 17>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_sclktx + &i2s0_8ch_sclkrx + &i2s0_8ch_lrcktx + &i2s0_8ch_lrckrx + &i2s0_8ch_sdi0 + &i2s0_8ch_sdi1 + &i2s0_8ch_sdi2 + &i2s0_8ch_sdi3 + &i2s0_8ch_sdo0 + &i2s0_8ch_sdo1 + &i2s0_8ch_sdo2 + &i2s0_8ch_sdo3 + &i2s0_8ch_mclk>; + status = "disabled"; + }; + + i2s1: i2s@ff7f0000 { + compatible = "rockchip,rk1808-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff7f0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 18>, <&dmac 19>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>; + reset-names = "reset-m", "reset-h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_sclk + &i2s1_2ch_lrck + &i2s1_2ch_sdi + &i2s1_2ch_sdo>; + status = "disabled"; + }; + + pdm: pdm@ff800000 { + compatible = "rockchip,rk1808-pdm", "rockchip,pdm"; + reg = <0x0 0xff800000 0x0 0x1000>; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 24>; + dma-names = "rx"; + resets = <&cru SRST_PDM>; + reset-names = "pdm-m"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk + &pdm_clk1 + &pdm_sdi0 + &pdm_sdi1 + &pdm_sdi2 + &pdm_sdi3>; + status = "disabled"; + }; + + vad: vad@ff810000 { + compatible = "rockchip,rk1808-vad"; + reg = <0x0 0xff810000 0x0 0x10000>; + reg-names = "vad"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = ; + rockchip,audio-sram = <&vad_sram>; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + status = "disabled"; + }; + + dfi: dfi@ff9c0000 { + reg = <0x00 0xff9c0000 0x00 0x400>; + compatible = "rockchip,rk1808-dfi"; + rockchip,pmugrf = <&pmugrf>; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk1808-dmc"; + dcf_reg = <&dcf>; + interrupts = ; + interrupt-names = "complete_irq"; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 924000 + SYS_STATUS_REBOOT 450000 + SYS_STATUS_SUSPEND 328000 + SYS_STATUS_VIDEO_1080P 924000 + SYS_STATUS_BOOST 924000 + SYS_STATUS_ISP 924000 + SYS_STATUS_PERFORMANCE 924000 + >; + auto-min-freq = <328000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,max-volt = <950000>; + rockchip,evb-irdrop = <12500>; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "leakage"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <800000>; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + opp-microvolt = <800000>; + }; + opp-324000000 { + opp-hz = /bits/ 64 <324000000>; + opp-microvolt = <800000>; + }; + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-microvolt = <800000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <800000>; + }; + opp-664000000 { + opp-hz = /bits/ 64 <664000000>; + opp-microvolt = <800000>; + }; + opp-784000000 { + opp-hz = /bits/ 64 <784000000>; + opp-microvolt = <800000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <800000>; + }; + /* 1066M is only for ddr4 */ + opp-1066000000 { + opp-hz = /bits/ 64 <1066000000>; + opp-microvolt = <800000>; + status = "disabled"; + }; + }; + + rk_rga: rk_rga@ffaf0000 { + compatible = "rockchip,rga2"; + dev_mode = <0>; + reg = <0x0 0xffaf0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK1808_PD_VIO>; + status = "disabled"; + }; + + cif: cif@ffae0000 { + compatible = "rockchip,rk1808-cif"; + reg = <0x0 0xffae0000 0x0 0x200>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + clocks = <&cru ACLK_CIF>, <&cru DCLK_CIF>, + <&cru HCLK_CIF>, <&cru SCLK_CIF_OUT>; + clock-names = "aclk_cif", "dclk_cif", + "hclk_cif", "sclk_cif_out"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, + <&cru SRST_CIF_I>, <&cru SRST_CIF_D>, + <&cru SRST_CIF_PCLKIN>; + reset-names = "rst_cif_a", "rst_cif_h", + "rst_cif_i", "rst_cif_d", + "rst_cif_pclkin"; + power-domains = <&power RK1808_PD_VIO>; + iommus = <&cif_mmu>; + status = "disabled"; + }; + + cif_mmu: iommu@ffae0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xffae0800 0x0 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; + clock-names = "aclk", "iface"; + power-domains = <&power RK1808_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vop_lite: vop@ffb00000 { + compatible = "rockchip,rk1808-vop-lit"; + reg = <0x0 0xffb00000 0x0 0x200>; + reg-names = "regs"; + interrupts = ; + clocks = <&cru ACLK_VOPLITE>, <&cru DCLK_VOPLITE>, + <&cru HCLK_VOPLITE>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK1808_PD_VIO>; + iommus = <&vopl_mmu>; + status = "disabled"; + + vop_lite_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_lite_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vop_lite>; + }; + + vop_lite_out_rgb: endpoint@1 { + reg = <1>; + remote-endpoint = <&rgb_in_vop_lite>; + }; + }; + }; + + vopl_mmu: iommu@ffb00f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xffb00f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOPLITE>, <&cru HCLK_VOPLITE>; + clock-names = "aclk", "iface"; + power-domains = <&power RK1808_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi_csi2_hw: mipi-csi2-hw@ffb10000 { + compatible = "rockchip,rk1808-mipi-csi2-hw"; + reg = <0x0 0xffb10000 0x0 0x100>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST>; + clock-names = "pclk_csi2host"; + status = "disabled"; + }; + + csi_tx: csi@ffb20000 { + compatible = "rockchip,rk1808-mipi-csi"; + reg = <0x0 0xffb20000 0x0 0x500>; + reg-names = "csi_regs"; + interrupts = ; + clocks = <&cru PCLK_CSI_TX>, <&mipi_dphy>; + clock-names = "pclk", "hs_clk"; + resets = <&cru SRST_CSITX_P>, + <&cru SRST_CSITX_TXBYTEHS>, + <&cru SRST_CSITX_TXESC>, + <&cru SRST_CSITX_CAM>, + <&cru SRST_CSITX_I>; + reset-names = "tx_apb", "tx_bytehs", "tx_esc", "tx_cam", "tx_i"; + phys = <&mipi_dphy>; + phy-names = "mipi_dphy"; + power-domains = <&power RK1808_PD_VIO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + + port { + csi_in_vop_raw: endpoint { + remote-endpoint = <&vop_raw_out_csi>; + }; + }; + }; + }; + + dsi: dsi@ffb30000 { + compatible = "rockchip,rk1808-mipi-dsi"; + reg = <0x0 0xffb30000 0x0 0x500>; + interrupts = ; + clocks = <&cru PCLK_DSI_TX>, <&mipi_dphy>; + clock-names = "pclk", "hs_clk"; + resets = <&cru SRST_MIPIDSI_HOST_P>; + reset-names = "apb"; + phys = <&mipi_dphy>; + phy-names = "mipi_dphy"; + power-domains = <&power RK1808_PD_VIO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + port { + dsi_in_vop_lite: endpoint { + remote-endpoint = <&vop_lite_out_dsi>; + }; + }; + }; + }; + + vop_raw: vop@ffb40000 { + compatible = "rockchip,rk1808-vop-raw"; + reg = <0x0 0xffb40000 0x0 0x500>; + reg-names = "regs"; + interrupts = ; + clocks = <&cru ACLK_VOPRAW>, <&cru DCLK_VOPRAW>, + <&cru HCLK_VOPRAW>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + power-domains = <&power RK1808_PD_VIO>; + iommus = <&vopr_mmu>; + status = "disabled"; + + vop_raw_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_raw_out_csi: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi_in_vop_raw>; + }; + }; + }; + + vopr_mmu: iommu@ffb40f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xffb40f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopr_mmu"; + clocks = <&cru ACLK_VOPRAW>, <&cru HCLK_VOPRAW>; + clock-names = "aclk", "iface"; + power-domains = <&power RK1808_PD_VIO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkisp1: rkisp1@ffb50000 { + compatible = "rockchip,rk1808-rkisp1"; + reg = <0x0 0xffb50000 0x0 0x8000>; + interrupts = , + , + ; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>, <&cru DCLK_CIF>; + clock-names = "aclk_isp", "hclk_isp", + "clk_isp", "pclk_isp"; + power-domains = <&power RK1808_PD_VIO>; + iommus = <&isp_mmu>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + isp_mmu: iommu@ffb58000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xffb58000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, + <&cru SCLK_ISP>; + clock-names = "aclk", "iface", "sclk"; + power-domains = <&power RK1808_PD_VIO>; + rk_iommu,disable_reset_quirk; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu_service: vpu_service@ffb80000 { + compatible = "rockchip,vpu_service"; + reg = <0x0 0xffb80000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "irq_enc", "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + power-domains = <&power RK1808_PD_VPU>; + resets = <&cru SRST_VPU_A>, <&cru SRST_VPU_H>; + reset-names = "video_a", "video_h"; + iommus = <&vpu_mmu>; + iommu_enabled = <1>; + allocator = <1>; /* 0 means ion, 1 means drm */ + status = "disabled"; + }; + + vpu_mmu: iommu@ffb80800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xffb80800 0x0 0x100>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK1808_PD_VPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + sdio: dwmmc@ffc60000 { + compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc60000 0x0 0x4000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + max-frequency = <150000000>; + fifo-depth = <0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + status = "disabled"; + }; + + npu: npu@ffbc0000 { + compatible = "rockchip,npu"; + reg = <0x0 0xffbc0000 0x0 0x1000>; + clocks = <&cru SCLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; + clock-names = "sclk_npu", "aclk_npu", "hclk_npu"; + assigned-clocks = <&cru SCLK_NPU>; + assigned-clock-rates = <800000000>; + interrupts = ; + power-domains = <&power RK1808_VD_NPU>; + operating-points-v2 = <&npu_opp_table>; + #cooling-cells = <2>; + status = "disabled"; + + npu_power_model: power-model { + compatible = "simple-power-model"; + ref-leakage = <31>; + static-coefficient = <100000>; + dynamic-coefficient = <3080>; + ts = <88610 303120 (-5000) 100>; + thermal-zone = "soc-thermal"; + }; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <800000>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 792 50000 + >; + + rockchip,max-volt = <880000>; + rockchip,evb-irdrop = <37500>; + nvmem-cells = <&npu_leakage>; + nvmem-cell-names = "leakage"; + + rockchip,pvtm-voltage-sel = < + 0 69000 0 + 69001 74000 1 + 74001 99999 2 + >; + rockchip,pvtm-ch = <0 0>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <850000 850000 880000>; + opp-microvolt-L0 = <850000 850000 880000>; + opp-microvolt-L1 = <825000 825000 880000>; + opp-microvolt-L2 = <800000 800000 880000>; + }; + }; + + sfc: sfc@ffc50000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xffc50000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + sdmmc: dwmmc@ffcf0000 { + compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffcf0000 0x0 0x4000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + max-frequency = <150000000>; + fifo-depth = <0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_detn>; + status = "disabled"; + }; + + emmc: dwmmc@ffd00000 { + compatible = "rockchip,rk1808-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffd00000 0x0 0x4000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + max-frequency = <150000000>; + fifo-depth = <0x100>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "disabled"; + }; + + usb_host0_ehci: usb@ffd80000 { + compatible = "generic-ehci"; + reg = <0x0 0xffd80000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + power-domains = <&power RK1808_PD_PCIE>; + }; + + usb_host0_ohci: usb@ffd90000 { + compatible = "generic-ohci"; + reg = <0x0 0xffd90000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + power-domains = <&power RK1808_PD_PCIE>; + }; + + gmac: ethernet@ffdd0000 { + compatible = "rockchip,rk1808-gmac"; + reg = <0x0 0xffdd0000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, + <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_GMAC_REF>, + <&cru SCLK_GMAC_REFOUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RGMII_SPEED>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac", "clk_mac_speed"; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + resets = <&cru SRST_GAMC_A>; + reset-names = "stmmaceth"; + /* power-domains = <&power RK1808_PD_GMAC>; */ + status = "disabled"; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,polling-delay = <200>; /* milliseconds */ + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk1808-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff4c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff4c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff690000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff690000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff6a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff6b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff6c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_2ma: pcfg-pull-none-2ma { + bias-disable; + drive-strength = <2>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_4ma: pcfg-pull-up-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_pull_none_2ma_smt: pcfg-pull-none-2ma-smt { + bias-disable; + drive-strength = <2>; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + pcfg_input_smt: pcfg-input-smt { + input-enable; + input-schmitt-enable; + }; + + cif-m0 { + cif_clkout_m0: cif-clkout-m0 { + rockchip,pins = + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + cif_d12d15_m0: cif-d12d15-m0 { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>,/* cif_d12 */ + <2 RK_PA1 1 &pcfg_pull_none>,/* cif_d13 */ + <2 RK_PA2 1 &pcfg_pull_none>,/* cif_d14 */ + <2 RK_PA3 1 &pcfg_pull_none>;/* cif_d15 */ + }; + + cif_d10d11_m0: cif-d10d11-m0 { + rockchip,pins = + <2 RK_PC2 1 &pcfg_pull_none>,/* cif_d10 */ + <2 RK_PC3 1 &pcfg_pull_none>;/* cif_d11 */ + }; + + cif_d2d9_m0: cif-d2d9-m0 { + rockchip,pins = + <2 RK_PA4 1 &pcfg_pull_none>,/* cif_d2 */ + <2 RK_PA5 1 &pcfg_pull_none>,/* cif_d3 */ + <2 RK_PA6 1 &pcfg_pull_none>,/* cif_d4 */ + <2 RK_PA7 1 &pcfg_pull_none>,/* cif_d5 */ + <2 RK_PB0 1 &pcfg_pull_none>,/* cif_d6 */ + <2 RK_PB1 1 &pcfg_pull_none>,/* cif_d7 */ + <2 RK_PB2 1 &pcfg_pull_none>,/* cif_d8 */ + <2 RK_PB3 1 &pcfg_pull_none>,/* cif_d9 */ + <2 RK_PB4 1 &pcfg_pull_none>,/* cif_vsync */ + <2 RK_PB5 1 &pcfg_pull_none>,/* cif_href */ + <2 RK_PB6 1 &pcfg_pull_none>;/* cif_clkin */ + }; + + cif_d0d1_m0: cif-d0d1-m0 { + rockchip,pins = + <2 RK_PC0 1 &pcfg_pull_none>,/* cif_d0 */ + <2 RK_PC1 1 &pcfg_pull_none>;/* cif_d1 */ + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PB1 1 &pcfg_pull_up_4ma>; + }; + + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_4ma>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_4ma>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_4ma>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_4ma>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_up_4ma>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_up_4ma>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_up_4ma>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_up_4ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <1 RK_PB2 1 &pcfg_pull_up_4ma>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = + /* rgmii_txen */ + <2 RK_PA1 2 &pcfg_pull_none_4ma>, + /* rgmii_txd1 */ + <2 RK_PA2 2 &pcfg_pull_none_4ma>, + /* rgmii_txd0 */ + <2 RK_PA3 2 &pcfg_pull_none_4ma>, + /* rgmii_rxd0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* rgmii_rxd1 */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_rxdv */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_mdio */ + <2 RK_PB0 2 &pcfg_pull_none_2ma>, + /* rgmii_mdc */ + <2 RK_PB2 2 &pcfg_pull_none_2ma>, + /* rgmii_txd3 */ + <2 RK_PB3 2 &pcfg_pull_none_4ma>, + /* rgmii_txd2 */ + <2 RK_PB4 2 &pcfg_pull_none_4ma>, + /* rgmii_rxd2 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd3 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_clk */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* rgmii_txclk */ + <2 RK_PC1 2 &pcfg_pull_none_4ma>, + /* rgmii_rxclk */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = + /* rmii_txen */ + <2 RK_PA1 2 &pcfg_pull_none_4ma>, + /* rmii_txd1 */ + <2 RK_PA2 2 &pcfg_pull_none_4ma>, + /* rmii_txd0 */ + <2 RK_PA3 2 &pcfg_pull_none_4ma>, + /* rmii_rxd0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* rmii_rxd1 */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* rmii_rxer */ + <2 RK_PA6 2 &pcfg_pull_none>, + /* rmii_rxdv */ + <2 RK_PA7 2 &pcfg_pull_none>, + /* rmii_mdio */ + <2 RK_PB0 2 &pcfg_pull_none_2ma>, + /* rmii_mdc */ + <2 RK_PB2 2 &pcfg_pull_none_2ma>, + /* rmii_clk */ + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_sda */ + <0 RK_PB1 1 &pcfg_pull_none_2ma_smt>, + /* i2c0_scl */ + <0 RK_PB0 1 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_sda */ + <0 RK_PC1 1 &pcfg_pull_none_2ma_smt>, + /* i2c1_scl */ + <0 RK_PC0 1 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c2m0 { + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2m0_sda */ + <3 RK_PB4 2 &pcfg_pull_none_2ma_smt>, + /* i2c2m0_scl */ + <3 RK_PB3 2 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c2m1 { + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2m1_sda */ + <1 RK_PB5 2 &pcfg_pull_none_2ma_smt>, + /* i2c2m1_scl */ + <1 RK_PB4 2 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + /* i2c3_sda */ + <2 RK_PD1 1 &pcfg_pull_none_2ma_smt>, + /* i2c3_scl */ + <2 RK_PD0 1 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = + /* i2c4_sda */ + <3 RK_PC3 3 &pcfg_pull_none_2ma_smt>, + /* i2c4_scl */ + <3 RK_PC2 3 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = + /* i2c5_sda */ + <4 RK_PC2 1 &pcfg_pull_none_2ma_smt>, + /* i2c5_scl */ + <4 RK_PC1 1 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2s1 { + i2s1_2ch_lrck: i2s1-2ch-lrck { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_none_2ma_smt>; + }; + i2s1_2ch_sclk: i2s1-2ch-sclk { + rockchip,pins = + <3 RK_PA1 1 &pcfg_pull_none_2ma_smt>; + }; + i2s1_2ch_mclk: i2s1-2ch-mclk { + rockchip,pins = + <3 RK_PA2 1 &pcfg_pull_none_2ma_smt>; + }; + i2s1_2ch_sdo: i2s1-2ch-sdo { + rockchip,pins = + <3 RK_PA3 1 &pcfg_pull_none_2ma>; + }; + i2s1_2ch_sdi: i2s1-2ch-sdi { + rockchip,pins = + <3 RK_PA4 1 &pcfg_pull_none_2ma>; + }; + }; + + i2s0 { + i2s0_8ch_sdi3: i2s0-8ch-sdi3 { + rockchip,pins = + <3 RK_PA5 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_sdi2: i2s0-8ch-sdi2 { + rockchip,pins = + <3 RK_PA6 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_sdi1: i2s0-8ch-sdi1 { + rockchip,pins = + <3 RK_PA7 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { + rockchip,pins = + <3 RK_PB0 1 &pcfg_pull_none_2ma_smt>; + }; + i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { + rockchip,pins = + <3 RK_PB1 1 &pcfg_pull_none_2ma_smt>; + }; + i2s0_8ch_sdo3: i2s0-8ch-sdo3 { + rockchip,pins = + <3 RK_PB2 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_sdo2: i2s0-8ch-sdo2 { + rockchip,pins = + <3 RK_PB3 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_sdo1: i2s0-8ch-sdo1 { + rockchip,pins = + <3 RK_PB4 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_mclk: i2s0-8ch-mclk { + rockchip,pins = + <3 RK_PB5 1 &pcfg_pull_none_2ma_smt>; + }; + i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { + rockchip,pins = + <3 RK_PB6 1 &pcfg_pull_none_2ma_smt>; + }; + i2s0_8ch_sclktx: i2s0-8ch-sclktx { + rockchip,pins = + <3 RK_PB7 1 &pcfg_pull_none_2ma_smt>; + }; + i2s0_8ch_sdo0: i2s0-8ch-sdo0 { + rockchip,pins = + <3 RK_PC0 1 &pcfg_pull_none_2ma>; + }; + i2s0_8ch_sdi0: i2s0-8ch-sdi0 { + rockchip,pins = + <3 RK_PC1 1 &pcfg_pull_none_2ma>; + }; + }; + + lcdc { + lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { + rockchip,pins = + /* lcdc_clkm0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + lcdc_rgb_den_pin: lcdc-rgb-den-pin { + rockchip,pins = + /* lcdc_denm0 */ + <2 RK_PC7 3 &pcfg_pull_none>; + }; + + lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { + rockchip,pins = + /* lcdc_hsyncm0 */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { + rockchip,pins = + /* lcdc_vsyncm0 */ + <2 RK_PB3 3 &pcfg_pull_none>; + }; + + lcdc_rgb_m1_hsync_pin: lcdc-rgb-m1-hsync-pin { + rockchip,pins = + /* lcdc_hsyncm1 */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + + lcdc_rgb_m1_vsync_pin: lcdc-rgb-m1-vsync-pin { + rockchip,pins = + /* lcdc_vsyncm1 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + lcdc_rgb666_data_pins: lcdc-rgb666-data-pins { + rockchip,pins = + /* lcdc_d0m0 */ + <2 RK_PA2 3 &pcfg_pull_none>, + /* lcdc_d1m0 */ + <2 RK_PA3 3 &pcfg_pull_none>, + /* lcdc_d2m0 */ + <2 RK_PC2 3 &pcfg_pull_none>, + /* lcdc_d3m0 */ + <2 RK_PC3 3 &pcfg_pull_none>, + /* lcdc_d4m0 */ + <2 RK_PC4 3 &pcfg_pull_none>, + /* lcdc_d5m0 */ + <2 RK_PC5 3 &pcfg_pull_none>, + /* lcdc_d6m0 */ + <2 RK_PA0 3 &pcfg_pull_none>, + /* lcdc_d7m0 */ + <2 RK_PA1 3 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PD3 1 &pcfg_pull_none>; + }; + + lcdc_rgb565_data_pins: lcdc-rgb565-data-pins { + rockchip,pins = + /* lcdc_d0m0 */ + <2 RK_PA2 3 &pcfg_pull_none>, + /* lcdc_d1m0 */ + <2 RK_PA3 3 &pcfg_pull_none>, + /* lcdc_d2m0 */ + <2 RK_PC2 3 &pcfg_pull_none>, + /* lcdc_d3m0 */ + <2 RK_PC3 3 &pcfg_pull_none>, + /* lcdc_d4m0 */ + <2 RK_PC4 3 &pcfg_pull_none>, + /* lcdc_d5m0 */ + <2 RK_PC5 3 &pcfg_pull_none>, + /* lcdc_d6m0 */ + <2 RK_PA0 3 &pcfg_pull_none>, + /* lcdc_d7m0 */ + <2 RK_PA1 3 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + pciusb { + pciusb_pins: pciusb-pins { + rockchip,pins = + /* pciusb_debug0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* pciusb_debug1 */ + <4 RK_PB5 3 &pcfg_pull_none>, + /* pciusb_debug2 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* pciusb_debug3 */ + <4 RK_PB7 3 &pcfg_pull_none>, + /* pciusb_debug4 */ + <4 RK_PC0 3 &pcfg_pull_none>, + /* pciusb_debug5 */ + <4 RK_PC1 3 &pcfg_pull_none>, + /* pciusb_debug6 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* pciusb_debug7 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + + pcie_clkreq: pcie-clkreq { + rockchip,pins = + /* pcie_clkreqn_m1 */ + <0 RK_PC6 1 &pcfg_pull_none >; + }; + }; + + pdm { + pdm_clk: pdm-clk { + rockchip,pins = + /* pdm_clk0 */ + <3 RK_PB0 2 &pcfg_pull_none_2ma>; + }; + + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + <3 RK_PA5 2 &pcfg_pull_none_2ma>; + }; + + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + <3 RK_PA6 2 &pcfg_pull_none_2ma>; + }; + + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + <3 RK_PA7 2 &pcfg_pull_none_2ma>; + }; + + pdm_clk1: pdm-clk1 { + rockchip,pins = + <3 RK_PB1 2 &pcfg_pull_none_2ma>; + }; + + pdm_sdi0: pdm-sdi0 { + rockchip,pins = + <3 RK_PC1 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <0 RK_PB7 1 &pcfg_pull_none_2ma>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <0 RK_PC3 1 &pcfg_pull_none_2ma>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <0 RK_PC5 1 &pcfg_pull_none_2ma>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = + <0 RK_PC4 1 &pcfg_pull_none_2ma>; + }; + }; + + pwm4 { + pwm4_pin: pwm4-pin { + rockchip,pins = + <1 RK_PB6 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm5 { + pwm5_pin: pwm5-pin { + rockchip,pins = + <1 RK_PB7 2 &pcfg_pull_none_2ma>; + }; + }; + pwm6 { + pwm6_pin: pwm6-pin { + rockchip,pins = + <3 RK_PA1 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm7 { + pwm7_pin: pwm7-pin { + rockchip,pins = + <3 RK_PA2 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm8 { + pwm8_pin: pwm8-pin { + rockchip,pins = + <3 RK_PD0 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm9 { + pwm9_pin: pwm9-pin { + rockchip,pins = + <3 RK_PD1 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm10 { + pwm10_pin: pwm10-pin { + rockchip,pins = + <3 RK_PD2 2 &pcfg_pull_none_2ma>; + }; + }; + + pwm11 { + pwm11_pin: pwm11-pin { + rockchip,pins = + <3 RK_PD3 2 &pcfg_pull_none_2ma>; + }; + }; + + sdmmc0 { + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <4 RK_PA2 1 &pcfg_pull_up_8ma>, + /* sdmmc0_d1 */ + <4 RK_PA3 1 &pcfg_pull_up_8ma>, + /* sdmmc0_d2 */ + <4 RK_PA4 1 &pcfg_pull_up_8ma>, + /* sdmmc0_d3 */ + <4 RK_PA5 1 &pcfg_pull_up_8ma>; + }; + + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_up_8ma>; + }; + + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + <4 RK_PA1 1 &pcfg_pull_up_8ma>; + }; + + sdmmc0_detn: sdmmc0-detn { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <4 RK_PB0 1 &pcfg_pull_up_4ma>, + /* sdmmc1_d1 */ + <4 RK_PB1 1 &pcfg_pull_up_4ma>, + /* sdmmc1_d2 */ + <4 RK_PB2 1 &pcfg_pull_up_4ma>, + /* sdmmc1_d3 */ + <4 RK_PB3 1 &pcfg_pull_up_4ma>; + }; + + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + <4 RK_PA6 1 &pcfg_pull_up_4ma>; + }; + + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + <4 RK_PA7 1 &pcfg_pull_up_4ma>; + }; + }; + + spi0 { + spi0_mosi: spi0-mosi { + rockchip,pins = + <1 RK_PB4 1 &pcfg_pull_up_2ma>; + }; + + spi0_miso: spi0-miso { + rockchip,pins = + <1 RK_PB5 1 &pcfg_pull_up_2ma>; + }; + + spi0_csn: spi0-csn { + rockchip,pins = + <1 RK_PB6 1 &pcfg_pull_up_2ma>; + }; + + spi0_clk: spi0-clk { + rockchip,pins = + <1 RK_PB7 1 &pcfg_pull_up_2ma>; + }; + + spi0_mosi_hs: spi0-mosi-hs { + rockchip,pins = + <1 RK_PB4 1 &pcfg_pull_up_2ma>; + }; + + spi0_miso_hs: spi0-miso-hs { + rockchip,pins = + <1 RK_PB5 1 &pcfg_pull_up_2ma>; + }; + + spi0_csn_hs: spi0-csn-hs { + rockchip,pins = + <1 RK_PB6 1 &pcfg_pull_up_2ma>; + }; + + spi0_clk_hs: spi0-clk-hs { + rockchip,pins = + <1 RK_PB7 1 &pcfg_pull_up_2ma>; + }; + }; + + spi1m0 { + spi1_clk: spi1-clk { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_up_2ma>; + }; + + spi1_mosi: spi1-mosi { + rockchip,pins = + <4 RK_PB5 2 &pcfg_pull_up_2ma>; + }; + + spi1_csn0: spi1-csn0 { + rockchip,pins = + <4 RK_PB6 2 &pcfg_pull_up_2ma>; + }; + + spi1_miso: spi1-miso { + rockchip,pins = + <4 RK_PB7 2 &pcfg_pull_up_2ma>; + }; + + spi1_csn1: spi1-csn1 { + rockchip,pins = + <4 RK_PC0 2 &pcfg_pull_up_2ma>; + }; + + spi1_clk_hs: spi1-clk-hs { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_up_2ma>; + }; + + spi1_mosi_hs: spi1-mosi-hs { + rockchip,pins = + <4 RK_PB5 2 &pcfg_pull_up_2ma>; + }; + + spi1_csn0_hs: spi1-csn0-hs { + rockchip,pins = + <4 RK_PB6 2 &pcfg_pull_up_2ma>; + }; + + spi1_miso_hs: spi1-miso-hs { + rockchip,pins = + <4 RK_PB7 2 &pcfg_pull_up_2ma>; + }; + + spi1_csn1_hs: spi1-csn1-hs { + rockchip,pins = + <4 RK_PC0 2 &pcfg_pull_up_2ma>; + }; + }; + + spi1m1 { + spi1m1_clk: spi1m1-clk { + rockchip,pins = + <3 RK_PC7 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_mosi: spi1m1-mosi { + rockchip,pins = + <3 RK_PD0 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins = + <3 RK_PD1 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_miso: spi1m1-miso { + rockchip,pins = + <3 RK_PD2 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_csn1: spi1m1-csn1 { + rockchip,pins = + <3 RK_PD3 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_clk_hs: spi1m1-clk-hs { + rockchip,pins = + <3 RK_PC7 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_mosi_hs: spi1m1-mosi-hs { + rockchip,pins = + <3 RK_PD0 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_csn0_hs: spi1m1-csn0-hs { + rockchip,pins = + <3 RK_PD1 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_miso_hs: spi1m1-miso-hs { + rockchip,pins = + <3 RK_PD2 3 &pcfg_pull_up_2ma>; + }; + + spi1m1_csn1_hs: spi1m1-csn1-hs { + rockchip,pins = + <3 RK_PD3 3 &pcfg_pull_up_2ma>; + }; + }; + + spi2m0 { + spi2m0_miso: spi2m0-miso { + rockchip,pins = + <1 RK_PA6 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_clk: spi2m0-clk { + rockchip,pins = + <1 RK_PA7 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_mosi: spi2m0-mosi { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_csn: spi2m0-csn { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_miso_hs: spi2m0-miso-hs { + rockchip,pins = + <1 RK_PA6 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_clk_hs: spi2m0-clk-hs { + rockchip,pins = + <1 RK_PA7 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_mosi_hs: spi2m0-mosi-hs { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_up_2ma>; + }; + + spi2m0_csn_hs: spi2m0-csn-hs { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_up_2ma>; + }; + }; + + spi2m1 { + spi2m1_miso: spi2m1-miso { + rockchip,pins = + <2 RK_PA4 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_clk: spi2m1-clk { + rockchip,pins = + <2 RK_PA5 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_mosi: spi2m1-mosi { + rockchip,pins = + <2 RK_PA6 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_csn: spi2m1-csn { + rockchip,pins = + <2 RK_PA7 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_miso_hs: spi2m1-miso-hs { + rockchip,pins = + <2 RK_PA4 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_clk_hs: spi2m1-clk-hs { + rockchip,pins = + <2 RK_PA5 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_mosi_hs: spi2m1-mosi-hs { + rockchip,pins = + <2 RK_PA6 3 &pcfg_pull_up_2ma>; + }; + + spi2m1_csn_hs: spi2m1-csn-hs { + rockchip,pins = + <2 RK_PA7 3 &pcfg_pull_up_2ma>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PB3 1 &pcfg_pull_up_2ma>, + /* uart0_tx */ + <0 RK_PB2 1 &pcfg_pull_up_2ma>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <0 RK_PB4 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <0 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <4 RK_PB0 2 &pcfg_pull_up_2ma>, + /* uart1_txm0 */ + <4 RK_PB1 2 &pcfg_pull_up_2ma>; + }; + + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <1 RK_PB4 3 &pcfg_pull_up_2ma>, + /* uart1_txm1 */ + <1 RK_PB5 3 &pcfg_pull_up_2ma>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = + <4 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <4 RK_PA3 2 &pcfg_pull_up_2ma>, + /* uart2_txm0 */ + <4 RK_PA2 2 &pcfg_pull_up_2ma>; + }; + + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <2 RK_PD1 2 &pcfg_pull_up_2ma>, + /* uart2_txm1 */ + <2 RK_PD0 2 &pcfg_pull_up_2ma>; + }; + + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rxm2 */ + <3 RK_PA4 2 &pcfg_pull_up_2ma>, + /* uart2_txm2 */ + <3 RK_PA3 2 &pcfg_pull_up_2ma>; + }; + }; + + uart3 { + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <0 RK_PC4 2 &pcfg_pull_up_2ma>, + /* uart3_txm0 */ + <0 RK_PC3 2 &pcfg_pull_up_2ma>; + }; + + uart3_ctsm0: uart3-ctsm0 { + rockchip,pins = + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + uart3_rtsm0: uart3-rtsm0 { + rockchip,pins = + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + /* uart4_rx */ + <4 RK_PB4 1 &pcfg_pull_up_2ma>, + /* uart4_tx */ + <4 RK_PB5 1 &pcfg_pull_up_2ma>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = + <4 RK_PB6 1 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = + <4 RK_PB7 1 &pcfg_pull_none>; + }; + }; + + uart5 { + uart5_xfer: uart5-xfer { + rockchip,pins = + /* uart5_rx */ + <3 RK_PC3 2 &pcfg_pull_up_2ma>, + /* uart5_tx */ + <3 RK_PC2 2 &pcfg_pull_up_2ma>; + }; + }; + + uart6 { + uart6_xfer: uart6-xfer { + rockchip,pins = + /* uart6_rx */ + <3 RK_PC5 2 &pcfg_pull_up_2ma>, + /* uart6_tx */ + <3 RK_PC4 2 &pcfg_pull_up_2ma>; + }; + }; + + uart7 { + uart7_xfer: uart7-xfer { + rockchip,pins = + /* uart7_rx */ + <3 RK_PC7 2 &pcfg_pull_up_2ma>, + /* uart7_tx */ + <3 RK_PC6 2 &pcfg_pull_up_2ma>; + }; + }; + + tsadc { + tsadc_otp_gpio: tsadc-otp-gpio { + rockchip,pins = + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tsadc_otp_out: tsadc-otp-out { + rockchip,pins = + <0 RK_PA6 2 &pcfg_pull_none>; + }; + }; + + xin32k { + clkin_32k: clkin-32k { + rockchip,pins = + <0 RK_PC2 1 &pcfg_pull_none>; + }; + + clkout_32k: clkout-32k { + rockchip,pins = + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/rk1808k.dtsi b/rk1808k.dtsi new file mode 100644 index 0000000..78bd92e --- /dev/null +++ b/rk1808k.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +&cpu0_opp_table { + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <1008000>; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_log>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 924000 + SYS_STATUS_REBOOT 924000 + >; +}; + +&dmc_opp_table { + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <664000>; + rockchip,thermal-zone = "soc-thermal"; +}; + +&thermal_zones { + soc-thermal { + sustainable-power = <1224>; + k_pu = <27>; + k_po = <55>; + k_i = <0>; + + trips { + trip-point-0 { + temperature = <85000>; + }; + trip-point-1 { + temperature = <100000>; + }; + }; + /delete-node/ cooling-maps; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; diff --git a/rk3308-ai-va-v10.dts b/rk3308-ai-va-v10.dts new file mode 100644 index 0000000..4ab9afd --- /dev/null +++ b/rk3308-ai-va-v10.dts @@ -0,0 +1,692 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308 voice assistant v10 board"; + compatible = "rockchip,rk3308-ai-va-v10", "rockchip,rk3308"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0c0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + adc-keys0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + func-key { + linux,code = ; + label = "function"; + press-threshold-microvolt = <17000>; + }; + }; + + adc-keys1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + play-key { + linux,code = ; + label = "play"; + press-threshold-microvolt = <625000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&mic_mute>; + + mute { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Mic Mute"; + debounce-interval = <100>; + }; + }; + + rotary { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&rotary_gpio>; + gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>, + <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + linux,axis = <0>; /* REL_X */ + rotary-encoder,relative-axis; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "i2s_8ch_0"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_0>; + }; + + codec { + sound-dai = <&dummy_codec>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch_0>; + }; + + codec { + sound-dai = <&tas5711>; + }; + }; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + vdd_log: vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + status = "okay"; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vccio_sdio: vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_1v8_codec: vcc-1v8-codec { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + vcc_3v3_codec: vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4_rts>; + pinctrl-1 = <&uart4_rts_pin>; + BT,power_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>; + wifi_chip_type = "ap6255"; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&dmc { + center-supply = <&vdd_core>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&fiq_debugger { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_flash>; + vccio4-supply = <&vccio_sdio>; + vccio5-supply = <&vcc_io>; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + is31fl3236: led-controller@3c { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; + + tas5711: tas5711@1b { + #sound-dai-cells = <0>; + compatible = "ti,tas5711"; + reg = <0x1b>; + clocks = <&cru SCLK_I2S0_8CH_TX_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_mclk>; + pdn-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2s_8ch_0 { + status = "okay"; + assigned-clocks = <&cru SCLK_I2S0_8CH_RX>; + assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>; + rockchip,clk-trcm = <1>; + #sound-dai-cells = <0>; +}; + +&pinctrl { + buttons { + mic_mute: mic-mute { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + rotary { + rotary_gpio: rotary-gpio { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart4_gpios: uart4-gpios { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&rockchip_suspend { + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM_REGULATOR + ) + >; + + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/rk3308-evb-amic-v10.dts b/rk3308-evb-amic-v10.dts new file mode 100644 index 0000000..557daa8 --- /dev/null +++ b/rk3308-evb-amic-v10.dts @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rk3308-evb-v10.dtsi" + +/ { + model = "Rockchip RK3308 evb analog mic board"; + compatible = "rockchip,rk3308-evb-amic-v10", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <0 1 2>; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&is31fl3236 { + reg = <0x3f>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-amic-v11.dts b/rk3308-evb-amic-v11.dts new file mode 100644 index 0000000..10c4743 --- /dev/null +++ b/rk3308-evb-amic-v11.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-v11.dtsi" + +/ { + model = "Rockchip RK3308 evb analog mic v11 board"; + compatible = "rockchip,rk3308-evb-amic-v11", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <1 2 3 0>; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,det-channel = <0>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-amic-v13.dts b/rk3308-evb-amic-v13.dts new file mode 100644 index 0000000..e5c3140 --- /dev/null +++ b/rk3308-evb-amic-v13.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-v13.dtsi" + +/ { + model = "Rockchip RK3308 evb analog mic v13 board"; + compatible = "rockchip,rk3308-evb-amic-v13", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <1 2 3 0>; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,det-channel = <0>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-audio-amic-v10.dts b/rk3308-evb-audio-amic-v10.dts new file mode 100644 index 0000000..1f4ad4f --- /dev/null +++ b/rk3308-evb-audio-amic-v10.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-audio-v10.dtsi" + +/ { + model = "Rockchip RK3308 evb audio analog mic v10 board"; + compatible = "rockchip,rk3308-evb-audio-amic-v10", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <1 2 3 0>; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,det-channel = <0>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-audio-v10-display-rgb.dts b/rk3308-evb-audio-v10-display-rgb.dts new file mode 100644 index 0000000..0a44477 --- /dev/null +++ b/rk3308-evb-audio-v10-display-rgb.dts @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-audio-amic-v10.dts" + +/ { + model = "Rockchip RK3308B EVB AUDIO DDR3 V10 Board + Rockchip RK3308 RGB ExtBoard V10"; + compatible = "rockchip,rk3308-evb-audio-rgb-display-v10", "rockchip,rk3308"; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + status = "okay"; + + display-timings { + native-mode = <&fx070_dhm11boe_timing>; + + fx070_dhm11boe_timing: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <2>; //value range <2~22> + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x1000000>; + linux,cma-default; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int>; + touch-gpio = <&gpio0 RK_PA6 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + max-x = <1024>; + max-y = <600>; + tp-size = <9110>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&pinctrl { + tp { + tp_int: tp-int { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3308-evb-audio-v10.dtsi b/rk3308-evb-audio-v10.dtsi new file mode 100644 index 0000000..28f5aff --- /dev/null +++ b/rk3308-evb-audio-v10.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +#include +#include "rk3308-evb-v11.dtsi" + +/ { + /delete-node/ wireless-wlan; + /delete-node/ wireless-bluetooth; + /delete-node/ gpio-keys; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>; + wifi_chip_type = "ap6256"; + WIFI,host_wake_irq = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4_rts>; + pinctrl-1 = <&uart4_rts_pin>; + BT,power_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&acodec { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; +}; + +&emmc { + status = "okay"; +}; + +&pinctrl { + acodec { + hp_det: hp-det { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; +}; + +&sfc { + status = "okay"; +}; + +&vccio_sd { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; +}; diff --git a/rk3308-evb-dmic-i2s-v10.dts b/rk3308-evb-dmic-i2s-v10.dts new file mode 100644 index 0000000..88c1e9c --- /dev/null +++ b/rk3308-evb-dmic-i2s-v10.dts @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rk3308-evb-v10.dtsi" + +/ { + model = "Rockchip RK3308 evb digital-i2s mic board"; + compatible = "rockchip,rk3308-evb-dmic-i2s-v10", "rockchip,rk3308"; + + i2s_16ch_dais: i2s-16ch-dais { + status = "disabled"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&i2s_8ch_0>, <&i2s_8ch_1>; + capture,channel-mapping = <8 8>; + playback,channel-mapping = <0 0>; + bitclock-master = <1 0>; + frame-master = <1 0>; + rockchip,grf = <&grf>; + }; + + i2s_8ch_0_2_dais: i2s-8ch-0-2-dais { + status = "okay"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&i2s_8ch_0>, <&i2s_8ch_2>; + capture,channel-mapping = <6 2>; + playback,channel-mapping = <0 2>; + }; + + i2s-dmic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,i2s-dmic-array"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch_0>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,cpu = <&i2s_8ch_0_2_dais>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_0 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_1 { + status = "disabled"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_1_m0_sdo0 + &i2s_8ch_1_m0_sdo1_sdi3 + &i2s_8ch_1_m0_sdo2_sdi2 + &i2s_8ch_1_m0_sdo3_sdi1 + &i2s_8ch_1_m0_sdi0>; +}; + +&i2s_8ch_2 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_0>; + rockchip,buffer-time-ms = <200>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-dmic-i2s-v11.dts b/rk3308-evb-dmic-i2s-v11.dts new file mode 100644 index 0000000..364f74a --- /dev/null +++ b/rk3308-evb-dmic-i2s-v11.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-v11.dtsi" + +/ { + model = "Rockchip RK3308 evb digital-i2s mic v11 board"; + compatible = "rockchip,rk3308-evb-dmic-i2s-v11", "rockchip,rk3308"; + + i2s_8ch_0_2_dais: i2s-8ch-0-2-dais { + status = "okay"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&i2s_8ch_0>, <&i2s_8ch_2>; + capture,channel-mapping = <6 2>; + playback,channel-mapping = <0 2>; + }; + + i2s-dmic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,i2s-dmic-array"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch_0>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,cpu = <&i2s_8ch_0_2_dais>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_0 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_2 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_0>; + rockchip,buffer-time-ms = <200>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-dmic-pdm-v10.dts b/rk3308-evb-dmic-pdm-v10.dts new file mode 100644 index 0000000..e2891ce --- /dev/null +++ b/rk3308-evb-dmic-pdm-v10.dts @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rk3308-evb-v10.dtsi" + +/ { + model = "Rockchip RK3308 evb digital-pdm mic board"; + compatible = "rockchip,rk3308-evb-dmic-pdm-v10", "rockchip,rk3308"; + + pdm_i2s_dais: pdm-i2s-dais { + status = "okay"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&pdm_8ch>, <&i2s_8ch_2>; + capture,channel-mapping = <6 2>; + playback,channel-mapping = <0 2>; + }; + + pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,cpu = <&pdm_i2s_dais>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&pdm_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_m2_clk + &pdm_m2_clkm + &pdm_m2_sdi0 + &pdm_m2_sdi1 + &pdm_m2_sdi2 + &pdm_m2_sdi3>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&pdm_8ch>; + rockchip,buffer-time-ms = <200>; + rockchip,det-channel = <2>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; + +&pdm_i2s_dais { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_2 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-dmic-pdm-v11.dts b/rk3308-evb-dmic-pdm-v11.dts new file mode 100644 index 0000000..c4a7178 --- /dev/null +++ b/rk3308-evb-dmic-pdm-v11.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-v11.dtsi" + +/ { + model = "Rockchip RK3308 evb digital-pdm mic v11 board"; + compatible = "rockchip,rk3308-evb-dmic-pdm-v11", "rockchip,rk3308"; + + pdm_i2s_dais: pdm-i2s-dais { + status = "okay"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&pdm_8ch>, <&i2s_8ch_2>; + capture,channel-mapping = <6 2>; + playback,channel-mapping = <0 2>; + bitclock-inversion = <1 0>; + }; + + pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,cpu = <&pdm_i2s_dais>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&rk_timer_rtc { + status = "okay"; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&pdm_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_m2_clk + &pdm_m2_clkm + &pdm_m2_sdi0 + &pdm_m2_sdi1 + &pdm_m2_sdi2 + &pdm_m2_sdi3>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&pdm_8ch>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + rockchip,buffer-time-ms = <200>; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_2 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&pdm_i2s_dais { + status = "okay"; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-dmic-pdm-v13.dts b/rk3308-evb-dmic-pdm-v13.dts new file mode 100644 index 0000000..d92dbcc --- /dev/null +++ b/rk3308-evb-dmic-pdm-v13.dts @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308-evb-v13.dtsi" + +/ { + model = "Rockchip RK3308 evb digital-pdm mic v13 board"; + compatible = "rockchip,rk3308-evb-dmic-pdm-v13", "rockchip,rk3308"; + + pdm_i2s_dais: pdm-i2s-dais { + status = "okay"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&pdm_8ch>, <&i2s_8ch_2>; + capture,channel-mapping = <6 2>; + playback,channel-mapping = <0 2>; + bitclock-inversion = <1 0>; + }; + + pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,cpu = <&pdm_i2s_dais>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&rk_timer_rtc { + status = "okay"; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_2ch_0 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&pdm_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_m2_clk + &pdm_m2_clkm + &pdm_m2_sdi0 + &pdm_m2_sdi1 + &pdm_m2_sdi2 + &pdm_m2_sdi3>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&pdm_8ch>; + rockchip,det-channel = <0>; + rockchip,mode = <1>; + rockchip,buffer-time-ms = <200>; + #sound-dai-cells = <0>; +}; + +&i2s_8ch_2 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&pdm_i2s_dais { + status = "okay"; + #sound-dai-cells = <0>; +}; diff --git a/rk3308-evb-ext-v10.dtsi b/rk3308-evb-ext-v10.dtsi new file mode 100644 index 0000000..f256ba0 --- /dev/null +++ b/rk3308-evb-ext-v10.dtsi @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_pins>; + spi-delay-us = <10>; + status = "okay"; + + sck-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + panel: panel { + compatible = "simple-panel-spi"; + reg = <0>; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + init-delay-ms = <10>; + width-mm = <217>; + height-mm = <136>; + rockchip,cmd-type = "spi"; + status = "okay"; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + /* type delay num val1 val2 val3 */ + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a + 01 00 01 66 /* + * interface pixel format: + * 66 for RGB666(18bit) + */ + + 00 00 01 b0 + 01 00 01 00 + + 00 00 01 b1 + 01 00 01 a0 /* + * frame rate control: + * a0 (60hz) for RGB666(18bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 32 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 00 01 29 + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + /* + * 10453500 for RGB666(18bit) + */ + clock-frequency = <10453500>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&pinctrl { + soft_spi { + spi_pins: spi-pins { + rockchip,pins = + /* spi sdo */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, + /* spi sdi */ + <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, + /* spi scl */ + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, + /* spi cs */ + <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3308-evb-v10.dtsi b/rk3308-evb-v10.dtsi new file mode 100644 index 0000000..66fcf6c --- /dev/null +++ b/rk3308-evb-v10.dtsi @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308 EVB"; + compatible = "rockchip,rk3308-evb", "rockchip,rk3308"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0c0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + adc-keys0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + func-key { + linux,code = ; + label = "function"; + press-threshold-microvolt = <18000>; + }; + }; + + adc-keys1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "micmute"; + press-threshold-microvolt = <1130000>; + }; + + home-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <901000>; + }; + + menu-key { + linux,code = ; + label = "play"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <18000>; + }; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + wakeup-source; + debounce-interval = <100>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + acodec_sound: acodec-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-acodec"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>; + }; + + bluetooth_sound: bluetooth-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-pcm"; + rockchip,mclk-fs = <128>; + rockchip,cpu = <&i2s_2ch_0>; + rockchip,codec = <&dummy_codec>; + rockchip,format = "dsp_b"; + rockchip,bitclock-inversion = <0>; + rockchip,wait-card-locked = <0>; + }; + + spdif_rx_sound: spdif-rx-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-rx-sound"; + simple-audio-card,cpu { + sound-dai = <&spdif_rx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + spdif_tx_sound: spdif-tx-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_tx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vdd_log: vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-early-min-microvolt = <1015000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + status = "okay"; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcc_3v3_codec: vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_sdio: vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_1v8_codec: vcc-1v8-codec { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vbus_host: vbus-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_drv>; + regulator-name = "vbus_host"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4_rts>; + pinctrl-1 = <&uart4_rts_pin>; + BT,power_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&acodec { + status = "okay"; + + rockchip,no-deep-low-power; + rockchip,loopback-grp = <3>; + hp-ctl-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + spk-ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&dmc { + center-supply = <&vdd_core>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&fiq_debugger { + status = "okay"; +}; + +&mac { + phy-supply = <&vcc_phy>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&mac_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk>; + snps,reset-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "disable"; +}; + +&io_domains { + status = "okay"; + + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_flash>; + vccio4-supply = <&vccio_sdio>; + vccio5-supply = <&vcc_io>; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + is31fl3236: led-controller@3c { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&i2s_8ch_2 { + status = "okay"; +}; + +&nandc { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM_REGULATOR + ) + >; + + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <300>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sfc { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_drv: usb-drv { + rockchip,pins = + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart4_gpios: uart4-gpios { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci{ + status = "okay"; +}; diff --git a/rk3308-evb-v11.dtsi b/rk3308-evb-v11.dtsi new file mode 100644 index 0000000..9a905ea --- /dev/null +++ b/rk3308-evb-v11.dtsi @@ -0,0 +1,848 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308 EVB V11"; + compatible = "rockchip,rk3308-evb-v11", "rockchip,rk3308"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0c0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "micmute"; + press-threshold-microvolt = <1130000>; + }; + + home-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <901000>; + }; + + menu-key { + linux,code = ; + label = "play"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <18000>; + }; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + wakeup-source; + debounce-interval = <100>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + acodec_sound: acodec-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-acodec"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>; + }; + + bluetooth_sound: bluetooth-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-pcm"; + rockchip,mclk-fs = <128>; + rockchip,cpu = <&i2s_2ch_0>; + rockchip,codec = <&dummy_codec>; + rockchip,format = "dsp_b"; + rockchip,bitclock-inversion = <0>; + rockchip,wait-card-locked = <0>; + }; + + spdif_rx_sound: spdif-rx-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-rx-sound"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_rx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + spdif_tx_sound: spdif-tx-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx-sound"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + tas5731_sound: tas5731-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,tas5731"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch_1>; + }; + simple-audio-card,codec { + sound-dai = <&tas5731>; + }; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + status = "okay"; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vccio_sdio: vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_1v8_codec: vcc-1v8-codec { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + vcc_3v3_codec: vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vbus_host: vbus-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_drv>; + regulator-name = "vbus_host"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart4_rts>; + pinctrl-1 = <&uart4_rts_pin>; + BT,power_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>; + wifi_chip_type = "ap6255"; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&acodec { + status = "okay"; + + rockchip,no-deep-low-power; + rockchip,loopback-grp = <0>; + hp-ctl-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + spk-ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&cpu0_opp_table { + opp-1200000000 { + status = "okay"; + }; + opp-1296000000 { + status = "okay"; + }; +}; + +&rk3308bs_cpu0_opp_table { + opp-1008000000 { + status = "okay"; + }; + opp-1104000000 { + status = "okay"; + }; +}; + +&dmc { + center-supply = <&vdd_log>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "disabled"; +}; + +&fiq_debugger { + status = "okay"; +}; + +&mac { + phy-supply = <&vcc_phy>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&mac_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk>; + snps,reset-gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "disable"; +}; + +&io_domains { + status = "okay"; + + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_flash>; + vccio4-supply = <&vccio_sdio>; + vccio5-supply = <&vccio_sd>; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + tas5731: tas5731@1a { + #sound-dai-cells = <0>; + compatible = "ti,tas5731"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S1_8CH_TX_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_1_m0_mclk>; + pdn-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + }; + + is31fl3236: led-controller@3f { + compatible = "issi,is31fl3236"; + reg = <0x3f>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&i2s_8ch_1 { + status = "disabled"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_1_m0_sclktx + &i2s_8ch_1_m0_lrcktx + &i2s_8ch_1_m0_sdo0 + &i2s_8ch_1_m0_mclk>; +}; + +&i2s_8ch_2 { + status = "okay"; +}; + +&nandc { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM_REGULATOR + ) + >; + + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <300>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_drv: usb-drv { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart4_gpios: uart4-gpios { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_wake_host: wifi-wake-host { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci{ + status = "okay"; +}; diff --git a/rk3308-evb-v13.dtsi b/rk3308-evb-v13.dtsi new file mode 100644 index 0000000..00e903e --- /dev/null +++ b/rk3308-evb-v13.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +#include +#include "rk3308-evb-v11.dtsi" + +/ { + model = "Rockchip RK3308 EVB V13"; + compatible = "rockchip,rk3308-evb-v13", "rockchip,rk3308"; + + /delete-node/ wireless-wlan; + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>; + wifi_chip_type = "ap6256"; + WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; diff --git a/rk3308-evb.dts b/rk3308-evb.dts new file mode 100644 index 0000000..5873ca8 --- /dev/null +++ b/rk3308-evb.dts @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308 EVB"; + compatible = "rockchip,rk3308-evb", "rockchip,rk3308"; + + chosen { + stdout-path = "serial4:1500000n8"; + }; + + adc-keys0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + func-key { + linux,code = ; + label = "function"; + press-threshold-microvolt = <18000>; + }; + }; + + adc-keys1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "micmute"; + press-threshold-microvolt = <1130000>; + }; + + home-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <901000>; + }; + + menu-key { + linux,code = ; + label = "play"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + debounce-interval = <100>; + wakeup-source; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc12v_dcin>; + }; + + vccio_sdio: vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&usb_drv>; + regulator-name = "vbus_host"; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&pinctrl { + buttons { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA6 0 &pcfg_pull_up>; + }; + }; + + usb { + usb_drv: usb-drv { + rockchip,pins = <0 RK_PC5 0 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 0 &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "okay"; +}; diff --git a/rk3308-fpga.dts b/rk3308-fpga.dts new file mode 100644 index 0000000..225aca3 --- /dev/null +++ b/rk3308-fpga.dts @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308 FPGA Platform"; + compatible = "rockchip,rk3308-fpga", "rockchip,rk3308"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0b0000 console=ttyFIQ0 init=/init initrd=0x9000000,0x18bfc0"; + }; + + memory@200000 { + device_type = "memory"; + reg = <0x0 0x00200000 0x0 0x0FE00000>; + }; +}; + +&fiq_debugger { + rockchip,serial-id = <1>; + rockchip,irq-mode-enable = <1>; + status = "ok"; +}; + +&cpu1 { + /delete-property/enable-method; +}; + +&cpu2 { + /delete-property/enable-method; +}; + +&cpu3 { + /delete-property/enable-method; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; + num-slots = <1>; + status = "okay"; +}; diff --git a/rk3308-roc-cc.dts b/rk3308-roc-cc.dts new file mode 100644 index 0000000..d9292da --- /dev/null +++ b/rk3308-roc-cc.dts @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3308.dtsi" + +/ { + model = "Firefly ROC-RK3308-CC board"; + compatible = "firefly,roc-rk3308-cc", "rockchip,rk3308"; + chosen { + stdout-path = "serial2:1500000n8"; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_recv_pin>; + }; + + ir_tx { + compatible = "pwm-ir-tx"; + pwms = <&pwm5 0 25000 0>; + }; + + leds { + compatible = "gpio-leds"; + + power_led: led-0 { + label = "firefly:red:power"; + linux,default-trigger = "ir-power-click"; + default-state = "on"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + user_led: led-1 { + label = "firefly:blue:user"; + linux,default-trigger = "ir-user-click"; + default-state = "off"; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + }; + }; + + typec_vcc5v: typec-vcc5v { + compatible = "regulator-fixed"; + regulator-name = "typec_vcc5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&typec_vcc5v>; + }; + + vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_sdmmc: vcc-sdmmc { + compatible = "regulator-gpio"; + regulator-name = "vcc_sdmmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + pwm-supply = <&vcc5v0_sys>; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&emmc { + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + rtc: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&pwm5 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5_pin_pull_down>; +}; + +&pinctrl { + ir-receiver { + ir_recv_pin: ir-recv-pin { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&sdmmc { + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <300>; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdmmc>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/rk3308-voice-module-board-v10.dts b/rk3308-voice-module-board-v10.dts new file mode 100644 index 0000000..2586d99 --- /dev/null +++ b/rk3308-voice-module-board-v10.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "arm/rk3308-voice-module-board-v10-aarch32.dts" + +/ { + model = "Rockchip RK3308 Voice Module Board V10"; + compatible = "rockchip,rk3308-voice-module-board-v10", "rockchip,rk3308"; +}; + +&ramoops { + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x30000>; + console-size = <0xc0000>; +}; diff --git a/rk3308.dtsi b/rk3308.dtsi new file mode 100644 index 0000000..fe3ab33 --- /dev/null +++ b/rk3308.dtsi @@ -0,0 +1,2726 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3308"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &mac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + dynamic-power-coefficient = <83>; + operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&l2>; + power-model { + compatible = "simple-power-model"; + leakage-range= <5 50>; + ls = <6086 6346 (-63)>; + static-coefficient = <100000>; + ts = <(-109130) 101460 (-1620) 30>; + thermal-zone = "soc-thermal"; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + operating-points-v2 = <&cpu0_opp_table>, <&rk3308bs_cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + next-level-cache = <&l2>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <1000000>; + rockchip,max-volt = <1325000>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1296 50000 + >; + + rockchip,evb-irdrop = <25000>; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + rockchip,pvtm-voltage-sel = < + 0 54000 0 + 54001 56000 1 + 56001 58500 2 + 58501 61000 3 + 61001 63500 4 + 63501 99999 5 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <1025000>; + rockchip,pvtm-ch = <0 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <35>; + rockchip,pvtm-temp-prop = <(-15) (-37)>; + rockchip,thermal-zone = "soc-thermal"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1325000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1025000 1025000 1325000>; + opp-microvolt-L0 = <1025000 1025000 1325000>; + opp-microvolt-L1 = <1025000 1025000 1325000>; + opp-microvolt-L2 = <1025000 1025000 1325000>; + opp-microvolt-L3 = <1000000 1000000 1325000>; + opp-microvolt-L4 = <975000 975000 1325000>; + opp-microvolt-L5 = <950000 950000 1325000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1125000 1125000 1325000>; + opp-microvolt-L0 = <1125000 1125000 1325000>; + opp-microvolt-L1 = <1100000 1100000 1325000>; + opp-microvolt-L2 = <1100000 1100000 1325000>; + opp-microvolt-L3 = <1075000 1075000 1325000>; + opp-microvolt-L4 = <1050000 1050000 1325000>; + opp-microvolt-L5 = <1025000 1025000 1325000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1250000 1250000 1325000>; + opp-microvolt-L0 = <1250000 1250000 1325000>; + opp-microvolt-L1 = <1225000 1225000 1325000>; + opp-microvolt-L2 = <1200000 1200000 1325000>; + opp-microvolt-L3 = <1175000 1175000 1325000>; + opp-microvolt-L4 = <1150000 1150000 1325000>; + opp-microvolt-L5 = <1125000 1125000 1325000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1300000 1300000 1325000>; + opp-microvolt-L0 = <1300000 1300000 1325000>; + opp-microvolt-L1 = <1275000 1275000 1325000>; + opp-microvolt-L2 = <1250000 1250000 1325000>; + opp-microvolt-L3 = <1225000 1225000 1325000>; + opp-microvolt-L4 = <1200000 1200000 1325000>; + opp-microvolt-L5 = <1175000 1175000 1325000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + }; + + rk3308bs_cpu0_opp_table: rk3308bs-cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-min-volt = <900000>; + rockchip,max-volt = <1200000>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1200 50000 + >; + + rockchip,evb-irdrop = <25000>; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "leakage"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <850000 850000 1200000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1200000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1000000 1000000 1200000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1125000 1125000 1200000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <1200000 1200000 1200000>; + clock-latency-ns = <40000>; + status = "disabled"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>; + nvmem-cell-names = "id"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + logo-memory-region = <&drm_logo>; + status = "disabled"; + + route { + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_rgb>; + }; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3308-dmc"; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>, <&rk3308bs_dmc_opp_table>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + rockchip,evb-irdrop = <25000>; + + opp-394000000 { + opp-hz = /bits/ 64 <394000000>; + opp-microvolt = <950000>; + }; + opp-452000000 { + opp-hz = /bits/ 64 <452000000>; + opp-microvolt = <975000>; + }; + opp-590000000 { + opp-hz = /bits/ 64 <590000000>; + opp-microvolt = <1000000>; + }; + }; + + rk3308bs_dmc_opp_table: rk3308bs-dmc-opp-table { + compatible = "operating-points-v2"; + + opp-394000000 { + opp-hz = /bits/ 64 <394000000>; + opp-microvolt = <900000>; + }; + opp-452000000 { + opp-hz = /bits/ 64 <452000000>; + opp-microvolt = <900000>; + }; + opp-590000000 { + opp-hz = /bits/ 64 <590000000>; + opp-microvolt = <900000>; + }; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "disabled"; + }; + + mac_clkin: external-mac-clock { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "mac_clkin"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + ramoops_mem: ramoops_mem { + reg = <0x0 0x110000 0x0 0xf0000>; + reg-names = "ramoops_mem"; + }; + + ramoops: ramoops { + compatible = "ramoops"; + record-size = <0x0 0x30000>; + console-size = <0x0 0xc0000>; + ftrace-size = <0x0 0x00000>; + pmsg-size = <0x0 0x00000>; + memory-region = <&ramoops_mem>; + }; + + rgb: rgb { + compatible = "rockchip,rk3308-rgb"; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_rgb>; + }; + }; + + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3308"; + status = "disabled"; + rockchip,sleep-mode-config = < + (0 + | RKPM_PMU_HW_PLLS_PD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO0_WAKEUP_EN + ) + >; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + grf: grf@ff000000 { + compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff000000 0x0 0x10000>; + + io_domains: io-domains { + compatible = "rockchip,rk3308-io-voltage-domain"; + status = "disabled"; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3308-pmu-pvtm"; + clocks = <&cru SCLK_PVTM_PMU>; + clock-names = "pmu"; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x500>; + mode-bootloader = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-fastboot = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + usb2phy_grf: syscon@ff008000 { + compatible = "rockchip,rk3308-usb2phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff008000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2phy@100 { + compatible = "rockchip,rk3308-usb2phy"; + reg = <0x100 0x10>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + u2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + detect_grf: syscon@ff00b000 { + compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff00b000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + core_grf: syscon@ff00c000 { + compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff00c000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pvtm: pvtm { + compatible = "rockchip,rk3308-pvtm"; + clocks = <&cru SCLK_PVTM_CORE>; + clock-names = "core"; + }; + }; + + i2c0: i2c@ff040000 { + compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff040000 0x0 0x1000>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ff050000 { + compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff050000 0x0 0x1000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff060000 { + compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff060000 0x0 0x1000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ff070000 { + compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff070000 0x0 0x1000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@ff080000 { + compatible = "rockchip,rk3308-wdt", "snps,dw-wdt"; + reg = <0x0 0xff080000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + uart0: serial@ff0a0000 { + compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff0a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 4>, <&dmac0 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "disabled"; + }; + + uart1: serial@ff0b0000 { + compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff0b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + status = "disabled"; + }; + + uart2: serial@ff0c0000 { + compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff0c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart3: serial@ff0d0000 { + compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff0d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + uart4: serial@ff0e0000 { + compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff0e0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 18>, <&dmac1 19>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; + status = "disabled"; + }; + + spi0: spi@ff120000 { + compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>; + pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>; + status = "disabled"; + }; + + spi1: spi@ff130000 { + compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>; + pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>; + status = "disabled"; + }; + + spi2: spi@ff140000 { + compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 16>, <&dmac1 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>; + pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>; + status = "disabled"; + }; + + pwm8: pwm@ff160000 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff160000 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm9: pwm@ff160010 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff160010 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm10: pwm@ff160020 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff160020 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm11: pwm@ff160030 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff160030 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm4: pwm@ff170000 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff170000 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm5: pwm@ff170010 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff170010 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm6: pwm@ff170020 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff170020 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm7: pwm@ff170030 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff170030 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm0: pwm@ff180000 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180000 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@ff180010 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180010 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@ff180020 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180020 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ff180030 { + compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff180030 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + rktimer: rktimer@ff1a0000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x0 0xff1a0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + rk_timer_rtc: rk-timer-rtc@ff1a0020 { + compatible = "rockchip,rk3308-timer-rtc"; + reg = <0x0 0xff1a0020 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>; + clock-names = "pclk", "timer"; + status = "disabled"; + }; + + saradc: saradc@ff1e0000 { + compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff1e0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + #io-channel-cells = <1>; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <360>; + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point@0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point@1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <115000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@ff1f0000 { + compatible = "rockchip,rk3308-tsadc"; + reg = <0x0 0xff1f0000 0x0 0x100>; + interrupts = ; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <50000>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_pin>; + pinctrl-1 = <&tsadc_otp_out>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + status = "disabled"; + }; + + otp: otp@ff210000 { + compatible = "rockchip,rk3308-otp"; + reg = <0x0 0xff210000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, + <&cru PCLK_OTP_PHY>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTP_PHY>; + reset-names = "otp_phy"; + + /* Data cells */ + otp_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@18 { + reg = <0x18 0x1>; + }; + }; + + dmac0: dma-controller@ff2c0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2c0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + dmac1: dma-controller@ff2d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff2d0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + vop: vop@ff2e0000 { + compatible = "rockchip,rk3308-vop"; + reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, + <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vop>; + }; + }; + }; + + rng: rng@ff2f0400 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xff2f0400 0x0 0x80>; + clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + clock-names = "clk_crypto", "clk_crypto_apk", + "aclk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO>, <&cru SCLK_CRYPTO_APK>, + <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>; + assigned-clock-rates = <150000000>, <150000000>, + <200000000>, <100000000>; + resets = <&cru SRST_CRYPTO>; + reset-names = "reset"; + status = "disabled"; + }; + + i2s_8ch_0: i2s@ff300000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff300000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_8CH_TX>, <&cru SCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>, + <&cru SCLK_I2S0_8CH_TX_SRC>, + <&cru SCLK_I2S0_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0_8CH_TX_M>, <&cru SRST_I2S0_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_sclktx + &i2s_8ch_0_sclkrx + &i2s_8ch_0_lrcktx + &i2s_8ch_0_lrckrx + &i2s_8ch_0_sdi0 + &i2s_8ch_0_sdi1 + &i2s_8ch_0_sdi2 + &i2s_8ch_0_sdi3 + &i2s_8ch_0_sdo0 + &i2s_8ch_0_sdo1 + &i2s_8ch_0_sdo2 + &i2s_8ch_0_sdo3 + &i2s_8ch_0_mclk>; + status = "disabled"; + }; + + i2s_8ch_1: i2s@ff310000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff310000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1_8CH_TX>, <&cru SCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>, + <&cru SCLK_I2S1_8CH_TX_SRC>, + <&cru SCLK_I2S1_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S1_8CH_TX_M>, <&cru SRST_I2S1_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + rockchip,io-multiplex; + status = "disabled"; + }; + + i2s_8ch_2: i2s@ff320000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff320000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S2_8CH_TX>, <&cru SCLK_I2S2_8CH_RX>, <&cru HCLK_I2S2_8CH>, + <&cru SCLK_I2S2_8CH_TX_SRC>, + <&cru SCLK_I2S2_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 4>, <&dmac1 5>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S2_8CH_TX_M>, <&cru SRST_I2S2_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + status = "disabled"; + }; + + i2s_8ch_3: i2s@ff330000 { + compatible = "rockchip,rk3308-i2s-tdm"; + reg = <0x0 0xff330000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S3_8CH_TX>, <&cru SCLK_I2S3_8CH_RX>, <&cru HCLK_I2S3_8CH>, + <&cru SCLK_I2S3_8CH_TX_SRC>, + <&cru SCLK_I2S3_8CH_RX_SRC>, + <&cru PLL_VPLL0>, + <&cru PLL_VPLL1>; + clock-names = "mclk_tx", "mclk_rx", "hclk", + "mclk_tx_src", "mclk_rx_src", + "mclk_root0", "mclk_root1"; + dmas = <&dmac1 7>; + dma-names = "rx"; + resets = <&cru SRST_I2S3_8CH_TX_M>, <&cru SRST_I2S3_8CH_RX_M>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,mclk-calibrate; + status = "disabled"; + }; + + i2s_2ch_0: i2s@ff350000 { + compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff350000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1 8>, <&dmac1 9>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>; + reset-names = "reset-m", "reset-h"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_2ch_0_sclk + &i2s_2ch_0_lrck + &i2s_2ch_0_sdi + &i2s_2ch_0_sdo>; + status = "disabled"; + }; + + i2s_2ch_1: i2s@ff360000 { + compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff360000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac1 11>; + dma-names = "rx"; + resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>; + reset-names = "reset-m", "reset-h"; + status = "disabled"; + }; + + pdm_8ch: pdm@ff380000 { + compatible = "rockchip,rk3308-pdm", "rockchip,pdm"; + reg = <0x0 0xff380000 0x0 0x1000>; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 12>; + dma-names = "rx"; + resets = <&cru SRST_PDM_M>; + reset-names = "pdm-m"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_m2_clk + &pdm_m2_sdi0 + &pdm_m2_sdi1 + &pdm_m2_sdi2 + &pdm_m2_sdi3>; + status = "disabled"; + }; + + spdif_tx: spdif-tx@ff3a0000 { + compatible = "rockchip,rk3308-spdif", "rockchip,rk3066-spdif"; + reg = <0x0 0xff3a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 13>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_out>; + status = "disabled"; + }; + + spdif_rx: spdif-rx@ff3b0000 { + compatible = "rockchip,rk3308-spdifrx"; + reg = <0x0 0xff3b0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF_RX>, <&cru HCLK_SPDIFRX>; + clock-names = "mclk", "hclk"; + dmas = <&dmac1 14>; + dma-names = "rx"; + resets = <&cru SRST_SPDIFRX_M>; + reset-names = "spdifrx-m"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_in>; + status = "disabled"; + }; + + vad: vad@ff3c0000 { + compatible = "rockchip,rk3308-vad"; + reg = <0x0 0xff3c0000 0x0 0x10000>; + reg-names = "vad"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = ; + rockchip,audio-sram = <&vad_sram>; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; + status = "disabled"; + }; + + usb20_otg: usb@ff400000 { + compatible = "rockchip,rk3308-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff400000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@ff440000 { + compatible = "generic-ehci"; + reg = <0x0 0xff440000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff450000 { + compatible = "generic-ohci"; + reg = <0x0 0xff450000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST>, <&cru HCLK_HOST_ARB>, <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + sdmmc: mmc@ff480000 { + compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff480000 0x0 0x4000>; + interrupts = ; + bus-width = <4>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + status = "disabled"; + }; + + emmc: mmc@ff490000 { + compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff490000 0x0 0x4000>; + interrupts = ; + bus-width = <8>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + sdio: mmc@ff4a0000 { + compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff4a0000 0x0 0x4000>; + interrupts = ; + bus-width = <4>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; + status = "disabled"; + }; + + nfc: nand-controller@ff4b0000 { + compatible = "rockchip,rk3308-nfc", + "rockchip,rv1108-nfc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + assigned-clocks = <&cru SCLK_NANDC>; + assigned-clock-rates = <150000000>; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_csn0 + &flash_rdn &flash_rdy &flash_wrn>; + pinctrl-names = "default"; + status = "disabled"; + }; + + nandc: nandc@ff4b0000 { + compatible = "rockchip,rk-nandc"; + reg = <0x0 0xff4b0000 0x0 0x4000>; + interrupts = ; + nandc_id = <0>; + clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; + clock-names = "clk_nandc", "hclk_nandc"; + status = "disabled"; + }; + + mac: ethernet@ff4e0000 { + compatible = "rockchip,rk3308-mac"; + reg = <0x0 0xff4e0000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX_TX>, + <&cru SCLK_MAC_RX_TX>, <&cru SCLK_MAC_REF>, + <&cru SCLK_MAC>, <&cru ACLK_MAC>, + <&cru PCLK_MAC>, <&cru SCLK_MAC_RMII>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac", "clk_mac_speed"; + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; + resets = <&cru SRST_MAC_A>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + sfc: spi@ff4c0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff4c0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + cru: clock-controller@ff500000 { + compatible = "rockchip,rk3308-cru"; + reg = <0x0 0xff500000 0x0 0x1000>; + rockchip,grf = <&grf>; + rockchip,boost = <&cpu_boost>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru SCLK_RTC32K>; + assigned-clock-rates = <32768>; + }; + + cpu_boost: cpu-boost@ff550000 { + compatible = "syscon"; + reg = <0x0 0xff550000 0x0 0x1000>; + }; + + acodec: acodec@ff560000 { + compatible = "rockchip,rk3308-codec"; + reg = <0x0 0xff560000 0x0 0x10000>; + rockchip,grf = <&grf>; + rockchip,detect-grf = <&detect_grf>; + interrupts = , + ; + clocks = <&cru PCLK_ACODEC>, + <&cru SCLK_I2S2_8CH_TX_OUT>, + <&cru SCLK_I2S2_8CH_RX_OUT>; + clock-names = "acodec", "mclk_tx", "mclk_rx"; + resets = <&cru SRST_ACODEC_P>; + reset-names = "acodec-reset"; + spk_ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + gic: interrupt-controller@ff580000 { + compatible = "arm,gic-400"; + reg = <0x0 0xff581000 0x0 0x1000>, + <0x0 0xff582000 0x0 0x2000>, + <0x0 0xff584000 0x0 0x2000>, + <0x0 0xff586000 0x0 0x2000>; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + #address-cells = <0>; + }; + + sram: sram@fff80000 { + compatible = "mmio-sram"; + reg = <0x0 0xfff80000 0x0 0x40000>; + ranges = <0 0x0 0xfff80000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + + /* reserved for ddr dvfs and system suspend/resume */ + ddr-sram@0 { + reg = <0x0 0x8000>; + }; + + /* reserved for vad audio buffer */ + vad_sram: vad-sram@8000 { + reg = <0x8000 0x38000>; + }; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,polling-delay = <200>; /* milliseconds */ + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3308-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff220000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff220000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff230000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff230000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff240000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff240000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff250000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_2ma: pcfg-pull-none-2ma { + bias-disable; + drive-strength = <2>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_4ma: pcfg-pull-up-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + can-m0 { + canm0_pins: canm0-pins { + rockchip,pins = + /* can_rxd_m0 */ + <0 RK_PB3 2 &pcfg_pull_none>, + /* can_txd_m0 */ + <0 RK_PB4 2 &pcfg_pull_none>; + }; + }; + + can-m1 { + canm1_pins: canm1-pins { + rockchip,pins = + /* can_rxd_m1 */ + <1 RK_PC6 5 &pcfg_pull_none>, + /* can_txd_m1 */ + <1 RK_PC7 5 &pcfg_pull_none>; + }; + }; + + can-m2 { + canm2_pins: canm2-pins { + rockchip,pins = + /* can_rxd_m2 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can_txd_m2 */ + <2 RK_PA3 4 &pcfg_pull_none>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = + <3 RK_PB1 2 &pcfg_pull_none_8ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = + <3 RK_PB0 2 &pcfg_pull_up_8ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + emmc_rstn: emmc-rstn { + rockchip,pins = + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up_8ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up_8ma>, + <3 RK_PA1 2 &pcfg_pull_up_8ma>, + <3 RK_PA2 2 &pcfg_pull_up_8ma>, + <3 RK_PA3 2 &pcfg_pull_up_8ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up_8ma>, + <3 RK_PA1 2 &pcfg_pull_up_8ma>, + <3 RK_PA2 2 &pcfg_pull_up_8ma>, + <3 RK_PA3 2 &pcfg_pull_up_8ma>, + <3 RK_PA4 2 &pcfg_pull_up_8ma>, + <3 RK_PA5 2 &pcfg_pull_up_8ma>, + <3 RK_PA6 2 &pcfg_pull_up_8ma>, + <3 RK_PA7 2 &pcfg_pull_up_8ma>; + }; + }; + + ext_micbias { + ext_micbias_en: ext-micbias-en { + rockchip,pins = + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + flash { + flash_csn0: flash-csn0 { + rockchip,pins = + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = + <3 RK_PB4 1 &pcfg_pull_none>; + }; + + flash_ale: flash-ale { + rockchip,pins = + <3 RK_PB3 1 &pcfg_pull_none>; + }; + + flash_cle: flash-cle { + rockchip,pins = + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = + <3 RK_PB2 1 &pcfg_pull_none>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_up_12ma>, + <3 RK_PA1 1 &pcfg_pull_up_12ma>, + <3 RK_PA2 1 &pcfg_pull_up_12ma>, + <3 RK_PA3 1 &pcfg_pull_up_12ma>, + <3 RK_PA4 1 &pcfg_pull_up_12ma>, + <3 RK_PA5 1 &pcfg_pull_up_12ma>, + <3 RK_PA6 1 &pcfg_pull_up_12ma>, + <3 RK_PA7 1 &pcfg_pull_up_12ma>; + }; + }; + + gmac { + rmii_pins: rmii-pins { + rockchip,pins = + /* mac_txen */ + <1 RK_PC1 3 &pcfg_pull_none_12ma>, + /* mac_txd1 */ + <1 RK_PC3 3 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 RK_PC2 3 &pcfg_pull_none_12ma>, + /* mac_rxd0 */ + <1 RK_PC4 3 &pcfg_pull_none>, + /* mac_rxd1 */ + <1 RK_PC5 3 &pcfg_pull_none>, + /* mac_rxer */ + <1 RK_PB7 3 &pcfg_pull_none>, + /* mac_rxdv */ + <1 RK_PC0 3 &pcfg_pull_none>, + /* mac_mdio */ + <1 RK_PB6 3 &pcfg_pull_none>, + /* mac_mdc */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + + mac_refclk_12ma: mac-refclk-12ma { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none_12ma>; + }; + + mac_refclk: mac-refclk { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + gmac-m1 { + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_txen */ + <4 RK_PB7 2 &pcfg_pull_none_12ma>, + /* mac_txd1 */ + <4 RK_PA5 2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <4 RK_PA4 2 &pcfg_pull_none_12ma>, + /* mac_rxd0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* mac_rxd1 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* mac_rxer */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* mac_rxdv */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* mac_mdio */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* mac_mdc */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + macm1_refclk_12ma: macm1-refclk-12ma { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none_12ma>; + }; + + macm1_refclk: macm1-refclk { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none_smt>, + <1 RK_PD1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <0 RK_PB3 1 &pcfg_pull_none_smt>, + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 RK_PA2 3 &pcfg_pull_none_smt>, + <2 RK_PA3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3-m0 { + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + <0 RK_PB7 2 &pcfg_pull_none_smt>, + <0 RK_PC0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c3-m1 { + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + <3 RK_PB4 2 &pcfg_pull_none_smt>, + <3 RK_PB5 2 &pcfg_pull_none_smt>; + }; + }; + + i2c3-m2 { + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + <2 RK_PA1 3 &pcfg_pull_none_smt>, + <2 RK_PA0 3 &pcfg_pull_none_smt>; + }; + }; + + i2s_2ch_0 { + i2s_2ch_0_mclk: i2s-2ch-0-mclk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + i2s_2ch_0_sclk: i2s-2ch-0-sclk { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + i2s_2ch_0_lrck: i2s-2ch-0-lrck { + rockchip,pins = + <4 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + i2s_2ch_0_sdo: i2s-2ch-0-sdo { + rockchip,pins = + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + i2s_2ch_0_sdi: i2s-2ch-0-sdi { + rockchip,pins = + <4 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s_8ch_0 { + i2s_8ch_0_mclk: i2s-8ch-0-mclk { + rockchip,pins = + <2 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { + rockchip,pins = + <2 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { + rockchip,pins = + <2 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { + rockchip,pins = + <2 RK_PA7 1 &pcfg_pull_none_smt>; + }; + + i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { + rockchip,pins = + <2 RK_PB0 1 &pcfg_pull_none_smt>; + }; + + i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { + rockchip,pins = + <2 RK_PB1 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { + rockchip,pins = + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { + rockchip,pins = + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { + rockchip,pins = + <2 RK_PB4 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { + rockchip,pins = + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { + rockchip,pins = + <2 RK_PB6 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { + rockchip,pins = + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { + rockchip,pins = + <2 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s_8ch_1_m0 { + i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { + rockchip,pins = + <1 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { + rockchip,pins = + <1 RK_PA3 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { + rockchip,pins = + <1 RK_PA4 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { + rockchip,pins = + <1 RK_PA5 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { + rockchip,pins = + <1 RK_PA6 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { + rockchip,pins = + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { + rockchip,pins = + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { + rockchip,pins = + <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + i2s_8ch_1_m1 { + i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { + rockchip,pins = + <1 RK_PB4 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { + rockchip,pins = + <1 RK_PB5 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { + rockchip,pins = + <1 RK_PB6 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { + rockchip,pins = + <1 RK_PB7 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { + rockchip,pins = + <1 RK_PC0 2 &pcfg_pull_none_smt>; + }; + + i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { + rockchip,pins = + <1 RK_PC1 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { + rockchip,pins = + <1 RK_PC2 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { + rockchip,pins = + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { + rockchip,pins = + <1 RK_PC4 2 &pcfg_pull_none>; + }; + + i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { + rockchip,pins = + <1 RK_PC5 2 &pcfg_pull_none>; + }; + }; + + lcdc { + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* dclk */ + <1 RK_PA0 1 &pcfg_pull_none_4ma>, + /* hsync */ + <1 RK_PA1 1 &pcfg_pull_none_4ma>, + /* vsync */ + <1 RK_PA2 1 &pcfg_pull_none_4ma>, + /* den */ + <1 RK_PA3 1 &pcfg_pull_none_4ma>, + /* d0 */ + <1 RK_PA4 1 &pcfg_pull_none_4ma>, + /* d1 */ + <1 RK_PA5 1 &pcfg_pull_none_4ma>, + /* d2 */ + <1 RK_PA6 1 &pcfg_pull_none_4ma>, + /* d3 */ + <1 RK_PA7 1 &pcfg_pull_none_4ma>, + /* d4 */ + <1 RK_PB0 1 &pcfg_pull_none_4ma>, + /* d5 */ + <1 RK_PB1 1 &pcfg_pull_none_4ma>, + /* d6 */ + <1 RK_PB2 1 &pcfg_pull_none_4ma>, + /* d7 */ + <1 RK_PB3 1 &pcfg_pull_none_4ma>, + /* d8 */ + <1 RK_PB4 1 &pcfg_pull_none_4ma>, + /* d9 */ + <1 RK_PB5 1 &pcfg_pull_none_4ma>, + /* d10 */ + <1 RK_PB6 1 &pcfg_pull_none_4ma>, + /* d11 */ + <1 RK_PB7 1 &pcfg_pull_none_4ma>, + /* d12 */ + <1 RK_PC0 1 &pcfg_pull_none_4ma>, + /* d13 */ + <1 RK_PC1 1 &pcfg_pull_none_4ma>, + /* d14 */ + <1 RK_PC2 1 &pcfg_pull_none_4ma>, + /* d15 */ + <1 RK_PC3 1 &pcfg_pull_none_4ma>, + /* d16 */ + <1 RK_PC4 1 &pcfg_pull_none_4ma>, + /* d17 */ + <1 RK_PC5 1 &pcfg_pull_none_4ma>; + }; + + lcdc_rgb888_m0: lcdc-rgb888-m0 { + rockchip,pins = + /* d18 */ + <1 RK_PC6 6 &pcfg_pull_none_4ma>, + /* d19 */ + <1 RK_PC7 6 &pcfg_pull_none_4ma>, + /* d20 */ + <2 RK_PB1 3 &pcfg_pull_none_4ma>, + /* d21 */ + <2 RK_PB2 3 &pcfg_pull_none_4ma>, + /* d22 */ + <2 RK_PB7 3 &pcfg_pull_none_4ma>, + /* d23 */ + <2 RK_PC0 3 &pcfg_pull_none_4ma>; + }; + + lcdc_rgb888_m1: lcdc-rgb888-m1 { + rockchip,pins = + /* d18 */ + <3 RK_PA6 3 &pcfg_pull_none_4ma>, + /* d19 */ + <3 RK_PA7 3 &pcfg_pull_none_4ma>, + /* d20 */ + <3 RK_PB0 3 &pcfg_pull_none_4ma>, + /* d21 */ + <3 RK_PB1 3 &pcfg_pull_none_4ma>, + /* d22 */ + <3 RK_PB2 4 &pcfg_pull_none_4ma>, + /* d23 */ + <3 RK_PB3 4 &pcfg_pull_none_4ma>; + }; + }; + + owire-m0 { + owirem0_pins: owirem0-pins { + rockchip,pins = + /* owire_m0 */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + owire-m1 { + owirem1_pins: owirem1-pins { + rockchip,pins = + /* owire_m1 */ + <1 RK_PC6 7 &pcfg_pull_none>; + }; + }; + + owire-m2 { + owirem2_pins: owirem2-pins { + rockchip,pins = + /* owire_m2 */ + <2 RK_PA2 5 &pcfg_pull_none>; + }; + }; + + pdm_m0 { + pdm_m0_clk: pdm-m0-clk { + rockchip,pins = + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + pdm_m0_sdi0: pdm-m0-sdi0 { + rockchip,pins = + <1 RK_PB3 3 &pcfg_pull_none>; + }; + + pdm_m0_sdi1: pdm-m0-sdi1 { + rockchip,pins = + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + pdm_m0_sdi2: pdm-m0-sdi2 { + rockchip,pins = + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + pdm_m0_sdi3: pdm-m0-sdi3 { + rockchip,pins = + <1 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm_m1 { + pdm_m1_clk: pdm-m1-clk { + rockchip,pins = + <1 RK_PB6 4 &pcfg_pull_none>; + }; + + pdm_m1_sdi0: pdm-m1-sdi0 { + rockchip,pins = + <1 RK_PC5 4 &pcfg_pull_none>; + }; + + pdm_m1_sdi1: pdm-m1-sdi1 { + rockchip,pins = + <1 RK_PC4 4 &pcfg_pull_none>; + }; + + pdm_m1_sdi2: pdm-m1-sdi2 { + rockchip,pins = + <1 RK_PC3 4 &pcfg_pull_none>; + }; + + pdm_m1_sdi3: pdm-m1-sdi3 { + rockchip,pins = + <1 RK_PC2 4 &pcfg_pull_none>; + }; + }; + + pdm_m2 { + pdm_m2_clkm: pdm-m2-clkm { + rockchip,pins = + <2 RK_PA4 3 &pcfg_pull_none>; + }; + + pdm_m2_clk: pdm-m2-clk { + rockchip,pins = + <2 RK_PA6 2 &pcfg_pull_none>; + }; + + pdm_m2_sdi0: pdm-m2-sdi0 { + rockchip,pins = + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + pdm_m2_sdi1: pdm-m2-sdi1 { + rockchip,pins = + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + pdm_m2_sdi2: pdm-m2-sdi2 { + rockchip,pins = + <2 RK_PB7 2 &pcfg_pull_none>; + }; + + pdm_m2_sdi3: pdm-m2-sdi3 { + rockchip,pins = + <2 RK_PC0 2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <0 RK_PB5 1 &pcfg_pull_none>; + }; + + pwm0_pin_pull_down: pwm0-pin-pull-down { + rockchip,pins = + <0 RK_PB5 1 &pcfg_pull_down>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + pwm1_pin_pull_down: pwm1-pin-pull-down { + rockchip,pins = + <0 RK_PB6 1 &pcfg_pull_down>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + pwm2_pin_pull_down: pwm2-pin-pull-down { + rockchip,pins = + <0 RK_PB7 1 &pcfg_pull_down>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + pwm3_pin_pull_down: pwm3-pin-pull-down { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_down>; + }; + }; + + pwm4 { + pwm4_pin: pwm4-pin { + rockchip,pins = + <0 RK_PA1 2 &pcfg_pull_none>; + }; + + pwm4_pin_pull_down: pwm4-pin-pull-down { + rockchip,pins = + <0 RK_PA1 2 &pcfg_pull_down>; + }; + }; + + pwm5 { + pwm5_pin: pwm5-pin { + rockchip,pins = + <0 RK_PC1 2 &pcfg_pull_none>; + }; + + pwm5_pin_pull_down: pwm5-pin-pull-down { + rockchip,pins = + <0 RK_PC1 2 &pcfg_pull_down>; + }; + }; + + pwm6 { + pwm6_pin: pwm6-pin { + rockchip,pins = + <0 RK_PC2 2 &pcfg_pull_none>; + }; + + pwm6_pin_pull_down: pwm6-pin-pull-down { + rockchip,pins = + <0 RK_PC2 2 &pcfg_pull_down>; + }; + }; + + pwm7 { + pwm7_pin: pwm7-pin { + rockchip,pins = + <2 RK_PB0 2 &pcfg_pull_none>; + }; + + pwm7_pin_pull_down: pwm7-pin-pull-down { + rockchip,pins = + <2 RK_PB0 2 &pcfg_pull_down>; + }; + }; + + pwm8 { + pwm8_pin: pwm8-pin { + rockchip,pins = + <2 RK_PB2 2 &pcfg_pull_none>; + }; + + pwm8_pin_pull_down: pwm8-pin-pull-down { + rockchip,pins = + <2 RK_PB2 2 &pcfg_pull_down>; + }; + }; + + pwm9 { + pwm9_pin: pwm9-pin { + rockchip,pins = + <2 RK_PB3 2 &pcfg_pull_none>; + }; + + pwm9_pin_pull_down: pwm9-pin-pull-down { + rockchip,pins = + <2 RK_PB3 2 &pcfg_pull_down>; + }; + }; + + pwm10 { + pwm10_pin: pwm10-pin { + rockchip,pins = + <2 RK_PB4 2 &pcfg_pull_none>; + }; + + pwm10_pin_pull_down: pwm10-pin-pull-down { + rockchip,pins = + <2 RK_PB4 2 &pcfg_pull_down>; + }; + }; + + pwm11 { + pwm11_pin: pwm11-pin { + rockchip,pins = + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + pwm11_pin_pull_down: pwm11-pin-pull-down { + rockchip,pins = + <2 RK_PC0 4 &pcfg_pull_down>; + }; + }; + + rtc { + rtc_32k: rtc-32k { + rockchip,pins = + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PD5 1 &pcfg_pull_none_4ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PD4 1 &pcfg_pull_up_4ma>; + }; + + sdmmc_det: sdmmc-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_up_4ma>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + <4 RK_PD6 1 &pcfg_pull_none_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PD0 1 &pcfg_pull_up_4ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PD0 1 &pcfg_pull_up_4ma>, + <4 RK_PD1 1 &pcfg_pull_up_4ma>, + <4 RK_PD2 1 &pcfg_pull_up_4ma>, + <4 RK_PD3 1 &pcfg_pull_up_4ma>; + }; + + sdmmc_gpio: sdmmc-gpio { + rockchip,pins = + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = + <4 RK_PA5 1 &pcfg_pull_none_8ma>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = + <4 RK_PA4 1 &pcfg_pull_up_8ma>; + }; + + sdio_pwren: sdio-pwren { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none_8ma>; + }; + + sdio_wrpt: sdio-wrpt { + rockchip,pins = + <0 RK_PA1 1 &pcfg_pull_none_8ma>; + }; + + sdio_intn: sdio-intn { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none_8ma>; + }; + + sdio_bus1: sdio-bus1 { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_up_8ma>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_up_8ma>, + <4 RK_PA1 1 &pcfg_pull_up_8ma>, + <4 RK_PA2 1 &pcfg_pull_up_8ma>, + <4 RK_PA3 1 &pcfg_pull_up_8ma>; + }; + + sdio_gpio: sdio-gpio { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + spdif_in { + spdif_in: spdif-in { + rockchip,pins = + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + spdif_out { + spdif_out: spdif-out { + rockchip,pins = + <0 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <2 RK_PA2 2 &pcfg_pull_up_4ma>; + }; + + spi0_csn0: spi0-csn0 { + rockchip,pins = + <2 RK_PA3 2 &pcfg_pull_up_4ma>; + }; + + spi0_miso: spi0-miso { + rockchip,pins = + <2 RK_PA0 2 &pcfg_pull_up_4ma>; + }; + + spi0_mosi: spi0-mosi { + rockchip,pins = + <2 RK_PA1 2 &pcfg_pull_up_4ma>; + }; + + spi0_clk_hs: spi0-clk-hs { + rockchip,pins = + <2 RK_PA2 2 &pcfg_pull_up_8ma>; + }; + + spi0_miso_hs: spi0-miso-hs { + rockchip,pins = + <2 RK_PA0 2 &pcfg_pull_up_8ma>; + }; + + spi0_mosi_hs: spi0-mosi-hs { + rockchip,pins = + <2 RK_PA1 2 &pcfg_pull_up_8ma>; + }; + + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <3 RK_PB3 3 &pcfg_pull_up_4ma>; + }; + + spi1_csn0: spi1-csn0 { + rockchip,pins = + <3 RK_PB5 3 &pcfg_pull_up_4ma>; + }; + + spi1_miso: spi1-miso { + rockchip,pins = + <3 RK_PB2 3 &pcfg_pull_up_4ma>; + }; + + spi1_mosi: spi1-mosi { + rockchip,pins = + <3 RK_PB4 3 &pcfg_pull_up_4ma>; + }; + + spi1_clk_hs: spi1-clk-hs { + rockchip,pins = + <3 RK_PB3 3 &pcfg_pull_up_8ma>; + }; + + spi1_miso_hs: spi1-miso-hs { + rockchip,pins = + <3 RK_PB2 3 &pcfg_pull_up_8ma>; + }; + + spi1_mosi_hs: spi1-mosi-hs { + rockchip,pins = + <3 RK_PB4 3 &pcfg_pull_up_8ma>; + }; + }; + + spi1-m1 { + spi1m1_miso: spi1m1-miso { + rockchip,pins = + <2 RK_PA4 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_mosi: spi1m1-mosi { + rockchip,pins = + <2 RK_PA5 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_clk: spi1m1-clk { + rockchip,pins = + <2 RK_PA7 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins = + <2 RK_PB1 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_miso_hs: spi1m1-miso-hs { + rockchip,pins = + <2 RK_PA4 2 &pcfg_pull_up_8ma>; + }; + + spi1m1_mosi_hs: spi1m1-mosi-hs { + rockchip,pins = + <2 RK_PA5 2 &pcfg_pull_up_8ma>; + }; + + spi1m1_clk_hs: spi1m1-clk-hs { + rockchip,pins = + <2 RK_PA7 2 &pcfg_pull_up_8ma>; + }; + + spi1m1_csn0_hs: spi1m1-csn0-hs { + rockchip,pins = + <2 RK_PB1 2 &pcfg_pull_up_8ma>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_up_4ma>; + }; + + spi2_csn0: spi2-csn0 { + rockchip,pins = + <1 RK_PD1 3 &pcfg_pull_up_4ma>; + }; + + spi2_miso: spi2-miso { + rockchip,pins = + <1 RK_PC6 3 &pcfg_pull_up_4ma>; + }; + + spi2_mosi: spi2-mosi { + rockchip,pins = + <1 RK_PC7 3 &pcfg_pull_up_4ma>; + }; + + spi2_clk_hs: spi2-clk-hs { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_up_8ma>; + }; + + spi2_miso_hs: spi2-miso-hs { + rockchip,pins = + <1 RK_PC6 3 &pcfg_pull_up_8ma>; + }; + + spi2_mosi_hs: spi2-mosi-hs { + rockchip,pins = + <1 RK_PC7 3 &pcfg_pull_up_8ma>; + }; + }; + + tsadc { + tsadc_otp_pin: tsadc-otp-pin { + rockchip,pins = + <0 RK_PB2 0 &pcfg_pull_none>; + }; + + tsadc_otp_out: tsadc-otp-out { + rockchip,pins = + <0 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <2 RK_PA1 1 &pcfg_pull_up>, + <2 RK_PA0 1 &pcfg_pull_up>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <2 RK_PA2 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + uart0_rts_pin: uart0-rts-pin { + rockchip,pins = + <2 RK_PA3 0 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <1 RK_PD1 1 &pcfg_pull_up>, + <1 RK_PD0 1 &pcfg_pull_up>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = + <1 RK_PC6 1 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = + <1 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + uart2-m0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + <1 RK_PC7 2 &pcfg_pull_up>, + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + uart2-m1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + <4 RK_PD3 2 &pcfg_pull_up>, + <4 RK_PD2 2 &pcfg_pull_up>; + }; + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = + <3 RK_PB5 4 &pcfg_pull_up>, + <3 RK_PB4 4 &pcfg_pull_up>; + }; + }; + + uart3-m1 { + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + <0 RK_PC2 3 &pcfg_pull_up>, + <0 RK_PC1 3 &pcfg_pull_up>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + <4 RK_PB1 1 &pcfg_pull_up>, + <4 RK_PB0 1 &pcfg_pull_up>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = + <4 RK_PA6 1 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + uart4_rts_pin: uart4-rts-pin { + rockchip,pins = + <4 RK_PA7 0 &pcfg_pull_none>; + }; + }; + }; +}; +#include "rk3308bs-pinctrl.dtsi" diff --git a/rk3308b-amp.dtsi b/rk3308b-amp.dtsi new file mode 100644 index 0000000..5a4548d --- /dev/null +++ b/rk3308b-amp.dtsi @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + rockchip_amp: rockchip-amp { + compatible = "rockchip,amp"; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>, + <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>, <&cru SCLK_TIMER5>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "okay"; + amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>; + amp-irqs = /bits/ 64 ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* remote amp core address */ + amp_reserved: amp@2e00000 { + reg = <0x0 0x2e00000 0x0 0x1200000>; + no-map; + }; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x07c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x08000000 0x0 0x100000>; + no-map; + }; + }; + + rpmsg: rpmsg@7c00000 { + compatible = "rockchip,rpmsg-softirq"; + interrupts = , + ; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; +}; + +&cpu3 { + status = "disabled"; +}; diff --git a/rk3308b-evb-amic-v10-amp.dts b/rk3308b-evb-amic-v10-amp.dts new file mode 100644 index 0000000..3120c0a --- /dev/null +++ b/rk3308b-evb-amic-v10-amp.dts @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308b-evb-v10.dtsi" +#include "rk3308b-amp.dtsi" + + +/ { + model = "Rockchip RK3308b evb analog mic v10 board"; + compatible = "rockchip,rk3308b-evb-amic-v10", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <1 2 3 0>; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_8ch_0 { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_sclktx + &i2s_8ch_0_lrcktx + &i2s_8ch_0_sdi0 + &i2s_8ch_0_sdo2>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,det-channel = <0>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308b-evb-amic-v10.dts b/rk3308b-evb-amic-v10.dts new file mode 100644 index 0000000..a8886d2 --- /dev/null +++ b/rk3308b-evb-amic-v10.dts @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308b-evb-v10.dtsi" + +/ { + model = "Rockchip RK3308b evb analog mic v10 board"; + compatible = "rockchip,rk3308b-evb-amic-v10", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <1 2 3 0>; +}; + +&acodec_sound { + status = "disabled"; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_8ch_0 { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_sclktx + &i2s_8ch_0_lrcktx + &i2s_8ch_0_sdi0 + &i2s_8ch_0_sdo2>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,det-channel = <0>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308b-evb-ext-v10.dtsi b/rk3308b-evb-ext-v10.dtsi new file mode 100644 index 0000000..e2414b6 --- /dev/null +++ b/rk3308b-evb-ext-v10.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + width-mm = <95>; + height-mm = <54>; + status = "okay"; + + display-timings { + native-mode = <&stt0430_enl2c_timing>; + + stt0430_enl2c_timing: timing0 { + clock-frequency = <12000000>; + hactive = <480>; + vactive = <272>; + hback-porch = <60>; + hfront-porch = <20>; + vback-porch = <28>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3308b-evb-v10.dtsi b/rk3308b-evb-v10.dtsi new file mode 100644 index 0000000..1d00090 --- /dev/null +++ b/rk3308b-evb-v10.dtsi @@ -0,0 +1,802 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include "rk3308.dtsi" + +/ { + model = "Rockchip RK3308B EVB V10"; + compatible = "rockchip,rk3308b-evb-v10", "rockchip,rk3308"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff0e0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rootfstype=squashfs rootwait snd_aloop.index=7 snd_aloop.use_raw_jiffies=1"; + }; + + acodec_sound: acodec-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-acodec"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "micmute"; + press-threshold-microvolt = <1130000>; + }; + + home-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <901000>; + }; + + menu-key { + linux,code = ; + label = "play"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <18000>; + }; + }; + + bluetooth_sound: bluetooth-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-pcm"; + rockchip,mclk-fs = <128>; + rockchip,cpu = <&i2s_8ch_0>; + rockchip,codec = <&dummy_codec>; + rockchip,format = "dsp_b"; + rockchip,bitclock-inversion = <0>; + rockchip,wait-card-locked = <0>; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + wakeup-source; + debounce-interval = <100>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + }; + + spdif_rx_sound: spdif-rx-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-rx-sound"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&spdif_rx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + spdif_tx_sound: spdif-tx-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx-sound"; + status = "disabled"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_tx>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vdd_core: vdd-core { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_core"; + regulator-min-microvolt = <827000>; + regulator-max-microvolt = <1340000>; + regulator-init-microvolt = <1015000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + status = "okay"; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vdd_1v0: vdd-1v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + vcc_3v3_codec: vcc_io: vcc-io { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_sdio: vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_1v8_codec: vcc-1v8-codec { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + + vccio_flash: vccio-flash { + compatible = "regulator-fixed"; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vbus_host: vbus-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_drv>; + regulator-name = "vbus_host"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_pin>; + BT,power_gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>; + wifi_chip_type = "ap6255"; + WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&acodec { + status = "okay"; + + rockchip,no-deep-low-power; + hp-ctl-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + spk-ctl-gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; +}; + +&cpu0 { + cpu-supply = <&vdd_core>; +}; + +&cpu0_opp_table { + opp-1200000000 { + status = "okay"; + }; + opp-1296000000 { + status = "okay"; + }; +}; + +&rk3308bs_cpu0_opp_table { + opp-1008000000 { + status = "okay"; + }; + opp-1104000000 { + status = "okay"; + }; +}; + +&dmc { + center-supply = <&vdd_log>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "disabled"; +}; + +&fiq_debugger { + rockchip,serial-id = <4>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio0-supply = <&vcc_io>; + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vccio_sdio>; + vccio3-supply = <&vccio_flash>; + vccio4-supply = <&vcc_io>; + vccio5-supply = <&vccio_sdio>; +}; + +&i2c1 { + clock-frequency = <400000>; + status = "okay"; + + is31fl3236: led-controller@3f { + compatible = "issi,is31fl3236"; + reg = <0x3f>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&i2s_8ch_1 { + status = "disabled"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_1_m0_sclktx + &i2s_8ch_1_m0_lrcktx + &i2s_8ch_1_m0_sdo0 + &i2s_8ch_1_m0_mclk>; +}; + +&i2s_8ch_2 { + status = "okay"; +}; + +&mac { + phy-supply = <&vcc_phy>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&mac_clkin>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rmiim1_pins &macm1_refclk>; + snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "disable"; +}; + +&nandc { + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + usb_drv: usb-drv { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_wake_host: wifi-wake-host { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin_pull_down>; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM_REGULATOR + ) + >; + + status = "okay"; +}; + +&spdif_rx { + #sound-dai-cells = <0>; +}; + +&spdif_tx { + #sound-dai-cells = <0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci{ + status = "okay"; +}; diff --git a/rk3308b-mipi-display-v11.dtsi b/rk3308b-mipi-display-v11.dtsi new file mode 100644 index 0000000..4581704 --- /dev/null +++ b/rk3308b-mipi-display-v11.dtsi @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ +#include +#include + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int>; + power-supply = <&vcc3v3_lcd_n>; + goodix,rst-gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + goodix,irq-gpio = <&gpio0 RK_PC0 IRQ_TYPE_LEVEL_LOW>; + }; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_mclk>; + clocks = <&cru SCLK_I2S0_8CH_TX_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S0_8CH_TX_OUT>; + assigned-clock-rates = <12000000>; + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S0_8CH_TX_OUT>, <&cru DCLK_VOP>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_OUT>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S0_8CH_TX_OUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + dsi { + compatible = "rockchip,rk618-dsi"; + clocks = <&clock MIPI_CLK>; + clock-names = "dsi"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi_in_rgb: endpoint { + remote-endpoint = <&rgb_out_dsi>; + }; + }; + }; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd_n>; + backlight = <&backlight>; + + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <65000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <48>; + hsync-len = <8>; + hback-porch = <52>; + vfront-porch = <16>; + vsync-len = <6>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + }; + }; +}; + + +&display_subsystem { + status = "okay"; +}; + +&pinctrl { + lcd { + lcd_en: lcd-en { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + tp_int: tp-int { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + logo,kernel = "logo_kernel.bmp"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3308bs-evb-amic-v11.dts b/rk3308bs-evb-amic-v11.dts new file mode 100644 index 0000000..e7c4644 --- /dev/null +++ b/rk3308bs-evb-amic-v11.dts @@ -0,0 +1,390 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308bs-evb-v11.dtsi" + +/ { + model = "Rockchip RK3308B-S evb analog mic v11 board"; + compatible = "rockchip,rk3308bs-evb-amic-v11", "rockchip,rk3308"; + + vad_acodec_sound: vad-acodec-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s_8ch_2>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&acodec { + rockchip,micbias1; + rockchip,micbias2; + rockchip,en-always-grps = <1 2 3>; + rockchip,adc-grps-route = <1 2 3 0>; +}; + +&bluetooth_sound { + status = "okay"; +}; + +&i2s_8ch_0 { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_0_sclktx + &i2s_8ch_0_lrcktx + &i2s_8ch_0_sdi0 + &i2s_8ch_0_sdo2>; +}; + +&i2c1 { + /delete-node/ led-controller@3c; + is31fl3236: led-controller@3f { + compatible = "issi,is31fl3236"; + reg = <0x3f>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&i2s_8ch_2>; + rockchip,det-channel = <0>; + rockchip,buffer-time-ms = <200>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308bs-evb-ddr3-v20-rk618-rgb2dsi.dts b/rk3308bs-evb-ddr3-v20-rk618-rgb2dsi.dts new file mode 100644 index 0000000..d3ceaec --- /dev/null +++ b/rk3308bs-evb-ddr3-v20-rk618-rgb2dsi.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308bs-evb-amic-v11.dts" +#include "rk3308b-mipi-display-v11.dtsi" + +/ { + model = "Rockchip RK3308B-S EVB DDR3 V20 Board + Rockchip RK3308B-S MIPI DISPLAY V10 Ext Board"; + compatible = "rockchip,rk3308bs-evb-ddr3-v20-rk618-rgb2dsi", "rockchip,rk3308"; +}; diff --git a/rk3308bs-evb-dmic-pdm-v11.dts b/rk3308bs-evb-dmic-pdm-v11.dts new file mode 100644 index 0000000..7c220df --- /dev/null +++ b/rk3308bs-evb-dmic-pdm-v11.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; + +#include "rk3308bs-evb-v11.dtsi" + +/ { + model = "Rockchip RK3308B-S evb digital-pdm mic v11 board"; + compatible = "rockchip,rk3308bs-evb-dmic-pdm-v11", "rockchip,rk3308"; + + pdm_i2s_dais: pdm-i2s-dais { + status = "okay"; + compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais"; + dais = <&pdm_8ch>, <&i2s_8ch_2>; + capture,channel-mapping = <6 2>; + playback,channel-mapping = <0 2>; + #sound-dai-cells = <0>; + }; + + pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + vad-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3308-vad"; + rockchip,cpu = <&pdm_i2s_dais>; + rockchip,codec = <&acodec>, <&vad>; + }; +}; + +&i2s_8ch_2 { + status = "okay"; + rockchip,no-dmaengine; + #sound-dai-cells = <0>; +}; + +&pdm_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_m2_clk + &pdm_m2_sdi0 + &pdm_m2_sdi1 + &pdm_m2_sdi2 + &pdm_m2_sdi3>; +}; + +&vad { + status = "okay"; + rockchip,audio-src = <&pdm_8ch>; + rockchip,buffer-time-ms = <200>; + rockchip,det-channel = <2>; + rockchip,mode = <1>; + #sound-dai-cells = <0>; +}; diff --git a/rk3308bs-evb-ext-mcu-v10.dtsi b/rk3308bs-evb-ext-mcu-v10.dtsi new file mode 100644 index 0000000..1217f90 --- /dev/null +++ b/rk3308bs-evb-ext-mcu-v10.dtsi @@ -0,0 +1,274 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + linux,cma-default; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + rockchip,data-sync-bypass; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) + */ + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + width-mm = <217>; + height-mm = <136>; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + //type delay num val1 val2 val3 + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a + 01 00 01 55 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit) + */ + + 00 00 01 b0 + 01 00 01 00 + + 00 00 01 b1 + 01 00 01 a0 /* + * frame rate control: + * 70 (45hz) for RGB3x8(8bit) + * a0 (60hz) for RGB565(16bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 32 01 29 + 00 00 01 2c + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + /* + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <10453500>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + status = "okay"; + + /* + * Default config is as follows: + * + * mcu-pix-total = <9>; + * mcu-cs-pst = <1>; + * mcu-cs-pend = <8>; + * mcu-rw-pst = <2>; + * mcu-rw-pend = <5>; + * mcu-hold-mode = <0>; // default set to 0 + * + * To increase the frame rate, reduce all parameters because + * the max dclk rate of mcu is 150M in rk3308. + */ + mcu-timing { + mcu-pix-total = <5>; + mcu-cs-pst = <1>; + mcu-cs-pend = <4>; + mcu-rw-pst = <2>; + mcu-rw-pend = <3>; + + mcu-hold-mode = <0>; // default set to 0 + }; +}; diff --git a/rk3308bs-evb-mcu-display-v20.dts b/rk3308bs-evb-mcu-display-v20.dts new file mode 100644 index 0000000..28be799 --- /dev/null +++ b/rk3308bs-evb-mcu-display-v20.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308bs-evb-amic-v11.dts" +#include "rk3308bs-evb-ext-mcu-v10.dtsi" + +/ { + model = "Rockchip RK3308B-S EVB DDR3 V20 Board + Rockchip RK3308 EVB ExtBoard V10"; + compatible = "rockchip,rk3308bs-evb-mcu-display-v20", "rockchip,rk3308"; +}; diff --git a/rk3308bs-evb-mipi-display-v11.dts b/rk3308bs-evb-mipi-display-v11.dts new file mode 100644 index 0000000..de5e68d --- /dev/null +++ b/rk3308bs-evb-mipi-display-v11.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; + +#include "rk3308bs-evb-dmic-pdm-v11.dts" +#include "rk3308b-mipi-display-v11.dtsi" + +/ { + model = "Rockchip RK3308B-S evb mipi display v11 board"; + compatible = "rockchip,rk3308bs-evb-mipi-display-v11", "rockchip,rk3308"; +}; + +&is31fl3236 { + status = "disabled"; +}; + +&lcdc_rgb888_m1 { + rockchip,pins = + /* d18 */ + <3 RK_PA6 3 &pcfg_pull_none_2ma>, + /* d19 */ + <3 RK_PA7 3 &pcfg_pull_none_2ma>, + /* d20 */ + <3 RK_PB0 3 &pcfg_pull_none_2ma>, + /* d21 */ + <3 RK_PB1 3 &pcfg_pull_none_2ma>, + /* d22 */ + <3 RK_PB2 4 &pcfg_pull_none_2ma>, + /* d23 */ + <3 RK_PB3 4 &pcfg_pull_none_2ma>; +}; + +&pdm_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&pdm_m2_clk + &pdm_m2_sdi0 + &pdm_m2_sdi1>; +}; diff --git a/rk3308bs-evb-rgb-display-v20.dts b/rk3308bs-evb-rgb-display-v20.dts new file mode 100644 index 0000000..4a3f7a1 --- /dev/null +++ b/rk3308bs-evb-rgb-display-v20.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3308bs-evb-amic-v11.dts" + +/ { + model = "Rockchip RK3308B-S EVB DDR3 V20 Board + Rockchip RK3308 RGB ExtBoard V10"; + compatible = "rockchip,rk3308bs-evb-rgb-display-v20", "rockchip,rk3308"; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + status = "okay"; + + display-timings { + native-mode = <&fx070_dhm11boe_timing>; + + fx070_dhm11boe_timing: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <2>; //value range <2~22> + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + linux,cma-default; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3308bs-evb-v11.dtsi b/rk3308bs-evb-v11.dtsi new file mode 100644 index 0000000..3812f2f --- /dev/null +++ b/rk3308bs-evb-v11.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + */ + +#include +#include "rk3308b-evb-v10.dtsi" + +/ { + model = "Rockchip RK3308B-S EVB V11"; + compatible = "rockchip,rk3308bs-evb-v11", "rockchip,rk3308"; + + /delete-node/ vdd-1v0; + /delete-node/ wireless-bluetooth; + /delete-node/ wireless-wlan; + + vdd_0v9: vdd-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_pin>; + BT,power_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>; + wifi_chip_type = "ap6256"; + WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&acodec_sound { + status = "disabled"; +}; + +&mac { + status = "okay"; +}; + +&vcc_ddr { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; +}; + +&vdd_log { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; +}; diff --git a/rk3308bs-pinctrl.dtsi b/rk3308bs-pinctrl.dtsi new file mode 100644 index 0000000..038ed00 --- /dev/null +++ b/rk3308bs-pinctrl.dtsi @@ -0,0 +1,750 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + */ + +&pinctrl { + /* default for rk3308 and 4ma for rk3308bs */ + pcfg_pull_none_0_4ma: pcfg-pull-none-0-4ma { + bias-disable; + drive-strength-s = <4>; + }; + pcfg_pull_none_0_4ma_smt: pcfg-pull-none-0-4ma-smt { + bias-disable; + drive-strength-s = <4>; + input-schmitt-enable; + }; + pcfg_pull_up_0_4ma: pcfg-pull-up-0-4ma { + bias-pull-up; + drive-strength-s = <4>; + }; + pcfg_pull_down_0_4ma: pcfg-pull-down-0-4ma { + bias-pull-down; + drive-strength-s = <4>; + }; + + /* default for rk3308 and 6ma for rk3308bs */ + pcfg_pull_none_0_6ma: pcfg-pull-none-0-6ma { + bias-disable; + drive-strength-s = <6>; + }; + pcfg_pull_up_0_6ma: pcfg-pull-up-0-6ma { + bias-pull-up; + drive-strength-s = <6>; + }; + pcfg_pull_down_0_6ma: pcfg-pull-down-0-6ma { + bias-pull-down; + drive-strength-s = <6>; + }; + + /* 4ma for rk3308 and 6ma for rk3308bs */ + pcfg_pull_none_4_6ma: pcfg-pull-none-4-6ma { + bias-disable; + drive-strength = <4>; + drive-strength-s = <6>; + }; + pcfg_pull_up_4_6ma: pcfg-pull-up-4-6ma { + bias-pull-up; + drive-strength = <4>; + drive-strength-s = <6>; + }; + pcfg_pull_down_4_6ma: pcfg-pull-down-4-6ma { + bias-pull-down; + drive-strength = <4>; + drive-strength-s = <6>; + }; + + /* 8ma for rk3308 and 6ma for rk3308bs */ + pcfg_pull_none_8_6ma: pcfg-pull-none-8-6ma { + bias-disable; + drive-strength = <8>; + drive-strength-s = <6>; + }; + pcfg_pull_up_8_6ma: pcfg-pull-up-8-6ma { + bias-pull-up; + drive-strength = <8>; + drive-strength-s = <6>; + }; + pcfg_pull_down_8_6ma: pcfg-pull-down-8-6ma { + bias-pull-down; + drive-strength = <8>; + drive-strength-s = <6>; + }; + + /* 8ma for rk3308 and 4ma for rk3308bs */ + pcfg_pull_none_8_4ma: pcfg-pull-none-8-4ma { + bias-disable; + drive-strength = <8>; + drive-strength-s = <4>; + }; + pcfg_pull_up_8_4ma: pcfg-pull-up-8-4ma { + bias-pull-up; + drive-strength = <8>; + drive-strength-s = <4>; + }; + pcfg_pull_down_8_4ma: pcfg-pull-down-8-4ma { + bias-pull-down; + drive-strength = <8>; + drive-strength-s = <4>; + }; + + /* 12ma for rk3308 and 4ma for rk3308bs */ + pcfg_pull_none_12_4ma: pcfg-pull-none-12-4ma { + bias-disable; + drive-strength = <12>; + drive-strength-s = <4>; + }; + pcfg_pull_up_12_4ma: pcfg-pull-up-12-4ma { + bias-pull-up; + drive-strength = <12>; + drive-strength-s = <4>; + }; + pcfg_pull_down_12_4ma: pcfg-pull-down-12-4ma { + bias-pull-down; + drive-strength = <12>; + drive-strength-s = <4>; + }; + + /* 12ma for rk3308 and 6ma for rk3308bs */ + pcfg_pull_none_12_6ma: pcfg-pull-none-12-6ma { + bias-disable; + drive-strength = <12>; + drive-strength-s = <6>; + }; + pcfg_pull_up_12_6ma: pcfg-pull-up-12-6ma { + bias-pull-up; + drive-strength = <12>; + drive-strength-s = <6>; + }; + pcfg_pull_down_12_6ma: pcfg-pull-down-12-6ma { + bias-pull-down; + drive-strength = <12>; + drive-strength-s = <6>; + }; +}; + +&pinctrl { + /delete-node/ i2s_2ch_0; + /delete-node/ i2s_8ch_0; + /delete-node/ i2s_8ch_1_m0; + /delete-node/ i2s_8ch_1_m1; + + i2s_2ch_0 { + i2s_2ch_0_mclk: i2s-2ch-0-mclk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + i2s_2ch_0_sclk: i2s-2ch-0-sclk { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + i2s_2ch_0_lrck: i2s-2ch-0-lrck { + rockchip,pins = + <4 RK_PB6 1 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_2ch_0_sdo: i2s-2ch-0-sdo { + rockchip,pins = + <4 RK_PB7 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_2ch_0_sdi: i2s-2ch-0-sdi { + rockchip,pins = + <4 RK_PC0 1 &pcfg_pull_none_0_4ma>; + }; + }; + + i2s_8ch_0 { + i2s_8ch_0_mclk: i2s-8ch-0-mclk { + rockchip,pins = + <2 RK_PA4 1 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_0_sclktx: i2s-8ch-0-sclktx { + rockchip,pins = + <2 RK_PA5 1 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx { + rockchip,pins = + <2 RK_PA6 1 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx { + rockchip,pins = + <2 RK_PA7 1 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx { + rockchip,pins = + <2 RK_PB0 1 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 { + rockchip,pins = + <2 RK_PB1 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 { + rockchip,pins = + <2 RK_PB2 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 { + rockchip,pins = + <2 RK_PB3 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 { + rockchip,pins = + <2 RK_PB4 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 { + rockchip,pins = + <2 RK_PB5 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 { + rockchip,pins = + <2 RK_PB6 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 { + rockchip,pins = + <2 RK_PB7 1 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 { + rockchip,pins = + <2 RK_PC0 1 &pcfg_pull_none_0_4ma>; + }; + }; + + + i2s_8ch_1_m0 { + i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk { + rockchip,pins = + <1 RK_PA2 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx { + rockchip,pins = + <1 RK_PA3 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx { + rockchip,pins = + <1 RK_PA4 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx { + rockchip,pins = + <1 RK_PA5 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx { + rockchip,pins = + <1 RK_PA6 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 { + rockchip,pins = + <1 RK_PA7 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 { + rockchip,pins = + <1 RK_PB2 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 { + rockchip,pins = + <1 RK_PB3 2 &pcfg_pull_none_0_4ma>; + }; + }; + + i2s_8ch_1_m1 { + i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk { + rockchip,pins = + <1 RK_PB4 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx { + rockchip,pins = + <1 RK_PB5 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx { + rockchip,pins = + <1 RK_PB6 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx { + rockchip,pins = + <1 RK_PB7 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx { + rockchip,pins = + <1 RK_PC0 2 &pcfg_pull_none_0_4ma_smt>; + }; + + i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 { + rockchip,pins = + <1 RK_PC1 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 { + rockchip,pins = + <1 RK_PC2 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 { + rockchip,pins = + <1 RK_PC3 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 { + rockchip,pins = + <1 RK_PC4 2 &pcfg_pull_none_0_4ma>; + }; + + i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 { + rockchip,pins = + <1 RK_PC5 2 &pcfg_pull_none_0_4ma>; + }; + }; +}; + +&pinctrl { + /delete-node/ sdmmc; + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PD5 1 &pcfg_pull_none_4_6ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PD4 1 &pcfg_pull_up_4ma>; + }; + + sdmmc_det: sdmmc-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_up_4ma>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + <4 RK_PD6 1 &pcfg_pull_none_4ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PD0 1 &pcfg_pull_up_4_6ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PD0 1 &pcfg_pull_up_4_6ma>, + <4 RK_PD1 1 &pcfg_pull_up_4_6ma>, + <4 RK_PD2 1 &pcfg_pull_up_4_6ma>, + <4 RK_PD3 1 &pcfg_pull_up_4_6ma>; + }; + + sdmmc_gpio: sdmmc-gpio { + rockchip,pins = + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; +}; + +&pinctrl { + /delete-node/ sdio; + sdio { + sdio_clk: sdio-clk { + rockchip,pins = + <4 RK_PA5 1 &pcfg_pull_none_8_6ma>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = + <4 RK_PA4 1 &pcfg_pull_up_8_6ma>; + }; + + sdio_pwren: sdio-pwren { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none_8_6ma>; + }; + + sdio_wrpt: sdio-wrpt { + rockchip,pins = + <0 RK_PA1 1 &pcfg_pull_none_8_6ma>; + }; + + sdio_intn: sdio-intn { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none_8_6ma>; + }; + + sdio_bus1: sdio-bus1 { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_up_8_6ma>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_up_8_6ma>, + <4 RK_PA1 1 &pcfg_pull_up_8_6ma>, + <4 RK_PA2 1 &pcfg_pull_up_8_6ma>, + <4 RK_PA3 1 &pcfg_pull_up_8_6ma>; + }; + + sdio_gpio: sdio-gpio { + rockchip,pins = + <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; +}; + +&pinctrl { + /delete-node/ gmac; + /delete-node/ gmac-m1; + gmac { + rmii_pins: rmii-pins { + rockchip,pins = + /* mac_txen */ + <1 RK_PC1 3 &pcfg_pull_none_12_6ma>, + /* mac_txd1 */ + <1 RK_PC3 3 &pcfg_pull_none_12_6ma>, + /* mac_txd0 */ + <1 RK_PC2 3 &pcfg_pull_none_12_6ma>, + /* mac_rxd0 */ + <1 RK_PC4 3 &pcfg_pull_none>, + /* mac_rxd1 */ + <1 RK_PC5 3 &pcfg_pull_none>, + /* mac_rxer */ + <1 RK_PB7 3 &pcfg_pull_none>, + /* mac_rxdv */ + <1 RK_PC0 3 &pcfg_pull_none>, + /* mac_mdio */ + <1 RK_PB6 3 &pcfg_pull_none>, + /* mac_mdc */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + + mac_refclk_12ma: mac-refclk-12ma { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none_12_6ma>; + }; + + mac_refclk: mac-refclk { + rockchip,pins = + <1 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + gmac-m1 { + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_txen */ + <4 RK_PB7 2 &pcfg_pull_none_12_6ma>, + /* mac_txd1 */ + <4 RK_PA5 2 &pcfg_pull_none_12_6ma>, + /* mac_txd0 */ + <4 RK_PA4 2 &pcfg_pull_none_12_6ma>, + /* mac_rxd0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* mac_rxd1 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* mac_rxer */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* mac_rxdv */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* mac_mdio */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* mac_mdc */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + macm1_refclk_12ma: macm1-refclk-12ma { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none_12_6ma>; + }; + + macm1_refclk: macm1-refclk { + rockchip,pins = + <4 RK_PB4 2 &pcfg_pull_none>; + }; + }; +}; + +&pinctrl { + /delete-node/ spi0; + /delete-node/ spi1; + /delete-node/ spi2; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <2 RK_PA2 2 &pcfg_pull_up_4ma>; + }; + + spi0_csn0: spi0-csn0 { + rockchip,pins = + <2 RK_PA3 2 &pcfg_pull_up_4ma>; + }; + + spi0_miso: spi0-miso { + rockchip,pins = + <2 RK_PA0 2 &pcfg_pull_up_4ma>; + }; + + spi0_mosi: spi0-mosi { + rockchip,pins = + <2 RK_PA1 2 &pcfg_pull_up_4ma>; + }; + + spi0_clk_hs: spi0-clk-hs { + rockchip,pins = + <2 RK_PA2 2 &pcfg_pull_up_8_4ma>; + }; + + spi0_miso_hs: spi0-miso-hs { + rockchip,pins = + <2 RK_PA0 2 &pcfg_pull_up_8_4ma>; + }; + + spi0_mosi_hs: spi0-mosi-hs { + rockchip,pins = + <2 RK_PA1 2 &pcfg_pull_up_8_4ma>; + }; + + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <3 RK_PB3 3 &pcfg_pull_up_4ma>; + }; + + spi1_csn0: spi1-csn0 { + rockchip,pins = + <3 RK_PB5 3 &pcfg_pull_up_4ma>; + }; + + spi1_miso: spi1-miso { + rockchip,pins = + <3 RK_PB2 3 &pcfg_pull_up_4ma>; + }; + + spi1_mosi: spi1-mosi { + rockchip,pins = + <3 RK_PB4 3 &pcfg_pull_up_4ma>; + }; + + spi1_clk_hs: spi1-clk-hs { + rockchip,pins = + <3 RK_PB3 3 &pcfg_pull_up_8_4ma>; + }; + + spi1_miso_hs: spi1-miso-hs { + rockchip,pins = + <3 RK_PB2 3 &pcfg_pull_up_8_4ma>; + }; + + spi1_mosi_hs: spi1-mosi-hs { + rockchip,pins = + <3 RK_PB4 3 &pcfg_pull_up_8_4ma>; + }; + }; + + spi1-m1 { + spi1m1_miso: spi1m1-miso { + rockchip,pins = + <2 RK_PA4 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_mosi: spi1m1-mosi { + rockchip,pins = + <2 RK_PA5 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_clk: spi1m1-clk { + rockchip,pins = + <2 RK_PA7 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins = + <2 RK_PB1 2 &pcfg_pull_up_4ma>; + }; + + spi1m1_miso_hs: spi1m1-miso-hs { + rockchip,pins = + <2 RK_PA4 2 &pcfg_pull_up_8_4ma>; + }; + + spi1m1_mosi_hs: spi1m1-mosi-hs { + rockchip,pins = + <2 RK_PA5 2 &pcfg_pull_up_8_4ma>; + }; + + spi1m1_clk_hs: spi1m1-clk-hs { + rockchip,pins = + <2 RK_PA7 2 &pcfg_pull_up_8_4ma>; + }; + + spi1m1_csn0_hs: spi1m1-csn0-hs { + rockchip,pins = + <2 RK_PB1 2 &pcfg_pull_up_8_4ma>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_up_4ma>; + }; + + spi2_csn0: spi2-csn0 { + rockchip,pins = + <1 RK_PD1 3 &pcfg_pull_up_4ma>; + }; + + spi2_miso: spi2-miso { + rockchip,pins = + <1 RK_PC6 3 &pcfg_pull_up_4ma>; + }; + + spi2_mosi: spi2-mosi { + rockchip,pins = + <1 RK_PC7 3 &pcfg_pull_up_4ma>; + }; + + spi2_clk_hs: spi2-clk-hs { + rockchip,pins = + <1 RK_PD0 3 &pcfg_pull_up_8_4ma>; + }; + + spi2_miso_hs: spi2-miso-hs { + rockchip,pins = + <1 RK_PC6 3 &pcfg_pull_up_8_4ma>; + }; + + spi2_mosi_hs: spi2-mosi-hs { + rockchip,pins = + <1 RK_PC7 3 &pcfg_pull_up_8_4ma>; + }; + }; +}; + +&pinctrl { + /delete-node/ lcdc; + + lcdc { + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* dclk */ + <1 RK_PA0 1 &pcfg_pull_none_4_6ma>, + /* hsync */ + <1 RK_PA1 1 &pcfg_pull_none_4_6ma>, + /* vsync */ + <1 RK_PA2 1 &pcfg_pull_none_4_6ma>, + /* den */ + <1 RK_PA3 1 &pcfg_pull_none_4_6ma>, + /* d0 */ + <1 RK_PA4 1 &pcfg_pull_none_4_6ma>, + /* d1 */ + <1 RK_PA5 1 &pcfg_pull_none_4_6ma>, + /* d2 */ + <1 RK_PA6 1 &pcfg_pull_none_4_6ma>, + /* d3 */ + <1 RK_PA7 1 &pcfg_pull_none_4_6ma>, + /* d4 */ + <1 RK_PB0 1 &pcfg_pull_none_4_6ma>, + /* d5 */ + <1 RK_PB1 1 &pcfg_pull_none_4_6ma>, + /* d6 */ + <1 RK_PB2 1 &pcfg_pull_none_4_6ma>, + /* d7 */ + <1 RK_PB3 1 &pcfg_pull_none_4_6ma>, + /* d8 */ + <1 RK_PB4 1 &pcfg_pull_none_4_6ma>, + /* d9 */ + <1 RK_PB5 1 &pcfg_pull_none_4_6ma>, + /* d10 */ + <1 RK_PB6 1 &pcfg_pull_none_4_6ma>, + /* d11 */ + <1 RK_PB7 1 &pcfg_pull_none_4_6ma>, + /* d12 */ + <1 RK_PC0 1 &pcfg_pull_none_4_6ma>, + /* d13 */ + <1 RK_PC1 1 &pcfg_pull_none_4_6ma>, + /* d14 */ + <1 RK_PC2 1 &pcfg_pull_none_4_6ma>, + /* d15 */ + <1 RK_PC3 1 &pcfg_pull_none_4_6ma>, + /* d16 */ + <1 RK_PC4 1 &pcfg_pull_none_4_6ma>, + /* d17 */ + <1 RK_PC5 1 &pcfg_pull_none_4_6ma>; + }; + + lcdc_rgb888_m0: lcdc-rgb888-m0 { + rockchip,pins = + /* d18 */ + <1 RK_PC6 6 &pcfg_pull_none_4_6ma>, + /* d19 */ + <1 RK_PC7 6 &pcfg_pull_none_4_6ma>, + /* d20 */ + <2 RK_PB1 3 &pcfg_pull_none_4_6ma>, + /* d21 */ + <2 RK_PB2 3 &pcfg_pull_none_4_6ma>, + /* d22 */ + <2 RK_PB7 3 &pcfg_pull_none_4_6ma>, + /* d23 */ + <2 RK_PC0 3 &pcfg_pull_none_4_6ma>; + }; + + lcdc_rgb888_m1: lcdc-rgb888-m1 { + rockchip,pins = + /* d18 */ + <3 RK_PA6 3 &pcfg_pull_none_4_6ma>, + /* d19 */ + <3 RK_PA7 3 &pcfg_pull_none_4_6ma>, + /* d20 */ + <3 RK_PB0 3 &pcfg_pull_none_4_6ma>, + /* d21 */ + <3 RK_PB1 3 &pcfg_pull_none_4_6ma>, + /* d22 */ + <3 RK_PB2 4 &pcfg_pull_none_4_6ma>, + /* d23 */ + <3 RK_PB3 4 &pcfg_pull_none_4_6ma>; + }; + }; +}; diff --git a/rk3308k.dtsi b/rk3308k.dtsi new file mode 100644 index 0000000..5f02591 --- /dev/null +++ b/rk3308k.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include "rk3308.dtsi" + +/ { + uboot-wide-temperature { + status = "okay"; + compatible = "rockchip,uboot-wide-temperature"; + }; +}; + +&cpu0_opp_table { + rockchip,high-temp = <55000>; + rockchip,high-temp-max-freq = <1008000>; +}; + +&rk3308bs_cpu0_opp_table { + rockchip,high-temp = <55000>; + rockchip,high-temp-max-freq = <1008000>; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_PMU_HW_PLLS_PD + | RKPM_PWM_VOLTAGE_DEFAULT + ) + >; +}; + +&thermal_zones { + soc-thermal { + sustainable-power = <422>; + rk3308bs-sustainable-power = <363>; + k_pu = <6>; + k_po = <1024>; + k_i = <0>; + + trips { + trip-point@0 { + temperature = <55000>; + }; + trip-point@1 { + temperature = <90000>; + }; + }; + }; +}; diff --git a/rk3318-a95x-z2.dts b/rk3318-a95x-z2.dts new file mode 100644 index 0000000..980e5e9 --- /dev/null +++ b/rk3318-a95x-z2.dts @@ -0,0 +1,374 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include "rk3328.dtsi" + +/ { + model = "A95X Z2"; + compatible = "zkmagic,a95x-z2", "rockchip,rk3318"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&cyx_led_pin>; + pinctrl-names = "default"; + + cyx_led: led-0 { + default-state = "on"; + gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_LOW>; + label = "CYX_LED"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&wifi_enable_h>; + pinctrl-names = "default"; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + /* Power tree */ + vccio_1v8: vccio-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vccio_3v3: vccio-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&otg_vbus_drv>; + pinctrl-names = "default"; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vccio_3v3>; + }; + + vdd_arm: vdd-arm { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&analog_sound { + status = "okay"; +}; + +&codec { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cpu0_opp_table { + opp-1200000000 { + status = "disabled"; + }; + + opp-1296000000 { + status = "disabled"; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + non-removable; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gmac2phy { + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + clock_in_out = "output"; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_log>; +}; + +&hdmi { + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&io_domains { + pmuio-supply = <&vccio_3v3>; + vccio1-supply = <&vccio_3v3>; + vccio2-supply = <&vccio_1v8>; + vccio3-supply = <&vccio_3v3>; + vccio4-supply = <&vccio_1v8>; + vccio5-supply = <&vccio_3v3>; + vccio6-supply = <&vccio_3v3>; + status = "okay"; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + cyx_led_pin: cyx-led-pin { + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin_pull_up: pwm0-pin-pull-up { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>; + }; + }; + + pwm1 { + pwm1_pin_pull_up: pwm1-pin-pull-up { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc1 { + clk_32k_out: clk-32k-out { + rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_pin_pull_up>; + pinctrl-names = "active"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_pin_pull_up>; + pinctrl-names = "active"; + status = "okay"; +}; + +&saradc { + vref-supply = <&vccio_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <125000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk &clk_32k_out>; + pinctrl-names = "default"; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; +}; + +&soc_crit { + temperature = <115000>; /* millicelsius */ +}; + +&target { + temperature = <105000>; /* millicelsius */ +}; + +&threshold { + temperature = <90000>; /* millicelsius */ +}; + +&tsadc { + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + phy-supply = <&vcc_otg_vbus>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3326-863-cif-sensor.dtsi b/rk3326-863-cif-sensor.dtsi new file mode 100644 index 0000000..c01f4d0 --- /dev/null +++ b/rk3326-863-cif-sensor.dtsi @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +#include "../../../../../drivers/soc/rockchip/rk_camera_sensor_info.h" +/{ + cif_sensor: cif_sensor { + compatible = "rockchip,sensor"; + status = "disabled"; + + gc2145_b { + is_front = <0>; + powerdown-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pwdn_active = ; + pwr_active = ; + rockchip,power_pmu_name1 = "vcc2v8_dvp"; + rockchip,power_pmu_voltage1 = <2800000>; + rockchip,power_pmu_name2 = "vcc1v8_dvp"; + rockchip,power_pmu_voltage2 = <1800000>; + mir = <0>; + flash_attach = <0>; + resolution = ; + powerup_sequence = ; + orientation = <90>; + i2c_add = ; + i2c_chl = <2>; + cif_chl = <0>; + mclk_rate = <24>; + }; + + gc0312_f { + is_front = <1>; + powerdown-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn_active = ; + pwr_active = ; + rockchip,power_pmu_name1 = "vcc2v8_dvp"; + rockchip,power_pmu_voltage1 = <2800000>; + rockchip,power_pmu_name2 = "vcc1v8_dvp"; + rockchip,power_pmu_voltage2 = <1800000>; + mir = <0>; + flash_attach = <0>; + resolution = ; + powerup_sequence = ; + orientation = <270>; + i2c_add = ; + i2c_chl = <2>; + cif_chl = <0>; + mclk_rate = <24>; + }; + }; +}; + diff --git a/rk3326-863-lp3-v10-avb.dts b/rk3326-863-lp3-v10-avb.dts new file mode 100644 index 0000000..174d05e --- /dev/null +++ b/rk3326-863-lp3-v10-avb.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3326-863-lp3-v10.dtsi" + +/ { + model = "Rockchip rk3326 863 avb board"; + compatible = "rockchip,rk3326-863-lp3-v10-avb", "rockchip,rk3326"; +}; + +&firmware_android { + compatible = "android,firmware"; + boot_devices = "ff390000.dwmmc,ff3b0000.nandc"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,avb"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + gc0312@21 { + status = "okay"; + compatible = "galaxycore,gc0312"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + + port { + gc0312_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; +}; + +&isp_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d0d1_m0 &dvp_d2d9_m0 &dvp_d10d11_m0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dvp_in_fcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc0312_out>; + }; + + dvp_in_bcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + }; + }; +}; diff --git a/rk3326-863-lp3-v10-rkisp1.dts b/rk3326-863-lp3-v10-rkisp1.dts new file mode 100644 index 0000000..2d0fa8a --- /dev/null +++ b/rk3326-863-lp3-v10-rkisp1.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3326-863-lp3-v10.dtsi" + +/ { + model = "Rockchip rk3326 863 rkisp1 board"; + compatible = "rockchip,rk3326-863-lp3-v10-rkisp1", "rockchip,rk3326"; +}; + +&i2c2 { + status = "okay"; + + gc0312: gc0312@21 { + status = "okay"; + compatible = "galaxycore,gc0312"; + reg = <0x21>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc0312_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + gc2145: gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; +}; + +&isp_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_d0d1_m0 &dvp_d2d9_m0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dvp_in_fcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc0312_out>; + }; + + dvp_in_bcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + }; + }; +}; diff --git a/rk3326-863-lp3-v10.dts b/rk3326-863-lp3-v10.dts new file mode 100644 index 0000000..7a399b3 --- /dev/null +++ b/rk3326-863-lp3-v10.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "rk3326-863-lp3-v10.dtsi" + +/ { + model = "Rockchip rk3326 863 board"; + compatible = "rockchip,rk3326-863-lp3-v10", "rockchip,rk3326"; +}; + +&cif { + status = "okay"; +}; + +&cif_sensor { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/rk3326-863-lp3-v10.dtsi b/rk3326-863-lp3-v10.dtsi new file mode 100644 index 0000000..c7b435a --- /dev/null +++ b/rk3326-863-lp3-v10.dtsi @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3326.dtsi" +#include "rk3326-863-cif-sensor.dtsi" +#include "px30-android.dtsi" + +/ { + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 10 10 11 11 12 12 13 + 13 14 14 15 15 16 16 17 + 17 18 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&cru SCLK_WIFI_PMU>; + clock-names = "clk_wifi_pmu"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "rtl8723cs"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,vbat_gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <108>; + height-mm = <172>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 + 05 14 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <2>; + hsync-len = <18>; + hback-porch = <18>; + vfront-porch = <4>; + vsync-len = <4>; + vback-porch = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu0_opp_table { + /* + * max IR-drop values on different freq condition for this board! + */ + rockchip,board-irdrop = < + /*MHz MHz uV */ + 0 815 37500 + 816 1119 50000 + 1200 1512 75000 + >; +}; + +&dmc_opp_table { + /* + * max IR-drop values on different freq condition for this board! + */ + rockchip,board-irdrop = < + /*MHz MHz uV */ + 451 800 75000 + >; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3548 3592 3636 3687 3740 3780 + 3806 3827 3846 3864 3889 3929 3964 + 3993 4015 4030 4041 4056 4076 4148>; + design_capacity = <4000>; + design_qmax = <4200>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3500>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + ts@40 { + status = "okay"; + compatible = "GSL,GSL3673_800X1280"; + reg = <0x40>; + irq_gpio_number = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + }; + + sensor@19 { + status = "okay"; + compatible = "gs_lis3dh"; + reg = <0x19>; + type = ; + irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <7>; + reprobe_en = <1>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_3v0>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc2v8_dvp>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + rockchip,low-power-mode; + status = "okay"; + }; + + u2phy_otg: otg-port { + rockchip,low-power-mode; + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vip_mmu { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; diff --git a/rk3326-86v-v10.dts b/rk3326-86v-v10.dts new file mode 100644 index 0000000..53fae4d --- /dev/null +++ b/rk3326-86v-v10.dts @@ -0,0 +1,840 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3326.dtsi" +#include "rk3326-863-cif-sensor.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip rk3326 86v board"; + compatible = "rockchip,rk3326-86v-v10", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <617000>; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 10 10 11 11 12 12 13 + 13 14 14 15 15 16 16 17 + 17 18 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + panel { + compatible ="simple-panel"; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + bus-format = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <100>; + hfront-porch = <120>; + vback-porch = <10>; + vfront-porch = <15>; + hsync-len = <100>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk817-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&cru SCLK_WIFI_PMU>; + clock-names = "clk_wifi_pmu"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; +}; + +&cif { + status = "okay"; +}; + +&cif_sensor { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu0_opp_table { + /* + * max IR-drop values on different freq condition for this board! + */ + rockchip,board-irdrop = < + /*MHz MHz uV */ + 0 815 75000 + 816 1119 75000 + 1200 1512 75000 + >; +}; + +&dmc_opp_table { + /* + * max IR-drop values on different freq condition for this board! + */ + rockchip,board-irdrop = < + /*MHz MHz uV */ + 451 800 75000 + >; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + /*mmc-hs200-1_8v;*/ + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3548 3592 3636 3687 3740 3780 + 3806 3827 3846 3864 3889 3929 3964 + 3993 4015 4030 4041 4056 4076 4148>; + design_capacity = <4000>; + design_qmax = <4200>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3500>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + ts@40 { + compatible = "gslX680-d708"; + reg = <0x40>; + touch-gpio = <&gpio0 RK_PB3 IRQ_TYPE_LEVEL_LOW>; + wake-gpio = <&gpio0 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + screen_max_x = <1024>; + screen_max_y = <600>; + revert_x = <1>; + status = "okay"; + }; + + sensor@1d { + status = "okay"; + compatible = "gs_lsm303d"; + reg = <0x1d>; + type = ; + irq-gpio = <&gpio0 RK_PA1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <5>; + reprobe_en = <1>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_3v0>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc2v8_dvp>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcdc { + lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ + <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ + <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ + <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ + <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ + <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ + <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ + <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ + <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ + <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ + <3 RK_PC5 1 &pcfg_pull_none_8ma>; /* LCDC_D17 */ + }; + + lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D17 */ + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_rgb { + connect = <&vopb_out_rgb>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "disabled"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + rockchip,low-power-mode; + status = "okay"; + }; + + u2phy_otg: otg-port { + rockchip,low-power-mode; + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vip_mmu { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; diff --git a/rk3326-evb-ai-va-v10.dts b/rk3326-evb-ai-va-v10.dts new file mode 100644 index 0000000..0c1df28 --- /dev/null +++ b/rk3326-evb-ai-va-v10.dts @@ -0,0 +1,1308 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3326.dtsi" +#include "rk3326-863-cif-sensor.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip rk3326 ai voice assistant evb board"; + compatible = "rockchip,rk3326-evb-ai-va-v10", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + mute-key { + linux,code = ; + label = "mute"; + press-threshold-microvolt = <1119000>; + }; + + mode-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <892000>; + }; + + media-key { + linux,code = ; + label = "media"; + press-threshold-microvolt = <616000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <15000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_2ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "pdm"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&rk809_codec 1>; + }; + }; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 1>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + test-power { + status = "okay"; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <40>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + + vcc5v0_host: SWITCH_REG1 { + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + pdmdata-out-enable; + use-ext-amplifier; + adc-for-loopback; + spk-ctl-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + hp-volume = <20>; + spk-volume = <20>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + }; + + is31fl3236: led-controller@3c { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; + + ls_stk3410: light@48 { + compatible = "ls_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3410: proximity@48 { + compatible = "ps_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio2_c3>; + //irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x4 2:x16 3:x64 */ + ps_led_current = <3>; /* 0:12.5mA 1:25mA 2:50mA 3:100mA */ + poll_delay_ms = <100>; + }; + +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-0 = <&i2s1_2ch_sclk + &i2s1_2ch_lrck + &i2s1_2ch_sdo>; +}; + +&i2s2_2ch { + status = "okay"; + rockchip,bclk-fs = <64>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc1v8_soc>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pdm { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk0m1 + &pdm_clk1 + &pdm_sdi0m1 + &pdm_sdi1 + &pdm_sdi2 + &pdm_sdi3>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d0d1_m0 &dvp_d2d9_m0>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326-evb-ai-va-v11-i2s-dmic.dts b/rk3326-evb-ai-va-v11-i2s-dmic.dts new file mode 100644 index 0000000..6e8f284 --- /dev/null +++ b/rk3326-evb-ai-va-v11-i2s-dmic.dts @@ -0,0 +1,1330 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3326.dtsi" +#include "rk3326-863-cif-sensor.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip rk3326 ai voice assistant evb v11 i2s-dmic board"; + compatible = "rockchip,rk3326-evb-ai-va-v11-i2s-dmic", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + mute-key { + linux,code = ; + label = "mute"; + press-threshold-microvolt = <1119000>; + }; + + mode-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <892000>; + }; + + media-key { + linux,code = ; + label = "media"; + press-threshold-microvolt = <616000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <15000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + multi_dais: multi-dais { + status = "okay"; + compatible = "rockchip,multi-dais"; + dais = <&pdm>, <&i2s0_8ch>; + capture,channel-mapping = <2 6>; + playback,channel-mapping = <0 0>; + #sound-dai-cells = <0>; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_2ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&multi_dais>; + }; + codec { + sound-dai = <&rk809_codec 1>; + }; + }; + }; + + bt-sound { + compatible = "simple-audio-card"; + status = "disabled"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 1>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + test-power { + status = "okay"; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6255"; + WIFI,host_wake_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <40>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + pdmdata-out-enable; + use-ext-amplifier; + adc-for-loopback; + spk-ctl-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + hp-volume = <20>; + spk-volume = <20>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB3 IRQ_TYPE_LEVEL_LOW>; + }; + + is31fl3236: led-controller@3c { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; + + ls_stk3410: light@48 { + compatible = "ls_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3410: proximity@48 { + compatible = "ps_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio2_c3>; + //irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x4 2:x16 3:x64 */ + ps_led_current = <3>; /* 0:12.5mA 1:25mA 2:50mA 3:100mA */ + poll_delay_ms = <100>; + }; + +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-0 = <&i2s1_2ch_sclk + &i2s1_2ch_lrck + &i2s1_2ch_sdo>; +}; + +&i2s2_2ch { + status = "okay"; + rockchip,bclk-fs = <64>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc1v8_soc>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pdm { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,no-dmaengine; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk0m1 + &pdm_sdi0m1>; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&tp_int>; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen-int { + tp_int: tp-int { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + vbus-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d0d1_m0 &dvp_d2d9_m0>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326-evb-ai-va-v11.dts b/rk3326-evb-ai-va-v11.dts new file mode 100644 index 0000000..f7af4fc --- /dev/null +++ b/rk3326-evb-ai-va-v11.dts @@ -0,0 +1,1317 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3326.dtsi" +#include "rk3326-863-cif-sensor.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip rk3326 ai voice assistant evb v11 board"; + compatible = "rockchip,rk3326-evb-ai-va-v11", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + mute-key { + linux,code = ; + label = "mute"; + press-threshold-microvolt = <1119000>; + }; + + mode-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <892000>; + }; + + media-key { + linux,code = ; + label = "media"; + press-threshold-microvolt = <616000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <15000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_2ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "pdm"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&rk809_codec 1>; + }; + }; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 1>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + test-power { + status = "okay"; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6255"; + WIFI,host_wake_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <40>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + pdmdata-out-enable; + use-ext-amplifier; + adc-for-loopback; + spk-ctl-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + hp-volume = <20>; + spk-volume = <20>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB3 IRQ_TYPE_LEVEL_LOW>; + }; + + is31fl3236: led-controller@3c { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; + + ls_stk3410: light@48 { + compatible = "ls_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3410: proximity@48 { + compatible = "ps_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio2_c3>; + //irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x4 2:x16 3:x64 */ + ps_led_current = <3>; /* 0:12.5mA 1:25mA 2:50mA 3:100mA */ + poll_delay_ms = <100>; + }; + +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-0 = <&i2s1_2ch_sclk + &i2s1_2ch_lrck + &i2s1_2ch_sdo>; +}; + +&i2s2_2ch { + status = "okay"; + rockchip,bclk-fs = <64>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc1v8_soc>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pdm { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk0m1 + &pdm_clk1 + &pdm_sdi0m1 + &pdm_sdi1 + &pdm_sdi2 + &pdm_sdi3>; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&tp_int>; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen-int { + tp_int: tp-int { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + vbus-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d0d1_m0 &dvp_d2d9_m0>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326-evb-ai-va-v12.dts b/rk3326-evb-ai-va-v12.dts new file mode 100644 index 0000000..71024a9 --- /dev/null +++ b/rk3326-evb-ai-va-v12.dts @@ -0,0 +1,1317 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3326.dtsi" +#include "rk3326-863-cif-sensor.dtsi" +#include "px30-android.dtsi" + +/ { + model = "Rockchip rk3326 ai voice assistant evb v12 board"; + compatible = "rockchip,rk3326-evb-ai-va-v12", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + mute-key { + linux,code = ; + label = "mute"; + press-threshold-microvolt = <1119000>; + }; + + mode-key { + linux,code = ; + label = "mode"; + press-threshold-microvolt = <892000>; + }; + + media-key { + linux,code = ; + label = "media"; + press-threshold-microvolt = <616000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <15000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_2ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "pdm"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&rk809_codec 1>; + }; + }; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 1>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + test-power { + status = "okay"; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6256"; + WIFI,host_wake_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <40>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + pdmdata-out-enable; + use-ext-amplifier; + adc-for-loopback; + spk-ctl-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + hp-volume = <20>; + spk-volume = <20>; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB3 IRQ_TYPE_LEVEL_LOW>; + }; + + is31fl3236: led-controller@3c { + compatible = "issi,is31fl3236"; + reg = <0x3c>; + #address-cells = <1>; + #size-cells = <0>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + + led1: led@1 { + label = "led1"; + reg = <1>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led2: led@2 { + label = "led2"; + reg = <2>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <0>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led3: led@3 { + label = "led3"; + reg = <3>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led4: led@4 { + label = "led4"; + reg = <4>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led5: led@5 { + label = "led5"; + reg = <5>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led6: led@6 { + label = "led6"; + reg = <6>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led7: led@7 { + label = "led7"; + reg = <7>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led8: led@8 { + label = "led8"; + reg = <8>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <200>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led9: led@9 { + label = "led9"; + reg = <9>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led10: led@10 { + label = "led10"; + reg = <10>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led11: led@11 { + label = "led11"; + reg = <11>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <300>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led12: led@12 { + label = "led12"; + reg = <12>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led13: led@13 { + label = "led13"; + reg = <13>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led14: led@14 { + label = "led14"; + reg = <14>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <400>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led15: led@15 { + label = "led15"; + reg = <15>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led16: led@16 { + label = "led16"; + reg = <16>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led17: led@17 { + label = "led17"; + reg = <17>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <500>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led18: led@18 { + label = "led18"; + reg = <18>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led19: led@19 { + label = "led19"; + reg = <19>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led20: led@20 { + label = "led20"; + reg = <20>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <600>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led21: led@21 { + label = "led21"; + reg = <21>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led22: led@22 { + label = "led22"; + reg = <22>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led23: led@23 { + label = "led23"; + reg = <23>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <700>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led124: led@24 { + label = "led24"; + reg = <24>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led25: led@25 { + label = "led25"; + reg = <25>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led26: led@26 { + label = "led26"; + reg = <26>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <800>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led27: led@27 { + label = "led27"; + reg = <27>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led28: led@28 { + label = "led28"; + reg = <28>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led29: led@29 { + label = "led29"; + reg = <29>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <900>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led30: led@30 { + label = "led30"; + reg = <30>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led31: led@31 { + label = "led31"; + reg = <31>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led32: led@32 { + label = "led32"; + reg = <32>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1000>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led33: led@33 { + label = "led33"; + reg = <33>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + + led34: led@34 { + label = "led34"; + reg = <34>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led35: led@35 { + label = "led35"; + reg = <35>; + led-max-microamp = <10000>; + linux,default-trigger = "timer"; + linux,default-trigger-delay-ms = <1100>; + linux,blink-delay-on-ms = <100>; + linux,blink-delay-off-ms = <1200>; + }; + + led36: led@36 { + label = "led36"; + reg = <36>; + led-max-microamp = <10000>; + linux,default-trigger = "default-on"; + }; + }; + + ls_stk3410: light@48 { + compatible = "ls_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3410: proximity@48 { + compatible = "ps_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio2_c3>; + //irq-gpio = <&gpio0 RK_PB7 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x4 2:x16 3:x64 */ + ps_led_current = <3>; /* 0:12.5mA 1:25mA 2:50mA 3:100mA */ + poll_delay_ms = <100>; + }; + +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-0 = <&i2s1_2ch_sclk + &i2s1_2ch_lrck + &i2s1_2ch_sdo>; +}; + +&i2s2_2ch { + status = "okay"; + rockchip,bclk-fs = <64>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc1v8_soc>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pdm { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk0m1 + &pdm_clk1 + &pdm_sdi0m1 + &pdm_sdi1 + &pdm_sdi2 + &pdm_sdi3>; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&tp_int>; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touchscreen-int { + tp_int: tp-int { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + vbus-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d0d1_m0 &dvp_d2d9_m0>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326-evb-lp3-v10-avb.dts b/rk3326-evb-lp3-v10-avb.dts new file mode 100644 index 0000000..9f79019 --- /dev/null +++ b/rk3326-evb-lp3-v10-avb.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3326.dtsi" +#include "px30-android.dtsi" +#include "rk3326-evb-lp3-v10.dtsi" +#include "rk3326-863-cif-sensor.dtsi" + +/ { + model = "Rockchip rk3326 evb board"; + compatible = "rockchip,rk3326-evb-lp3-v10-avb", "rockchip,rk3326"; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d2d9_m0>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326-evb-lp3-v10-linux.dts b/rk3326-evb-lp3-v10-linux.dts new file mode 100644 index 0000000..a6dfb18 --- /dev/null +++ b/rk3326-evb-lp3-v10-linux.dts @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3326.dtsi" +#include "rk3326-linux.dtsi" +#include "rk3326-evb-lp3-v10.dtsi" + +/ { + model = "Rockchip rk3326 evb lpddr3 v10 board for linux"; + compatible = "rockchip,rk3326-evb-lp3-v10-linux", "rockchip,rk3326"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait"; + }; + + /delete-node/ test-power; +}; + +&cif_new { + status = "okay"; + + port { + cif_in: endpoint { + remote-endpoint = <&gc2155_out>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* 24M mclk is shared for multiple cameras */ + pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + gc2155: gc2155@3c { + compatible = "gc,gc2155"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_pin_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + /* hw changed the pwdn to gpio2_b5 */ + pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + + port { + gc2155_out: endpoint { + remote-endpoint = <&cif_in>; + }; + }; + }; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&pinctrl { + cif-pin-m0 { + cif_pin_m0: cif-pin-m0 { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ + <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ + <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ + <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ + <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ + <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ + <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ + <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ + <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ + <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ + <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ + }; + }; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&vip_mmu { + status = "okay"; +}; diff --git a/rk3326-evb-lp3-v10-robot-linux.dts b/rk3326-evb-lp3-v10-robot-linux.dts new file mode 100644 index 0000000..2791c7a --- /dev/null +++ b/rk3326-evb-lp3-v10-robot-linux.dts @@ -0,0 +1,748 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "px30-robot.dtsi" + +/ { + model = "Rockchip rk3326 evb lpddr3 v10 board for robot linux"; + compatible = "rockchip,rk3326-evb-lp3-v10-robot-linux", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk817-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk817 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cif_new { + status = "okay"; + + port { + cif_in: endpoint { + remote-endpoint = <&gc2155_out>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3625 3685 3697 3718 3735 3748 + 3760 3774 3788 3802 3816 3834 3853 + 3877 3908 3946 3975 4018 4071 4106>; + design_capacity = <2500>; + design_qmax = <2750>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <3500>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <1>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* 24M mclk is shared for multiple cameras */ + pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + gc2155: gc2155@3c { + compatible = "gc,gc2155"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_pin_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + /* hw changed the pwdn to gpio2_b5 */ + pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + + port { + gc2155_out: endpoint { + remote-endpoint = <&cif_in>; + }; + }; + }; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&rk_rga { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vip_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&pinctrl { + cif-pin-m0 { + cif_pin_m0: cif-pin-m0 { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ + <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ + <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ + <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ + <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ + <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ + <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ + <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ + <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ + <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ + <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ + }; + + cif_pin_m1: cif-pin-m1 { + rockchip,pins = + <3 RK_PA3 3 &pcfg_pull_none>,/* cif_data2 */ + <3 RK_PA5 3 &pcfg_pull_none>,/* cif_data3 */ + <3 RK_PA7 3 &pcfg_pull_none>,/* cif_data4 */ + <3 RK_PB0 3 &pcfg_pull_none>,/* cif_data5 */ + <3 RK_PB1 3 &pcfg_pull_none>,/* cif_data6 */ + <3 RK_PB4 3 &pcfg_pull_none>,/* cif_data7 */ + <3 RK_PB6 3 &pcfg_pull_none>,/* cif_data8 */ + <3 RK_PB7 3 &pcfg_pull_none>,/* cif_data9 */ + <3 RK_PD1 3 &pcfg_pull_none>,/* cif_sync */ + <3 RK_PD2 3 &pcfg_pull_none>,/* cif_href */ + <3 RK_PD3 3 &pcfg_pull_none>;/* cif_clkin */ + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/rk3326-evb-lp3-v10-robot-no-gpu-linux.dts b/rk3326-evb-lp3-v10-robot-no-gpu-linux.dts new file mode 100644 index 0000000..9c4dcf7 --- /dev/null +++ b/rk3326-evb-lp3-v10-robot-no-gpu-linux.dts @@ -0,0 +1,728 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "px30-robot-no-gpu.dtsi" + +/ { + model = "Rockchip rk3326 evb lpddr3 v10 board for robot linux"; + compatible = "rockchip,rk3326-evb-lp3-v10-robot-linux", "rockchip,rk3326"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk817-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk817 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cif_new { + status = "okay"; + + port { + cif_in: endpoint { + remote-endpoint = <&gc2155_out>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3625 3685 3697 3718 3735 3748 + 3760 3774 3788 3802 3816 3834 3853 + 3877 3908 3946 3975 4018 4071 4106>; + design_capacity = <2500>; + design_qmax = <2750>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <3500>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <1>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + /* 24M mclk is shared for multiple cameras */ + pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + gc2155: gc2155@3c { + compatible = "gc,gc2155"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_pin_m0>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + /* hw changed the pwdn to gpio2_b5 */ + pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + + port { + gc2155_out: endpoint { + remote-endpoint = <&cif_in>; + }; + }; + }; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v8_dvp>; + + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&rk_rga { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vip_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&pinctrl { + cif-pin-m0 { + cif_pin_m0: cif-pin-m0 { + rockchip,pins = + <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ + <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ + <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ + <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ + <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ + <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ + <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ + <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ + <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ + <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ + <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/rk3326-evb-lp3-v10.dts b/rk3326-evb-lp3-v10.dts new file mode 100644 index 0000000..cc2057e --- /dev/null +++ b/rk3326-evb-lp3-v10.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3326.dtsi" +#include "px30-android.dtsi" +#include "rk3326-evb-lp3-v10.dtsi" +#include "rk3326-863-cif-sensor.dtsi" + +/ { + model = "Rockchip rk3326 evb board"; + compatible = "rockchip,rk3326-evb-lp3-v10", "rockchip,rk3326"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; + +&rk_isp { + status = "okay"; +}; diff --git a/rk3326-evb-lp3-v10.dtsi b/rk3326-evb-lp3-v10.dtsi new file mode 100644 index 0000000..5b9eaf4 --- /dev/null +++ b/rk3326-evb-lp3-v10.dtsi @@ -0,0 +1,868 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +/ { + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "back"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "homepage"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 1>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk817 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + test-power { + status = "okay"; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc18_lcd_n: vcc18-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc18_lcd_n"; + regulator-boot-on; + gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + power-supply = <&vcc18_lcd_n>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 fa 01 11 + 39 00 04 b9 f1 12 83 + 39 00 1c ba 33 81 05 f9 0e 0e 00 00 00 + 00 00 00 00 00 44 25 00 91 0a + 00 00 02 4f 01 00 00 37 + 15 00 02 b8 25 + 39 00 04 bf 02 11 00 + 39 00 0b b3 0c 10 0a 50 03 ff 00 00 00 + 00 + 39 00 0a c0 73 73 50 50 00 00 08 70 00 + 15 00 02 bc 46 + 15 00 02 cc 0b + 15 00 02 b4 80 + 39 00 04 b2 c8 12 30 + 39 00 0f e3 07 07 0b 0b 03 0b 00 00 00 + 00 ff 00 c0 10 + 39 00 0d c1 53 00 1e 1e 77 e1 cc dd 67 + 77 33 33 + 39 00 07 c6 00 00 ff ff 01 ff + 39 00 03 b5 09 09 + 39 00 03 b6 87 95 + 39 00 40 e9 c2 10 05 05 10 05 a0 12 31 + 23 3f 81 0a a0 37 18 00 80 01 + 00 00 00 00 80 01 00 00 00 48 + f8 86 42 08 88 88 80 88 88 88 + 58 f8 87 53 18 88 88 81 88 88 + 88 00 00 00 01 00 00 00 00 00 + 00 00 00 00 + 39 00 3e ea 00 1a 00 00 00 00 02 00 00 + 00 00 00 1f 88 81 35 78 88 88 + 85 88 88 88 0f 88 80 24 68 88 + 88 84 88 88 88 23 10 00 00 1c + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 30 05 a0 00 00 + 00 00 + 39 00 23 e0 00 06 08 2a 31 3f 38 36 07 + 0c 0d 11 13 12 13 11 18 00 06 + 08 2a 31 3f 38 36 07 0c 0d 11 + 13 12 13 11 18 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3625 3685 3697 3718 3735 3748 + 3760 3774 3788 3802 3816 3834 3853 + 3877 3908 3946 3975 4018 4071 4106>; + design_capacity = <2500>; + design_qmax = <2750>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <3500>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <1>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <275>; + i2c-scl-falling-time-ns = <16>; + + sensor@f { + status = "okay"; + compatible = "ak8963"; + reg = <0x0f>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <1>; + reprobe_en = <1>; + }; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + power-supply = <&vcc18_lcd_n>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + }; + + sensor@4c { + status = "okay"; + compatible = "gs_mma7660"; + reg = <0x4c>; + type = ; + irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <1>; + reprobe_en = <1>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_pin>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; diff --git a/rk3326-evb-lp3-v11-avb.dts b/rk3326-evb-lp3-v11-avb.dts new file mode 100644 index 0000000..4b1c4ea --- /dev/null +++ b/rk3326-evb-lp3-v11-avb.dts @@ -0,0 +1,354 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3326.dtsi" +#include "px30-android.dtsi" +#include "rk3326-evb-lp3-v10.dtsi" +#include "rk3326-863-cif-sensor.dtsi" + +/ { + model = "Rockchip rk3326 evb board"; + compatible = "rockchip,rk3326-evb-lp3-v11-avb", "rockchip,rk3326"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc18_lcd_n>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 78 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "default"; + //pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0 &dvp_d2d9_m0>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326-evb-lp3-v11.dts b/rk3326-evb-lp3-v11.dts new file mode 100644 index 0000000..f8a3eef --- /dev/null +++ b/rk3326-evb-lp3-v11.dts @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3326.dtsi" +#include "px30-android.dtsi" +#include "rk3326-evb-lp3-v10.dtsi" +#include "rk3326-863-cif-sensor.dtsi" + +/ { + model = "Rockchip rk3326 evb board"; + compatible = "rockchip,rk3326-evb-lp3-v11", "rockchip,rk3326"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc18_lcd_n>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; +}; + +&rk_isp { + status = "okay"; +}; diff --git a/rk3326-evb-lp3-v12-linux.dts b/rk3326-evb-lp3-v12-linux.dts new file mode 100644 index 0000000..ed0781d --- /dev/null +++ b/rk3326-evb-lp3-v12-linux.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; + +#include "rk3326-evb-lp3-v10-linux.dts" + +/ { + model = "Rockchip rk3326 evb lpddr3 v12 board for linux"; + compatible = "rockchip,rk3326-evb-lp3-v12-linux", "rockchip,rk3326"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + power-supply = <&vcc18_lcd_n>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/rk3326-linux.dtsi b/rk3326-linux.dtsi new file mode 100644 index 0000000..f3ed899 --- /dev/null +++ b/rk3326-linux.dtsi @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + compatible = "rockchip,linux", "rockchip,rk3326"; + + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + }; +}; + +&cpu0_opp_table { + rockchip,avs = <1>; +}; + +&display_subsystem { + status = "disabled"; + logo-memory-region = <&drm_logo>; + + route { + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_lvds>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_rgb>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; diff --git a/rk3326-odroid-go2.dts b/rk3326-odroid-go2.dts new file mode 100644 index 0000000..3376810 --- /dev/null +++ b/rk3326-odroid-go2.dts @@ -0,0 +1,555 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Hardkernel Co., Ltd + * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include +#include +#include +#include "rk3326.dtsi" + +/ { + model = "ODROID-GO Advance"; + compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_bl>; + pwms = <&pwm1 0 25000 0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&btn_pins>; + + /* + * *** ODROIDGO2-Advance Switch layout *** + * |------------------------------------------------| + * | sw15 sw16 | + * |------------------------------------------------| + * | sw1 |-------------------| sw8 | + * | sw3 sw4 | | sw7 sw5 | + * | sw2 | LCD Display | sw6 | + * | | | | + * | |-------------------| | + * | sw9 sw10 sw11 sw12 sw13 sw14 | + * |------------------------------------------------| + */ + + sw1 { + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + label = "DPAD-UP"; + linux,code = ; + }; + sw2 { + gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + label = "DPAD-DOWN"; + linux,code = ; + }; + sw3 { + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + label = "DPAD-LEFT"; + linux,code = ; + }; + sw4 { + gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>; + label = "DPAD-RIGHT"; + linux,code = ; + }; + sw5 { + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + label = "BTN-A"; + linux,code = ; + }; + sw6 { + gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + label = "BTN-B"; + linux,code = ; + }; + sw7 { + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + label = "BTN-Y"; + linux,code = ; + }; + sw8 { + gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + label = "BTN-X"; + linux,code = ; + }; + sw9 { + gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>; + label = "F1"; + linux,code = ; + }; + sw10 { + gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>; + label = "F2"; + linux,code = ; + }; + sw11 { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + label = "F3"; + linux,code = ; + }; + sw12 { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>; + label = "F4"; + linux,code = ; + }; + sw13 { + gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>; + label = "F5"; + linux,code = ; + }; + sw14 { + gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>; + label = "F6"; + linux,code = ; + }; + sw15 { + gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; + label = "TOP-LEFT"; + linux,code = ; + }; + sw16 { + gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>; + label = "TOP-RIGHT"; + linux,code = ; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&blue_led_pin>; + + blue_led: led-0 { + label = "blue:heartbeat"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc_host { + compatible = "regulator-fixed"; + regulator-name = "vcc_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <&vccsys>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&cru { + assigned-clocks = <&cru PLL_NPLL>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, + <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>, + <&cru PLL_CPLL>; + + assigned-clock-rates = <1188000000>, + <200000000>, <200000000>, + <150000000>, <150000000>, + <100000000>, <200000000>, + <17000000>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + panel@0 { + compatible = "elida,kd35t133"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc_lcd>; + reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + vdd-supply = <&vcc_lcd>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <16>; + i2c-scl-rising-time-ns = <280>; + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "xin32k"; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-name = "vcc_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-name = "vcc3v3_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_bl: LDO_REG7 { + regulator-name = "vcc_bl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lcd: LDO_REG8 { + regulator-name = "vcc_lcd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc_cam: LDO_REG9 { + regulator-name = "vcc_cam"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; +}; + +/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */ +&i2c1 { + clock-frequency = <400000>; + status = "okay"; +}; + +/* I2S 1 Channel Used */ +&i2s1_2ch { + status = "okay"; +}; + +&io_domains { + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc { + cap-sd-highspeed; + card-detect-delay = <200>; + cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "disabled"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&pinctrl { + btns { + btn_pins: btn-pins { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + blue_led_pin: blue-led-pin { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dc_det: dc-det { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3326.dtsi b/rk3326.dtsi new file mode 100644 index 0000000..004bda9 --- /dev/null +++ b/rk3326.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "px30.dtsi" + +&cru { + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1040000000>; +}; + +&display_subsystem { + ports = <&vopb_out>; +}; + +&gpu_opp_table { + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <1150000>; + opp-microvolt-L2 = <1100000>; + opp-microvolt-L3 = <1050000>; + }; +}; + +&rgb { + phys = <&video_phy>; + phy-names = "phy"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_m1_rgb_pins>; + pinctrl-1 = <&lcdc_m1_sleep_pins>; +}; + +&pinctrl { + lcdc { + lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ + <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ + <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ + <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ + <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ + <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ + <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ + <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ + <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ + <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ + <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ + <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ + <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ + <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ + <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ + <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ + <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ + <3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ + }; + + lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ + }; + }; +}; + +/delete-node/ &dsi_in_vopl; +/delete-node/ &lvds_vopl_in; +/delete-node/ &rgb_in_vopl; +/delete-node/ &vopl; +/delete-node/ &vopl_mmu; diff --git a/rk3326/rk3326-evb-rpdzkj-rk817.dtsi b/rk3326/rk3326-evb-rpdzkj-rk817.dtsi new file mode 100755 index 0000000..3b08761 --- /dev/null +++ b/rk3326/rk3326-evb-rpdzkj-rk817.dtsi @@ -0,0 +1,381 @@ + +/ { + test-power { + status = "disabled"; + }; + + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3250>; + rockchip,screen-on-voltage = <3300>; + status = "okay"; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <280>; + i2c-scl-falling-time-ns = <16>; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_3v0>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + status = "okay"; + compatible = "rk817,battery"; + ocv_table = <3300 3337 3374 3411 3447 3485 3524 + 3561 3598 3635 3672 3709 3746 3785 + 3822 3859 3896 3933 3970 4007 4050>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <3300>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; //test mode, 1 to force report 66% + + //rpdzkj add Mandatory configuration under the condition of no battery, the power connected to external DC is 0, and 50% is reported + dc_rpdzkj_psy = <1>; //强制é…置无电池情况下接外部DC电é‡ä¸º0上报50% 1:enable 0:not + }; + + charger { + status = "okay"; + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <3000>;//1500 + max_chrg_current = <1000>;//2000 + max_chrg_voltage = <4350>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + // extcon = <&u2phy>; //otg charging + + //power_dc2otg = <1>; + //dc_det_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; //å¯é…ç½®pins 读å–dc转3.3V以下电压åšdc充电检测脚 + //rpdzkj add Configure external DC to detect and report charging status + rpdzkj_dc_vbus = <1>; //é…置外部DCæ£€æµ‹ä¸ŠæŠ¥å……ç”µçŠ¶æ€ 1:enable 0:not + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc1v8_soc>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc1v8_dvp>; + vccio4-supply = <&vcc_3v0>; + vccio5-supply = <&vcc_3v0>; + vccio6-supply = <&vcc1v8_soc>; +}; diff --git a/rk3326/rp-adc-key.dtsi b/rk3326/rp-adc-key.dtsi new file mode 100755 index 0000000..c21ff21 --- /dev/null +++ b/rk3326/rp-adc-key.dtsi @@ -0,0 +1,40 @@ + +/ { + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; +}; diff --git a/rk3326/rp-audio-rk817.dtsi b/rk3326/rp-audio-rk817.dtsi new file mode 100755 index 0000000..d1ae86c --- /dev/null +++ b/rk3326/rp-audio-rk817.dtsi @@ -0,0 +1,43 @@ + +/ { + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + // hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + // io-channels = <&saradc 1>; + // io-channel-names = "adc-detect"; + // keyup-threshold-microvolt = <1800000>; + // poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk817_codec>; + // pinctrl-names = "default"; + // pinctrl-0 = <&hp_det>; + // play-pause-key { + // label = "playpause"; + // linux,code = ; + // press-threshold-microvolt = <2000>; + // }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk3326/rp-lcd-lvds-10-1280-800.dtsi b/rk3326/rp-lcd-lvds-10-1280-800.dtsi new file mode 100755 index 0000000..2795f79 --- /dev/null +++ b/rk3326/rp-lcd-lvds-10-1280-800.dtsi @@ -0,0 +1,244 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + + panel@0 { + compatible = "simple-panel"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <217>; + height-mm = <136>; + bus-format = ; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + disp_timings0: display-timings { + native-mode = <&lvds_timing0>; + lvds_timing0: timing0 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <138>; + hfront-porch = <136>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "LVDS"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_vopb_in { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_lvds { + connect = <&vopb_out_lvds>; + status = "okay"; +}; + +&dsi_in_vopb { + status = "disabled"; +}; + +&route_dsi { + status = "disabled"; +}; + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1280>; + gtp_resolution_y = <800>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group2 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; + + goodix,cfg-group3 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-lvds-7-1024-600.dtsi b/rk3326/rp-lcd-lvds-7-1024-600.dtsi new file mode 100755 index 0000000..e67e6f8 --- /dev/null +++ b/rk3326/rp-lcd-lvds-7-1024-600.dtsi @@ -0,0 +1,228 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + + panel@0 { + compatible = "simple-panel"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <217>; + height-mm = <136>; + bus-format = ; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + disp_timings0: display-timings { + native-mode = <&lvds_timing0>; + lvds_timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "LVDS"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_vopb_in { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_lvds { + connect = <&vopb_out_lvds>; + status = "okay"; +}; + +&dsi_in_vopb { + status = "disabled"; +}; + +&route_dsi { + status = "disabled"; +}; + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ + 5A 00 04 58 02 05 3D 00 01 + 08 32 0F 5A 32 03 05 00 00 + 00 00 02 00 00 18 1A 1E 14 + 87 29 0A 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 + 2B FF 7F 19 46 32 3C 78 94 + D5 02 08 00 00 04 98 40 00 + 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 + 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 02 04 06 08 0A + 0C 0E 10 12 14 FF FF FF FF + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 1D 1E 1F 20 + 21 22 24 26 28 29 2A FF FF + FF FF FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6F 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-10-1200-1920.dtsi b/rk3326/rp-lcd-mipi-10-1200-1920.dtsi new file mode 100755 index 0000000..ff50ad8 --- /dev/null +++ b/rk3326/rp-lcd-mipi-10-1200-1920.dtsi @@ -0,0 +1,237 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "270"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <1000>; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; + + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-10-1920-1200.dtsi b/rk3326/rp-lcd-mipi-10-1920-1200.dtsi new file mode 100755 index 0000000..4db0a8e --- /dev/null +++ b/rk3326/rp-lcd-mipi-10-1920-1200.dtsi @@ -0,0 +1,220 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <1200>; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <60>; //60 + hfront-porch = <16>; //16 + vback-porch = <23>; //23 + vfront-porch = <12>; //12 + hsync-len = <20>; //20 + vsync-len = <3>; //3 + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1200>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ + 55 80 07 B0 04 0A 3D 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 8E 2F 99 17 15 31 + 0D 00 00 02 9B 03 1D 00 00 00 00 + 00 00 00 00 00 00 00 1E 78 94 C5 + 02 08 00 00 00 5B 22 00 4C 2D 00 + 41 3C 00 38 4F 00 32 69 00 32 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 0C + 0D 0E 0F 10 11 14 15 16 17 FF FF + 00 00 00 00 00 00 00 00 00 00 00 + 02 04 06 07 08 0A 0C 0D 0F 10 11 + 12 13 19 1B 1C 1E 1F 20 21 22 23 + 24 25 26 27 28 29 FF FF FF 00 00 + 00 00 00 00 00 00 00 00 6B 01 + ]; + + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-10-800-1280-v3.dtsi b/rk3326/rp-lcd-mipi-10-800-1280-v3.dtsi new file mode 100755 index 0000000..72da952 --- /dev/null +++ b/rk3326/rp-lcd-mipi-10-800-1280-v3.dtsi @@ -0,0 +1,227 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "90"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 78 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi b/rk3326/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi new file mode 100755 index 0000000..55e746d --- /dev/null +++ b/rk3326/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi @@ -0,0 +1,268 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + //MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <45>; + hfront-porch = <45>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 4D D0 02 00 05 05 35 00 01 08 32 + 08 5A 3C 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 29 0A 55 57 B5 + 06 00 00 00 41 22 10 00 01 00 0F + 00 2A 00 00 19 50 32 3C 78 94 D5 + 02 08 00 00 04 A2 40 00 8F 4A 00 + 80 55 00 73 61 00 67 70 00 67 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 + 06 08 0A 0F 10 12 FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF 8D 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-5.5-1080-1920.dtsi b/rk3326/rp-lcd-mipi-5.5-1080-1920.dtsi new file mode 100755 index 0000000..5dcad4b --- /dev/null +++ b/rk3326/rp-lcd-mipi-5.5-1080-1920.dtsi @@ -0,0 +1,242 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <60>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 15 00 02 FE 00 + 15 00 02 C2 08 + 15 00 02 35 00 + 15 00 02 53 20 + 15 00 02 51 FF + + 05 78 01 01 //add for reboot init fail + + 05 78 01 29 + 05 78 01 11 + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <138000000>; + hactive = <1080>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <36>; + vback-porch = <6>; + vfront-porch = <6>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1080>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ + 47 38 04 80 07 0A 05 00 + 01 08 28 05 50 32 03 05 + 00 00 00 00 00 00 00 00 + 00 00 00 8B 2B 0D 17 15 + 31 0D 00 00 00 9A 03 2D + 00 00 00 00 00 03 64 32 + 00 00 00 0F 2C 94 C5 02 + 07 00 00 04 9E 10 00 82 + 14 00 6B 19 00 57 20 00 + 4A 27 00 4A 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 FF 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 0F 10 12 + 13 26 24 22 21 20 1F 1E + 1D 1C 18 16 FF FF FF FF + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 8C 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-5.5-720-1280-v2.dtsi b/rk3326/rp-lcd-mipi-5.5-720-1280-v2.dtsi new file mode 100755 index 0000000..7b7a784 --- /dev/null +++ b/rk3326/rp-lcd-mipi-5.5-720-1280-v2.dtsi @@ -0,0 +1,215 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <60>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + 39 00 05 B8 26 22 20 03 + 39 00 04 BF 02 11 00 + 39 00 0B B3 0C 10 0A 50 03 FF 00 00 00 00 + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + 39 00 02 BC 46 + 39 00 02 CC 0B + 39 00 02 B4 80 + 39 00 04 B2 C8 12 30 + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 00 C0 10 + 39 00 0D C1 53 00 1E 1E 77 C1 FF FF AF AF 7F 7F + 39 00 03 B5 07 07 + 39 00 03 B6 70 70 + 39 00 07 C6 00 00 FF FF 01 FF + 39 00 40 E9 C2 10 05 04 FE 02 81 12 31 45 3F 83 12 91 3B 2A 08 05 00 00 00 00 08 05 00 00 00 00 FF 02 46 02 48 68 88 88 88 80 88 FF 13 57 13 58 78 88 88 88 81 88 00 00 00 00 00 12 B1 3B 00 00 00 00 00 + 39 00 3E EA 00 1A 00 00 00 00 00 00 00 00 00 00 FF 31 75 31 18 78 88 88 88 85 88 FF 20 64 20 08 68 88 88 88 84 88 20 10 00 00 54 00 00 00 00 00 00 00 C0 00 00 0C 00 00 00 00 30 02 A1 00 00 00 00 + 39 00 23 E0 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A + 05 ff 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <42>; + hfront-porch = <44>; + vback-porch = <10>; + vfront-porch = <14>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt1x"; + reg = <0x5d>; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-7-1024-600.dtsi b/rk3326/rp-lcd-mipi-7-1024-600.dtsi new file mode 100755 index 0000000..13d354f --- /dev/null +++ b/rk3326/rp-lcd-mipi-7-1024-600.dtsi @@ -0,0 +1,252 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ //old touch + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + + goodix,cfg-group5 = [ //new touch + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-7-1200-1920.dtsi b/rk3326/rp-lcd-mipi-7-1200-1920.dtsi new file mode 100755 index 0000000..765f395 --- /dev/null +++ b/rk3326/rp-lcd-mipi-7-1200-1920.dtsi @@ -0,0 +1,306 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 14 42 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 de 03 00 + 39 60 03 c9 02 23 + + 39 00 02 b0 00 + 39 00 06 14 08 b0 00 22 00 + 39 30 02 b4 0c + 39 40 03 b6 3a d3 + 39 50 02 51 e6 + 39 30 02 53 2c + + 05 78 01 29 + 05 78 01 11 + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 8c 83 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 c9 02 23 + 39 60 03 ca 01 23 + 39 10 03 cb 10 05 + 39 10 03 cc 05 10 + 39 10 03 d0 00 00 + + + 39 10 03 b6 03 00 + 39 10 03 de 03 00 + 39 10 03 d6 05 00 + 39 60 03 b7 4b 02 + + 05 00 01 2c + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ //sensor id 0 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + + + goodix,cfg-group2 = [ //sensor id 2 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + + goodix,cfg-group5 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-7-720-1280.dtsi b/rk3326/rp-lcd-mipi-7-720-1280.dtsi new file mode 100755 index 0000000..577dc5f --- /dev/null +++ b/rk3326/rp-lcd-mipi-7-720-1280.dtsi @@ -0,0 +1,485 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 39 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 75 03 + + 39 00 02 E0 01 + //39 00 02 4A 30 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 0A 07 + 39 00 02 0C 74 + 39 00 02 17 00 + 39 00 02 18 D7 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B D7 + 39 00 02 1C 01 + 39 00 02 1F 74 + 39 00 02 20 19 + 39 00 02 21 19 + 39 00 02 22 0E + 39 00 02 27 43 + + 39 00 02 37 09 + 39 00 02 38 04 + 39 00 02 39 08 + 39 00 02 3A 18 + 39 00 02 3B 18 + 39 00 02 3C 72 + 39 00 02 3E FF + 39 00 02 3E FF + 39 00 02 3F FF + 39 00 02 40 04 + 39 00 02 41 A0 + 39 00 02 43 08 + 39 00 02 44 07 + 39 00 02 45 30 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 65 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 0F + + 39 00 02 5D 7C + 39 00 02 5E 5F + 39 00 02 5F 4D + 39 00 02 60 3F + 39 00 02 61 39 + 39 00 02 62 29 + 39 00 02 63 2B + 39 00 02 64 12 + 39 00 02 65 28 + 39 00 02 66 24 + 39 00 02 67 22 + 39 00 02 68 3E + 39 00 02 69 2C + 39 00 02 6A 33 + 39 00 02 6B 26 + 39 00 02 6C 23 + 39 00 02 6D 18 + 39 00 02 6E 09 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 5F + 39 00 02 72 4D + 39 00 02 73 3F + 39 00 02 74 39 + 39 00 02 75 29 + 39 00 02 76 2B + 39 00 02 77 12 + 39 00 02 78 28 + 39 00 02 79 24 + 39 00 02 7A 22 + 39 00 02 7B 3E + 39 00 02 7C 2C + 39 00 02 7D 33 + 39 00 02 7E 26 + 39 00 02 7F 23 + 39 00 02 80 18 + 39 00 02 81 09 + 39 00 02 82 00 + + 39 00 02 E0 02 + 39 00 02 00 37 + 39 00 02 01 17 + 39 00 02 02 0A + 39 00 02 03 06 + 39 00 02 04 08 + 39 00 02 05 04 + 39 00 02 06 00 + 39 00 02 07 1F + 39 00 02 08 1F + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 1F + 39 00 02 10 3F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1E + 39 00 02 14 10 + 39 00 02 15 1F + + 39 00 02 16 37 + 39 00 02 17 17 + 39 00 02 18 0B + 39 00 02 19 07 + 39 00 02 1A 09 + 39 00 02 1B 05 + 39 00 02 1C 01 + 39 00 02 1D 1F + 39 00 02 1E 1F + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 1F + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1E + 39 00 02 2A 11 + 39 00 02 2B 1F + 39 00 02 2C 37 + 39 00 02 2D 17 + 39 00 02 2E 05 + 39 00 02 2F 09 + 39 00 02 30 07 + 39 00 02 31 0B + 39 00 02 32 11 + 39 00 02 33 1F + 39 00 02 34 1F + 39 00 02 35 1F + 39 00 02 36 1F + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 3F + 39 00 02 3D 1F + 39 00 02 3E 1E + 39 00 02 3F 1F + 39 00 02 40 01 + + 39 00 02 41 1F + 39 00 02 42 38 + 39 00 02 43 18 + 39 00 02 44 04 + 39 00 02 45 08 + 39 00 02 46 06 + 39 00 02 47 0A + 39 00 02 48 10 + 39 00 02 49 1F + 39 00 02 4A 1F + 39 00 02 4B 1F + 39 00 02 4C 1F + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1E + 39 00 02 55 1F + 39 00 02 56 00 + 39 00 02 57 1F + 39 00 02 58 10 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 10 + 39 00 02 5C 01 + 39 00 02 5D 50 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 30 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 06 + 39 00 02 64 6A + 39 00 02 65 55 + 39 00 02 66 08 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 08 + 39 00 02 6A 6E + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 80 + 39 00 02 76 00 + 39 00 02 77 0D + 39 00 02 78 18 + 39 00 02 79 00 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 04 + 39 00 02 04 01 + 39 00 02 0E 38 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E6 02 + //39 00 02 36 00 + 39 C8 02 11 00 + 39 C8 02 29 00 + + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <65000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <34>; + hfront-porch = <34>; + vback-porch = <6>; + vfront-porch = <20>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ + 57 58 02 00 04 05 35 00 01 08 32 0F + 5A 32 03 05 00 00 00 00 02 00 00 18 + 1A 1E 14 8A 2A 0C 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 2B FF 7F + 19 46 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 40 30 FF + FF 27 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 24 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0F 10 12 13 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 81 01 + ]; + + goodix,cfg-group2 = [ + 5A 58 02 00 04 05 35 00 01 08 + 32 0F 5A 32 03 05 00 00 00 00 + 02 00 00 18 1A 1E 14 8A 2A 0C + 55 57 B5 06 00 00 00 20 33 1C + 14 01 00 0F 00 2B FF 7F 19 46 + 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 + 61 00 6F 70 00 6F 00 00 00 00 + F0 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 08 0A 0F 10 + 12 13 24 22 21 20 1F 1E 1D 1C + 18 16 FF FF FF FF FF FF 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 5E 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-8-1200-1920.dtsi b/rk3326/rp-lcd-mipi-8-1200-1920.dtsi new file mode 100755 index 0000000..0d7f0bf --- /dev/null +++ b/rk3326/rp-lcd-mipi-8-1200-1920.dtsi @@ -0,0 +1,247 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "90"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ + 5E B0 04 80 07 05 05 00 01 0F 28 05 + 50 32 03 05 00 00 00 00 00 00 00 00 + 00 00 00 8C 2C 0E 52 54 31 0D 00 00 + 01 80 04 1C 00 00 00 00 00 03 64 32 + 00 00 00 52 66 94 C5 02 07 00 00 04 + 83 53 00 82 57 00 80 5B 00 7F 5F 00 + 7E 63 00 7E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 08 0A 0C 0F 10 12 13 14 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 22 01 + ]; + + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-mipi-8-800-1280-v3.dtsi b/rk3326/rp-lcd-mipi-8-800-1280-v3.dtsi new file mode 100755 index 0000000..9b88ddb --- /dev/null +++ b/rk3326/rp-lcd-mipi-8-800-1280-v3.dtsi @@ -0,0 +1,471 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "90"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + + prepare-delay-ms = <60>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + power-supply = <&vcc18_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 57 //54 + 39 00 02 04 D3 //D4 + 39 00 02 05 00 + 39 00 02 06 11 + 39 00 02 07 08 //09 + 39 00 02 08 00 + 39 00 02 09 00 + 39 00 02 0a 3F //00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F //00 + 39 00 02 10 3F //00 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 78 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 //GCH/L + 39 00 02 44 00 + + + 39 00 02 50 00 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + 39 00 02 5e 00 + 39 00 02 5f 0D //FW_CGOUT_L[1] + 39 00 02 60 0D //FW_CGOUT_L[2] + 39 00 02 61 0C //FW_CGOUT_L[3] + 39 00 02 62 0C //FW_CGOUT_L[4] + 39 00 02 63 0F //FW_CGOUT_L[5] + 39 00 02 64 0F //FW_CGOUT_L[6] + 39 00 02 65 0E //FW_CGOUT_L[7] + 39 00 02 66 0E //FW_CGOUT_L[8] + 39 00 02 67 08 //FW_CGOUT_L[9] + 39 00 02 68 02 //FW_CGOUT_L[10] + 39 00 02 69 02 //FW_CGOUT_L[11] + 39 00 02 6a 02 //FW_CGOUT_L[12] + 39 00 02 6b 02 //FW_CGOUT_L[13] + 39 00 02 6c 02 //FW_CGOUT_L[14] + 39 00 02 6d 02 //FW_CGOUT_L[15] + 39 00 02 6e 02 //FW_CGOUT_L[16] + 39 00 02 6f 02 //FW_CGOUT_L[17] + 39 00 02 70 14 //FW_CGOUT_L[18] + 39 00 02 71 15 //FW_CGOUT_L[19] + 39 00 02 72 06 //FW_CGOUT_L[20] + 39 00 02 73 02 //FW_CGOUT_L[21] + 39 00 02 74 02 //FW_CGOUT_L[22] + + 39 00 02 75 0D //BW_CGOUT_L[1] + 39 00 02 76 0D //BW_CGOUT_L[2] + 39 00 02 77 0C //BW_CGOUT_L[3] + 39 00 02 78 0C //BW_CGOUT_L[4] + 39 00 02 79 0F //BW_CGOUT_L[5] + 39 00 02 7a 0F //BW_CGOUT_L[6] + 39 00 02 7b 0E //BW_CGOUT_L[7] + 39 00 02 7c 0E //BW_CGOUT_L[8] + 39 00 02 7d 08 //BW_CGOUT_L[9] + 39 00 02 7e 02 //BW_CGOUT_L[10] + 39 00 02 7f 02 //BW_CGOUT_L[11] + 39 00 02 80 02 //BW_CGOUT_L[12] + 39 00 02 81 02 //BW_CGOUT_L[13] + 39 00 02 82 02 //BW_CGOUT_L[14] + 39 00 02 83 02 //BW_CGOUT_L[15] + 39 00 02 84 02 //BW_CGOUT_L[16] + 39 00 02 85 02 //BW_CGOUT_L[17] + 39 00 02 86 14 //BW_CGOUT_L[18] + 39 00 02 87 15 //BW_CGOUT_L[19] + 39 00 02 88 06 //BW_CGOUT_L[20] + 39 00 02 89 02 //BW_CGOUT_L[21] + 39 00 02 8A 02 //BW_CGOUT_L[22] + + + + 39 00 04 FF 98 81 04 + + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 87 + 39 00 02 55 84 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 10 + 39 00 02 62 00 + + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 1F + 39 00 02 A3 12 + 39 00 02 A4 16 + 39 00 02 A5 29 + 39 00 02 A6 1E + 39 00 02 A7 1F + 39 00 02 A8 7E + 39 00 02 A9 1B + 39 00 02 AA 28 + 39 00 02 AB 6D + 39 00 02 AC 19 + 39 00 02 AD 18 + 39 00 02 AE 4C + 39 00 02 AF 1E + 39 00 02 B0 23 + 39 00 02 B1 52 + 39 00 02 B2 6D + 39 00 02 B3 3F + + 39 00 02 C0 00 + 39 00 02 C1 12 + 39 00 02 C2 20 + 39 00 02 C3 10 + 39 00 02 C4 13 + 39 00 02 C5 27 + 39 00 02 C6 1B + 39 00 02 C7 1D + 39 00 02 C8 75 + 39 00 02 C9 1F + 39 00 02 CA 28 + 39 00 02 CB 68 + 39 00 02 CC 1A + 39 00 02 CD 18 + 39 00 02 CE 4D + 39 00 02 CF 25 + 39 00 02 D0 2E + 39 00 02 D1 53 + 39 00 02 D2 60 + 39 00 02 D3 3F + + 39 00 04 FF 98 81 00 + 39 00 02 35 00 + 05 80 01 11 + 05 20 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <70>; + hfront-porch = <70>; + vback-porch = <22>; + vfront-porch = <16>; + hsync-len = <20>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + + +// TP +&i2c1 { + status = "okay"; + clock-frequency = <200000>; + + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + /** jc */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01 + ]; + }; +}; + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-lcd-rgb-7-1024-600.dtsi b/rk3326/rp-lcd-rgb-7-1024-600.dtsi new file mode 100755 index 0000000..0986406 --- /dev/null +++ b/rk3326/rp-lcd-rgb-7-1024-600.dtsi @@ -0,0 +1,306 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + + + panel { + status = "okay"; + compatible = "simple-panel"; + backlight = <&backlight>; + + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + //bus-format = ; + bus-format = ; + + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + power-supply = <&vcc18_lcd_n>; + //enable-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <137>; + hfront-porch = <183>; + vback-porch = <15>; + vfront-porch = <20>; + hsync-len = <24>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "RGB"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; +}; + +&rgb { + status = "okay"; + phys = <&video_phy>; + phy-names = "phy"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_m0_rgb_pins>; + pinctrl-1 = <&lcdc_m0_sleep_pins>; + + + + +}; + + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "okay"; + + +}; + +&video_phy { + status = "okay"; +}; + +&route_rgb { + connect = <&vopb_out_rgb>; + status = "okay"; +}; + +&dsi_in_vopb { + status = "disabled"; +}; + +&route_dsi { + status = "disabled"; +}; + +// TP +//&i2c1 { +// status = "okay"; +// clock-frequency = <200000>; +// +// gt9xx: goodix_ts@5d { +// /***** tp pin ******/ +// pinctrl-names = "default"; +// pinctrl-0 = <&goodix_irq>; +// goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +// goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; +// +// status = "okay"; +// compatible = "goodix,gt9xx"; +// reg = <0x5d>; +// gtp_resolution_x = <1024>; +// gtp_resolution_y = <600>; +// gtp_int_tarigger = <1>; +// gtp_change_x2y = <0>; +// gtp_overturn_x = <0>; +// gtp_overturn_y = <0>; +// gtp_send_cfg = <1>; +// gtp_touch_wakeup = <1>; +// +// /** +// * goodix_rst_gpio = <>; +// * goodix_irq_gpio = <>; +// * +// * touch panel interrupt and reset pin +// * please refer to ***-lcd-gpio.dtsi +// * that included in main dts. +// */ +// +// goodix,cfg-group0 = [ +// 46 00 04 58 02 0A 3D 00 01 08 +// 28 05 50 32 03 05 00 00 00 00 +// 00 00 00 18 1A 1E 14 8D 2D 88 +// 17 15 31 0D 00 00 01 9B 03 1D +// 00 00 00 00 00 00 00 00 00 00 +// 00 1E 5A 94 C5 02 08 00 00 00 +// 61 21 00 57 29 00 4E 34 00 48 +// 41 00 43 51 00 43 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 01 04 05 06 07 08 09 +// 0C 0D 0E 0F 10 11 14 15 FF FF +// FF FF 00 00 00 00 00 00 00 00 +// 00 00 00 02 04 06 07 08 0A 0C +// 0F 10 11 12 13 19 1B 1C 1E 1F +// 20 21 22 23 24 25 26 27 FF FF +// FF FF FF FF 00 00 00 00 00 00 +// 00 00 00 00 FD 01 +// ]; +// +// +// goodix,cfg-group1 = [ +// 46 00 04 58 02 0A 3D 00 01 08 +// 28 05 50 32 03 05 00 00 00 00 +// 00 00 00 18 1A 1E 14 8D 2D 88 +// 17 15 31 0D 00 00 01 9B 03 1D +// 00 00 00 00 00 00 00 00 00 00 +// 00 1E 5A 94 C5 02 08 00 00 00 +// 61 21 00 57 29 00 4E 34 00 48 +// 41 00 43 51 00 43 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 01 04 05 06 07 08 09 +// 0C 0D 0E 0F 10 11 14 15 FF FF +// FF FF 00 00 00 00 00 00 00 00 +// 00 00 00 02 04 06 07 08 0A 0C +// 0F 10 11 12 13 19 1B 1C 1E 1F +// 20 21 22 23 24 25 26 27 FF FF +// FF FF FF FF 00 00 00 00 00 00 +// 00 00 00 00 FD 01 +// ]; +// +// goodix,cfg-group3 = [ +// 46 00 04 58 02 0A 3D 00 01 08 +// 28 05 50 32 03 05 00 00 00 00 +// 00 00 00 18 1A 1E 14 8D 2D 88 +// 17 15 31 0D 00 00 01 9B 03 1D +// 00 00 00 00 00 00 00 00 00 00 +// 00 1E 5A 94 C5 02 08 00 00 00 +// 61 21 00 57 29 00 4E 34 00 48 +// 41 00 43 51 00 43 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 01 04 05 06 07 08 09 +// 0C 0D 0E 0F 10 11 14 15 FF FF +// FF FF 00 00 00 00 00 00 00 00 +// 00 00 00 02 04 06 07 08 0A 0C +// 0F 10 11 12 13 19 1B 1C 1E 1F +// 20 21 22 23 24 25 26 27 FF FF +// FF FF FF FF 00 00 00 00 00 00 +// 00 00 00 00 FD 01 +// ]; +// }; +//}; +// +// +//&pinctrl { +// goodix { +// goodix_irq: goodix-irq { +// rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +// }; +// }; +//}; + diff --git a/rk3326/rp-mipi-camera-rk3326.dtsi b/rk3326/rp-mipi-camera-rk3326.dtsi new file mode 100755 index 0000000..15f2e33 --- /dev/null +++ b/rk3326/rp-mipi-camera-rk3326.dtsi @@ -0,0 +1,153 @@ +#include "../../../../../../drivers/soc/rockchip/rk_camera_sensor_info.h" + +/{ + cif_sensor: cif_sensor { + compatible = "rockchip,sensor"; + status = "okay"; + + ov5640_a { + status = "okay"; + is_front = <0>; + powerdown-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pwdn_active = ; + pwr_active = ; + rockchip,power_pmu_name1 = "vcc2v8_dvp"; + rockchip,power_pmu_voltage1 = <2800000>; + rockchip,power_pmu_name2 = "vcc1v8_dvp"; + rockchip,power_pmu_voltage2 = <1800000>; + mir = <0>; + flash_attach = <0>; + resolution = ; + powerup_sequence = ; + orientation = <0>; + i2c_add = ; + i2c_chl = <2>; + cif_chl = <0>; + mclk_rate = <24>; + }; + /* + gc2145_b { + is_front = <0>; + powerdown-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pwdn_active = ; + pwr_active = ; + rockchip,power_pmu_name1 = "vcc2v8_dvp"; + rockchip,power_pmu_voltage1 = <2800000>; + rockchip,power_pmu_name2 = "vcc1v8_dvp"; + rockchip,power_pmu_voltage2 = <1800000>; + mir = <0>; + flash_attach = <0>; + resolution = ; + powerup_sequence = ; + orientation = <90>; + i2c_add = ; + i2c_chl = <2>; + cif_chl = <0>; + mclk_rate = <24>; + }; + + gc0312_f { + is_front = <1>; + powerdown-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn_active = ; + pwr_active = ; + rockchip,power_pmu_name1 = "vcc2v8_dvp"; + rockchip,power_pmu_voltage1 = <2800000>; + rockchip,power_pmu_name2 = "vcc1v8_dvp"; + rockchip,power_pmu_voltage2 = <1800000>; + mir = <0>; + flash_attach = <0>; + resolution = ; + powerup_sequence = ; + orientation = <270>; + i2c_add = ; + i2c_chl = <2>; + cif_chl = <0>; + mclk_rate = <24>; + }; + */ + }; +}; + +&isp_mmu { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov13850_a: ov13850_a@10 { + status = "okay"; + compatible = "ovti,ov13850"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + port { + ov13850_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13850_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; diff --git a/rk3326/rp-rk3326s-board.dtsi b/rk3326/rp-rk3326s-board.dtsi new file mode 100755 index 0000000..421045f --- /dev/null +++ b/rk3326/rp-rk3326s-board.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +/ { + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc18_lcd_n: vcc18-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc18_lcd_n"; + regulator-boot-on; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS0"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "true"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; + }; + +}; + +&bus_apll { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-sdio; + no-mmc; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_pin>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + diff --git a/rk3326/rp-rk3326s.dts b/rk3326/rp-rk3326s.dts new file mode 100755 index 0000000..29586ba --- /dev/null +++ b/rk3326/rp-rk3326s.dts @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "../rk3326.dtsi" +#include "../rk3326-linux.dtsi" +#include "rk3326-evb-rpdzkj-rk817.dtsi" +#include "rp-rk3326s-board.dtsi" + +/* audio */ +#include "rp-audio-rk817.dtsi" + +/* usb */ +#include "rp-usb-rk3326.dtsi" + +/* adc key */ +#include "rp-adc-key.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6256-rk3326.dtsi" + +/* mipi camera */ +#include "rp-mipi-camera-rk3326.dtsi" + + +/***************** SINGLE LCD ****************/ +/* MIPI DSI */ +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5.5-1080-1920.dtsi" +#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-720-1280.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-8-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-10-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-1920-1200.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-7-1024-600.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/* RGB */ +//#include "rp-lcd-rgb-7-1024-600.dtsi" + +/ { + model = "rp-rk3326s"; + compatible = "rpdzkj,rp-rk3326s-v10", "rockchip,rk3326"; + + vdd_3v3_5v_control: vdd_3v3_5v_control { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_5v_control"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; //In the uboot phase fixed.c resolves gpio + gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_control>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "okay"; + }; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&led_set>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + led { //system led + gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb_otg_switch { + gpio_num = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_channel_switch { + gpio_num = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_pwr { + gpio_num = <&nca9555_gpio IO_03 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd_4g { + gpio_num = <&nca9555_gpio IO_01 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + + spk_en { //spk enable + gpio_num = <&nca9555_gpio IO_04 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vcc_1v2_camera { + gpio_num = <&nca9555_gpio IO_02 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio1b7 { + gpio_num = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_05 { + gpio_num = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_06 { + gpio_num = <&nca9555_gpio IO_06 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_07 { + gpio_num = <&nca9555_gpio IO_07 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_10 { + gpio_num = <&nca9555_gpio IO_10 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_11 { + gpio_num = <&nca9555_gpio IO_11 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_12 { + gpio_num = <&nca9555_gpio IO_12 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_13 { + gpio_num = <&nca9555_gpio IO_13 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_14 { + gpio_num = <&nca9555_gpio IO_14 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_15 { + gpio_num = <&nca9555_gpio IO_15 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_16 { + gpio_num = <&nca9555_gpio IO_16 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_17 { + gpio_num = <&nca9555_gpio IO_17 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; +}; + +&i2c0 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + +&i2c1 { + status = "okay"; + + nca9555: mfd-gpio@20 { + compatible = "nca9555"; + reg = <0x20>; + status = "okay"; + + nca9555_gpio: gpio-normal@20 { + compatible = "nca9555-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + status = "okay"; +}; + +&pinctrl { + rp_power_set { + led_set: led-set{ + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + power_control{ + vdd_control: vdd_control { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3326/rp-usb-rk3326.dtsi b/rk3326/rp-usb-rk3326.dtsi new file mode 100755 index 0000000..edfd98d --- /dev/null +++ b/rk3326/rp-usb-rk3326.dtsi @@ -0,0 +1,15 @@ +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; diff --git a/rk3326/rp-wifi-bt-ap6256-rk3326.dtsi b/rk3326/rp-wifi-bt-ap6256-rk3326.dtsi new file mode 100755 index 0000000..e22e8a0 --- /dev/null +++ b/rk3326/rp-wifi-bt-ap6256-rk3326.dtsi @@ -0,0 +1,84 @@ + +/{ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <100>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6256"; + WIFI,host_wake_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + // WIFI,poweren_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + // pinctrl-1 = <&uart1_rts_gpio>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&nca9555_gpio IO_00 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + +}; + + +&sdio { + supports-sdio; + bus-width = <4>; + cap-sd-highspeed; + no-sd; + no-mmc; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3328-a1.dts b/rk3328-a1.dts new file mode 100644 index 0000000..37f307c --- /dev/null +++ b/rk3328-a1.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (c) 2017-2019 Arm Ltd. + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Beelink A1"; + compatible = "azw,beelink-a1", "rockchip,rk3328"; + + /* + * UART pins, as viewed with bottom of case removed: + * + * Front + * /------- + * L / o <- Gnd + * e / o <-- Rx + * f / o <--- Tx + * t / o <---- +3.3v + * | + */ + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_host_5v: usb3-current-switch { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-beelink-gs1"; + }; +}; + +&analog_sound { + simple-audio-card,name = "Analog A/V"; + status = "okay"; +}; + +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-handle = <&rtl8211f>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,aal; + snps,pbl = <0x4>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211f: ethernet-phy@0 { + reg = <0>; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_logic>; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <1000000>; + i2c-scl-falling-time-ns = <5>; + i2c-scl-rising-time-ns = <83>; + status = "okay"; + + pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_11: LDO_REG3 { + regulator-name = "vdd_11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s1 { + status = "okay"; +}; + +&io_domains { + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vdd_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vdd_18>; + pmuio-supply = <&vcc_io>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + bt_dis: bt-dis { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + bt_wake_host: bt-wake-host { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + chip_en: chip-en { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_output_low>; + }; + + host_wake_bt: host-wake-bt { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wl_dis: wl-dis { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + wl_wake_host: wl-wake-host { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_io>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + pinctrl-names = "default"; + pinctrl-0 = <&bt_dis &bt_wake_host &chip_en &host_wake_bt &wl_dis &wl_wake_host>; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328-android.dtsi b/rk3328-android.dtsi new file mode 100644 index 0000000..73327ed --- /dev/null +++ b/rk3328-android.dtsi @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff130000 kpti=0 coherent_pool=1m"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <159>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <0>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "okay"; + }; + + firmware { + firmware_android: android {}; + + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + + secure_memory: secure-memory@20000000 { + compatible = "rockchip,secure-memory"; + reg = <0x0 0x20000000 0x0 0x0>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; +}; + +&display_subsystem { + logo-memory-region = <&drm_logo>; + status = "okay"; + secure-memory-region = <&secure_memory>; + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "fullscreen"; + connect = <&vop_out_hdmi>; + }; + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "fullscreen"; + connect = <&vop_out_tve>; + }; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/rk3328-box-liantong-avb.dts b/rk3328-box-liantong-avb.dts new file mode 100644 index 0000000..ee04d89 --- /dev/null +++ b/rk3328-box-liantong-avb.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3328-box-liantong.dtsi" + +/ { + model = "Rockchip RK3328 box liantong avb"; + compatible = "rockchip,rk3328-box-liantong-avb", "rockchip,rk3328"; +}; diff --git a/rk3328-box-liantong.dts b/rk3328-box-liantong.dts new file mode 100644 index 0000000..dcff872 --- /dev/null +++ b/rk3328-box-liantong.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "rk3328-box-liantong.dtsi" + +/ { + model = "Rockchip RK3328 box liantong"; + compatible = "rockchip,rk3328-box-liantong", "rockchip,rk3328"; +}; + +&firmware_android{ + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/platform/ff520000.dwmmc/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/ff520000.dwmmc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3328-box-liantong.dtsi b/rk3328-box-liantong.dtsi new file mode 100644 index 0000000..e64cf04 --- /dev/null +++ b/rk3328-box-liantong.dtsi @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +#include "rk3328.dtsi" +#include "rk3328-android.dtsi" +#include "rk3328-box-plus-dram-timing.dtsi" +#include + +/ { + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-rk3328"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vccio_1v8_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vccio_3v3_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + rtc-fake { + compatible = "rtc-fake"; + status = "okay"; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip-spdif"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc_host_vbus: host-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vccio_3v3_reg>; + }; + + vdd_arm: vdd-center { + compatible = "pwm-regulator"; + rockchip,pwm_id = <0>; + rockchip,pwm_voltage = <1250000>; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vcc_arm"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_logic: vdd-log { + compatible = "pwm-regulator"; + rockchip,pwm_id = <1>; + rockchip,pwm_voltage = <1100000>; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vcc_log"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + regulator-settling-time-up-us = <250>; + regulator-always-on; + regulator-boot-on; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + BT,power_gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8822bs"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio1 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&avsd { + status = "okay"; +}; + +&codec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 786000 + SYS_STATUS_REBOOT 786000 + SYS_STATUS_SUSPEND 786000 + SYS_STATUS_VIDEO_1080P 786000 + SYS_STATUS_VIDEO_4K 786000 + SYS_STATUS_VIDEO_4K_10B 786000 + SYS_STATUS_PERFORMANCE 786000 + SYS_STATUS_BOOST 786000 + >; +}; + +&dmc_opp_table { + opp-800000000 { + status = "disabled"; + }; + + opp-850000000 { + status = "disabled"; + }; + + opp-933000000 { + status = "disabled"; + }; + + opp-1066000000 { + status = "disabled"; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "disabled"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_logic>; +}; + +&hdmi { + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&hdmiphy { + rockchip,phy-table = + <165000000 0x07 0x0a 0x0a 0x0a 0x00 0x00 0x08 + 0x08 0x08 0x00 0xac 0xcc 0xcc 0xcc>, + <340000000 0x0b 0x0d 0x0d 0x0d 0x07 0x15 0x08 + 0x08 0x08 0x3f 0xac 0xcc 0xcd 0xdd>, + <594000000 0x10 0x1a 0x1a 0x1a 0x07 0x15 0x08 + 0x08 0x08 0x00 0xac 0xcc 0xcc 0xcc>; + status = "okay"; +}; + +&secure_memory { + /* + * enable like this: + * reg = <0x0 0x20000000 0x0 0x10000000>; + */ + reg = <0x0 0x20000000 0x0 0x0>; +}; + +&i2s0 { + #sound-dai-cells = <0>; + rockchip,bclk-fs = <128>; + status = "okay"; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vccio_3v3_reg>; + vccio2-supply = <&vccio_1v8_reg>; + vccio3-supply = <&vccio_3v3_reg>; + vccio4-supply = <&vccio_1v8_reg>; + vccio5-supply = <&vccio_3v3_reg>; + vccio6-supply = <&vccio_3v3_reg>; + pmuio-supply = <&vccio_3v3_reg>; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin_pull_up>; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin_pull_up>; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; + vcodec-supply = <&vdd_logic>; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + |RKPM_SLP_CTR_VOL_PWM0 + |RKPM_SLP_CTR_VOL_PWM1 + ) + >; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <125000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + no-sd; + no-mmc; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc_ext { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + keep-power-in-suspend; + max-frequency = <150000000>; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0ext_clk &sdmmc0ext_cmd &sdmmc0ext_dectn &sdmmc0ext_bus4>; + no-sdio; + no-mmc; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + no-sdio; + no-mmc; + status = "okay"; + vmmc-supply = <&vcc_sd>; +}; + +&spdif { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; +}; + +&threshold { + temperature = <90000>; /* millicelsius */ +}; + +&target { + temperature = <105000>; /* millicelsius */ +}; + +&soc_crit { + temperature = <115000>; /* millicelsius */ +}; + +&tsadc { + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&tve { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + vbus-supply = <&vcc_otg_vbus>; + status = "okay"; + }; +}; + +&u3phy { + vbus-supply = <&vcc_host_vbus>; + status = "okay"; +}; + +&u3phy_utmi { + status = "okay"; +}; + +&u3phy_pipe { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vepu22 { + status = "okay"; +}; + +&vepu22_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328-box-plus-dram-timing.dtsi b/rk3328-box-plus-dram-timing.dtsi new file mode 100644 index 0000000..0ea2705 --- /dev/null +++ b/rk3328-box-plus-dram-timing.dtsi @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + */ +#include +#include + +&ddr_timing { + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <0>; + ddr3a0_ddr4a10_de-skew = <0>; + ddr3a3_ddr4a6_de-skew = <1>; + ddr3a2_ddr4a4_de-skew = <1>; + ddr3a5_ddr4a8_de-skew = <0>; + ddr3a4_ddr4a5_de-skew = <2>; + ddr3a7_ddr4a11_de-skew = <0>; + ddr3a6_ddr4a7_de-skew = <2>; + ddr3a9_ddr4a0_de-skew = <1>; + ddr3a8_ddr4a13_de-skew = <0>; + ddr3a11_ddr4a3_de-skew = <2>; + ddr3a10_ddr4cs0_de-skew = <0>; + ddr3a13_ddr4a2_de-skew = <1>; + ddr3a12_ddr4ba1_de-skew = <0>; + ddr3a15_ddr4odt0_de-skew = <0>; + ddr3a14_ddr4a1_de-skew = <1>; + ddr3ba1_ddr4a15_de-skew = <0>; + ddr3ba0_ddr4bg0_de-skew = <0>; + ddr3ras_ddr4cke_de-skew = <0>; + ddr3ba2_ddr4ba0_de-skew = <1>; + ddr3we_ddr4bg1_de-skew = <1>; + ddr3cas_ddr4a12_de-skew = <0>; + ddr3ckn_ddr4ckn_de-skew = <5>; + ddr3ckp_ddr4ckp_de-skew = <5>; + ddr3cke_ddr4a16_de-skew = <1>; + ddr3odt0_ddr4a14_de-skew = <0>; + ddr3cs0_ddr4act_de-skew = <1>; + ddr3reset_ddr4reset_de-skew = <0>; + ddr3cs1_ddr4cs1_de-skew = <0>; + ddr3odt1_ddr4odt1_de-skew = <0>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <8>; + cs0_dq0_rx_de-skew = <7>; + cs0_dq0_tx_de-skew = <8>; + cs0_dq1_rx_de-skew = <7>; + cs0_dq1_tx_de-skew = <8>; + cs0_dq2_rx_de-skew = <7>; + cs0_dq2_tx_de-skew = <8>; + cs0_dq3_rx_de-skew = <7>; + cs0_dq3_tx_de-skew = <8>; + cs0_dq4_rx_de-skew = <7>; + cs0_dq4_tx_de-skew = <8>; + cs0_dq5_rx_de-skew = <7>; + cs0_dq5_tx_de-skew = <8>; + cs0_dq6_rx_de-skew = <7>; + cs0_dq6_tx_de-skew = <8>; + cs0_dq7_rx_de-skew = <7>; + cs0_dq7_tx_de-skew = <8>; + cs0_dqs0_rx_de-skew = <6>; + cs0_dqs0p_tx_de-skew = <9>; + cs0_dqs0n_tx_de-skew = <9>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <7>; + cs0_dq8_rx_de-skew = <7>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <7>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_rx_de-skew = <7>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <7>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_rx_de-skew = <7>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <7>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_rx_de-skew = <7>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <7>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1_rx_de-skew = <7>; + cs0_dqs1p_tx_de-skew = <9>; + cs0_dqs1n_tx_de-skew = <9>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <8>; + cs0_dq16_rx_de-skew = <7>; + cs0_dq16_tx_de-skew = <8>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq17_tx_de-skew = <8>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq19_tx_de-skew = <8>; + cs0_dq20_rx_de-skew = <7>; + cs0_dq20_tx_de-skew = <8>; + cs0_dq21_rx_de-skew = <7>; + cs0_dq21_tx_de-skew = <8>; + cs0_dq22_rx_de-skew = <7>; + cs0_dq22_tx_de-skew = <8>; + cs0_dq23_rx_de-skew = <7>; + cs0_dq23_tx_de-skew = <8>; + cs0_dqs2_rx_de-skew = <6>; + cs0_dqs2p_tx_de-skew = <9>; + cs0_dqs2n_tx_de-skew = <9>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3_rx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <9>; + cs0_dqs3n_tx_de-skew = <9>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <8>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq0_tx_de-skew = <8>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq1_tx_de-skew = <8>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq2_tx_de-skew = <8>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq3_tx_de-skew = <8>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq4_tx_de-skew = <8>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq5_tx_de-skew = <8>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq6_tx_de-skew = <8>; + cs1_dq7_rx_de-skew = <7>; + cs1_dq7_tx_de-skew = <8>; + cs1_dqs0_rx_de-skew = <6>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1_rx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <8>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <8>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq19_tx_de-skew = <8>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq20_tx_de-skew = <8>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <8>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <7>; + cs1_dq23_tx_de-skew = <8>; + cs1_dqs2_rx_de-skew = <6>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3_rx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; +}; diff --git a/rk3328-dram-2layer-timing.dtsi b/rk3328-dram-2layer-timing.dtsi new file mode 100644 index 0000000..0841fac --- /dev/null +++ b/rk3328-dram-2layer-timing.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&ddr_timing { + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <2>; + ddr3a0_ddr4a10_de-skew = <4>; + ddr3a3_ddr4a6_de-skew = <6>; + ddr3a2_ddr4a4_de-skew = <5>; + ddr3a5_ddr4a8_de-skew = <7>; + ddr3a4_ddr4a5_de-skew = <7>; + ddr3a7_ddr4a11_de-skew = <7>; + ddr3a6_ddr4a7_de-skew = <7>; + ddr3a9_ddr4a0_de-skew = <7>; + ddr3a8_ddr4a13_de-skew = <4>; + ddr3a11_ddr4a3_de-skew = <4>; + ddr3a10_ddr4cs0_de-skew = <4>; + ddr3a13_ddr4a2_de-skew = <7>; + ddr3a12_ddr4ba1_de-skew = <5>; + ddr3a15_ddr4odt0_de-skew = <7>; + ddr3a14_ddr4a1_de-skew = <6>; + ddr3ba1_ddr4a15_de-skew = <3>; + ddr3ba0_ddr4bg0_de-skew = <9>; + ddr3ras_ddr4cke_de-skew = <6>; + ddr3ba2_ddr4ba0_de-skew = <8>; + ddr3we_ddr4bg1_de-skew = <4>; + ddr3cas_ddr4a12_de-skew = <4>; + ddr3ckn_ddr4ckn_de-skew = <14>; + ddr3ckp_ddr4ckp_de-skew = <14>; + ddr3cke_ddr4a16_de-skew = <5>; + ddr3odt0_ddr4a14_de-skew = <9>; + ddr3cs0_ddr4act_de-skew = <9>; + ddr3reset_ddr4reset_de-skew = <10>; + ddr3cs1_ddr4cs1_de-skew = <7>; + ddr3odt1_ddr4odt1_de-skew = <7>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <15>; + cs0_dm0_tx_de-skew = <14>; + cs0_dq0_rx_de-skew = <13>; + cs0_dq0_tx_de-skew = <13>; + cs0_dq1_rx_de-skew = <14>; + cs0_dq1_tx_de-skew = <14>; + cs0_dq2_rx_de-skew = <13>; + cs0_dq2_tx_de-skew = <13>; + cs0_dq3_rx_de-skew = <15>; + cs0_dq3_tx_de-skew = <14>; + cs0_dq4_rx_de-skew = <15>; + cs0_dq4_tx_de-skew = <14>; + cs0_dq5_rx_de-skew = <15>; + cs0_dq5_tx_de-skew = <14>; + cs0_dq6_rx_de-skew = <15>; + cs0_dq6_tx_de-skew = <14>; + cs0_dq7_rx_de-skew = <15>; + cs0_dq7_tx_de-skew = <14>; + cs0_dqs0_rx_de-skew = <13>; + cs0_dqs0p_tx_de-skew = <15>; + cs0_dqs0n_tx_de-skew = <15>; + + cs0_dm1_rx_de-skew = <11>; + cs0_dm1_tx_de-skew = <11>; + cs0_dq8_rx_de-skew = <12>; + cs0_dq8_tx_de-skew = <13>; + cs0_dq9_rx_de-skew = <13>; + cs0_dq9_tx_de-skew = <12>; + cs0_dq10_rx_de-skew = <12>; + cs0_dq10_tx_de-skew = <13>; + cs0_dq11_rx_de-skew = <15>; + cs0_dq11_tx_de-skew = <13>; + cs0_dq12_rx_de-skew = <9>; + cs0_dq12_tx_de-skew = <11>; + cs0_dq13_rx_de-skew = <12>; + cs0_dq13_tx_de-skew = <12>; + cs0_dq14_rx_de-skew = <9>; + cs0_dq14_tx_de-skew = <11>; + cs0_dq15_rx_de-skew = <13>; + cs0_dq15_tx_de-skew = <12>; + cs0_dqs1_rx_de-skew = <14>; + cs0_dqs1p_tx_de-skew = <14>; + cs0_dqs1n_tx_de-skew = <14>; + + cs0_dm2_rx_de-skew = <10>; + cs0_dm2_tx_de-skew = <12>; + cs0_dq16_rx_de-skew = <11>; + cs0_dq16_tx_de-skew = <12>; + cs0_dq17_rx_de-skew = <11>; + cs0_dq17_tx_de-skew = <12>; + cs0_dq18_rx_de-skew = <11>; + cs0_dq18_tx_de-skew = <12>; + cs0_dq19_rx_de-skew = <13>; + cs0_dq19_tx_de-skew = <13>; + cs0_dq20_rx_de-skew = <12>; + cs0_dq20_tx_de-skew = <13>; + cs0_dq21_rx_de-skew = <11>; + cs0_dq21_tx_de-skew = <12>; + cs0_dq22_rx_de-skew = <12>; + cs0_dq22_tx_de-skew = <12>; + cs0_dq23_rx_de-skew = <12>; + cs0_dq23_tx_de-skew = <12>; + cs0_dqs2_rx_de-skew = <11>; + cs0_dqs2p_tx_de-skew = <14>; + cs0_dqs2n_tx_de-skew = <14>; + + cs0_dm3_rx_de-skew = <10>; + cs0_dm3_tx_de-skew = <11>; + cs0_dq24_rx_de-skew = <9>; + cs0_dq24_tx_de-skew = <12>; + cs0_dq25_rx_de-skew = <10>; + cs0_dq25_tx_de-skew = <12>; + cs0_dq26_rx_de-skew = <13>; + cs0_dq26_tx_de-skew = <13>; + cs0_dq27_rx_de-skew = <14>; + cs0_dq27_tx_de-skew = <13>; + cs0_dq28_rx_de-skew = <8>; + cs0_dq28_tx_de-skew = <10>; + cs0_dq29_rx_de-skew = <10>; + cs0_dq29_tx_de-skew = <12>; + cs0_dq30_rx_de-skew = <14>; + cs0_dq30_tx_de-skew = <13>; + cs0_dq31_rx_de-skew = <15>; + cs0_dq31_tx_de-skew = <14>; + cs0_dqs3_rx_de-skew = <12>; + cs0_dqs3p_tx_de-skew = <15>; + cs0_dqs3n_tx_de-skew = <15>; + + cs1_dm0_rx_de-skew = <11>; + cs1_dm0_tx_de-skew = <10>; + cs1_dq0_rx_de-skew = <9>; + cs1_dq0_tx_de-skew = <9>; + cs1_dq1_rx_de-skew = <10>; + cs1_dq1_tx_de-skew = <10>; + cs1_dq2_rx_de-skew = <9>; + cs1_dq2_tx_de-skew = <9>; + cs1_dq3_rx_de-skew = <11>; + cs1_dq3_tx_de-skew = <10>; + cs1_dq4_rx_de-skew = <11>; + cs1_dq4_tx_de-skew = <10>; + cs1_dq5_rx_de-skew = <11>; + cs1_dq5_tx_de-skew = <10>; + cs1_dq6_rx_de-skew = <11>; + cs1_dq6_tx_de-skew = <10>; + cs1_dq7_rx_de-skew = <11>; + cs1_dq7_tx_de-skew = <10>; + cs1_dqs0_rx_de-skew = <9>; + cs1_dqs0p_tx_de-skew = <10>; + cs1_dqs0n_tx_de-skew = <10>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <8>; + cs1_dq8_tx_de-skew = <9>; + cs1_dq9_rx_de-skew = <9>; + cs1_dq9_tx_de-skew = <8>; + cs1_dq10_rx_de-skew = <8>; + cs1_dq10_tx_de-skew = <9>; + cs1_dq11_rx_de-skew = <11>; + cs1_dq11_tx_de-skew = <9>; + cs1_dq12_rx_de-skew = <5>; + cs1_dq12_tx_de-skew = <7>; + cs1_dq13_rx_de-skew = <8>; + cs1_dq13_tx_de-skew = <8>; + cs1_dq14_rx_de-skew = <5>; + cs1_dq14_tx_de-skew = <7>; + cs1_dq15_rx_de-skew = <9>; + cs1_dq15_tx_de-skew = <8>; + cs1_dqs1_rx_de-skew = <9>; + cs1_dqs1p_tx_de-skew = <10>; + cs1_dqs1n_tx_de-skew = <10>; + + cs1_dm2_rx_de-skew = <6>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <8>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <8>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <9>; + cs1_dq19_tx_de-skew = <9>; + cs1_dq20_rx_de-skew = <8>; + cs1_dq20_tx_de-skew = <9>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <8>; + cs1_dq22_rx_de-skew = <8>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <8>; + cs1_dq23_tx_de-skew = <8>; + cs1_dqs2_rx_de-skew = <7>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <4>; + cs1_dm3_tx_de-skew = <5>; + cs1_dq24_rx_de-skew = <3>; + cs1_dq24_tx_de-skew = <6>; + cs1_dq25_rx_de-skew = <4>; + cs1_dq25_tx_de-skew = <6>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <8>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <2>; + cs1_dq28_tx_de-skew = <4>; + cs1_dq29_rx_de-skew = <4>; + cs1_dq29_tx_de-skew = <6>; + cs1_dq30_rx_de-skew = <8>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <9>; + cs1_dq31_tx_de-skew = <8>; + cs1_dqs3_rx_de-skew = <6>; + cs1_dqs3p_tx_de-skew = <8>; + cs1_dqs3n_tx_de-skew = <8>; +}; diff --git a/rk3328-dram-default-timing.dtsi b/rk3328-dram-default-timing.dtsi new file mode 100644 index 0000000..2ed2c4a --- /dev/null +++ b/rk3328-dram-default-timing.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = ; + ddr4_speed_bin = ; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + + auto_pd_dis_freq = <1066>; + auto_sr_dis_freq = <800>; + ddr3_dll_dis_freq = <300>; + ddr4_dll_dis_freq = <625>; + phy_dll_dis_freq = <400>; + + ddr3_odt_dis_freq = <100>; + phy_ddr3_odt_dis_freq = <100>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_ck_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <666>; + phy_lpddr3_odt_dis_freq = <666>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_ck_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + phy_lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + + ddr4_odt_dis_freq = <666>; + phy_ddr4_odt_dis_freq = <666>; + ddr4_drv = ; + ddr4_odt = ; + phy_ddr4_ca_drv = ; + phy_ddr4_ck_drv = ; + phy_ddr4_dq_drv = ; + phy_ddr4_odt = ; + + /* CA de-skew, one step is 47.8ps, range 0-15 */ + ddr3a1_ddr4a9_de-skew = <7>; + ddr3a0_ddr4a10_de-skew = <7>; + ddr3a3_ddr4a6_de-skew = <8>; + ddr3a2_ddr4a4_de-skew = <8>; + ddr3a5_ddr4a8_de-skew = <7>; + ddr3a4_ddr4a5_de-skew = <9>; + ddr3a7_ddr4a11_de-skew = <7>; + ddr3a6_ddr4a7_de-skew = <9>; + ddr3a9_ddr4a0_de-skew = <8>; + ddr3a8_ddr4a13_de-skew = <7>; + ddr3a11_ddr4a3_de-skew = <9>; + ddr3a10_ddr4cs0_de-skew = <7>; + ddr3a13_ddr4a2_de-skew = <8>; + ddr3a12_ddr4ba1_de-skew = <7>; + ddr3a15_ddr4odt0_de-skew = <7>; + ddr3a14_ddr4a1_de-skew = <8>; + ddr3ba1_ddr4a15_de-skew = <7>; + ddr3ba0_ddr4bg0_de-skew = <7>; + ddr3ras_ddr4cke_de-skew = <7>; + ddr3ba2_ddr4ba0_de-skew = <8>; + ddr3we_ddr4bg1_de-skew = <8>; + ddr3cas_ddr4a12_de-skew = <7>; + ddr3ckn_ddr4ckn_de-skew = <8>; + ddr3ckp_ddr4ckp_de-skew = <8>; + ddr3cke_ddr4a16_de-skew = <8>; + ddr3odt0_ddr4a14_de-skew = <7>; + ddr3cs0_ddr4act_de-skew = <8>; + ddr3reset_ddr4reset_de-skew = <7>; + ddr3cs1_ddr4cs1_de-skew = <7>; + ddr3odt1_ddr4odt1_de-skew = <7>; + + /* DATA de-skew + * RX one step is 25.1ps, range 0-15 + * TX one step is 47.8ps, range 0-15 + */ + cs0_dm0_rx_de-skew = <7>; + cs0_dm0_tx_de-skew = <8>; + cs0_dq0_rx_de-skew = <7>; + cs0_dq0_tx_de-skew = <8>; + cs0_dq1_rx_de-skew = <7>; + cs0_dq1_tx_de-skew = <8>; + cs0_dq2_rx_de-skew = <7>; + cs0_dq2_tx_de-skew = <8>; + cs0_dq3_rx_de-skew = <7>; + cs0_dq3_tx_de-skew = <8>; + cs0_dq4_rx_de-skew = <7>; + cs0_dq4_tx_de-skew = <8>; + cs0_dq5_rx_de-skew = <7>; + cs0_dq5_tx_de-skew = <8>; + cs0_dq6_rx_de-skew = <7>; + cs0_dq6_tx_de-skew = <8>; + cs0_dq7_rx_de-skew = <7>; + cs0_dq7_tx_de-skew = <8>; + cs0_dqs0_rx_de-skew = <6>; + cs0_dqs0p_tx_de-skew = <9>; + cs0_dqs0n_tx_de-skew = <9>; + + cs0_dm1_rx_de-skew = <7>; + cs0_dm1_tx_de-skew = <7>; + cs0_dq8_rx_de-skew = <7>; + cs0_dq8_tx_de-skew = <8>; + cs0_dq9_rx_de-skew = <7>; + cs0_dq9_tx_de-skew = <7>; + cs0_dq10_rx_de-skew = <7>; + cs0_dq10_tx_de-skew = <8>; + cs0_dq11_rx_de-skew = <7>; + cs0_dq11_tx_de-skew = <7>; + cs0_dq12_rx_de-skew = <7>; + cs0_dq12_tx_de-skew = <8>; + cs0_dq13_rx_de-skew = <7>; + cs0_dq13_tx_de-skew = <7>; + cs0_dq14_rx_de-skew = <7>; + cs0_dq14_tx_de-skew = <8>; + cs0_dq15_rx_de-skew = <7>; + cs0_dq15_tx_de-skew = <7>; + cs0_dqs1_rx_de-skew = <7>; + cs0_dqs1p_tx_de-skew = <9>; + cs0_dqs1n_tx_de-skew = <9>; + + cs0_dm2_rx_de-skew = <7>; + cs0_dm2_tx_de-skew = <8>; + cs0_dq16_rx_de-skew = <7>; + cs0_dq16_tx_de-skew = <8>; + cs0_dq17_rx_de-skew = <7>; + cs0_dq17_tx_de-skew = <8>; + cs0_dq18_rx_de-skew = <7>; + cs0_dq18_tx_de-skew = <8>; + cs0_dq19_rx_de-skew = <7>; + cs0_dq19_tx_de-skew = <8>; + cs0_dq20_rx_de-skew = <7>; + cs0_dq20_tx_de-skew = <8>; + cs0_dq21_rx_de-skew = <7>; + cs0_dq21_tx_de-skew = <8>; + cs0_dq22_rx_de-skew = <7>; + cs0_dq22_tx_de-skew = <8>; + cs0_dq23_rx_de-skew = <7>; + cs0_dq23_tx_de-skew = <8>; + cs0_dqs2_rx_de-skew = <6>; + cs0_dqs2p_tx_de-skew = <9>; + cs0_dqs2n_tx_de-skew = <9>; + + cs0_dm3_rx_de-skew = <7>; + cs0_dm3_tx_de-skew = <7>; + cs0_dq24_rx_de-skew = <7>; + cs0_dq24_tx_de-skew = <8>; + cs0_dq25_rx_de-skew = <7>; + cs0_dq25_tx_de-skew = <7>; + cs0_dq26_rx_de-skew = <7>; + cs0_dq26_tx_de-skew = <7>; + cs0_dq27_rx_de-skew = <7>; + cs0_dq27_tx_de-skew = <7>; + cs0_dq28_rx_de-skew = <7>; + cs0_dq28_tx_de-skew = <7>; + cs0_dq29_rx_de-skew = <7>; + cs0_dq29_tx_de-skew = <7>; + cs0_dq30_rx_de-skew = <7>; + cs0_dq30_tx_de-skew = <7>; + cs0_dq31_rx_de-skew = <7>; + cs0_dq31_tx_de-skew = <7>; + cs0_dqs3_rx_de-skew = <7>; + cs0_dqs3p_tx_de-skew = <9>; + cs0_dqs3n_tx_de-skew = <9>; + + cs1_dm0_rx_de-skew = <7>; + cs1_dm0_tx_de-skew = <8>; + cs1_dq0_rx_de-skew = <7>; + cs1_dq0_tx_de-skew = <8>; + cs1_dq1_rx_de-skew = <7>; + cs1_dq1_tx_de-skew = <8>; + cs1_dq2_rx_de-skew = <7>; + cs1_dq2_tx_de-skew = <8>; + cs1_dq3_rx_de-skew = <7>; + cs1_dq3_tx_de-skew = <8>; + cs1_dq4_rx_de-skew = <7>; + cs1_dq4_tx_de-skew = <8>; + cs1_dq5_rx_de-skew = <7>; + cs1_dq5_tx_de-skew = <8>; + cs1_dq6_rx_de-skew = <7>; + cs1_dq6_tx_de-skew = <8>; + cs1_dq7_rx_de-skew = <7>; + cs1_dq7_tx_de-skew = <8>; + cs1_dqs0_rx_de-skew = <6>; + cs1_dqs0p_tx_de-skew = <9>; + cs1_dqs0n_tx_de-skew = <9>; + + cs1_dm1_rx_de-skew = <7>; + cs1_dm1_tx_de-skew = <7>; + cs1_dq8_rx_de-skew = <7>; + cs1_dq8_tx_de-skew = <8>; + cs1_dq9_rx_de-skew = <7>; + cs1_dq9_tx_de-skew = <7>; + cs1_dq10_rx_de-skew = <7>; + cs1_dq10_tx_de-skew = <8>; + cs1_dq11_rx_de-skew = <7>; + cs1_dq11_tx_de-skew = <7>; + cs1_dq12_rx_de-skew = <7>; + cs1_dq12_tx_de-skew = <8>; + cs1_dq13_rx_de-skew = <7>; + cs1_dq13_tx_de-skew = <7>; + cs1_dq14_rx_de-skew = <7>; + cs1_dq14_tx_de-skew = <8>; + cs1_dq15_rx_de-skew = <7>; + cs1_dq15_tx_de-skew = <7>; + cs1_dqs1_rx_de-skew = <7>; + cs1_dqs1p_tx_de-skew = <9>; + cs1_dqs1n_tx_de-skew = <9>; + + cs1_dm2_rx_de-skew = <7>; + cs1_dm2_tx_de-skew = <8>; + cs1_dq16_rx_de-skew = <7>; + cs1_dq16_tx_de-skew = <8>; + cs1_dq17_rx_de-skew = <7>; + cs1_dq17_tx_de-skew = <8>; + cs1_dq18_rx_de-skew = <7>; + cs1_dq18_tx_de-skew = <8>; + cs1_dq19_rx_de-skew = <7>; + cs1_dq19_tx_de-skew = <8>; + cs1_dq20_rx_de-skew = <7>; + cs1_dq20_tx_de-skew = <8>; + cs1_dq21_rx_de-skew = <7>; + cs1_dq21_tx_de-skew = <8>; + cs1_dq22_rx_de-skew = <7>; + cs1_dq22_tx_de-skew = <8>; + cs1_dq23_rx_de-skew = <7>; + cs1_dq23_tx_de-skew = <8>; + cs1_dqs2_rx_de-skew = <6>; + cs1_dqs2p_tx_de-skew = <9>; + cs1_dqs2n_tx_de-skew = <9>; + + cs1_dm3_rx_de-skew = <7>; + cs1_dm3_tx_de-skew = <7>; + cs1_dq24_rx_de-skew = <7>; + cs1_dq24_tx_de-skew = <8>; + cs1_dq25_rx_de-skew = <7>; + cs1_dq25_tx_de-skew = <7>; + cs1_dq26_rx_de-skew = <7>; + cs1_dq26_tx_de-skew = <7>; + cs1_dq27_rx_de-skew = <7>; + cs1_dq27_tx_de-skew = <7>; + cs1_dq28_rx_de-skew = <7>; + cs1_dq28_tx_de-skew = <7>; + cs1_dq29_rx_de-skew = <7>; + cs1_dq29_tx_de-skew = <7>; + cs1_dq30_rx_de-skew = <7>; + cs1_dq30_tx_de-skew = <7>; + cs1_dq31_rx_de-skew = <7>; + cs1_dq31_tx_de-skew = <7>; + cs1_dqs3_rx_de-skew = <7>; + cs1_dqs3p_tx_de-skew = <9>; + cs1_dqs3n_tx_de-skew = <9>; + }; +}; diff --git a/rk3328-evb-android-avb.dts b/rk3328-evb-android-avb.dts new file mode 100644 index 0000000..0d72e05 --- /dev/null +++ b/rk3328-evb-android-avb.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3328-evb-android.dtsi" + +/ { + model = "Rockchip RK3328 EVB avb"; + compatible = "rockchip,rk3328-evb-avb", "rockchip,rk3328"; +}; diff --git a/rk3328-evb-android.dts b/rk3328-evb-android.dts new file mode 100644 index 0000000..6d50444 --- /dev/null +++ b/rk3328-evb-android.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "rk3328-evb-android.dtsi" + +/ { + model = "Rockchip RK3328 EVB"; + compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; +}; + +&firmware_android{ + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/platform/ff520000.dwmmc/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/ff520000.dwmmc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3328-evb-android.dtsi b/rk3328-evb-android.dtsi new file mode 100644 index 0000000..708d580 --- /dev/null +++ b/rk3328-evb-android.dtsi @@ -0,0 +1,716 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +#include "rk3328.dtsi" +#include "rk3328-android.dtsi" +#include + +/ { + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-rk3328"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip-spdif"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc_host_vbus: host-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk805 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + BT,power_gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio1 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&avsd { + status = "okay"; +}; + +&codec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "disabled"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_logic>; +}; + +&hdmi { + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&hdmiphy { + rockchip,phy-table = + <165000000 0x07 0x0a 0x0a 0x0a 0x00 0x00 0x08 + 0x08 0x08 0x00 0xac 0xcc 0xcc 0xcc>, + <340000000 0x0b 0x0d 0x0d 0x0d 0x07 0x15 0x08 + 0x08 0x08 0x3f 0xac 0xcc 0xcd 0xdd>, + <594000000 0x10 0x1a 0x1a 0x1a 0x07 0x15 0x08 + 0x08 0x08 0x00 0xac 0xcc 0xcc 0xcc>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "rk805-clkout1", "rk805-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + rtc { + status = "okay"; + }; + + pwrkey { + status = "disabled"; + }; + + gpio { + status = "okay"; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_11: LDO_REG3 { + regulator-name = "vdd_11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + }; + }; +}; + +&secure_memory { + /* + * enable like this: + * reg = <0x0 0x20000000 0x0 0x10000000>; + */ + reg = <0x0 0x20000000 0x0 0x0>; +}; + +&i2s0 { + #sound-dai-cells = <0>; + rockchip,bclk-fs = <128>; + status = "okay"; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_18emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vdd_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; /* gpio2_a6 */ + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; + vcodec-supply = <&vdd_logic>; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,virtual-poweroff = <1>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + max-frequency = <125000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + no-sd; + no-mmc; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + no-sdio; + no-mmc; + status = "okay"; + vmmc-supply = <&vcc_sd>; +}; + +&spdif { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm2_tx>; + status = "okay"; +}; + +&threshold { + temperature = <90000>; /* millicelsius */ +}; + +&target { + temperature = <105000>; /* millicelsius */ +}; + +&soc_crit { + temperature = <115000>; /* millicelsius */ +}; + +&tsadc { + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&tve { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + vbus-supply = <&vcc_otg_vbus>; + status = "okay"; + }; +}; + +&u3phy { + vbus-supply = <&vcc_host_vbus>; + status = "okay"; +}; + +&u3phy_utmi { + status = "okay"; +}; + +&u3phy_pipe { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vepu22 { + status = "okay"; +}; + +&vepu22_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328-evb.dts b/rk3328-evb.dts new file mode 100644 index 0000000..468a9ae --- /dev/null +++ b/rk3328-evb.dts @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" +#include + +/ { + model = "Rockchip RK3328 EVB"; + compatible = "rockchip,rk3328-evb", "rockchip,rk3328"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff130000 swiotlb=1 kpti=0 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait coherent_pool=1m"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <159>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + }; + + vcc_host_vbus: host-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk805 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + BT,power_gpio = <&gpio1 21 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio1 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&avsd { + status = "okay"; +}; + +&cif { + status = "disabled"; +}; + +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + logo-memory-region = <&drm_logo>; + status = "okay"; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "fullscreen"; + connect = <&vop_out_hdmi>; + }; + }; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "disabled"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&hdmi { + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk805-clkout1", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + status = "okay"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + rtc { + status = "okay"; + }; + + pwrkey { + status = "okay"; + }; + + gpio { + status = "okay"; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&i2s0 { + #sound-dai-cells = <0>; + rockchip,bclk-fs = <128>; + status = "okay"; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + status = "okay"; + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0x39 KEY_POWER>, + <0x73 KEY_MUTE>, + <0xa4 KEY_PLAYPAUSE>, + <0x75 KEY_VOLUMEDOWN>, + <0x77 KEY_VOLUMEUP>, + <0x7d KEY_MENU>, + <0xf9 KEY_HOME>, + <0x5f KEY_BACK>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xaa KEY_REPLY>, + <0x55 KEY_1>, + <0x5b KEY_2>, + <0xf8 KEY_3>, + <0x57 KEY_4>, + <0xed KEY_5>, + <0xee KEY_6>, + <0x59 KEY_7>, + <0xf1 KEY_8>, + <0xf2 KEY_9>, + <0xe0 KEY_BACKSPACE>, + <0x79 KEY_0>, + <0xa4 KEY_SETUP>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga { + status = "okay"; +}; + +&rkvdec { + vcodec-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + rockchip,virtual-poweroff = <1>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <150000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + no-mmc; + no-sd; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + no-sdio; + no-mmc; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&u3phy { + vbus-supply = <&vcc_host_vbus>; + status = "okay"; +}; + +&u3phy_pipe { + status = "okay"; +}; + +&u3phy_utmi { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328-nanopi-r2s.dts b/rk3328-nanopi-r2s.dts new file mode 100644 index 0000000..83a0bdb --- /dev/null +++ b/rk3328-nanopi-r2s.dts @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 David Bauer + */ + +/dts-v1/; + +#include +#include +#include "rk3328.dtsi" + +/ { + model = "FriendlyElec NanoPi R2S"; + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clk: gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-0 = <&reset_button_pin>; + pinctrl-names = "default"; + + reset { + label = "reset"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <50>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>; + pinctrl-names = "default"; + + lan_led: led-0 { + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:lan"; + }; + + sys_led: led-1 { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:red:sys"; + }; + + wan_led: led-2 { + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "nanopi-r2s:green:wan"; + }; + }; + + vcc_io_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + enable-active-high; + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&sdio_vcc_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_io_sdio"; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-settling-time-us = <5000>; + regulator-type = "voltage"; + startup-delay-us = <2000>; + states = <1800000 0x1>, + <3300000 0x0>; + vin-supply = <&vcc_io_33>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sdmmc0m1_pin>; + pinctrl-names = "default"; + regulator-name = "vcc_sd"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io_33>; + }; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&display_subsystem { + status = "disabled"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>; + clock_in_out = "input"; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc_io_33>; + pinctrl-0 = <&rgmiim1_pins>; + pinctrl-names = "default"; + rx_delay = <0x18>; + snps,aal; + tx_delay = <0x24>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + pinctrl-0 = <ð_phy_reset_pin>; + pinctrl-names = "default"; + reset-assert-us = <10000>; + reset-deassert-us = <50000>; + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pmic_int_l>; + pinctrl-names = "default"; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vdd_5v>; + vcc2-supply = <&vdd_5v>; + vcc3-supply = <&vdd_5v>; + vcc4-supply = <&vdd_5v>; + vcc5-supply = <&vcc_io_33>; + vcc6-supply = <&vdd_5v>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io_33: DCDC_REG4 { + regulator-name = "vcc_io_33"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + pmuio-supply = <&vcc_io_33>; + vccio1-supply = <&vcc_io_33>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io_33>; + vccio6-supply = <&vcc_io_33>; + status = "okay"; +}; + +&pinctrl { + button { + reset_button_pin: reset-button-pin { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ethernet-phy { + eth_phy_reset_pin: eth-phy-reset-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + lan_led_pin: lan-led-pin { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_pin: wan-led-pin { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdio_vcc_pin: sdio-vcc-pin { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>; + pinctrl-names = "default"; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_io_sdio>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/rk3328-roc-cc.dts b/rk3328-roc-cc.dts new file mode 100644 index 0000000..22ab5e1 --- /dev/null +++ b/rk3328-roc-cc.dts @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Firefly roc-rk3328-cc"; + compatible = "firefly,roc-rk3328-cc", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sdio: sdmmcio-regulator { + compatible = "regulator-gpio"; + gpios = <&grf_gpio 0 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "vcc_sdio"; + regulator-type = "voltage"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + leds { + compatible = "gpio-leds"; + + power_led: led-0 { + label = "firefly:blue:power"; + linux,default-trigger = "heartbeat"; + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + user_led: led-1 { + label = "firefly:yellow:user"; + linux,default-trigger = "mmc1"; + gpios = <&rk805 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,aal; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,rxpbl = <0x4>; + snps,txpbl = <0x4>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio1>; + interrupts = <24 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_sdio>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328-rock64-android-avb.dts b/rk3328-rock64-android-avb.dts new file mode 100644 index 0000000..adc1dd7 --- /dev/null +++ b/rk3328-rock64-android-avb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3328-rock64-android.dtsi" + +/ { + model = "Pine64 Rock64 avb"; + compatible = "pine64,rock64-android-avb", "rockchip,rk3328"; +}; + +&firmware_android{ + compatible = "android,firmware"; + boot_devices = "ff520000.dwmmc"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,avb"; + }; + }; +}; diff --git a/rk3328-rock64-android.dts b/rk3328-rock64-android.dts new file mode 100644 index 0000000..66e8391 --- /dev/null +++ b/rk3328-rock64-android.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "rk3328-rock64-android.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64-android", "rockchip,rk3328"; +}; + +&firmware_android{ + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/platform/ff520000.dwmmc/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/ff520000.dwmmc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3328-rock64-android.dtsi b/rk3328-rock64-android.dtsi new file mode 100644 index 0000000..3dad4f4 --- /dev/null +++ b/rk3328-rock64-android.dtsi @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +#include "rk3328.dtsi" +#include "rk3328-android.dtsi" +#include + +/ { + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip-rk3328"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip-hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&avsd { + status = "okay"; +}; + +&codec { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; + status = "disabled"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_logic>; +}; + +&hdmi { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "rk805-clkout1", "rk805-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + + rtc { + status = "okay"; + }; + + pwrkey { + status = "disabled"; + }; + + gpio { + status = "okay"; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-init-microvolt = <1225000>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_11: LDO_REG3 { + regulator-name = "vdd_11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + }; + }; +}; + +&i2s0 { + #sound-dai-cells = <0>; + rockchip,bclk-fs = <128>; + status = "okay"; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc_18emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vdd_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pwmir_pin>; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; + vcodec-supply = <&vdd_logic>; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,virtual-poweroff = <1>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + no-sdio; + no-mmc; + status = "okay"; + vmmc-supply = <&vcc_sd>; +}; + +&spi0 { + status = "okay"; + + flash@0 { + compatible = "gigadevice,gd25q128", "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + m25p,fast-read; + /* The max SCLK of the flash 104/80 MHZ */ + spi-max-frequency = <50000000>; + }; +}; + +&threshold { + temperature = <90000>; /* millicelsius */ +}; + +&target { + temperature = <105000>; /* millicelsius */ +}; + +&soc_crit { + temperature = <115000>; /* millicelsius */ +}; + +&tsadc { + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + +}; + +&u2phy_host { + phy-supply = <&vcc_host1_5v>; + status = "okay"; +}; + +&u2phy_otg { + phy-supply = <&vcc_otg_5v>; + status = "okay"; +}; + +&u3phy { + phy-supply = <&vcc_host_5v>; + status = "okay"; +}; + +&u3phy_utmi { + status = "okay"; +}; + +&u3phy_pipe { + status = "okay"; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vepu22 { + status = "okay"; +}; + +&vepu22_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328-rock64.dts b/rk3328-rock64.dts new file mode 100644 index 0000000..e0bc031 --- /dev/null +++ b/rk3328-rock64.dts @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_pin>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&ir_int>; + pinctrl-names = "default"; + }; + + leds { + compatible = "gpio-leds"; + + power_led: led-0 { + gpios = <&rk805 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + }; + + standby_led: led-1 { + gpios = <&rk805 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3328"; + dais = <&i2s1_p0 + &spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; +}; + +&codec { + mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + port@0 { + codec_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: pmic@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rk805-clkout1", "rk805-clkout2"; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc18_emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&i2s1 { + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_p0_0>; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spdif { + pinctrl-0 = <&spdifm0_tx>; + status = "okay"; + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usbdrd3 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3328.dtsi b/rk3328.dtsi new file mode 100644 index 0000000..7dcf177 --- /dev/null +++ b/rk3328.dtsi @@ -0,0 +1,2554 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3328-dram-default-timing.dtsi" + +/ { + compatible = "rockchip,rk3328"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac2io; + ethernet1 = &gmac2phy; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + clocks = <&cru ARMCLK>; + #cooling-cells = <2>; + cpu-idle-states = <&CPU_SLEEP>; + dynamic-power-coefficient = <120>; + enable-method = "psci"; + next-level-cache = <&l2>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,video-4k-freq = <1008000>; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&cpu_leakage>; + nvmem-cell-names = "cpu_leakage"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <950000 950000 1350000>; + opp-microvolt-L0 = <950000 950000 1350000>; + opp-microvolt-L1 = <950000 950000 1350000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <950000 950000 1350000>; + opp-microvolt-L0 = <950000 950000 1350000>; + opp-microvolt-L1 = <950000 950000 1350000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <1050000 1050000 1350000>; + opp-microvolt-L0 = <1050000 1050000 1350000>; + opp-microvolt-L1 = <1000000 1000000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1150000 1150000 1350000>; + opp-microvolt-L0 = <1150000 1150000 1350000>; + opp-microvolt-L1 = <1100000 1100000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1275000 1275000 1350000>; + opp-microvolt-L0 = <1275000 1275000 1350000>; + opp-microvolt-L1 = <1225000 1225000 1350000>; + clock-latency-ns = <40000>; + }; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <1350000 1350000 1350000>; + opp-microvolt-L0 = <1350000 1350000 1350000>; + opp-microvolt-L1 = <1300000 1300000 1350000>; + clock-latency-ns = <40000>; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3328-dmc"; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + ddr_timing = <&ddr_timing>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 786000 + SYS_STATUS_REBOOT 786000 + SYS_STATUS_SUSPEND 786000 + SYS_STATUS_VIDEO_1080P 786000 + SYS_STATUS_VIDEO_4K 786000 + SYS_STATUS_VIDEO_4K_10B 924000 + SYS_STATUS_PERFORMANCE 924000 + SYS_STATUS_BOOST 924000 + >; + auto-min-freq = <786000>; + auto-freq-en = <0>; + #cooling-cells = <2>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "ddr_leakage"; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <950000>; + status = "disabled"; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1025000>; + opp-microvolt-L0 = <1025000>; + opp-microvolt-L1 = <1000000>; + status = "disabled"; + }; + opp-786000000 { + opp-hz = /bits/ 64 <786000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-798000000 { + opp-hz = /bits/ 64 <798000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + opp-924000000 { + opp-hz = /bits/ 64 <924000000>; + opp-microvolt = <1125000>; + opp-microvolt-L0 = <1125000>; + opp-microvolt-L1 = <1100000>; + }; + /* 1056M is only for ddr4 */ + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <1175000>; + opp-microvolt-L0 = <1175000>; + opp-microvolt-L1 = <1150000>; + status = "disabled"; + }; + }; + + analog_sound: analog-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,rk3328"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&codec>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&efuse_id>, <&efuse_cpu_version>; + nvmem-cell-names = "id", "cpu-version"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3328"; + rockchip,sleep-mode-config = <0>; + rockchip,virtual-poweroff = <0>; + status = "disabled"; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + rockchip,polling-delay = <200>; /* milliseconds */ + rockchip,video-4k-offline-cpus = "3"; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif"; + + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + i2s0: i2s@ff000000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff000000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 11>, <&dmac 12>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S0>, <&cru SRST_I2S0_H>; + reset-names = "reset-m", "reset-h"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@ff010000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff010000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 14>, <&dmac 15>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S1>, <&cru SRST_I2S1_H>; + reset-names = "reset-m", "reset-h"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@ff020000 { + compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff020000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&dmac 0>, <&dmac 1>; + dma-names = "tx", "rx"; + resets = <&cru SRST_I2S2>, <&cru SRST_I2S2_H>; + reset-names = "reset-m", "reset-h"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s2m0_mclk + &i2s2m0_sclk + &i2s2m0_lrcktx + &i2s2m0_lrckrx + &i2s2m0_sdo + &i2s2m0_sdi>; + pinctrl-1 = <&i2s2m0_sleep>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif: spdif@ff030000 { + compatible = "rockchip,rk3328-spdif"; + reg = <0x0 0xff030000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 10>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@ff040000 { + compatible = "rockchip,pdm"; + reg = <0x0 0xff040000 0x0 0x1000>; + clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 16>; + dma-names = "rx"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_fsync + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + pinctrl-1 = <&pdmm0_clk_sleep + &pdmm0_fsync_sleep + &pdmm0_sdi0_sleep + &pdmm0_sdi1_sleep + &pdmm0_sdi2_sleep + &pdmm0_sdi3_sleep>; + status = "disabled"; + }; + + tsp: tsp@ff050000 { + compatible = "rockchip,rk3328-tsp"; + reg = <0x0 0xff050000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "irq_tsp"; + clocks = <&cru SCLK_TSP>, <&cru ACLK_TSP>, <&cru HCLK_TSP>; + clock-names = "clk_tsp", "aclk_tsp", "hclk_tsp"; + pinctrl-names = "default"; + pinctrl-0 = <&tsp_d0 + &tsp_d1 + &tsp_d2 + &tsp_d3 + &tsp_d4 + &tsp_d5 + &tsp_d6 + &tsp_d7 + &tsp_sync + &tsp_clk + &tsp_fail + &tsp_valid>; + status = "disabled"; + }; + + rng: rng@ff060000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff060000 0x0 0x4000>; + + clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; + clock-names = "clk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO>, <&cru HCLK_CRYPTO_SLV>; + assigned-clock-rates = <150000000>, <100000000>; + status = "disabled"; + }; + + grf: syscon@ff100000 { + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff100000 0x0 0x1000>; + + io_domains: io-domains { + compatible = "rockchip,rk3328-io-voltage-domain"; + status = "disabled"; + }; + + grf_gpio: grf-gpio { + compatible = "rockchip,rk3328-grf-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + power: power-controller { + compatible = "rockchip,rk3328-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + power-domain@RK3328_PD_HEVC { + reg = ; + }; + power-domain@RK3328_PD_VIDEO { + reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + pm_qos = <&qos_rkvdec_r>, <&qos_rkvdec_w>; + }; + power-domain@RK3328_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + }; + }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x5c8>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + }; + }; + + thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <1000>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point-0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + target: trip-point-1 { + temperature = <85000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <115000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map2 { + trip = <&target>; + cooling-device = <&rkvdec THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map3 { + trip = <&target>; + cooling-device = <&dmc THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + }; + + uart0: serial@ff110000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff110000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 2>, <&dmac 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@ff120000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff120000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 4>, <&dmac 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@ff130000 { + compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff130000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 6>, <&dmac 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + pmu: power-management@ff140000 { + compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff140000 0x0 0x1000>; + }; + + i2c0: i2c@ff150000 { + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + status = "disabled"; + }; + + i2c1: i2c@ff160000 { + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + i2c2: i2c@ff170000 { + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff180000 { + compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff180000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + spi0: spi@ff190000 { + compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff190000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac 8>, <&dmac 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>; + status = "disabled"; + }; + + wdt: watchdog@ff1a0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff1a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_BUS_PRE>; + status = "disabled"; + }; + + pwm0: pwm@ff1b0000 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0000 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@ff1b0010 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0010 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@ff1b0020 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0020 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@ff1b0030 { + compatible = "rockchip,rk3328-pwm"; + reg = <0x0 0xff1b0030 0x0 0x10>; + interrupts = ; + clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; + clock-names = "pwm", "pclk"; + pinctrl-names = "active"; + pinctrl-0 = <&pwmir_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + dmac: dma-controller@ff1f0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff1f0000 0x0 0x4000>; + interrupts = , + ; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + tsadc: tsadc@ff250000 { + compatible = "rockchip,rk3328-tsadc"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <50000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <100000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + efuse: efuse@ff260000 { + compatible = "rockchip,rk3328-efuse"; + reg = <0x0 0xff260000 0x0 0x50>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru SCLK_EFUSE>; + clock-names = "pclk_efuse"; + rockchip,efuse-size = <0x20>; + + /* Data cells */ + efuse_id: id@7 { + reg = <0x07 0x10>; + }; + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + logic_leakage: logic-leakage@19 { + reg = <0x19 0x1>; + }; + efuse_cpu_version: cpu-version@1a { + reg = <0x1a 0x1>; + bits = <3 3>; + }; + }; + + saradc: adc@ff280000 { + compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + gpu: gpu@ff300000 { + compatible = "arm,mali-450"; + reg = <0x0 0xff300000 0x0 0x30000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "Mali_GP_IRQ", + "Mali_GP_MMU_IRQ", + "IRQPP", + "Mali_PP0_IRQ", + "Mali_PP0_MMU_IRQ", + "Mali_PP1_IRQ", + "Mali_PP1_MMU_IRQ"; + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + #cooling-cells = <2>; /* min followed by max */ + operating-points-v2 = <&gpu_opp_table>; + resets = <&cru SRST_GPU_A>; + status = "disabled"; + + gpu_power_model: power_model { + compatible = "arm,mali-simple-power-model"; + voltage = <900>; + frequency = <500>; + static-power = <300>; + dynamic-power = <396>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "gpu_leakage"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <950000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-microvolt-L0 = <1050000>; + opp-microvolt-L1 = <1025000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1150000>; + opp-microvolt-L0 = <1150000>; + opp-microvolt-L1 = <1100000>; + }; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <3>; + rockchip,resetgroup-count = <4>; + rockchip,grf = <&grf>; + rockchip,grf-offset = <0x040c>; + rockchip,grf-values = <0x8000000>; + rockchip,grf-names = "grf_vepu2"; + status = "disabled"; + }; + + vepu: vepu@ff340000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xff340000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_H264>, <&cru HCLK_H264>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_RKVENC_H264_A>, + <&cru SRST_RKVENC_H264_H>; + reset-names = "video_a", "video_h"; + iommus = <&vepu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <3>; + power-domains = <&power RK3328_PD_HEVC>; + status = "disabled"; + }; + + vepu_mmu: iommu@ff340800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff340800 0x0 0x40>; + interrupts = ; + interrupt-names = "vepu_mmu"; + clocks = <&cru ACLK_H264>, <&cru HCLK_H264>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3328_PD_HEVC>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vdpu: vdpu@ff350000 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xff350400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3328_PD_VPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff350800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff350800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VPU>; + status = "disabled"; + }; + + avsd: avsd_plus@ff351000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xff351000 0x0 0x200>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3328_PD_VPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + rkvdec: rkvdec@ff36000 { + compatible = "rockchip,rkv-decoder-rk3328", "rockchip,rkv-decoder-v2"; + reg = <0x0 0xff360000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", + "clk_core"; + rockchip,normal-rates = <300000000>, <0>, <300000000>, <300000000>; + rockchip,advanced-rates = <400000000>, <0>, <400000000>, <300000000>; + rockchip,default-max-load = <2088960>; + resets = <&cru SRST_VDEC_A>, <&cru SRST_VDEC_H>, + <&cru SRST_VDEC_NIU_A>, <&cru SRST_VDEC_NIU_H>, + <&cru SRST_VDEC_CABAC>, <&cru SRST_VDEC_CORE>; + reset-names = "video_a", "video_h", "niu_a", "niu_h", + "video_cabac", "video_core"; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + power-domains = <&power RK3328_PD_VIDEO>; + operating-points-v2 = <&rkvdec_opp_table>; + #cooling-cells = <2>; + devfreq = <&dmc>; + status = "disabled"; + + vcodec_power_model: vcodec_power_model { + compatible = "vcodec_power_model"; + dynamic-power-coefficient = <120>; + static-power-coefficient = <200>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "soc-thermal"; + }; + }; + + rkvdec_opp_table: rkvdec-opp-table { + compatible = "operating-points-v2"; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 254 1 + >; + nvmem-cells = <&logic_leakage>; + nvmem-cell-names = "rkvdec_leakage"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <950000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1075000>; + opp-microvolt-L0 = <1075000>; + opp-microvolt-L1 = <1050000>; + }; + }; + + rkvdec_mmu: iommu@ff360480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3328_PD_VIDEO>; + status = "disabled"; + }; + + vop: vop@ff370000 { + compatible = "rockchip,rk3328-vop"; + reg = <0x0 0xff370000 0x0 0x3efc>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; + assigned-clocks = <&cru DCLK_LCDC>; + assigned-clock-parents = <&cru HDMIPHY>; + resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; + reset-names = "axi", "ahb", "dclk"; + iommus = <&vop_mmu>; + status = "disabled"; + + vop_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vop_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vop>; + }; + vop_out_tve: endpoint@1 { + reg = <1>; + remote-endpoint = <&tve_in_vop>; + }; + }; + }; + + tve: tve@ff373e00 { + compatible = "rockchip,rk3328-tve"; + reg = <0x0 0xff373e00 0x0 0x100>, + <0x0 0xff420000 0x0 0x10000>; + rockchip,saturation = <0x00376749>; + rockchip,brightcontrast = <0x0000a305>; + rockchip,adjtiming = <0xb6c00880>; + rockchip,lumafilter0 = <0x01ff0000>; + rockchip,lumafilter1 = <0xf40200fe>; + rockchip,lumafilter2 = <0xf332d70c>; + rockchip,daclevel = <0x22>; + rockchip,dac1level = <0x7>; + status = "disabled"; + + ports { + tve_in: port { + #address-cells = <1>; + #size-cells = <0>; + tve_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_tve>; + }; + }; + }; + }; + + vop_mmu: iommu@ff373f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff373f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + cif: cif@ff380000 { + compatible = "rockchip,cif", "rockchip,rk3328-cif"; + reg = <0x0 0xff380000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>; + clock-names = "aclk_cif", "hclk_cif"; + resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_P>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_p"; + status = "disabled"; + }; + + rga: rga@ff3900000 { + compatible = "rockchip,rga2"; + dev_mode = <1>; + reg = <0x0 0xff390000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + status = "disabled"; + }; + + iep: iep@ff3a0000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + iommus = <&iep_mmu>; + reg = <0x0 0xff3a0000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3328_PD_VIDEO>; + allocator = <1>; + version = <2>; + status = "disabled"; + }; + + iep_mmu: iommu@ff3a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff3a0800 0x0 0x40>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "hclk"; + power-domains = <&power RK3328_PD_VIDEO>; + #iommu-cells = <0>; + status = "disabled"; + }; + + hdmi: hdmi@ff3c0000 { + compatible = "rockchip,rk3328-dw-hdmi"; + reg = <0x0 0xff3c0000 0x0 0x20000>; + reg-io-width = <4>; + interrupts = , + ; + clocks = <&cru PCLK_HDMI>, + <&cru SCLK_HDMI_SFC>, + <&cru SCLK_RTC32K>; + clock-names = "iahb", + "isfr", + "cec"; + phys = <&hdmiphy>; + phy-names = "hdmi"; + pinctrl-names = "default", "pin"; + pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>; + pinctrl-1 = <&i2c3_pins>; + resets = <&cru SRST_HDMI_P>, + <&cru SRST_HDMIPHY>; + reset-names = "hdmi", + "hdmiphy"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vop: endpoint@0 { + reg = <0>; + remote-endpoint = <&vop_out_hdmi>; + }; + }; + }; + }; + + codec: codec@ff410000 { + compatible = "rockchip,rk3328-codec"; + reg = <0x0 0xff410000 0x0 0x1000>; + clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>; + clock-names = "pclk", "mclk"; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hdmiphy: phy@ff430000 { + compatible = "rockchip,rk3328-hdmi-phy"; + reg = <0x0 0xff430000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>; + clock-names = "sysclk", "refclk", "refpclk"; + clock-output-names = "hdmi_phy"; + #clock-cells = <0>; + nvmem-cells = <&efuse_cpu_version>; + nvmem-cell-names = "cpu-version"; + #phy-cells = <0>; + status = "disabled"; + }; + + cru: clock-controller@ff440000 { + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon"; + reg = <0x0 0xff440000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + /* + * CPLL should run at 1200, but that is to high for + * the initial dividers of most of its children. + * We need set cpll child clk div first, + * and then set the cpll frequency. + */ + <&cru DCLK_LCDC>, <&cru SCLK_PDM>, + <&cru SCLK_RTC32K>, <&cru SCLK_UART0>, + <&cru SCLK_UART1>, <&cru SCLK_UART2>, + <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>, + <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>, + <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>, + <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>, + <&cru SCLK_SDIO>, <&cru SCLK_TSP>, + <&cru SCLK_WIFI>, <&cru ARMCLK>, + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>, + <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>, + <&cru SCLK_RTC32K>; + assigned-clock-parents = + <&cru HDMIPHY>, <&cru PLL_APLL>, + <&cru PLL_GPLL>, <&xin24m>, + <&xin24m>, <&xin24m>; + assigned-clock-rates = + <0>, <61440000>, + <0>, <24000000>, + <24000000>, <24000000>, + <15000000>, <15000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, + <50000000>, <100000000>, + <100000000>, <100000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <24000000>, <600000000>, + <491520000>, <1200000000>, + <150000000>, <75000000>, + <75000000>, <150000000>, + <75000000>, <75000000>, + <32768>; + }; + + usb2phy_grf: syscon@ff450000 { + compatible = "rockchip,rk3328-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xff450000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rk3328-usb2phy"; + reg = <0x100 0x10>; + clocks = <&xin24m>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + }; + + usb3phy_grf: syscon@ff460000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xff460000 0x0 0x1000>; + }; + + u3phy: usb3-phy@ff470000 { + compatible = "rockchip,rk3328-u3phy"; + reg = <0x0 0xff470000 0x0 0x0>; + rockchip,u3phygrf = <&usb3phy_grf>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "linestate"; + clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>; + clock-names = "u3phy-otg", "u3phy-pipe"; + resets = <&cru SRST_USB3PHY_U2>, + <&cru SRST_USB3PHY_U3>, + <&cru SRST_USB3PHY_PIPE>, + <&cru SRST_USB3OTG_UTMI>, + <&cru SRST_USB3PHY_OTG_P>, + <&cru SRST_USB3PHY_PIPE_P>; + reset-names = "u3phy-u2-por", "u3phy-u3-por", + "u3phy-pipe-mac", "u3phy-utmi-mac", + "u3phy-utmi-apb", "u3phy-pipe-apb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + u3phy_utmi: utmi@ff470000 { + reg = <0x0 0xff470000 0x0 0x8000>; + #phy-cells = <0>; + status = "disabled"; + }; + + u3phy_pipe: pipe@ff478000 { + reg = <0x0 0xff478000 0x0 0x8000>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + sdmmc: mmc@ff500000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff500000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + sdio: mmc@ff510000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff510000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + emmc: mmc@ff520000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff520000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + status = "disabled"; + }; + + gmac2io: ethernet@ff540000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff540000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>, + <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>, + <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>, + <&cru PCLK_MAC2IO>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + resets = <&cru SRST_GMAC2IO_A>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,txpbl = <0x4>; + status = "disabled"; + }; + + gmac2phy: ethernet@ff550000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff550000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, + <&cru SCLK_MAC2PHY_OUT>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_macphy"; + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clocks = <&cru SCLK_MAC2PHY_OUT>; + resets = <&cru SRST_MACPHY>; + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; + phy-is-integrated; + }; + }; + }; + + usb20_otg: usb@ff580000 { + compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>; + clock-names = "otg", "otg_pmu"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <280>; + g-tx-fifo-size = <256 128 128 64 32 16>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ehci: usb@ff5c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xff5c0000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff5d0000 { + compatible = "generic-ohci"; + reg = <0x0 0xff5d0000 0x0 0x10000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + sdmmc_ext: mmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + status = "disabled"; + }; + + usbdrd3: usbdrd { + compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; + clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@ff600000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff600000 0x0 0x100000>; + interrupts = ; + dr_mode = "host"; + phys = <&u3phy_utmi>, <&u3phy_pipe>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis-del-phy-power-chg-quirk; + snps,dis_enblslpm_quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + qos_rkvdec_r: qos@ff750000 { + compatible = "syscon"; + reg = <0x0 0xff750000 0x0 0x20>; + }; + + qos_rkvdec_w: qos@ff750080 { + compatible = "syscon"; + reg = <0x0 0xff750080 0x0 0x20>; + }; + + qos_vpu: qos@ff778000 { + compatible = "syscon"; + reg = <0x0 0xff778000 0x0 0x20>; + }; + + dfi: dfi@ff790000 { + compatible = "rockchip,rk3328-dfi"; + reg = <0x00 0xff790000 0x00 0x400>; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + gic: interrupt-controller@ff811000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xff811000 0 0x1000>, + <0x0 0xff812000 0 0x2000>, + <0x0 0xff814000 0 0x2000>, + <0x0 0xff816000 0 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3328-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff210000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff210000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff220000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff220000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff230000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff230000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff240000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff240000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_2ma: pcfg-pull-none-2ma { + bias-disable; + drive-strength = <2>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_4ma: pcfg-pull-up-4ma { + bias-pull-up; + drive-strength = <4>; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_12ma: pcfg-pull-up-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>, + <2 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>, + <0 RK_PA6 2 &pcfg_pull_none>; + }; + i2c3_pins: i2c3-pins { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tsp { + tsp_d0: tsp-d0 { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>; + }; + tsp_d1: tsp-d1 { + rockchip,pins = <3 RK_PA5 1 &pcfg_pull_none>; + }; + tsp_d2: tsp-d2 { + rockchip,pins = <3 RK_PA6 1 &pcfg_pull_none>; + }; + tsp_d3: tsp-d3 { + rockchip,pins = <3 RK_PA7 1 &pcfg_pull_none>; + }; + tsp_d4: tsp-d4 { + rockchip,pins = <3 RK_PB0 1 &pcfg_pull_none>; + }; + tsp_d5: tsp-d5 { + rockchip,pins = <2 RK_PC0 3 &pcfg_pull_none>; + }; + tsp_d6: tsp-d6 { + rockchip,pins = <2 RK_PC1 3 &pcfg_pull_none>; + }; + tsp_d7: tsp-d7 { + rockchip,pins = <2 RK_PC2 3 &pcfg_pull_none>; + }; + tsp_sync: tsp-sync { + rockchip,pins = <2 RK_PB7 3 &pcfg_pull_none>; + }; + tsp_clk: tsp-clk { + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none>; + }; + tsp_fail: tsp-fail { + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; + }; + tsp_valid: tsp-valid { + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + hdmi_i2c { + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>, + <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + pdm-0 { + pdmm0_clk: pdmm0-clk { + rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>; + }; + + pdmm0_fsync: pdmm0-fsync { + rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>; + }; + + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>; + }; + + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>; + }; + + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>; + }; + + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>; + }; + + pdmm0_clk_sleep: pdmm0-clk-sleep { + rockchip,pins = + <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi0_sleep: pdmm0-sdi0-sleep { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi1_sleep: pdmm0-sdi1-sleep { + rockchip,pins = + <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi2_sleep: pdmm0-sdi2-sleep { + rockchip,pins = + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_sdi3_sleep: pdmm0-sdi3-sleep { + rockchip,pins = + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; + }; + + pdmm0_fsync_sleep: pdmm0-fsync-sleep { + rockchip,pins = + <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + tsadc { + otp_pin: otp-pin { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>, + <1 RK_PB0 1 &pcfg_pull_up>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>; + }; + + uart0_rts_pin: uart0-rts-pin { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>, + <3 RK_PA6 4 &pcfg_pull_up>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>; + }; + + uart1_rts_pin: uart1-rts-pin { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + uart2-0 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>, + <1 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + uart2-1 { + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>, + <2 RK_PA1 1 &pcfg_pull_up>; + }; + }; + + spi0-0 { + spi0m0_clk: spi0m0-clk { + rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>; + }; + + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; + }; + + spi0m0_tx: spi0m0-tx { + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>; + }; + + spi0m0_rx: spi0m0-rx { + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; + }; + + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>; + }; + }; + + spi0-1 { + spi0m1_clk: spi0m1-clk { + rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>; + }; + + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>; + }; + + spi0m1_tx: spi0m1-tx { + rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>; + }; + + spi0m1_rx: spi0m1-rx { + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>; + }; + + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>; + }; + }; + + spi0-2 { + spi0m2_clk: spi0m2-clk { + rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>; + }; + + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>; + }; + + spi0m2_tx: spi0m2-tx { + rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>; + }; + + spi0m2_rx: spi0m2-rx { + rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + i2s1 { + i2s1_mclk: i2s1-mclk { + rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>; + }; + + i2s1_sclk: i2s1-sclk { + rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>; + }; + + i2s1_lrckrx: i2s1-lrckrx { + rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>; + }; + + i2s1_lrcktx: i2s1-lrcktx { + rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>; + }; + + i2s1_sdi: i2s1-sdi { + rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>; + }; + + i2s1_sdo: i2s1-sdo { + rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; + }; + + i2s1_sdio1: i2s1-sdio1 { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>; + }; + + i2s1_sdio2: i2s1-sdio2 { + rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>; + }; + + i2s1_sdio3: i2s1-sdio3 { + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; + }; + + i2s1_sleep: i2s1-sleep { + rockchip,pins = + <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, + <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s2-0 { + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; + }; + + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>; + }; + + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>; + }; + + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>; + }; + + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>; + }; + + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>; + }; + + i2s2m0_sleep: i2s2m0-sleep { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>, + <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + i2s2-1 { + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>; + }; + + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>; + }; + + i2s2m1_lrckrx: i2sm1-lrckrx { + rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>; + }; + + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>; + }; + + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>; + }; + + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>; + }; + + i2s2m1_sleep: i2s2m1-sleep { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>; + }; + }; + + spdif-0 { + spdifm0_tx: spdifm0-tx { + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + spdif-1 { + spdifm1_tx: spdifm1-tx { + rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + spdif-2 { + spdifm2_tx: spdifm2-tx { + rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdmmc0-0 { + sdmmc0m0_pwren: sdmmc0m0-pwren { + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>; + }; + + sdmmc0m0_pin: sdmmc0m0-pin { + rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0-1 { + sdmmc0m1_pwren: sdmmc0m1-pwren { + rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>; + }; + + sdmmc0m1_pin: sdmmc0m1-pin { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0 { + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>; + }; + + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>; + }; + + sdmmc0_dectn: sdmmc0-dectn { + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_wrprt: sdmmc0-wrprt { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>; + }; + + sdmmc0_bus1: sdmmc0-bus1 { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>; + }; + + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>, + <1 RK_PA1 1 &pcfg_pull_up_8ma>, + <1 RK_PA2 1 &pcfg_pull_up_8ma>, + <1 RK_PA3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc0_pins: sdmmc0-pins { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc0ext { + sdmmc0ext_clk: sdmmc0ext-clk { + rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>; + }; + + sdmmc0ext_cmd: sdmmc0ext-cmd { + rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_wrprt: sdmmc0ext-wrprt { + rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_dectn: sdmmc0ext-dectn { + rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_bus1: sdmmc0ext-bus1 { + rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_bus4: sdmmc0ext-bus4 { + rockchip,pins = + <3 RK_PA4 3 &pcfg_pull_up_4ma>, + <3 RK_PA5 3 &pcfg_pull_up_4ma>, + <3 RK_PA6 3 &pcfg_pull_up_4ma>, + <3 RK_PA7 3 &pcfg_pull_up_4ma>; + }; + + sdmmc0ext_pins: sdmmc0ext-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + sdmmc1 { + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>; + }; + + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_wrprt: sdmmc1-wrprt { + rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_dectn: sdmmc1-dectn { + rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_bus1: sdmmc1-bus1 { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>, + <1 RK_PB7 1 &pcfg_pull_up_8ma>, + <1 RK_PC0 1 &pcfg_pull_up_8ma>, + <1 RK_PC1 1 &pcfg_pull_up_8ma>; + }; + + sdmmc1_pins: sdmmc1-pins { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>, + <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>; + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>; + }; + + emmc_pwren: emmc-pwren { + rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>; + }; + + emmc_rstnout: emmc-rstnout { + rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = + <0 RK_PA7 2 &pcfg_pull_up_12ma>, + <2 RK_PD4 2 &pcfg_pull_up_12ma>, + <2 RK_PD5 2 &pcfg_pull_up_12ma>, + <2 RK_PD6 2 &pcfg_pull_up_12ma>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = + <0 RK_PA7 2 &pcfg_pull_up_12ma>, + <2 RK_PD4 2 &pcfg_pull_up_12ma>, + <2 RK_PD5 2 &pcfg_pull_up_12ma>, + <2 RK_PD6 2 &pcfg_pull_up_12ma>, + <2 RK_PD7 2 &pcfg_pull_up_12ma>, + <3 RK_PC0 2 &pcfg_pull_up_12ma>, + <3 RK_PC1 2 &pcfg_pull_up_12ma>, + <3 RK_PC2 2 &pcfg_pull_up_12ma>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; + }; + pwm0_pin_pull_up: pwm0-pin-pull-up { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_up>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>; + }; + pwm1_pin_pull_up: pwm1-pin-pull-up { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + pwmir { + pwmir_pin: pwmir-pin { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + gmac-1 { + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* mac_txclk */ + <1 RK_PB4 2 &pcfg_pull_none_8ma>, + /* mac_rxclk */ + <1 RK_PB5 2 &pcfg_pull_none_4ma>, + /* mac_mdio */ + <1 RK_PC3 2 &pcfg_pull_none_4ma>, + /* mac_txen */ + <1 RK_PD1 2 &pcfg_pull_none_8ma>, + /* mac_clk */ + <1 RK_PC5 2 &pcfg_pull_none_4ma>, + /* mac_rxdv */ + <1 RK_PC6 2 &pcfg_pull_none_4ma>, + /* mac_mdc */ + <1 RK_PC7 2 &pcfg_pull_none_4ma>, + /* mac_rxd1 */ + <1 RK_PB2 2 &pcfg_pull_none_4ma>, + /* mac_rxd0 */ + <1 RK_PB3 2 &pcfg_pull_none_4ma>, + /* mac_txd1 */ + <1 RK_PB0 2 &pcfg_pull_none_8ma>, + /* mac_txd0 */ + <1 RK_PB1 2 &pcfg_pull_none_8ma>, + /* mac_rxd3 */ + <1 RK_PB6 2 &pcfg_pull_none_4ma>, + /* mac_rxd2 */ + <1 RK_PB7 2 &pcfg_pull_none_4ma>, + /* mac_txd3 */ + <1 RK_PC0 2 &pcfg_pull_none_8ma>, + /* mac_txd2 */ + <1 RK_PC1 2 &pcfg_pull_none_8ma>, + + /* mac_txclk */ + <0 RK_PB0 1 &pcfg_pull_none_8ma>, + /* mac_txen */ + <0 RK_PB4 1 &pcfg_pull_none_8ma>, + /* mac_clk */ + <0 RK_PD0 1 &pcfg_pull_none_4ma>, + /* mac_txd1 */ + <0 RK_PC0 1 &pcfg_pull_none_8ma>, + /* mac_txd0 */ + <0 RK_PC1 1 &pcfg_pull_none_8ma>, + /* mac_txd3 */ + <0 RK_PC7 1 &pcfg_pull_none_8ma>, + /* mac_txd2 */ + <0 RK_PC6 1 &pcfg_pull_none_8ma>; + }; + + rmiim1_pins: rmiim1-pins { + rockchip,pins = + /* mac_mdio */ + <1 RK_PC3 2 &pcfg_pull_none_2ma>, + /* mac_txen */ + <1 RK_PD1 2 &pcfg_pull_none_12ma>, + /* mac_clk */ + <1 RK_PC5 2 &pcfg_pull_none_2ma>, + /* mac_rxer */ + <1 RK_PD0 2 &pcfg_pull_none_2ma>, + /* mac_rxdv */ + <1 RK_PC6 2 &pcfg_pull_none_2ma>, + /* mac_mdc */ + <1 RK_PC7 2 &pcfg_pull_none_2ma>, + /* mac_rxd1 */ + <1 RK_PB2 2 &pcfg_pull_none_2ma>, + /* mac_rxd0 */ + <1 RK_PB3 2 &pcfg_pull_none_2ma>, + /* mac_txd1 */ + <1 RK_PB0 2 &pcfg_pull_none_12ma>, + /* mac_txd0 */ + <1 RK_PB1 2 &pcfg_pull_none_12ma>, + + /* mac_mdio */ + <0 RK_PB3 1 &pcfg_pull_none>, + /* mac_txen */ + <0 RK_PB4 1 &pcfg_pull_none>, + /* mac_clk */ + <0 RK_PD0 1 &pcfg_pull_none>, + /* mac_mdc */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* mac_txd1 */ + <0 RK_PC0 1 &pcfg_pull_none>, + /* mac_txd0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + gmac2phy { + fephyled_speed10: fephyled-speed10 { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>; + }; + + fephyled_speed100: fephyled-speed100 { + rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>; + }; + + fephyled_duplex: fephyled-duplex { + rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; + }; + + fephyled_rxm0: fephyled-rxm0 { + rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>; + }; + + fephyled_txm0: fephyled-txm0 { + rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>; + }; + + fephyled_linkm0: fephyled-linkm0 { + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; + }; + + fephyled_rxm1: fephyled-rxm1 { + rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>; + }; + + fephyled_txm1: fephyled-txm1 { + rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>; + }; + + fephyled_linkm1: fephyled-linkm1 { + rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>; + }; + }; + + tsadc_pin { + tsadc_int: tsadc-int { + rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>; + }; + tsadc_pin: tsadc-pin { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi_pin { + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; + }; + + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>; + }; + }; + + cif-0 { + dvp_d2d9_m0:dvp-d2d9-m0 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* cif_d5m0 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* cif_d6m0 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* cif_d7m0 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* cif_href */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* cif_vsync */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* cif_clkoutm0 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* cif_clkin */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + cif-1 { + dvp_d2d9_m1:dvp-d2d9-m1 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* cif_d5m1 */ + <2 RK_PC0 4 &pcfg_pull_none>, + /* cif_d6m1 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* cif_d7m1 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* cif_href */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* cif_vsync */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* cif_clkoutm1 */ + <2 RK_PB7 4 &pcfg_pull_none>, + /* cif_clkin */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/rk3358-evb-ddr3-v10-linux.dts b/rk3358-evb-ddr3-v10-linux.dts new file mode 100644 index 0000000..16a6362 --- /dev/null +++ b/rk3358-evb-ddr3-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3358-evb-ddr3.dtsi" +#include "rk3358-linux.dtsi" + +/ { + model = "Rockchip linux RK3358 EVB DDR3 board"; + compatible = "rockchip,rk3358-evb-ddr3-v10-linux", "rockchip,px30", "rockchip,rk3358"; +}; diff --git a/rk3358-evb-ddr3.dtsi b/rk3358-evb-ddr3.dtsi new file mode 100644 index 0000000..104af90 --- /dev/null +++ b/rk3358-evb-ddr3.dtsi @@ -0,0 +1,1077 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +#include +#include +#include +#include +#include "rk3358.dtsi" + +/ { + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <1>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 1>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + /*clocks = <&rk809 1>;*/ + /*clock-names = "ext_clock";*/ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host_vbus: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + enable-active-high; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6210"; + WIFI,host_wake_irq = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 13 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v0_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc3v0_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + power-supply = <&vcc3v3_lcd>; + goodix,rst-gpio = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA5 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c2 { + status = "okay"; + + clock-frequency = <100000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ + pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout_m0>; + port { + ucam_out: endpoint { + remote-endpoint = <&mipi_in_ucam>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_3v0>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_3v0>; + vccio4-supply = <&vcc3v0_pmu>; + vccio5-supply = <&vcc_3v0>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v0_pmu>; + pmuio2-supply = <&vcc3v0_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc1v8_soc>; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + supports-sd; + card-detect-delay = <800>; + ignore-pm-notify; + /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + supports-sdio; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + phy-supply = <&vcc5v0_host_vbus>; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3358-linux.dtsi b/rk3358-linux.dtsi new file mode 100644 index 0000000..97d6434 --- /dev/null +++ b/rk3358-linux.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + compatible = "rockchip,linux", "rockchip,rk3358", "rockchip,px30"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <0>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; diff --git a/rk3358.dtsi b/rk3358.dtsi new file mode 100644 index 0000000..dd12235 --- /dev/null +++ b/rk3358.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "px30.dtsi" + +&cpu0_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; + /delete-node/ opp-1200000000; + /delete-node/ opp-1248000000; + /delete-node/ opp-1296000000; + /delete-node/ opp-1416000000; + /delete-node/ opp-1512000000; + + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <1125000 1125000 1125000>; + clock-latency-ns = <40000>; + }; +}; + +&cru { + assigned-clocks = <&cru PLL_NPLL>; + assigned-clock-rates = <1040000000>; +}; + +&display_subsystem { + status = "disabled"; + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_lvds>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_rgb>; + }; + }; +}; + +&dmc_opp_table { + /delete-node/ opp-194000000; + /delete-node/ opp-328000000; + /delete-node/ opp-450000000; + /delete-node/ opp-528000000; + /delete-node/ opp-666000000; + + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <1050000>; + }; +}; + +&gpu_opp_table { + /delete-node/ opp-200000000; + /delete-node/ opp-300000000; + /delete-node/ opp-400000000; + /delete-node/ opp-480000000; + + opp-520000000 { + opp-hz = /bits/ 64 <520000000>; + opp-microvolt = <1125000>; + }; +}; + +&rgb { + phys = <&video_phy>; + phy-names = "phy"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_m1_rgb_pins>; + pinctrl-1 = <&lcdc_m1_sleep_pins>; +}; + +&pinctrl { + lcdc { + lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { + rockchip,pins = + <3 RK_PA0 1 &pcfg_pull_none_8ma>, /* LCDC_DCLK */ + <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ + <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ + <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ + <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ + <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ + <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ + <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ + <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ + <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ + <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ + <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* LCDC_D17 */ + <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* LCDC_D18 */ + <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* LCDC_D19 */ + <3 RK_PD0 1 &pcfg_pull_none_8ma>, /* LCDC_D20 */ + <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* LCDC_D21 */ + <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* LCDC_D22 */ + <3 RK_PD3 1 &pcfg_pull_none_8ma>; /* LCDC_D23 */ + }; + + lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { + rockchip,pins = + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ + <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ + <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */ + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D23 */ + }; + }; +}; diff --git a/rk3358m-vehicle-ddr3.dtsi b/rk3358m-vehicle-ddr3.dtsi new file mode 100644 index 0000000..1033cdd --- /dev/null +++ b/rk3358m-vehicle-ddr3.dtsi @@ -0,0 +1,1105 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd + * + */ + +#include +#include +#include +#include +#include "rk3358.dtsi" + +/ { + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + backlight_2: backlight-2 { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 10000000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_pwren &lcd0_rst>; + enable-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_HIGH>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <60>; + }; + + /* The THine 827-Q (rgb to dual lvds) don't need driver */ + panel-rgb { + compatible = "simple-panel"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pwdn_rgb>; /* This the pwdn of THine-827-Q */ + power-supply = <&vcc3v3_lcd>; + backlight = <&backlight_2>; + enable-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <0>; + enable-delay-ms = <5>; + disable-delay-ms = <10>; + unprepare-delay-ms = <0>; + + width-mm = <292>; + height-mm = <109>; + + bus-format = ; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <88200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <40>; + hsync-len = <20>; + hback-porch = <24>; + vfront-porch = <5>; + vsync-len = <4>; + vback-porch = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; + + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "AP6212"; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart1_rts>; + pinctrl-1 = <&uart1_rts_gpio>; + BT,reset_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "disabled"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&mipi_en>; + enable-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + + backlight = <&backlight>; + prepare-delay-ms = <0>; + reset-delay-ms = <0>; + init-delay-ms = <80>; + enable-delay-ms = <0>; + disable-delay-ms = <10>; + unprepare-delay-ms = <60>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 ff 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 53 + 15 00 02 05 13 + 15 00 02 06 04 + 15 00 02 07 02 + 15 00 02 08 02 + 15 00 02 09 00 + 15 00 02 0a 00 + 15 00 02 0b 00 + 15 00 02 0c 00 + 15 00 02 0d 00 + 15 00 02 0e 00 + 15 00 02 0f 00 + + 15 00 02 10 00 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 08 + 15 00 02 16 10 + 15 00 02 17 00 + 15 00 02 18 08 + 15 00 02 19 00 + 15 00 02 1a 00 + 15 00 02 1b 00 + 15 00 02 1c 00 + 15 00 02 1d 00 + 15 00 02 1e c0 + 15 00 02 1f 80 + + 15 00 02 20 02 + 15 00 02 21 09 + 15 00 02 22 00 + 15 00 02 23 00 + 15 00 02 24 00 + 15 00 02 25 00 + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 55 + 15 00 02 29 03 + 15 00 02 2a 00 + 15 00 02 2b 00 + 15 00 02 2c 00 + 15 00 02 2d 00 + 15 00 02 2e 00 + 15 00 02 2f 00 + + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 00 + 15 00 02 33 00 + 15 00 02 34 04 + 15 00 02 35 05 + 15 00 02 36 05 + 15 00 02 37 00 + 15 00 02 38 3c + 15 00 02 39 35 + 15 00 02 3a 00 + 15 00 02 3b 40 + 15 00 02 3c 00 + 15 00 02 3d 00 + 15 00 02 3e 00 + 15 00 02 3f 00 + + 15 00 02 40 00 + 15 00 02 41 88 + 15 00 02 42 00 + 15 00 02 43 00 + 15 00 02 44 1f + + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 ab + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5a 89 + 15 00 02 5b ab + 15 00 02 5c cd + 15 00 02 5d ef + 15 00 02 5e 03 + 15 00 02 5f 14 + + 15 00 02 60 15 + 15 00 02 61 0c + 15 00 02 62 0d + 15 00 02 63 0e + 15 00 02 64 0f + 15 00 02 65 10 + 15 00 02 66 11 + 15 00 02 67 08 + 15 00 02 68 02 + 15 00 02 69 0a + 15 00 02 6a 02 + 15 00 02 6b 02 + 15 00 02 6c 02 + 15 00 02 6d 02 + 15 00 02 6e 02 + 15 00 02 6f 02 + + 15 00 02 70 02 + 15 00 02 71 02 + 15 00 02 72 06 + 15 00 02 73 02 + 15 00 02 74 02 + 15 00 02 75 14 + 15 00 02 76 15 + 15 00 02 77 0f + 15 00 02 78 0e + 15 00 02 79 0d + 15 00 02 7a 0c + 15 00 02 7b 11 + 15 00 02 7c 10 + 15 00 02 7d 06 + 15 00 02 7e 02 + 15 00 02 7f 0a + + 15 00 02 80 02 + 15 00 02 81 02 + 15 00 02 82 02 + 15 00 02 83 02 + 15 00 02 84 02 + 15 00 02 85 02 + 15 00 02 86 02 + 15 00 02 87 02 + 15 00 02 88 08 + 15 00 02 89 02 + 15 00 02 8a 02 + + 39 00 04 ff 98 81 04 + 15 00 02 00 80 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 66 fe + 15 00 02 82 15 + 15 00 02 84 15 + 15 00 02 85 15 + 15 00 02 3a 24 + 15 00 02 32 ac + 15 00 02 8c 80 + 15 00 02 3c f5 + 15 00 02 88 33 + + 39 00 04 ff 98 81 01 + 15 00 02 22 0a + 15 00 02 31 00 + 15 00 02 53 78 + 15 00 02 50 5b + 15 00 02 51 5b + 15 00 02 60 20 + 15 00 02 61 00 + 15 00 02 62 0d + 15 00 02 63 00 + + 15 00 02 a0 00 + 15 00 02 a1 10 + 15 00 02 a2 1c + 15 00 02 a3 13 + 15 00 02 a4 15 + 15 00 02 a5 26 + 15 00 02 a6 1a + 15 00 02 a7 1d + 15 00 02 a8 67 + 15 00 02 a9 1c + 15 00 02 aa 29 + 15 00 02 ab 5b + 15 00 02 ac 26 + 15 00 02 ad 28 + 15 00 02 ae 5c + 15 00 02 af 30 + 15 00 02 b0 31 + 15 00 02 b1 2e + 15 00 02 b2 32 + 15 00 02 b3 00 + + 15 00 02 c0 00 + 15 00 02 c1 10 + 15 00 02 c2 1c + 15 00 02 c3 13 + 15 00 02 c4 15 + 15 00 02 c5 26 + 15 00 02 c6 1a + 15 00 02 c7 1d + 15 00 02 c8 67 + 15 00 02 c9 1c + 15 00 02 ca 29 + 15 00 02 cb 5b + 15 00 02 cc 26 + 15 00 02 cd 28 + 15 00 02 ce 5c + 15 00 02 cf 30 + 15 00 02 d0 31 + 15 00 02 d1 2e + 15 00 02 d2 32 + 15 00 02 d3 00 + 39 00 04 ff 98 81 00 + 05 00 01 11 + 05 01 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hfront-porch = <40>; + hsync-len = <10>; + hback-porch = <40>; + vfront-porch = <22>; + vsync-len = <4>; + vback-porch = <11>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopb { + status = "disabled"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&route_dsi { + connect = <&vopb_out_dsi>; + status = "disabled"; +}; + +&rgb { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + /delete-property/ phys; + /delete-property/ phy-names; + + pinctrl-0 = <&lcdc_m0_rgb_pins>; + pinctrl-1 = <&lcdc_m0_sleep_pins>; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "okay"; +}; + +&rgb_in_vopl { + status = "disabled"; +}; + +&route_rgb { + connect = <&vopb_out_rgb>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + supports-emmc; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_1v0: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vdd_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-off; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc5v0_host: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host"; + }; + + vcc3v3_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc3v3_lcd"; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S1_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc3v3_pmu>; + vccio5-supply = <&vcc_1v8>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam: endpoint@1 { + reg = <1>; + // remote-endpoint = <&ucam_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + supports-sdio; + ignore-pm-notify; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + status = "okay"; + phy-supply = <&vcc5v0_host>; + }; + + u2phy_otg: otg-port { + status = "okay"; + }; +}; + +&usb20_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&pinctrl { + lcd { + lcd0_pwren: lcd0-pwren { + rockchip,pins = <1 RK_PD6 RK_FUNC_GPIO &pcfg_output_high>; + }; + lcd0_rst: lcd0-rst { + rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_output_high>; + }; + mipi_en: mipi-en { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; + }; + pwdn_rgb: pwdn-rgb { + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA4 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3358m-vehicle-v10.dts b/rk3358m-vehicle-v10.dts new file mode 100644 index 0000000..e992955 --- /dev/null +++ b/rk3358m-vehicle-v10.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3358m-vehicle-ddr3.dtsi" +#include "rk3358-linux.dtsi" + +/ { + model = "Rockchip linux RK3358M VEHICLE DDR3 board"; + compatible = "rockchip,rk3358m-vehicle-ddr3-v10-linux", "rockchip,px30", "rockchip,rk3358"; + + memory: memory { + device_type = "memory"; + reg = <0x00000000 0x0 0x0 0x20000000>; + }; + + ramdisk: ramdisk { + compatible = "rockchip,ramdisk"; + memory-region = <&ramdisk_r>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + atf: atf@40000 { + reg = <0x0 0x00000 0x0 0x200000>; + no-map; + }; + + ramdisk_r: ramdisk_r@4000000 { + // Do not exceed 132MB which used by TEE + reg = <0x0 0x4000000 0x0 0x4000000>; + }; + }; +}; diff --git a/rk3368-808-evb.dts b/rk3368-808-evb.dts new file mode 100644 index 0000000..7e803a8 --- /dev/null +++ b/rk3368-808-evb.dts @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3368-808.dtsi" + +/ { + model = "Rockchip rk3368 808 evb board"; + compatible = "rockchip,rk3368-808-evb", "rockchip,rk3368"; +}; + +&chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 androidboot.selinux=permissive init=/init kpti=0"; +}; + +&fiq_debugger { + status = "okay"; +}; + +&cif { + status = "disabled"; +}; + +&cif_clkout { + /* cif_clkout */ + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>; +}; + +&dmc { + vop-dclk-mode = <1>; + status = "okay"; +}; + +&isp_dvp_d2d9 { + rockchip,pins = + /* cif_data4 ... cif_data9 */ + <1 RK_PA2 1 &pcfg_pull_down>, + <1 RK_PA3 1 &pcfg_pull_down>, + <1 RK_PA4 1 &pcfg_pull_down>, + <1 RK_PA5 1 &pcfg_pull_down>, + <1 RK_PA6 1 &pcfg_pull_down>, + <1 RK_PA7 1 &pcfg_pull_down>, + /* cif_sync, cif_href */ + <1 RK_PB0 1 &pcfg_pull_down>, + <1 RK_PB1 1 &pcfg_pull_down>, + /* cif_clkin */ + <1 RK_PB2 1 &pcfg_pull_down>; +}; + +&isp_dvp_d10d11 { + rockchip,pins = + /* cif_data10, cif_data11 */ + <1 RK_PB6 1 &pcfg_pull_down>, + <1 RK_PB7 1 &pcfg_pull_down>; +}; + +&i2c3 { + status = "okay"; + + gc2145: gc2145@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + pinctrl-names = "default"; + pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>; + power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&isp_dvp_in>; + }; + }; + }; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&isp { + status = "disabled"; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&pinctrl { + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; +}; + +&rkisp1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_dvp_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + + }; +}; + +/* + * In sleep mode, should be close vcca_33 and vcc_lan, + * but due to small defects in hardware settings and + * the system sleeps and wakes up, 4g module can not disconnect the network, + * so system sleep mode cannot be turned off vcca_33 and vcc_lan. + * This configuration will result in increased power consumption, + * please configure according to the actual needs of the project. + */ +&vcca_33 { + regulator-state-mem { + regulator-on-in-suspend; + }; +}; + +&vcc_lan { + regulator-state-mem { + regulator-on-in-suspend; + }; +}; diff --git a/rk3368-808.dtsi b/rk3368-808.dtsi new file mode 100644 index 0000000..fdea0c7 --- /dev/null +++ b/rk3368-808.dtsi @@ -0,0 +1,982 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" + +/ { + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch>; + }; + codec { + sound-dai = <&rt5640>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s_8ch>; + }; + codec { + sound-dai = <&hdmi>; + }; + }; + }; + + rk_headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc_lcd: vcc-lcd-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pwr>; + regulator-name = "vcc_lcd"; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + panel { + compatible = "samsung,lsl070nl01", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <120>; + prepare-delay-ms = <2>; + unprepare-delay-ms = <20>; + disable-delay-ms = <50>; + width-mm = <68>; + height-mm = <121>; + rockchip,data-mapping = "vesa"; + rockchip,data-width = <24>; + rockchip,output = "lvds"; + status = "disabled"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1024000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + sdio_vref = <1800>; //1800mv or 3300mv + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + + /* BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; */ + BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + + rk_modem: rk-modem { + compatible="4g-modem-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <<e_vbat <e_power_en <e_reset>; + 4G,vbat-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + 4G,power-gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + 4G,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + logic-supply = <&vdd_log>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_log>; + devfreq-events = <&dfi>; + upthreshold = <60>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 600000 + SYS_STATUS_REBOOT 600000 + SYS_STATUS_SUSPEND 240000 + SYS_STATUS_VIDEO_1080P 396000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_PERFORMANCE 600000 + SYS_STATUS_BOOST 396000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 528000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 582 240000 + 583 99999 396000 + >; + auto-min-freq = <240000>; + auto-freq-en = <0>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&sdmmc { + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "disabled"; +}; + +&sdio0 { + clock-frequency = <100000000>; + clock-freq-min-max = <200000 100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + status = "okay"; + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + rockchip,system-power-controller; + wakeup-source; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcca_18: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_18"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + +}; + +&i2c1 { + status = "okay"; + + rt5640: rt5640@1c { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + /* spk-con-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; */ + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + }; + + mpu6500_acc: mpu_acc@68 { + status = "okay"; + compatible = "mpu6500_acc"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + reg = <0x68>; + irq-gpio = <&gpio2 17 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <5>; + + }; + + mpu6500_gyro: mpu_gyro@68 { + status = "okay"; + compatible = "mpu6500_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <5>; + }; + + ak8963_compass: ak8963_compass@d { + status = "okay"; + compatible = "ak8963"; + pinctrl-names = "default"; + pinctrl-0 = <&ak8963_irq_gpio>; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio2 18 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <7>; + }; +}; + +&i2c2 { + status = "okay"; + + gslx680@40 { + compatible = "gslX6801"; + reg = <0x40>; + screen_max_x = <1920>; + screen_max_y = <1200>; + power-supply = <&vcc_lcd>; + touch-gpio = <&gpio0 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + +}; + +&i2c3 { + status = "okay"; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_2ch_bus>; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcca_18>; + dvp-supply = <&vcc_18>; + flash0-supply = <&vcc18_flash>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_io>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vcc_io>; + vop-supply = <&vcca_33>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + vbus-supply = <&vcc_otg_vbus>; + }; + + u2phy_host: host-port { + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&edp { + status = "disabled"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "sitronix,st7703", "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + prepare-delay-ms = <2>; + reset-delay-ms = <1>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&st7703_timing>; + + st7703_timing: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&vdd_cpu>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&route_hdmi { + status = "okay"; +}; + +&pinctrl { + camera { + camera_pwr: camera-pwr { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_pwr: lcd-pwr { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + i2s { + i2s_2ch_bus: i2s-2ch-bus { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ak8963 { + ak8963_irq_gpio: ak8963_irq_gpio { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rk-modem { + lte_vbat: lte-vbat { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lte_power_en: lte-power-en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lte_reset: lte-reset { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3368-android.dtsi b/rk3368-android.dtsi new file mode 100644 index 0000000..c6d8d55 --- /dev/null +++ b/rk3368-android.dtsi @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 firmware_class.path=/system/vendor/firmware"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + interrupts = ; /* signal irq */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + ion { + compatible = "rockchip,ion"; + #address-cells = <1>; + #size-cells = <0>; + + cma-heap { + reg = <0x00000000 0x2800000>; + }; + + system-heap { + }; + }; + + firmware { + firmware_android: android {}; + + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + rga@ff920000 { + compatible = "rockchip,rga2"; + dev_mode = <1>; + reg = <0x0 0xff920000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + status = "okay"; + }; +}; + +&cluster1_opp { + rockchip,avs = <1>; +}; + +&display_subsystem { + status = "okay"; + + logo-memory-region = <&drm_logo>; + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_dsi>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_edp>; + }; + + route_hdmi: route-hdmi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_hdmi>; + }; + + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_lvds>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vop_out_rgb>; + }; + + }; +}; + +&dsi { + panel@0 { + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&hevc { + status = "okay"; +}; + +&hevc_mmu { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&mailbox { + status = "okay"; +}; + +&mailbox_scpi { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&vop { + support-multi-area; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&isp { + status = "okay"; +}; + +&isp_mmu { + status = "okay"; +}; + +&cif { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&vip_mmu { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&pinctrl { + isp { + cif_clkout: cif-clkout { + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout + }; + + isp_dvp_d2d9: isp-dvp-d2d9 { + rockchip,pins = + <1 RK_PA0 1 &pcfg_pull_none>,//cif_data2 + <1 RK_PA1 1 &pcfg_pull_none>,//cif_data3 + <1 RK_PA2 1 &pcfg_pull_none>,//cif_data4 + <1 RK_PA3 1 &pcfg_pull_none>,//cif_data5 + <1 RK_PA4 1 &pcfg_pull_none>,//cif_data6 + <1 RK_PA5 1 &pcfg_pull_none>,//cif_data7 + <1 RK_PA6 1 &pcfg_pull_none>,//cif_data8 + <1 RK_PA7 1 &pcfg_pull_none>,//cif_data9 + <1 RK_PB0 1 &pcfg_pull_none>,//cif_sync + <1 RK_PB1 1 &pcfg_pull_none>,//cif_href + <1 RK_PB2 1 &pcfg_pull_none>,//cif_clkin + <1 RK_PB3 1 &pcfg_pull_none>;//cif_clkout + }; + + isp_dvp_d0d1: isp-dvp-d0d1 { + rockchip,pins = + <1 RK_PB4 1 &pcfg_pull_none>,//cif_data0 + <1 RK_PB5 1 &pcfg_pull_none>;//cif_data1 + }; + + isp_dvp_d10d11:isp_d10d11 { + rockchip,pins = + <1 RK_PB6 1 &pcfg_pull_none>,//cif_data10 + <1 RK_PB7 1 &pcfg_pull_none>;//cif_data11 + }; + + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + <1 RK_PB4 1 &pcfg_pull_none>,//cif_data0 + <1 RK_PB5 1 &pcfg_pull_none>,//cif_data1 + <1 RK_PA0 1 &pcfg_pull_none>,//cif_data2 + <1 RK_PA1 1 &pcfg_pull_none>,//cif_data3 + <1 RK_PA2 1 &pcfg_pull_none>,//cif_data4 + <1 RK_PA3 1 &pcfg_pull_none>,//cif_data5 + <1 RK_PA4 1 &pcfg_pull_none>,//cif_data6 + <1 RK_PA5 1 &pcfg_pull_none>;//cif_data7 + }; + + isp_dvp_d4d11: isp-dvp-d4d11 { + rockchip,pins = + <1 RK_PA2 1 &pcfg_pull_none>,//cif_data4 + <1 RK_PA3 1 &pcfg_pull_none>,//cif_data5 + <1 RK_PA4 1 &pcfg_pull_none>,//cif_data6 + <1 RK_PA5 1 &pcfg_pull_none>,//cif_data7 + <1 RK_PA6 1 &pcfg_pull_none>,//cif_data8 + <1 RK_PA7 1 &pcfg_pull_none>,//cif_data9 + <1 RK_PB6 1 &pcfg_pull_none>,//cif_data10 + <1 RK_PC1 1 &pcfg_pull_none>;//cif_data11 + }; + + isp_shutter: isp-shutter { + rockchip,pins = + <3 RK_PC3 2 &pcfg_pull_none>, //SHUTTEREN + <3 RK_PC6 2 &pcfg_pull_none>;//SHUTTERTRIG + }; + + isp_flash_trigger: isp-flash-trigger { + rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>; //ISP_FLASHTRIGOU + }; + + isp_prelight: isp-prelight { + rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG + }; + + isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU + }; + }; +}; diff --git a/rk3368-cif-sensor.dtsi b/rk3368-cif-sensor.dtsi new file mode 100644 index 0000000..7d2aac2 --- /dev/null +++ b/rk3368-cif-sensor.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +#include "../../../../../drivers/soc/rockchip/rk_camera_sensor_info.h" + +/{ + cif_sensor: cif_sensor { + compatible = "rockchip,sensor"; + status = "okay"; + + tp2825 { + status = "okay"; + is_front = <0>; + powerdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio1 13 IRQ_TYPE_EDGE_FALLING>; + pwdn_active = ; + mir = <0>; + flash_attach = <1>; + flash_active = <1>; + resolution = ; + powerup_sequence = ; + orientation = <0>; + i2c_add = ; + i2c_chl = <3>; + cif_chl = <0>; + ad_chl = <0>; // 0 ~ 4; + mclk_rate = <24>; + rockchip,camera-module-defrect0 = <960 480 0 4 960 472>; + rockchip,camera-module-interface0 = "cvbs_ntsc"; + rockchip,camera-module-defrect1 = <960 576 0 4 960 568>; + rockchip,camera-module-interface1 = "cvbs_pal"; + rockchip,camera-module-defrect2 = <1280 720 8 20 1280 720>; + rockchip,camera-module-interface2 = "bt601_8_pp"; + rockchip,camera-module-channel = <4 0>; + }; + }; +}; diff --git a/rk3368-evb-act8846.dts b/rk3368-evb-act8846.dts new file mode 100644 index 0000000..160f2c7 --- /dev/null +++ b/rk3368-evb-act8846.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2015 Caesar Wang + */ + +/dts-v1/; +#include "rk3368-evb.dtsi" + +/ { + model = "Rockchip RK3368 EVB with ACT8846 pmic"; + compatible = "rockchip,rk3368-evb-act8846", "rockchip,rk3368"; +}; + +&i2c0 { + clock-frequency = <400000>; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + status = "okay"; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_io>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "VCC_DDR"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "VCC_IO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "VDD_LOG"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "VCC_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "VCCIO_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "VDD10_LCD"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "VCCA_CODEC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcca_tp: REG8 { + regulator-name = "VCCA_TP"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vccio_pmu: REG9 { + regulator-name = "VCCIO_PMU"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_10: REG10 { + regulator-name = "VDD_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "VCC_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "VCC18_LCD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; diff --git a/rk3368-evb.dtsi b/rk3368-evb.dtsi new file mode 100644 index 0000000..87fabc6 --- /dev/null +++ b/rk3368-evb.dtsi @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2015 Caesar Wang + */ + +#include +#include +#include "rk3368.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; + pwm-delay-us = <10000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + wakeup-source; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + }; + }; + + /* supplies both host and otg */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rmii"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + backlight { + bl_en: bl-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc-clk { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc-cmd { + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_rst: bt-rst { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3368-geekbox.dts b/rk3368-geekbox.dts new file mode 100644 index 0000000..46357d1 --- /dev/null +++ b/rk3368-geekbox.dts @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Andreas Färber + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "GeekBox"; + compatible = "geekbuying,geekbox", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + blue_led: led-0 { + gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "geekbox:blue:led"; + default-state = "on"; + }; + + red_led: led-1 { + gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + label = "geekbox:red:led"; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + non-removable; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + interrupt-parent = <&gpio0>; + interrupts = ; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcc33_lcd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_lcd"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcca_18: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_18"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + }; + }; + }; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3368-lion-haikou.dts b/rk3368-lion-haikou.dts new file mode 100644 index 0000000..7fcb1ea --- /dev/null +++ b/rk3368-lion-haikou.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "rk3368-lion.dtsi" + +/ { + model = "Theobroma Systems RK3368-uQ7 Baseboard"; + compatible = "tsd,rk3368-lion-haikou", "rockchip,rk3368"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + i2cmux2 { + i2c@0 { + eeprom: eeprom@50 { + compatible = "atmel,24c01"; + pagesize = <8>; + reg = <0x50>; + }; + }; + }; + + leds { + pinctrl-0 = <&module_led_pins>, <&sd_card_led_pin>; + + sd_card_led: led-3 { + label = "sd_card_led"; + gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio2 RK_PB3 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <25000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi2 { + cs-gpios = <0>, <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart1 { + /* alternate function of GPIO5/6 */ + status = "disabled"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&haikou_pin_hog>; + + hog { + haikou_pin_hog: haikou-pin-hog { + rockchip,pins = + /* LID_BTN */ + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + /* BATLOW# */ + <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + /* BIOS_DISABLE# */ + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sd_card_led_pin: sd-card-led-pin { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_cd_pin: sdmmc-cd-pin { + rockchip,pins = + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3368-lion.dtsi b/rk3368-lion.dtsi new file mode 100644 index 0000000..24d28be --- /dev/null +++ b/rk3368-lion.dtsi @@ -0,0 +1,314 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "rk3368.dtsi" + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + i2cmux1 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c1>; + mux-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + + /* Q7_GPO_I2C */ + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* Q7_SMB */ + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + i2cmux2 { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c2>; + mux-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + + /* Q7_LVDS_BLC_I2C */ + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; + }; + + /* Q7_GP2_I2C */ + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pins>; + + module_led1: led-1 { + label = "module_led1"; + gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + + module_led2: led-2 { + label = "module_led2"; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + clock-frequency = <150000000>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc33_io>; + vqmmc-supply = <&vcc18_io>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc33_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + snps,reset-gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + tx_delay = <0x10>; + rx_delay = <0x10>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>, <&pmic_sleep>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_sys>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: DCDC_REG2 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + }; + + vcc33_io: DCDC_REG4 { + regulator-name = "vcc33_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc33_video: LDO_REG2 { + regulator-name = "vcc33_video"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd10_pll: LDO_REG3 { + regulator-name = "vdd10_pll"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc18_io: LDO_REG4 { + regulator-name = "vcc18_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + vdd10_video: LDO_REG6 { + regulator-name = "vdd10_video"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc18_video: LDO_REG8 { + regulator-name = "vcc18_video"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&pinctrl { + leds { + module_led_pins: module-led-pins { + rockchip,pins = + <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; +}; + +&spi1 { + status = "okay"; + + norflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3368-orion-r68-meta.dts b/rk3368-orion-r68-meta.dts new file mode 100644 index 0000000..ecce16e --- /dev/null +++ b/rk3368-orion-r68-meta.dts @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Matthias Brugger + */ + +/dts-v1/; +#include +#include "rk3368.dtsi" + +/ { + model = "Rockchip Orion R68"; + compatible = "tronsmart,orion-r68-meta", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + wakeup-source; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "GPIO Power"; + linux,code = ; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + red_led: led-0 { + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + label = "orion:red:led"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + default-state = "on"; + }; + + blue_led: led-1 { + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + label = "orion:blue:led"; + pinctrl-names = "default"; + pinctrl-0 = <&stby_pwren>; + default-state = "off"; + }; + }; + + vcc_18: vcc18-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + /* supplies both host and otg */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_io: vcc-io-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sd: vcc-sd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sd"; + gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vccio_sd: vcc-io-sd-regulator { + compatible = "regulator-fixed"; + regulator-name= "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vccio_wl: vccio-wl-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vdd_10: vdd-10-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-pwrseq = <&emmc_pwrseq>; + mmc-hs200-1_2v; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + /* rtc_int is not connected */ + }; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc-clk { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc-cmd { + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + leds { + stby_pwren: stby-pwren { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_ctl: led-ctl { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up_drv_8ma>, + <2 RK_PA6 1 &pcfg_pull_up_drv_8ma>, + <2 RK_PA7 1 &pcfg_pull_up_drv_8ma>, + <2 RK_PB0 1 &pcfg_pull_up_drv_8ma>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + clock-frequency = <50000000>; + max-frequency = <50000000>; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3368-p9-avb.dts b/rk3368-p9-avb.dts new file mode 100644 index 0000000..6a97178 --- /dev/null +++ b/rk3368-p9-avb.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3368-p9.dtsi" + +/ { + model = "Rockchip rk3368 p9 avb board"; + compatible = "rockchip,p9-avb", "rockchip,rk3368"; +}; + +&firmware_android { + compatible = "android,firmware"; + boot_devices = "ff0f0000.dwmmc,ff400000.nandc"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,avb"; + }; + }; +}; + +&chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 androidboot.selinux=permissive init=/init kpti=0"; +}; diff --git a/rk3368-p9.dts b/rk3368-p9.dts new file mode 100644 index 0000000..29658be --- /dev/null +++ b/rk3368-p9.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3368-p9.dtsi" + +/ { + model = "Rockchip rk3368 p9 board"; + compatible = "rockchip,p9", "rockchip,rk3368"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + diff --git a/rk3368-p9.dtsi b/rk3368-p9.dtsi new file mode 100644 index 0000000..1bd9b91 --- /dev/null +++ b/rk3368-p9.dtsi @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" + +/ { + es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk-es8316-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&es8316>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + rk_key: rockchip-key { + compatible = "rockchip,key"; + status = "okay"; + + io-channels = <&saradc 1>; + + vol-up-key { + linux,code = <115>; + label = "volume up"; + rockchip,adc_value = <1>; + }; + + vol-down-key { + linux,code = <114>; + label = "volume down"; + rockchip,adc_value = <170>; + }; + + power-key { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + /* wifi_chip_type - wifi chip define + * ap6210, ap6330, ap6335 + * rtl8188eu, rtl8723bs, rtl8723bu + * esp8089 + */ + wifi_chip_type = "ap6210"; + sdio_vref = <1800>; //1800mv or 3300mv + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + + //BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&cpu_l0 { + cpu-supply = <&syr827>; +}; + +&cpu_l1 { + cpu-supply = <&syr827>; +}; + +&cpu_l2 { + cpu-supply = <&syr827>; +}; + +&cpu_l3 { + cpu-supply = <&syr827>; +}; + +&cpu_b0 { + cpu-supply = <&syr827>; +}; + +&cpu_b1 { + cpu-supply = <&syr827>; +}; + +&cpu_b2 { + cpu-supply = <&syr827>; +}; + +&cpu_b3 { + cpu-supply = <&syr827>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&nandc0 { + status = "disabled"; +}; + +&sdmmc { + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "disabled"; +}; + +&sdio0 { + clock-frequency = <50000000>; + clock-freq-min-max = <200000 50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + syr827: syr827@40 { + compatible = "silergy,syr827"; + status = "okay"; + reg = <0x40>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + status = "okay"; + reg = <0x1c>; + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_pmu: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_wl: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + + hdmi_switch: HDMI_SWITCH { + regulator-always-on; + regulator-boot-on; + regulator-name = "hdmi_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk818-battery"; + pinctrl-names = "default"; + pinctrl-0 = <&dc_irq_gpio>; + ocv_table = < + 3400 3650 3693 3707 3731 3749 3760 + 3770 3782 3796 3812 3829 3852 3882 + 3915 3951 3981 4047 4086 4132 4182>; + design_capacity = <8650>; + design_qmax = <8800>; + bat_res = <85>; + max_input_current = <2000>; + max_chrg_current = <1800>; + max_chrg_voltage = <4200>; + sleep_enter_current = <600>; + sleep_exit_current = <600>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3850>; + fb_temperature = <115>; + sample_res = <20>; + max_soc_offset = <60>; + energy_mode = <0>; + monitor_sec = <5>; + virtual_power = <0>; + power_dc2otg = <1>; + support_usb_adp = <1>; + support_dc_adp = <1>; + dc_det_gpio = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + es8316: es8316@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + spk-con-gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + }; +}; + +&i2c2 { + status = "okay"; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio0 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + max-x = <1920>; + max-y = <1200>; + tp-size = <89>; + status = "okay"; + tp-supply = <&vcc_tp>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 14 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <7>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <7>; + }; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + reg = <0x68>; + irq-gpio = <&gpio3 14 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <1 0 0 0 1 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <1>; + support-hw-poweroff = <1>; + mpu-debug = <1>; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vccio_pmu>; + vop-supply = <&vccio_pmu>; +}; + +&pwm0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <120>; + enable-delay-ms = <200>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <145000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <16>; + hfront-porch = <24>; + vback-porch = <10>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&syr827>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel_gpio: vsel-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3368-px5-evb-android.dts b/rk3368-px5-evb-android.dts new file mode 100644 index 0000000..a91fd25 --- /dev/null +++ b/rk3368-px5-evb-android.dts @@ -0,0 +1,957 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" +#include "rk3368-cif-sensor.dtsi" +#include +#include + +/ { + model = "Rockchip PX5 EVB V11"; + compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1c0000 firmware_class.path=/system/vendor/firmware"; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <4>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <0>; + /* Only 115200 and 1500000 */ + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + interrupts = ; + }; + + firmware { + android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/platform/ff0f0000.dwmmc/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/ff0f0000.dwmmc/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait"; + }; + }; + }; + }; + + xin32k: xin32k { + status = "okay"; + compatible = "pwm-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + pwms = <&pwm1 0 30518 0>; /* 1 / 30518 ns = 32.7675 KHz */ + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; /* GPIO3_A5 */ + }; + + es8396-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,es8396-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Microphone Headset", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "MIC", "Microphone Jack", + "DMIC", "Microphone Headset", + "Headphone Jack", "LOUTP", + "Headphone Jack", "ROUTN"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&es8396>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + }; + + rk_key: rockchip-key { + compatible = "rockchip,key"; + status = "okay"; + + io-channels = <&saradc 1>; + + vol-up-key { + linux,code = <115>; + label = "volume up"; + rockchip,adc_value = <1>; + }; + + vol-down-key { + linux,code = <114>; + label = "volume down"; + rockchip,adc_value = <170>; + }; + + power-key { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + + menu-key { + linux,code = <59>; + label = "menu"; + rockchip,adc_value = <355>; + }; + + home-key { + linux,code = <102>; + label = "home"; + rockchip,adc_value = <746>; + }; + + back-key { + linux,code = <158>; + label = "back"; + rockchip,adc_value = <560>; + }; + + camera-key { + linux,code = <212>; + label = "camera"; + rockchip,adc_value = <450>; + }; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + + wifi_chip_type = "rtl8723ds"; + sdio_vref = <1800>; /*1800mv or 3300mv*/ + WIFI,host_wake_irq = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + WIFI,vbat_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + + keep_bt_power_on; + BT,power_gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>; /* GPIO3_A4 */ + BT,reset_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; /* GPIO3_A2 */ + BT,wake_gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; /* GPIO3_A7 */ + BT,wake_host_irq = <&gpio3 3 GPIO_ACTIVE_HIGH>; /* GPIO3_A3 */ + + status = "okay"; + }; + + gpio_det: gpio-det { + compatible = "gpio-detection"; + status = "okay"; + + pinctrl-0 = <&gpio3_b1 &gpio3_b2>; + pinctrl-names = "default"; + + car-reverse { + car-reverse-gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + linux,debounce-ms = <5>; + label = "car-reverse"; + gpio,wakeup; + }; + + car-acc { + car-acc-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + linux,debounce-ms = <5>; + label = "car-acc"; + gpio,wakeup; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-low; + gpio = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + vcc18_lcd_n: vcc18-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc18_lcd_n"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <70000>; + vin-supply = <&vcc_18>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + panel { + compatible = "samsung,lsl070nl01", "simple-panel"; + power-supply = <&vcc33_lcd>; + backlight = <&backlight>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <120>; + bus-format = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <48000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <90>; + hfront-porch = <90>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <90>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&cif_sensor { + status = "okay"; +}; + +&cluster0_opp { + rockchip,threshold-freq = <408000>; + rockchip,freq-limit; +}; + +&cluster1_opp { + rockchip,threshold-freq = <1416000>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + logic-supply = <&vdd_log>; +}; + +&isp { + pinctrl-names = + "isp_mipi_fl_prefl", "isp_flash_as_gpio", + "isp_flash_as_trigger_out"; + pinctrl-0 = <&isp_prelight>; + pinctrl-1 = <&isp_flash_trigger_as_gpio>; + pinctrl-2 = <&isp_flash_trigger>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + clock-frequency = <150000000>; + keep-power-in-suspend; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; +}; + +&sdmmc { + status = "okay"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&sdio0 { + status = "okay"; + clock-frequency = <50000000>; + clock-freq-min-max = <200000 50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + regulator-ramp-delay = <6000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + avdd_33: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avdd_33"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc33_lcd: SWITCH_REG2 { + regulator-boot-on; + regulator-name = "vcc33_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + bma2x2: bma250@18 { + compatible = "bma2xx_acc"; + status = "okay"; + reg = <0x18>; + type = ; + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_c1>; + irq-gpio = <&gpio2 17 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <1>; + poll_delay_ms = <200>; + layout = <6>; + reprobe_en = <1>;/* this sensor need to be probe again */ + }; + + ls_stk3410: light@48 { + compatible = "ls_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3410: proximity@48 { + compatible = "ps_stk3410"; + status = "okay"; + reg = <0x48>; + type = ; + pinctrl-names = "default"; + pinctrl-0 = <&gpio2_c3>; + irq-gpio = <&gpio2 19 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x4 2:x16 3:x64 */ + ps_led_current = <3>; /* 0:12.5mA 1:25mA 2:50mA 3:100mA */ + poll_delay_ms = <100>; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <200000>; + + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio3>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING>; + power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio3 RK_PD4 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + max-x = <1024>; + max-y = <600>; + tp-size = <910>; + tp-supply = <&vcc_io>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <200000>; + + fm1288: fm1288@60{ + compatible = "fm1288"; + reg = <0x60>; + pwd-gpios = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + bypass-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + es8396: es8396@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "es8396"; + reg = <0x10>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + spk-con-gpio = <&gpio2 RK_PC7 GPIO_ACTIVE_HIGH>; + lineout-con-gpio = <&gpio0 RK_PD7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_bus>; +}; + +&io_domains { + status = "okay"; + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_io>; +}; + +&pmu_io_domains { + status = "okay"; + pmu-supply = <&vcc_io>; + vop-supply = <&vcca_33>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + vop-dclk-mode = <1>; + center-supply = <&vdd_log>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 600000 + SYS_STATUS_REBOOT 600000 + SYS_STATUS_SUSPEND 192000 + SYS_STATUS_VIDEO_1080P 600000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_PERFORMANCE 600000 + SYS_STATUS_BOOST 600000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 600000 + >; + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&route_lvds { + status = "okay"; +}; + +&mailbox { + status = "okay"; +}; + +&mailbox_scpi { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&thermal_zones { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&vdd_cpu>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer &uart1_cts>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&uart4 { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gpio0_gpio { + gpio0_c7: gpio0-c7 { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + gpio0_a3: gpio0-a3 { + rockchip,pins = <0 RK_PA3 3 &pcfg_pull_none>; + }; + gpio0_c2: gpio0-c2 { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + gpio0_c3: gpio0-c3 { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio0_c1: gpio0-c1 { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio2_c1: gpio2-c1 { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + gpio2_c3: gpio2-c3 { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + gpio3_b1: gpio3-b1 { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + gpio3_b2: gpio3-b2 { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + i2s { + i2s_8ch_bus: i2s-8ch-bus { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3368-px5-evb.dts b/rk3368-px5-evb.dts new file mode 100644 index 0000000..5ffd7b4 --- /dev/null +++ b/rk3368-px5-evb.dts @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "Rockchip PX5 EVB"; + compatible = "rockchip,px5-evb", "rockchip,px5", "rockchip,rk3368"; + + chosen { + stdout-path = "serial4:115200n8"; + }; + + memory@0 { + reg = <0x0 0x0 0x0 0x40000000>; + device_type = "memory"; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + wakeup-source; + }; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + mmc-hs200-1_8v; + no-sdio; + no-sd; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_flash>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&pmic_sleep>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vcc18_flash: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_flash"; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + avdd_33: LDO_REG4 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avdd_33"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vcc_sd: SWITCH_REG1 { + regulator-name = "vcc_sd"; + }; + + vcc33_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lcd"; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma250"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = ; + }; +}; + +&i2c2 { + status = "okay"; + + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&gpio3>; + interrupts = ; + power-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + silead,max-fingers = <5>; + }; +}; + +&pinctrl { + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_sleep: pmic-sleep { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdmmc { + status = "okay"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + no-sdio; + sd-uhs-sdr12; + sd-uhs-sdr25; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_bus4>, <&sdmmc_cd>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&tsadc { + status = "okay"; + rockchip,hw-tshut-mode = <0>; /* CRU */ + rockchip,hw-tshut-polarity = <1>; /* high */ +}; + +&uart4 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3368-r88-dcdc.dts b/rk3368-r88-dcdc.dts new file mode 100644 index 0000000..b1700e5 --- /dev/null +++ b/rk3368-r88-dcdc.dts @@ -0,0 +1,640 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" +#include + +/ { + model = "Rockchip R88"; + compatible = "rockchip,r88", "rockchip,rk3368"; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + button@0 { + gpio-key,wakeup = <1>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <116>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + work { + gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>; + label = "r88:green:led"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 30 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vccio_1v8_reg: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vccio_3v3_reg: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + vdd_gpu: vdd-arm-regulator { + compatible = "pwm-regulator"; + rockchip,pwm_id = <1>; + rockchip,pwm_voltage = <1100000>; + pwms = <&pwm1 0 25000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8189es"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + //clocks = <&rk808 1>; + //clock-names = "ext_clock"; + /* wifi-bt-power-toggle; */ + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + /* BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; */ + BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +}; + +&sdmmc { + status = "disabled"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rmii"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio3 12 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 50000 50000>; + //assigned-clocks = <&cru SCLK_RMII_SRC>; + //assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin_pull_down>; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + status = "okay"; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +/* xz3215: xz3215@40 { + compatible = "xz3216"; + reg = <0x40>; + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulators { + #address-cells = <1>; + #size-cells = <0>; + vdd_cpu: regulator@0 { + reg = <0>; + regulator-compatible = "xz_dcdc1"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <603000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + fcs,suspend-voltage-selector = <1>; + //regulator-initial-mode = <0x1>; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +*/ + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + /* rtc_int is not connected */ + }; +}; + +&io_domains { + status = "ok"; + + dvp-supply = <&vccio_1v8_reg>; /* DVPIO_VDD */ + /*flash0-supply = <&vcc18_flash>;*/ /* FLASH0_VDD (emmc) */ + sdcard-supply = <&vccio_3v3_reg>; /* SDMMC0_VDD (sdmmc) */ + + audio-supply = <&vccio_3v3_reg>; /* APIO3_VDD */ + gpio30-supply = <&vccio_3v3_reg>; /* APIO1_VDD */ + gpio1830-supply = <&vccio_3v3_reg>; /* APIO4_VDD (gpujtag) */ + wifi-supply = <&vccio_3v3_reg>; /* APIO2_VDD (sdio0) */ +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + no-sd; + no-mmc; + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio:vsel1_gpio{ + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc-clk { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc-cmd { + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + stby_pwren: stby-pwren { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_ctl: led-ctl { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vccio_3v3_reg>; + vop-supply = <&vccio_3v3_reg>; +}; + +&saradc { + vref-supply = <&vccio_1v8_reg>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_otg { + dr_mode = "device"; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&mailbox { + status = "okay"; +}; + +&mailbox_scpi { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + logic-supply = <&vdd_gpu>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&pwm3 { + status = "okay"; + + interrupts = ; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; diff --git a/rk3368-r88.dts b/rk3368-r88.dts new file mode 100644 index 0000000..2582fa4 --- /dev/null +++ b/rk3368-r88.dts @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2015 Heiko Stuebner + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include + +/ { + model = "Rockchip R88"; + compatible = "rockchip,r88", "rockchip,rk3368"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; + + emmc_pwrseq: emmc-pwrseq { + compatible = "mmc-pwrseq-emmc"; + pinctrl-0 = <&emmc_reset>; + pinctrl-names = "default"; + reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + wakeup-source; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + work_led: led-0 { + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + label = "r88:green:led"; + pinctrl-names = "default"; + pinctrl-0 = <&led_ctl>; + }; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_rst>, <&wifi_reg_on>; + + reset-gpios = + /* BT_RST_N */ + <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>, + + /* WL_REG_ON */ + <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + }; + + vcc_18: vcc18-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + /* supplies both host and otg */ + vcc_host: vcc-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_io: vcc-io-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_lan: vcc-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vccio_wl: vccio-wl-regulator { + compatible = "regulator-fixed"; + regulator-name = "vccio_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_io>; + }; + + vdd_10: vdd-10-regulator { + compatible = "regulator-fixed"; + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-pwrseq = <&emmc_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rmii"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + pinctrl-names = "default"; + pinctrl-0 = <&rmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-enable-ramp-delay = <300>; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + /* rtc_int is not connected */ + }; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + wifi-supply = <&vccio_wl>; +}; + +&sdio0 { + assigned-clocks = <&cru SCLK_SDIO0>; + assigned-clock-parents = <&cru PLL_CPLL>; + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vccio_wl>; + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + bias-disable; + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + emmc { + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC3 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC4 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC5 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC6 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PC7 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD0 2 &pcfg_pull_up_drv_8ma>, + <1 RK_PD1 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc-clk { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none_drv_8ma>; + }; + + emmc-cmd { + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up_drv_8ma>; + }; + + emmc_reset: emmc-reset { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + stby_pwren: stby-pwren { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + led_ctl: led-ctl { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_reg_on: wifi-reg-on { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_rst: bt-rst { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_otg { + dr_mode = "host"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3368-sheep-lvds.dts b/rk3368-sheep-lvds.dts new file mode 100644 index 0000000..f15245c --- /dev/null +++ b/rk3368-sheep-lvds.dts @@ -0,0 +1,626 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" + +/ { + model = "Rockchip Sheep board"; + compatible = "rockchip,sheep", "rockchip,rk3368"; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 PWM_POLARITY_INVERTED>; + brightness-levels = < + 135 135 136 136 137 137 138 138 + 139 139 140 140 141 141 142 142 + 143 143 143 144 144 145 145 146 + 146 147 147 148 148 149 149 150 + 150 151 151 151 152 152 153 153 + 154 154 155 155 156 156 157 157 + 158 158 159 159 159 160 160 161 + 161 162 162 163 163 164 164 165 + 165 166 166 167 167 167 168 168 + 169 169 170 170 171 171 172 172 + 173 173 174 174 175 175 175 176 + 176 177 177 178 178 179 179 180 + 180 181 181 182 182 183 183 183 + 184 184 185 185 186 186 187 187 + 188 188 189 189 190 190 191 191 + 191 192 192 193 193 194 194 195 + 195 196 196 197 197 198 198 199 + 199 199 200 200 201 201 202 202 + 203 203 204 204 205 205 206 206 + 207 207 207 208 208 209 209 210 + 210 211 211 212 212 213 213 214 + 214 215 215 215 216 216 217 217 + 218 218 219 219 220 220 221 221 + 222 222 223 223 223 224 224 225 + 225 226 226 227 227 228 228 229 + 229 230 230 231 231 231 232 232 + 233 233 234 234 235 235 236 236 + 237 237 238 238 239 239 239 240 + 240 241 241 242 242 243 243 244 + 244 245 245 246 246 247 247 247 + 248 248 249 249 250 250 251 251 + 252 252 253 253 254 254 255 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + }; + + rk_key: rockchip-key { + compatible = "rockchip,key"; + status = "okay"; + + io-channels = <&saradc 1>; + + vol-up-key { + linux,code = <115>; + label = "volume up"; + rockchip,adc_value = <1>; + }; + + vol-down-key { + linux,code = <114>; + label = "volume down"; + rockchip,adc_value = <170>; + }; + + power-key { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + + menu-key { + linux,code = <59>; + label = "menu"; + rockchip,adc_value = <355>; + }; + + home-key { + linux,code = <102>; + label = "home"; + rockchip,adc_value = <746>; + }; + + back-key { + linux,code = <158>; + label = "back"; + rockchip,adc_value = <560>; + }; + + camera-key { + linux,code = <212>; + label = "camera"; + rockchip,adc_value = <450>; + }; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + bus-format = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <54000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <134>; + hfront-porch = <134>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <134>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +}; + +&sdmmc { + status = "okay"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +}; + +&i2c0 { + status = "okay"; + + syr827: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + status = "okay"; + + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + status = "okay"; + + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_pmu: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_wl: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + }; + }; +}; + +&cpu_l0 { + cpu-supply = <&syr827>; +}; + +&cpu_l1 { + cpu-supply = <&syr827>; +}; + +&cpu_l2 { + cpu-supply = <&syr827>; +}; + +&cpu_l3 { + cpu-supply = <&syr827>; +}; + +&cpu_b0 { + cpu-supply = <&syr827>; +}; + +&cpu_b1 { + cpu-supply = <&syr827>; +}; + +&cpu_b2 { + cpu-supply = <&syr827>; +}; + +&cpu_b3 { + cpu-supply = <&syr827>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&i2c1 { + status = "okay"; + + rt5640: rt5640@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + realtek,in1-differential; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio0 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1900>; + tp-size = <911>; + tp-supply = <&vcc_tp>; + status = "okay"; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pmu_io_domains { + status = "okay"; + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; +}; + +&pwm0 { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&mailbox { + status = "okay"; +}; + +&mailbox_scpi { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + +}; + +&route_lvds { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&syr827>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3368-sheep.dts b/rk3368-sheep.dts new file mode 100644 index 0000000..d77e83f --- /dev/null +++ b/rk3368-sheep.dts @@ -0,0 +1,710 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" + +/ { + model = "Rockchip Sheep board"; + compatible = "rockchip,sheep", "rockchip,rk3368"; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 PWM_POLARITY_INVERTED>; + brightness-levels = < + 135 135 136 136 137 137 138 138 + 139 139 140 140 141 141 142 142 + 143 143 143 144 144 145 145 146 + 146 147 147 148 148 149 149 150 + 150 151 151 151 152 152 153 153 + 154 154 155 155 156 156 157 157 + 158 158 159 159 159 160 160 161 + 161 162 162 163 163 164 164 165 + 165 166 166 167 167 167 168 168 + 169 169 170 170 171 171 172 172 + 173 173 174 174 175 175 175 176 + 176 177 177 178 178 179 179 180 + 180 181 181 182 182 183 183 183 + 184 184 185 185 186 186 187 187 + 188 188 189 189 190 190 191 191 + 191 192 192 193 193 194 194 195 + 195 196 196 197 197 198 198 199 + 199 199 200 200 201 201 202 202 + 203 203 204 204 205 205 206 206 + 207 207 207 208 208 209 209 210 + 210 211 211 212 212 213 213 214 + 214 215 215 215 216 216 217 217 + 218 218 219 219 220 220 221 221 + 222 222 223 223 223 224 224 225 + 225 226 226 227 227 228 228 229 + 229 230 230 231 231 231 232 232 + 233 233 234 234 235 235 236 236 + 237 237 238 238 239 239 239 240 + 240 241 241 242 242 243 243 244 + 244 245 245 246 246 247 247 247 + 248 248 249 249 250 250 251 251 + 252 252 253 253 254 254 255 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + }; + + rk_key: rockchip-key { + compatible = "rockchip,key"; + status = "okay"; + + io-channels = <&saradc 1>; + + vol-up-key { + linux,code = <115>; + label = "volume up"; + rockchip,adc_value = <1>; + }; + + vol-down-key { + linux,code = <114>; + label = "volume down"; + rockchip,adc_value = <170>; + }; + + power-key { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + + menu-key { + linux,code = <59>; + label = "menu"; + rockchip,adc_value = <355>; + }; + + home-key { + linux,code = <102>; + label = "home"; + rockchip,adc_value = <746>; + }; + + back-key { + linux,code = <158>; + label = "back"; + rockchip,adc_value = <560>; + }; + + camera-key { + linux,code = <212>; + label = "camera"; + rockchip,adc_value = <450>; + }; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +}; + +&sdmmc { + status = "okay"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +}; + +&i2c0 { + status = "okay"; + + syr827: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + status = "okay"; + + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + status = "okay"; + + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_pmu: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_wl: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + }; + + battery { + compatible = "rk818-battery"; + pinctrl-names = "default"; + pinctrl-0 = <&dc_irq_gpio>; + ocv_table = < + 3400 3650 3693 3707 3731 3749 3760 + 3770 3782 3796 3812 3829 3852 3882 + 3915 3951 3981 4047 4086 4132 4182>; + design_capacity = <8650>; + design_qmax = <8800>; + bat_res = <85>; + max_input_current = <2000>; + max_chrg_current = <1800>; + max_chrg_voltage = <4200>; + sleep_enter_current = <600>; + sleep_exit_current = <600>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3850>; + fb_temperature = <115>; + sample_res = <10>; + max_soc_offset = <60>; + energy_mode = <0>; + monitor_sec = <5>; + virtual_power = <0>; + power_dc2otg = <1>; + support_usb_adp = <1>; + support_dc_adp = <1>; + dc_det_gpio = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&cpu_l0 { + cpu-supply = <&syr827>; +}; + +&cpu_l1 { + cpu-supply = <&syr827>; +}; + +&cpu_l2 { + cpu-supply = <&syr827>; +}; + +&cpu_l3 { + cpu-supply = <&syr827>; +}; + +&cpu_b0 { + cpu-supply = <&syr827>; +}; + +&cpu_b1 { + cpu-supply = <&syr827>; +}; + +&cpu_b2 { + cpu-supply = <&syr827>; +}; + +&cpu_b3 { + cpu-supply = <&syr827>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rt5640: rt5640@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + #sound-dai-cells = <0>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + realtek,in1-differential; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio0 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1900>; + tp-size = <911>; + tp-supply = <&vcc_tp>; + status = "okay"; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; +}; + +&pwm0 { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; + + u2phy_otg: otg-port { + vbus-supply = <&vcc_otg_vbus>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&mailbox { + status = "okay"; +}; + +&mailbox_scpi { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <120>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <150000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <80>; + hfront-porch = <81>; + vback-porch = <21>; + vfront-porch = <21>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&syr827>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel_gpio: vsel-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otg_vbus_drv: otg-bus-drv { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3368-sziauto-rk618.dts b/rk3368-sziauto-rk618.dts new file mode 100644 index 0000000..f4f167f --- /dev/null +++ b/rk3368-sziauto-rk618.dts @@ -0,0 +1,772 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" +#include +#include + +/ { + model = "Rockchip rk3368 Sziauto board"; + compatible = "rockchip,sziauto", "rockchip,rk3368"; + + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + bus-format = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <136000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <60>; + hfront-porch = <60>; + hsync-len = <40>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 50000 0>; + brightness-levels = < + 32 32 34 34 36 36 38 38 40 40 + 42 42 44 44 46 46 48 48 50 50 + 52 52 54 54 56 56 58 58 60 60 + 62 62 64 64 66 66 68 68 70 70 + 72 72 74 74 76 76 78 78 80 80 + 82 82 84 84 86 86 88 88 90 90 + 92 92 94 94 96 96 98 98 100 100 + 102 102 104 104 106 106 108 108 110 110 + 112 112 114 114 116 116 118 118 120 120 + 122 122 124 124 126 126 128 128 130 130 + 132 132 134 134 136 136 138 138 140 140 + 142 142 144 144 146 146 148 148 150 150 + 152 152 154 154 156 156 158 158 160 160 + 162 162 164 164 166 166 168 168 170 170 + 172 172 174 174 176 176 178 178 180 180 + 182 182 184 184 186 186 188 188 190 190 + 192 192 194 194 196 196 198 198 200 200 + 202 202 204 204 206 206 208 208 210 210 + 212 212 214 214 216 216 218 218 220 220 + 222 222 224 224 225 225 226 226 227 227 + 228 228 229 229 230 230 231 231 232 232 + 233 233 234 234 235 235 236 236 237 237 + 238 238 239 239 240 240 241 241 242 242 + 243 243 244 244 245 245 246 246 247 247 + 248 248 249 249 250 250 251 251 252 252 + 253 253 254 254 255 255>; + default-brightness-level = <120>; + enable-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + }; + + rockchip-key { + compatible = "rockchip,key"; + io-channels = <&saradc 1>; + status = "okay"; + + vol-up-key { + linux,code = <115>; + label = "volume up"; + rockchip,adc_value = <1>; + }; + + vol-down-key { + linux,code = <114>; + label = "volume down"; + rockchip,adc_value = <170>; + }; + + power-key { + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + + menu-key { + linux,code = <59>; + label = "menu"; + rockchip,adc_value = <355>; + }; + + home-key { + linux,code = <102>; + label = "home"; + rockchip,adc_value = <746>; + }; + + back-key { + linux,code = <158>; + label = "back"; + rockchip,adc_value = <560>; + }; + + camera-key { + linux,code = <212>; + label = "camera"; + rockchip,adc_value = <450>; + }; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&i2c5 { + status = "okay"; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "clkin"; + assigned-clocks = <&cru SCLK_I2S_8CH_OUT>; + assigned-clock-rates = <11289600>; + reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru SCLK_I2S_8CH_OUT>, <&cru DCLK_VOP>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, <&clock DITHER_CLK>; + assigned-clock-parents = <&cru SCLK_I2S_8CH_OUT>, <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, <&clock VIF_PLL_CLK>, + <&cru SCLK_I2S_8CH_OUT>, <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + hdmi { + compatible = "rockchip,rk618-hdmi"; + clocks = <&clock HDMI_CLK>; + clock-names = "hdmi"; + assigned-clocks = <&clock HDMI_CLK>; + assigned-clock-parents = <&clock VIF0_CLK>; + interrupt-parent = <&gpio3>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_vif: endpoint { + remote-endpoint = <&vif_out_hdmi>; + }; + }; + + port@1 { + reg = <1>; + + hdmi_out_scaler: endpoint { + remote-endpoint = <&scaler_in_hdmi>; + }; + }; + }; + }; + + lvds { + compatible = "rockchip,rk618-lvds"; + clocks = <&clock LVDS_CLK>; + clock-names = "lvds"; + dual-channel; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_scaler: endpoint { + remote-endpoint = <&scaler_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; + + scaler { + compatible = "rockchip,rk618-scaler"; + clocks = <&clock SCALER_CLK>, <&clock VIF0_CLK>, + <&clock DITHER_CLK>; + clock-names = "scaler", "vif", "dither"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + scaler_in_hdmi: endpoint { + remote-endpoint = <&hdmi_out_scaler>; + }; + }; + + port@1 { + reg = <1>; + + scaler_out_lvds: endpoint { + remote-endpoint = <&lvds_in_scaler>; + }; + }; + }; + }; + + vif { + compatible = "rockchip,rk618-vif"; + clocks = <&clock VIF0_CLK>, <&clock VIF0_PRE_CLK>; + clock-names = "vif", "vif_pre"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + vif_in_rgb: endpoint { + remote-endpoint = <&rgb_out_vif>; + }; + }; + + port@1 { + reg = <1>; + + vif_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_vif>; + }; + }; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_vif: endpoint { + remote-endpoint = <&vif_in_rgb>; + }; + }; + }; +}; + +&route_rgb { + status = "okay"; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; +}; + +&sdmmc { + status = "disabled"; + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; +}; + +&sdio0 { + clock-frequency = <50000000>; + clock-freq-min-max = <200000 50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + syr827: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + reg = <0x1c>; + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_tp"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_pmu: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_pmu"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_wl: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_wl"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + }; + }; +}; + +&cpu_l0 { + cpu-supply = <&syr827>; +}; + +&cpu_l1 { + cpu-supply = <&syr827>; +}; + +&cpu_l2 { + cpu-supply = <&syr827>; +}; + +&cpu_l3 { + cpu-supply = <&syr827>; +}; + +&cpu_b0 { + cpu-supply = <&syr827>; +}; + +&cpu_b1 { + cpu-supply = <&syr827>; +}; + +&cpu_b2 { + cpu-supply = <&syr827>; +}; + +&cpu_b3 { + cpu-supply = <&syr827>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&io_domains { + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; + status = "okay"; +}; + +&pmu_io_domains { + pmu-supply = <&vcc_io>; + vop-supply = <&vcc_io>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&mailbox { + status = "okay"; +}; + +&mailbox_scpi { + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&syr827>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3368-tablet.dts b/rk3368-tablet.dts new file mode 100644 index 0000000..1674731 --- /dev/null +++ b/rk3368-tablet.dts @@ -0,0 +1,1070 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" +/ { + model = "Rockchip rk3368 tablet board"; + compatible = "rockchip,tablet", "rockchip,rk3368"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1024000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 16 16 16 16 16 16 16 + 17 17 17 17 17 17 17 17 + 18 18 18 18 18 18 18 18 + 19 19 19 19 19 19 19 19 + 20 20 20 20 20 20 20 20 + 21 21 21 21 21 21 21 21 + 22 22 22 22 22 22 22 22 + 23 23 23 23 23 23 23 23 + 24 24 24 24 24 24 24 24 + 25 25 25 25 25 25 25 25 + 26 26 26 26 26 26 26 26 + 27 27 27 27 27 27 27 27 + 28 28 28 28 28 28 28 28 + 27 27 27 27 27 27 27 27 + 30 30 30 30 30 30 30 30 + 31 31 31 31 31 31 31 31 + 32 32 32 32 32 32 32 32 + 33 33 33 33 33 33 33 33 + 34 34 34 34 34 34 34 34 + 35 35 35 35 35 35 35 35 + 36 36 36 36 36 36 36 36 + 37 37 37 37 37 37 37 37 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; + }; + + es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + system-clock-frequency = <11289600>; + }; + simple-audio-card,codec { + sound-dai = <&es8316>; + system-clock-frequency = <11289600>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + /* wifi_chip_type - wifi chip define + * ap6210, ap6330, ap6335 + * rtl8188eu, rtl8723bs, rtl8723bu + * esp8089 + */ + wifi_chip_type = "ap6255"; + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + + //BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + +}; + +&cif_clkout { + /* cif_clkout */ + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_logic>; + devfreq-events = <&dfi>; + upthreshold = <60>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 600000 + SYS_STATUS_REBOOT 600000 + SYS_STATUS_SUSPEND 240000 + SYS_STATUS_VIDEO_1080P 396000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_PERFORMANCE 600000 + SYS_STATUS_BOOST 396000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 528000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 582 240000 + 583 99999 396000 + >; + auto-min-freq = <240000>; + auto-freq-en = <1>; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + back-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <8>; + enable-delay-ms = <3>; + reset-delay-ms = <50>; + init-delay-ms = <20>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + width-mm = <153>; + height-mm = <85>; + panel-init-sequence = [ + 05 1e 01 01 + 15 00 02 80 47 + 15 00 02 81 40 + 15 00 02 82 04 + 15 00 02 83 77 + 15 00 02 84 0f + 15 00 02 85 70 + 15 78 02 86 70 + ]; + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <49500000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <120>; + hfront-porch = <80>; + vback-porch = <14>; + vfront-porch = <14>; + hsync-len = <40>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4526@10 { + compatible = "tcs,tcs4526"; + reg = <0x10>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + status = "okay"; + reg = <0x1c>; + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + extcon = <&u2phy>; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_pmu: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_wl: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk818-battery"; + pinctrl-names = "default"; + pinctrl-0 = <&dc_irq_gpio>; + ocv_table = < + 3400 3652 3680 3707 3730 3747 3764 + 3772 3781 3792 3807 3828 3861 3899 + 3929 3958 3987 4038 4079 4127 4186>; + design_capacity = <7536>; + design_qmax = <8290>; + bat_res = <100>; + max_input_current = <1750>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + sleep_enter_current = <600>; + sleep_exit_current = <600>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3850>; + fb_temperature = <115>; + sample_res = <20>; + max_soc_offset = <60>; + energy_mode = <0>; + monitor_sec = <5>; + virtual_power = <0>; + power_dc2otg = <0>; + support_usb_adp = <1>; + support_dc_adp = <1>; + dc_det_gpio = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + es8316: es8316@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + spk-con-gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + extcon = <&rk_headset>; + }; +}; + +&i2c2 { + status = "okay"; + + ts@5a { + compatible = "cst2xxse"; + reg = <0x5a>; + irq-gpio = <&gpio0 RK_PB4 IRQ_TYPE_LEVEL_LOW>; + //touch-gpio = <&gpio1 GPIO_B0 IRQ_TYPE_LEVEL_LOW>; /* TP_INT == GPIO1_B0 */ + //reset-gpio = <&gpio0 GPIO_D1 GPIO_ACTIVE_LOW>; /* TP_RST == GPIO0_D1 */ + //power-gpio = <&gpio0 GPIO_C5 GPIO_ACTIVE_LOW>; + //max-x = <800>; + //max-y = <480>; + status = "okay"; + }; + +}; + +&i2c3 { + status = "okay"; + + gc0312: gc0312@21 { + status = "okay"; + compatible = "galaxycore,gc0312"; + reg = <0x21>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc0312_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + gc2145: gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "disabled"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan-9569A2"; + power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + reg = <0x68>; + irq-gpio = <&gpio3 14 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <1 0 0 0 1 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <1>; + support-hw-poweroff = <1>; + mpu-debug = <1>; + }; + + sensor@4c { + status = "okay"; + compatible = "gs_mc3230"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <9>; + reprobe_en = <1>; + irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>; + }; + + sensor@18 { + status = "okay"; + compatible = "gs_sc7a30"; + reg = <0x18>; + type = ; + irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + reprobe_en = <1>; + }; + + sensor@10 { + status = "okay"; + compatible = "light_cm3218"; + pinctrl-names = "default"; + pinctrl-0 = <&cm3218_irq_gpio>; + reg = <0x10>; + type = ; + irq-gpio = <&gpio3 15 IRQ_TYPE_EDGE_FALLING>; + irq_enable = <1>; + poll_delay_ms = <30>; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&isp_dvp_d2d9 { + rockchip,pins = + /* cif_data4 ... cif_data9 */ + <1 RK_PA2 1 &pcfg_pull_down>, + <1 RK_PA3 1 &pcfg_pull_down>, + <1 RK_PA4 1 &pcfg_pull_down>, + <1 RK_PA5 1 &pcfg_pull_down>, + <1 RK_PA6 1 &pcfg_pull_down>, + <1 RK_PA7 1 &pcfg_pull_down>, + /* cif_sync, cif_href */ + <1 RK_PB0 1 &pcfg_pull_down>, + <1 RK_PB1 1 &pcfg_pull_down>, + /* cif_clkin */ + <1 RK_PB2 1 &pcfg_pull_down>; +}; + +&isp_dvp_d10d11 { + rockchip,pins = + /* cif_data10, cif_data11 */ + <1 RK_PB6 1 &pcfg_pull_down>, + <1 RK_PB7 1 &pcfg_pull_down>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vccio_pmu>; + vop-supply = <&vccio_pmu>; +}; + +&pwm0 { + status = "okay"; +}; + +&pinctrl { + camera { + camera_pwr: camera-pwr { + rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel_gpio: vsel-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm3218 { + cm3218_irq_gpio: cm3218-irq-gpio { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>; + port { + #address-cells = <1>; + #size-cells = <0>; + + dvp_in_fcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc0312_out>; + }; + + dvp_in_bcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + + isp_mipi_in: endpoint@2 { + reg = <2>; + remote-endpoint = <&dphy_rx_out>; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "disabled"; +}; + +&sdio0 { + max-frequency = <100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&vdd_cpu>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + diff --git a/rk3368-xikp-avb.dts b/rk3368-xikp-avb.dts new file mode 100644 index 0000000..b455e32 --- /dev/null +++ b/rk3368-xikp-avb.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3368-xikp.dtsi" + +/ { + model = "Rockchip rk3368 xkp avb board"; + compatible = "rockchip,xkp-avb", "rockchip,rk3368"; +}; + +&firmware_android { + compatible = "android,firmware"; + boot_devices = "ff0f0000.dwmmc,ff400000.nandc"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,dtbo"; + }; + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,avb"; + }; + }; +}; + +&chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 androidboot.selinux=permissive init=/init kpti=0"; +}; + +&i2c3 { + status = "okay"; + + gc2145: gc2145@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&isp_dvp_in>; + }; + }; + }; + + ov8858: ov8858@36 { + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan-9569A2"; + power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&isp { + status = "disabled"; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_dvp_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + + isp_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx_out>; + }; + }; +}; diff --git a/rk3368-xikp.dts b/rk3368-xikp.dts new file mode 100644 index 0000000..bc320ff --- /dev/null +++ b/rk3368-xikp.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3368-xikp.dtsi" + +/ { + model = "Rockchip rk3368 xkp board"; + compatible = "rockchip,xkp", "rockchip,rk3368"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; \ No newline at end of file diff --git a/rk3368-xikp.dtsi b/rk3368-xikp.dtsi new file mode 100644 index 0000000..9648749 --- /dev/null +++ b/rk3368-xikp.dtsi @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" + +/ { + es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk-es8316-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&es8316>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1024000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + /* wifi_chip_type - wifi chip define + * ap6210, ap6330, ap6335 + * rtl8188eu, rtl8723bs, rtl8723bu + * esp8089 + */ + wifi_chip_type = "ap6255"; + sdio_vref = <1800>; //1800mv or 3300mv + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + + //BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&cpu_l0 { + cpu-supply = <&syr827>; +}; + +&cpu_l1 { + cpu-supply = <&syr827>; +}; + +&cpu_l2 { + cpu-supply = <&syr827>; +}; + +&cpu_l3 { + cpu-supply = <&syr827>; +}; + +&cpu_b0 { + cpu-supply = <&syr827>; +}; + +&cpu_b1 { + cpu-supply = <&syr827>; +}; + +&cpu_b2 { + cpu-supply = <&syr827>; +}; + +&cpu_b3 { + cpu-supply = <&syr827>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_logic>; + devfreq-events = <&dfi>; + upthreshold = <60>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 600000 + SYS_STATUS_REBOOT 600000 + SYS_STATUS_SUSPEND 240000 + SYS_STATUS_VIDEO_1080P 396000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_PERFORMANCE 600000 + SYS_STATUS_BOOST 396000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 528000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 582 240000 + 583 99999 396000 + >; + auto-min-freq = <240000>; + auto-freq-en = <1>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&sdmmc { + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "disabled"; +}; + +&sdio0 { + clock-frequency = <100000000>; + clock-freq-min-max = <200000 100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + syr827: syr827@40 { + compatible = "silergy,syr827"; + status = "okay"; + reg = <0x40>; + + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + status = "okay"; + reg = <0x1c>; + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + extcon = <&u2phy>; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_io>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1250000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_tp: LDO_REG2 { + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_pmu: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_wl: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk818-battery"; + pinctrl-names = "default"; + pinctrl-0 = <&dc_irq_gpio>; + ocv_table = < + 3400 3652 3680 3707 3730 3747 3764 + 3772 3781 3792 3807 3828 3861 3899 + 3929 3958 3987 4038 4079 4127 4186>; + design_capacity = <7536>; + design_qmax = <8290>; + bat_res = <100>; + max_input_current = <1750>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + sleep_enter_current = <600>; + sleep_exit_current = <600>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3850>; + fb_temperature = <115>; + sample_res = <20>; + max_soc_offset = <60>; + energy_mode = <0>; + monitor_sec = <5>; + virtual_power = <0>; + power_dc2otg = <0>; + support_usb_adp = <1>; + support_dc_adp = <1>; + dc_det_gpio = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + es8316: es8316@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + spk-con-gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + }; +}; + +&i2c2 { + status = "okay"; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio0 12 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + max-x = <1920>; + max-y = <1200>; + tp-size = <89>; + configfile-num = <1>; + status = "okay"; + tp-supply = <&vcc_tp>; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + reg = <0x68>; + irq-gpio = <&gpio3 14 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <1 0 0 0 1 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <1>; + support-hw-poweroff = <1>; + mpu-debug = <1>; + }; + + sensor@4c { + status = "okay"; + compatible = "gs_mc3230"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <4>; + reprobe_en = <1>; + }; + + sensor@19 { + status = "okay"; + compatible = "gs_lis3dh"; + reg = <0x19>; + type = ; + irq-gpio = <&gpio3 14 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + reprobe_en = <1>; + }; + + sensor@10 { + status = "okay"; + compatible = "light_cm3218"; + pinctrl-names = "default"; + pinctrl-0 = <&cm3218_irq_gpio>; + reg = <0x10>; + type = ; + irq-gpio = <&gpio3 15 IRQ_TYPE_EDGE_FALLING>; + irq_enable = <1>; + poll_delay_ms = <30>; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + dvp-supply = <&vcc_18>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vccio_pmu>; + vop-supply = <&vccio_pmu>; +}; + +&pwm0 { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <120>; + enable-delay-ms = <200>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <159000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&syr827>; + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel_gpio: vsel-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm3218 { + cm3218_irq_gpio: cm3218-irq-gpio { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3368.dtsi b/rk3368.dtsi new file mode 100644 index 0000000..cf6b66e --- /dev/null +++ b/rk3368.dtsi @@ -0,0 +1,1247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2015 Heiko Stuebner + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3368"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + }; + + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + core2 { + cpu = <&cpu_b2>; + }; + core3 { + cpu = <&cpu_b3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_l1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_l2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_l3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x100>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x101>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_b2: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x102>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu_b3: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x103>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + amba: bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff250000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC_PERI>; + clock-names = "apb_pclk"; + }; + + dmac_bus: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff600000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-broken-no-flushp; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC_BUS>; + clock-names = "apb_pclk"; + }; + }; + + arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = , + , + , + , + , + , + , + ; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, + <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, + <&cpu_b2>, <&cpu_b3>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + sdmmc: mmc@ff0c0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0c0000 0x0 0x4000>; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + resets = <&cru SRST_MMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio0: mmc@ff0d0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0d0000 0x0 0x4000>; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, + <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@ff0f0000 { + compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff0f0000 0x0 0x4000>; + max-frequency = <150000000>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + interrupts = ; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + saradc: saradc@ff100000 { + compatible = "rockchip,saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + spi0: spi@ff110000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff110000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff120000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff120000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff130000 { + compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff130000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff140000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + status = "disabled"; + }; + + i2c3: i2c@ff150000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + status = "disabled"; + }; + + i2c4: i2c@ff160000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + status = "disabled"; + }; + + i2c5: i2c@ff170000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff170000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C5>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + status = "disabled"; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff1c0000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1c0000 0x0 0x100>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + thermal-zones { + cpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <75000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_alert1: cpu_alert1 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <95000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <80000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <115000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3368-tsadc"; + reg = <0x0 0xff280000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_pin>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + + gmac: ethernet@ff290000 { + compatible = "rockchip,rk3368-gmac"; + reg = <0x0 0xff290000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_MAC>, + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, + <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; + clock-names = "stmmaceth", + "mac_clk_rx", "mac_clk_tx", + "clk_mac_ref", "clk_mac_refout", + "aclk_mac", "pclk_mac"; + status = "disabled"; + }; + + usb_host0_ehci: usb@ff500000 { + compatible = "generic-ehci"; + reg = <0x0 0xff500000 0x0 0x100>; + interrupts = ; + clocks = <&cru HCLK_HOST0>; + status = "disabled"; + }; + + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0x0 0xff580000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + dr_mode = "otg"; + g-np-tx-fifo-size = <16>; + g-rx-fifo-size = <275>; + g-tx-fifo-size = <256 128 128 64 64 32>; + status = "disabled"; + }; + + i2c0: i2c@ff650000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff650000 0x0 0x1000>; + clocks = <&cru PCLK_I2C0>; + clock-names = "i2c"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ff660000 { + compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; + reg = <0x0 0xff660000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + status = "disabled"; + }; + + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680020 0x0 0x10>; + #pwm-cells = <3>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff680030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM1>; + clock-names = "pwm"; + status = "disabled"; + }; + + uart2: serial@ff690000 { + compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + mbox: mbox@ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0x0 0xff6b0000 0x0 0x1000>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + pmugrf: syscon@ff738000 { + compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xff738000 0x0 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3368-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3368-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff770000 0x0 0x1000>; + + io_domains: io-domains { + compatible = "rockchip,rk3368-io-voltage-domain"; + status = "disabled"; + }; + }; + + wdt: watchdog@ff800000 { + compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; + reg = <0x0 0xff800000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + status = "disabled"; + }; + + timer@ff810000 { + compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xff810000 0x0 0x20>; + interrupts = ; + }; + + spdif: spdif@ff880000 { + compatible = "rockchip,rk3368-spdif"; + reg = <0x0 0xff880000 0x0 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&dmac_bus 3>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + status = "disabled"; + }; + + i2s_2ch: i2s-2ch@ff890000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; + dmas = <&dmac_bus 6>, <&dmac_bus 7>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2s_8ch: i2s-8ch@ff898000 { + compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff898000 0x0 0x1000>; + interrupts = ; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_bus>; + status = "disabled"; + }; + + iep_mmu: iommu@ff900800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff900800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + isp_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, + <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + vop_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff930300 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + hevc_mmu: iommu@ff9a0440 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0440 0x0 0x40>, + <0x0 0xff9a0480 0x0 0x40>; + interrupts = ; + interrupt-names = "hevc_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff9a0800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff9a0800 0x0 0x100>; + interrupts = , + ; + interrupt-names = "vepu_mmu", "vdpu_mmu"; + clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + efuse256: efuse@ffb00000 { + compatible = "rockchip,rk3368-efuse"; + reg = <0x0 0xffb00000 0x0 0x20>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE256>; + clock-names = "pclk_efuse"; + + cpu_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + temp_adjust: temp-adjust@1f { + reg = <0x1f 0x1>; + }; + }; + + gic: interrupt-controller@ffb71000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0x0 0xffb71000 0x0 0x1000>, + <0x0 0xffb72000 0x0 0x2000>, + <0x0 0xffb74000 0x0 0x2000>, + <0x0 0xffb76000 0x0 0x2000>; + interrupts = ; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3368-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + + gpio0: gpio0@ff750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff750000 0x0 0x100>; + clocks = <&cru PCLK_GPIO0>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO1>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3@ff7a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff7a0000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_up>, + <1 RK_PC4 2 &pcfg_pull_up>, + <1 RK_PC5 2 &pcfg_pull_up>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, + <1 RK_PC3 2 &pcfg_pull_up>, + <1 RK_PC4 2 &pcfg_pull_up>, + <1 RK_PC5 2 &pcfg_pull_up>, + <1 RK_PC6 2 &pcfg_pull_up>, + <1 RK_PC7 2 &pcfg_pull_up>, + <1 RK_PD0 2 &pcfg_pull_up>, + <1 RK_PD1 2 &pcfg_pull_up>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none_12ma>, + <3 RK_PB1 1 &pcfg_pull_none_12ma>, + <3 RK_PB2 1 &pcfg_pull_none_12ma>, + <3 RK_PB6 1 &pcfg_pull_none_12ma>, + <3 RK_PD4 1 &pcfg_pull_none_12ma>, + <3 RK_PB5 1 &pcfg_pull_none_12ma>, + <3 RK_PB7 1 &pcfg_pull_none>, + <3 RK_PC0 1 &pcfg_pull_none>, + <3 RK_PC1 1 &pcfg_pull_none>, + <3 RK_PC2 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PC3 1 &pcfg_pull_none>, + <3 RK_PB0 1 &pcfg_pull_none_12ma>, + <3 RK_PB1 1 &pcfg_pull_none_12ma>, + <3 RK_PB5 1 &pcfg_pull_none_12ma>, + <3 RK_PB7 1 &pcfg_pull_none>, + <3 RK_PC0 1 &pcfg_pull_none>, + <3 RK_PC4 1 &pcfg_pull_none>, + <3 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, + <3 RK_PD7 2 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, + <1 RK_PC1 1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, + <3 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, + <3 RK_PD3 2 &pcfg_pull_none>; + }; + }; + + i2s { + i2s_8ch_bus: i2s-8ch-bus { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; + }; + + pwm0_pin_pull_down: pwm0-pin-pull-down { + rockchip,pins = <3 RK_PB0 2 &pcfg_pull_down>; + }; + + vop_pwm_pin: vop-pwm { + rockchip,pins = <3 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; + }; + + pwm1_pin_pull_down: pwm1-pin-pull-down { + rockchip,pins = <0 RK_PB0 2 &pcfg_pull_down>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>; + }; + + pwm3_pin_pull_down: pwm3-pin-pull-down { + rockchip,pins = <3 RK_PD6 3 &pcfg_pull_down>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, + <2 RK_PD5 1 &pcfg_pull_up>, + <2 RK_PD6 1 &pcfg_pull_up>, + <2 RK_PD7 1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; + }; + + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, + <2 RK_PA6 1 &pcfg_pull_up>, + <2 RK_PA7 1 &pcfg_pull_up>, + <2 RK_PB0 1 &pcfg_pull_up>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; + }; + }; + + tsadc { + otp_pin: otp-pin { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, + <2 RK_PD1 1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, + <2 RK_PA5 2 &pcfg_pull_none>; + }; + /* no rts / cts for uart2 */ + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, + <3 RK_PD6 3 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, + <0 RK_PD2 3 &pcfg_pull_none>; + }; + + uart4_cts: uart4-cts { + rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; + }; + + uart4_rts: uart4-rts { + rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/rk3368a-817-tablet-bnd.dts b/rk3368a-817-tablet-bnd.dts new file mode 100644 index 0000000..eeaf205 --- /dev/null +++ b/rk3368a-817-tablet-bnd.dts @@ -0,0 +1,1074 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include +#include +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" +/ { + model = "Rockchip rk3368a tablet rk817 board"; + compatible = "rockchip,tablet", "rockchip,rk3368a", "rockchip,rk3368"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1024000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 10 10 10 11 12 13 14 15 + 16 16 16 16 16 16 16 16 + 17 17 17 17 17 17 17 17 + 18 18 18 18 18 18 18 18 + 19 19 19 19 19 19 19 19 + 20 20 20 20 20 20 20 20 + 21 21 21 21 21 21 21 21 + 22 22 22 22 22 22 22 22 + 23 23 23 23 23 23 23 23 + 24 24 24 24 24 24 24 24 + 25 25 25 25 25 25 25 25 + 26 26 26 26 26 26 26 26 + 27 27 27 27 27 27 27 27 + 28 28 28 28 28 28 28 28 + 27 27 27 27 27 27 27 27 + 30 30 30 30 30 30 30 30 + 31 31 31 31 31 31 31 31 + 32 32 32 32 32 32 32 32 + 33 33 33 33 33 33 33 33 + 34 34 34 34 34 34 34 34 + 35 35 35 35 35 35 35 35 + 36 36 36 36 36 36 36 36 + 37 37 37 37 37 37 37 37 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38 + 38 38 38 38 38 38 38 38>; + default-brightness-level = <200>; + enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3500>; + rockchip,screen-on-voltage = <3600>; + status = "okay"; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip-rk817-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + /* wifi_chip_type - wifi chip define + * ap6210, ap6330, ap6335 + * rtl8188eu, rtl8723bs, rtl8723bu + * esp8089 + */ + wifi_chip_type = "ap6255"; + WIFI,vbat_gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + + //BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + +}; + +&cif_clkout { + /* cif_clkout */ + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_logic>; + devfreq-events = <&dfi>; + upthreshold = <60>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 600000 + SYS_STATUS_REBOOT 600000 + SYS_STATUS_SUSPEND 240000 + SYS_STATUS_VIDEO_1080P 396000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_PERFORMANCE 600000 + SYS_STATUS_BOOST 396000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 528000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 582 240000 + 583 99999 396000 + >; + vop-dclk-mode = <1>; + auto-min-freq = <240000>; + auto-freq-en = <0>; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + /* back-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; */ + reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <8>; + enable-delay-ms = <3>; + reset-delay-ms = <50>; + init-delay-ms = <20>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + width-mm = <153>; + height-mm = <85>; + panel-init-sequence = [ + 05 1e 01 01 + 15 00 02 80 47 + 15 00 02 81 40 + 15 00 02 82 04 + 15 00 02 83 77 + 15 00 02 84 0f + 15 00 02 85 70 + 15 78 02 86 70 + ]; + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <49500000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <120>; + hfront-porch = <80>; + vback-porch = <14>; + vfront-porch = <14>; + hsync-len = <40>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4526@10 { + compatible = "tcs,tcs4526"; + reg = <0x10>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_io>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_3v3: DCDC_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3548 3592 3636 3687 3740 3780 + 3806 3827 3846 3864 3889 3929 3964 + 3993 4015 4030 4041 4056 4076 4148>; + design_capacity = <4000>; + design_qmax = <4200>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3500>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + ts@5a { + compatible = "cst2xxse"; + reg = <0x5a>; + irq-gpio = <&gpio0 RK_PB4 IRQ_TYPE_LEVEL_LOW>; + //touch-gpio = <&gpio1 GPIO_B0 IRQ_TYPE_LEVEL_LOW>; /* TP_INT == GPIO1_B0 */ + //reset-gpio = <&gpio0 GPIO_D1 GPIO_ACTIVE_LOW>; /* TP_RST == GPIO0_D1 */ + //power-gpio = <&gpio0 GPIO_C5 GPIO_ACTIVE_LOW>; + //max-x = <800>; + //max-y = <480>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + + gc0312: gc0312@21 { + status = "okay"; + compatible = "galaxycore,gc0312"; + reg = <0x21>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc0312_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + gc2145: gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "disabled"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan-9569A2"; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + sc7a30: sc7a30@18 { + status = "okay"; + compatible = "gs_sc7a30"; + reg = <0x18>; + type = ; + pinctrl-names = "default"; + pinctrl-0 = <&sc7a30_irq_gpio>; + irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + reprobe_en = <1>; + }; + +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + dvp-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_3v3>; +}; + +&isp_dvp_d2d9 { + rockchip,pins = + /* cif_data4 ... cif_data9 */ + <1 RK_PA2 1 &pcfg_pull_down>, + <1 RK_PA3 1 &pcfg_pull_down>, + <1 RK_PA4 1 &pcfg_pull_down>, + <1 RK_PA5 1 &pcfg_pull_down>, + <1 RK_PA6 1 &pcfg_pull_down>, + <1 RK_PA7 1 &pcfg_pull_down>, + /* cif_sync, cif_href */ + <1 RK_PB0 1 &pcfg_pull_down>, + <1 RK_PB1 1 &pcfg_pull_down>, + /* cif_clkin */ + <1 RK_PB2 1 &pcfg_pull_down>; +}; + +&isp_dvp_d10d11 { + rockchip,pins = + /* cif_data10, cif_data11 */ + <1 RK_PB6 1 &pcfg_pull_down>, + <1 RK_PB7 1 &pcfg_pull_down>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vcc3v3_pmu>; + vop-supply = <&vcc3v3_pmu>; +}; + +&pwm0 { + status = "okay"; +}; + +&pinctrl { + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA0 2 &pcfg_pull_none>; + }; + + vsel_gpio: vsel-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sc7a30 { + sc7a30_irq_gpio: sc7a30_irq_gpio { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>; + port { + #address-cells = <1>; + #size-cells = <0>; + + dvp_in_fcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc0312_out>; + }; + + dvp_in_bcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + + isp_mipi_in: endpoint@2 { + reg = <2>; + remote-endpoint = <&dphy_rx_out>; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sdio0 { + max-frequency = <50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&vdd_cpu>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + diff --git a/rk3368a-817-tablet.dts b/rk3368a-817-tablet.dts new file mode 100644 index 0000000..31f25e4 --- /dev/null +++ b/rk3368a-817-tablet.dts @@ -0,0 +1,1333 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include +#include +#include +#include "rk3368.dtsi" +#include "rk3368-android.dtsi" +/ { + model = "Rockchip rk3368a tablet rk817 board"; + compatible = "rockchip,tablet", "rockchip,rk3368a", "rockchip,rk3368"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1024000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 30 30 30 31 31 31 32 32 + 32 33 33 33 34 34 34 35 + 35 35 36 36 36 37 37 37 + 38 38 38 39 39 39 40 40 + 40 41 41 41 42 42 42 43 + 43 43 44 44 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 232 232 233 233 233 234 234 + 234 235 235 235 236 236 236 237 + 237 238 238 239 239 240 240 240>; + default-brightness-level = <200>; + enable-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3400>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip-rk817-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + /* wifi_chip_type - wifi chip define + * ap6210, ap6330, ap6335 + * rtl8188eu, rtl8723bs, rtl8723bu + * esp8089 + */ + wifi_chip_type = "rtl8723bs"; + WIFI,vbat_gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + pinctrl-names = "default","rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_rts_gpio>; + + //BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + BT,reset_gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; + + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_host: vcc-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host"; + regulator-always-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + +}; + +&cif_clkout { + /* cif_clkout */ + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + logic-supply = <&vdd_logic>; +}; + +&dsi { + status = "okay"; + //rockchip,lane-rate = <500>; + + panel:panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <135>; + height-mm = <216>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + 15 00 02 01 00 + 15 00 02 02 00 + 15 00 02 03 53 + 15 00 02 04 00 + 15 00 02 05 00 + 15 00 02 06 08 + 15 00 02 07 00 + 15 00 02 08 00 + 15 00 02 09 00 + 15 00 02 0A 00 + 15 00 02 0B 00 + 15 00 02 0C 00 + 15 00 02 0D 00 + 15 00 02 0E 00 + 15 00 02 0F 26 + 15 00 02 10 26 + 15 00 02 11 00 + 15 00 02 12 00 + 15 00 02 13 00 + 15 00 02 14 00 + 15 00 02 15 00 + 15 00 02 16 00 + 15 00 02 17 00 + 15 00 02 18 00 + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B 00 + 15 00 02 1C 00 + 15 00 02 1D 00 + 15 00 02 1E 40 + 15 00 02 1F C0 + 15 00 02 20 06 + 15 00 02 21 01 + 15 00 02 22 07 + 15 00 02 23 00 + 15 00 02 24 8A + 15 00 02 25 8A + 15 00 02 26 00 + 15 00 02 27 00 + 15 00 02 28 33 + 15 00 02 29 33 + 15 00 02 2A 00 + 15 00 02 2B 00 + 15 00 02 2C 08 + 15 00 02 2D 08 + 15 00 02 2E 0B + 15 00 02 2F 0B + 15 00 02 30 00 + 15 00 02 31 00 + 15 00 02 32 42 + 15 00 02 33 00 + 15 00 02 34 00 + 15 00 02 35 0A + 15 00 02 36 00 + 15 00 02 37 08 + 15 00 02 38 3C + 15 00 02 39 00 + 15 00 02 3A 00 + 15 00 02 3B 00 + 15 00 02 3C 00 + 15 00 02 3D 00 + 15 00 02 3E 00 + 15 00 02 3F 00 + 15 00 02 40 00 + 15 00 02 41 00 + 15 00 02 42 00 + 15 00 02 43 08 + 15 00 02 44 00 + 15 00 02 50 01 + 15 00 02 51 23 + 15 00 02 52 45 + 15 00 02 53 67 + 15 00 02 54 89 + 15 00 02 55 AB + 15 00 02 56 01 + 15 00 02 57 23 + 15 00 02 58 45 + 15 00 02 59 67 + 15 00 02 5A 89 + 15 00 02 5B AB + 15 00 02 5C CD + 15 00 02 5D EF + 15 00 02 5E 00 + 15 00 02 5F 01 + 15 00 02 60 01 + 15 00 02 61 06 + 15 00 02 62 06 + 15 00 02 63 06 + 15 00 02 64 06 + 15 00 02 65 00 + 15 00 02 66 00 + 15 00 02 67 17 + 15 00 02 68 02 + 15 00 02 69 16 + 15 00 02 6A 16 + 15 00 02 6B 02 + 15 00 02 6C 0D + 15 00 02 6D 0D + 15 00 02 6E 0C + 15 00 02 6F 0C + 15 00 02 70 0F + 15 00 02 71 0F + 15 00 02 72 0E + 15 00 02 73 0E + 15 00 02 74 02 + 15 00 02 75 01 + 15 00 02 76 01 + 15 00 02 77 06 + 15 00 02 78 06 + 15 00 02 79 06 + 15 00 02 7A 06 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 17 + 15 00 02 7E 02 + 15 00 02 7F 16 + 15 00 02 80 16 + 15 00 02 81 02 + 15 00 02 82 0D + 15 00 02 83 0D + 15 00 02 84 0C + 15 00 02 85 0C + 15 00 02 86 0F + 15 00 02 87 0F + 15 00 02 88 0E + 15 00 02 89 0E + 15 00 02 8A 02 + 39 00 04 FF 98 81 04 + 15 00 02 6E 2B + 15 00 02 6F 35 + 15 00 02 3A A4 + 15 00 02 8D 1A + 15 00 02 87 BA + 15 00 02 B2 D1 + 15 00 02 88 0B + 15 00 02 38 01 + 15 00 02 39 00 + 15 00 02 B5 07 + 15 00 02 31 75 + 15 00 02 3B 98 + 39 00 04 FF 98 81 01 + 15 00 02 22 0A + 15 00 02 31 00 + 15 00 02 53 40 + 15 00 02 55 40 + 15 00 02 50 95 + 15 00 02 51 90 + 15 00 02 60 22 + 15 00 02 62 20 + 15 00 02 A0 00 + 15 00 02 A1 1B + 15 00 02 A2 2A + 15 00 02 A3 14 + 15 00 02 A4 17 + 15 00 02 A5 2B + 15 00 02 A6 1F + 15 00 02 A7 20 + 15 00 02 A8 93 + 15 00 02 A9 1E + 15 00 02 AA 2A + 15 00 02 AB 7E + 15 00 02 AC 1B + 15 00 02 AD 19 + 15 00 02 AE 4C + 15 00 02 AF 22 + 15 00 02 B0 28 + 15 00 02 B1 4B + 15 00 02 B2 59 + 15 00 02 B3 23 + 15 00 02 C0 00 + 15 00 02 C1 1B + 15 00 02 C2 2A + 15 00 02 C3 14 + 15 00 02 C4 17 + 15 00 02 C5 2B + 15 00 02 C6 1F + 15 00 02 C7 20 + 15 00 02 C8 93 + 15 00 02 C9 1E + 15 00 02 CA 2A + 15 00 02 CB 7E + 15 00 02 CC 1B + 15 00 02 CD 19 + 15 00 02 CE 4C + 15 00 02 CF 22 + 15 00 02 D0 28 + 15 00 02 D1 4B + 15 00 02 D2 59 + 15 00 02 D3 23 + //39 00 04 FF 98 81 04 + //05 00 02 2D 80 + //05 00 02 2F 31 + 39 00 04 FF 98 81 00 + 05 78 01 11 + 05 14 01 29 + 15 00 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <78000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <60>;//70 //16 + hsync-len = <30>; //20 //5 + hback-porch = <60>; //59 + vfront-porch = <20>; //16 //8 + vsync-len = <8>; //5 + vback-porch = <16>; //22 //3 + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_logic>; + devfreq-events = <&dfi>; + upthreshold = <60>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 600000 + SYS_STATUS_REBOOT 600000 + SYS_STATUS_SUSPEND 240000 + SYS_STATUS_VIDEO_1080P 396000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_PERFORMANCE 600000 + SYS_STATUS_BOOST 396000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 528000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 582 240000 + 583 99999 396000 + >; + vop-dclk-mode = <1>; + auto-min-freq = <240000>; + auto-freq-en = <0>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + no-sdio; + no-sd; + disable-wp; + non-removable; + num-slots = <1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + status = "okay"; + reg = <0x40>; + + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vcc_io>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_ts_gpio1: rk817_ts_gpio1 { + pins = "gpio_ts"; + function = "pin_fun1"; + /* output-low; */ + /* input-enable; */ + }; + + rk817_gt_gpio2: rk817_gt_gpio2 { + pins = "gpio_gt"; + function = "pin_fun1"; + }; + + rk817_pin_ts: rk817_pin_ts { + pins = "gpio_ts"; + function = "pin_fun0"; + }; + + rk817_pin_gt: rk817_pin_gt { + pins = "gpio_gt"; + function = "pin_fun0"; + }; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_3v3: DCDC_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v0: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vcc_1v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc1v8_soc: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v0_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-name = "vcc1v0_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc3v3_pmu: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_sd: LDO_REG6 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vcc2v8_dvp: LDO_REG7 { + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <2800000>; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd1v5_dvp: LDO_REG9 { + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3500 3548 3592 3636 3687 3740 3780 + 3806 3827 3846 3864 3889 3929 3964 + 3993 4015 4030 4041 4056 4076 4148>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4200>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + out-l2spk-r2hp; + spk-ctl-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + ts@40 { + status = "okay"; + compatible = "GSL,GSL_THZY"; + reg = <0x40>; + irq_gpio_number = <&gpio0 RK_PB4 IRQ_TYPE_LEVEL_HIGH>; + rst_gpio_number = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + status = "okay"; + + gc032a: gc032a@21 { + status = "okay"; + compatible = "galaxycore,gc032a"; + reg = <0x21>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc0312_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + gc2145: gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_mipi_out: endpoint { + remote-endpoint = <&mipi_in_bcam>; + data-lanes = <1>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "disabled"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru SCLK_VIP_OUT>; + clock-names = "xvclk"; + + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vdd1v5_dvp>; + + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan-9569A2"; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + sensor@26 { + compatible = "gs_da223"; + reg = <0x26>; + type = ; + irq_enable = <0>; + poll_delay_ms = <10>; + layout = <3>; + }; + + sensor@19 { + compatible = "gs_sc7a20"; + reg = <0x19>; + type = ; + irq_enable = <0>; + poll_delay_ms = <10>; + layout = <1>; + }; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + reg = <0x68>; + irq-gpio = <&gpio3 14 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <1 0 0 0 1 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <1>; + support-hw-poweroff = <1>; + mpu-debug = <1>; + }; + + sensor@4c { + status = "disabled"; + compatible = "gs_mc3230"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <9>; + reprobe_en = <1>; + irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>; + }; + + sensor@18 { + status = "gs_mc3230"; + compatible = "gs_sc7a30"; + reg = <0x18>; + type = ; + irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + reprobe_en = <1>; + }; + + sensor@10 { + status = "gs_mc3230"; + compatible = "light_cm3218"; + pinctrl-names = "default"; + pinctrl-0 = <&cm3218_irq_gpio>; + reg = <0x10>; + type = ; + irq-gpio = <&gpio3 15 IRQ_TYPE_EDGE_FALLING>; + irq_enable = <1>; + poll_delay_ms = <30>; + }; +}; + +&i2s_8ch { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + + dvp-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_io>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vcc_3v3>; +}; + +&isp_dvp_d2d9 { + rockchip,pins = + /* cif_data4 ... cif_data9 */ + <1 RK_PA2 1 &pcfg_pull_down>, + <1 RK_PA3 1 &pcfg_pull_down>, + <1 RK_PA4 1 &pcfg_pull_down>, + <1 RK_PA5 1 &pcfg_pull_down>, + <1 RK_PA6 1 &pcfg_pull_down>, + <1 RK_PA7 1 &pcfg_pull_down>, + /* cif_sync, cif_href */ + <1 RK_PB0 1 &pcfg_pull_down>, + <1 RK_PB1 1 &pcfg_pull_down>, + /* cif_clkin */ + <1 RK_PB2 1 &pcfg_pull_down>; +}; + +&isp_dvp_d10d11 { + rockchip,pins = + /* cif_data10, cif_data11 */ + <1 RK_PB6 1 &pcfg_pull_down>, + <1 RK_PB7 1 &pcfg_pull_down>; +}; + +&isp_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_bcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc2145_mipi_out>; + data-lanes = <1>; + }; + + mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp_mipi_in>; + }; + }; + }; +}; + +&nandc0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmu-supply = <&vcc3v3_pmu>; + vop-supply = <&vcc3v3_pmu>; +}; + +&pwm0 { + status = "okay"; +}; + +&pinctrl { + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA0 2 &pcfg_pull_none>; + }; + + vsel_gpio: vsel-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm3218 { + cm3218_irq_gpio: cm3218-irq-gpio { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dc_det { + dc_irq_gpio: dc-irq-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcfg_pull_none_4ma: pcfg-pull-none-4ma { + bias-disable; + drive-strength = <4>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_input_high: pcfg-input-high { + bias-pull-up; + input-enable; + }; + + pcfg_input: pcfg-input { + input-enable; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_rts_gpio: uart0-rts-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkisp1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>; + port { + #address-cells = <1>; + #size-cells = <0>; + + dvp_in_fcam: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc0312_out>; + }; + + isp_mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy_rx_out>; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + Rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF + | RKPM_SLP_PMU_PLLS_PWRDN + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_SFT_PLLS_DEEP + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_SFT_PD_NBSCUS + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_USB_WKUP_EN + | RKPM_CLUSTER_L_WKUP_EN + ) + >; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + clock-frequency = <37500000>; + clock-freq-min-max = <400000 37500000>; + no-sdio; + no-mmc; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + vmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "disabled"; +}; + +&sdio0 { + max-frequency = <50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + tsadc-supply = <&vdd_cpu>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&u2phy { + status = "okay"; + + u2phy_otg: otg-port { + status = "okay"; + }; + + u2phy_host: host-port { + phy-supply = <&vcc_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + diff --git a/rk3399-android.dtsi b/rk3399-android.dtsi new file mode 100644 index 0000000..231fd6d --- /dev/null +++ b/rk3399-android.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3399-vop-clk-set.dtsi" +#include + +/ { + compatible = "rockchip,android", "rockchip,rk3399"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m"; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&cpu_id>; + nvmem-cell-names = "id"; + }; + + debug: debug { + compatible = "rockchip,debug"; + reg = <0x0 0xfe430000 0x0 0x1000>, + <0x0 0xfe432000 0x0 0x1000>, + <0x0 0xfe434000 0x0 0x1000>, + <0x0 0xfe436000 0x0 0x1000>, + <0x0 0xfe610000 0x0 0x1000>, + <0x0 0xfe710000 0x0 0x1000>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + vendor_storage_rm: vendor-storage-rm@00000000 { + compatible = "rockchip,vendor-storage-rm"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + + secure_memory: secure-memory@20000000 { + compatible = "rockchip,secure-memory"; + reg = <0x0 0x20000000 0x0 0x10000000>; + status = "disabled"; + }; + + stb_devinfo: stb-devinfo@00000000 { + compatible = "rockchip,stb-devinfo"; + reg = <0x0 0x0 0x0 0x0>; + }; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + vendor_storage: vendor-storage { + compatible = "rockchip,ram-vendor-storage"; + memory-region = <&vendor_storage_rm>; + status = "okay"; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rga2"; + dev_mode = <1>; + reg = <0x0 0xff680000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3399_PD_RGA>; + status = "okay"; + }; + + hdmi_dp_sound: hdmi-dp-sound { + status = "disabled"; + compatible = "rockchip,rk3399-hdmi-dp"; + rockchip,cpu = <&i2s2>; + rockchip,codec = <&hdmi>, <&cdn_dp>; + }; + + firmware { + firmware_android: android {}; + + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&uart2 { + status = "disabled"; +}; + +&vopb { + support-multi-area; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + support-multi-area; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + secure-memory-region = <&secure_memory>; + route { + route_hdmi: route-hdmi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + panel@0 { + reg = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&i2s2 { + #sound-dai-cells = <0>; + rockchip,bclk-fs = <128>; +}; + +&rkvdec { + status = "okay"; +}; + +&vdec_mmu { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&pvtm { + status = "okay"; +}; + +&rng { + status = "okay"; +}; + +&pinctrl { + isp { + cif_clkout: cif-clkout { + rockchip,pins = + /*cif_clkout*/ + <2 RK_PB3 3 &pcfg_pull_none>; + }; + + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + /*cif_data0*/ + <2 RK_PA0 3 &pcfg_pull_none>, + /*cif_data1*/ + <2 RK_PA1 3 &pcfg_pull_none>, + /*cif_data2*/ + <2 RK_PA2 3 &pcfg_pull_none>, + /*cif_data3*/ + <2 RK_PA3 3 &pcfg_pull_none>, + /*cif_data4*/ + <2 RK_PA4 3 &pcfg_pull_none>, + /*cif_data5*/ + <2 RK_PA5 3 &pcfg_pull_none>, + /*cif_data6*/ + <2 RK_PA6 3 &pcfg_pull_none>, + /*cif_data7*/ + <2 RK_PA7 3 &pcfg_pull_none>, + /*cif_sync*/ + <2 RK_PB0 3 &pcfg_pull_none>, + /*cif_href*/ + <2 RK_PB1 3 &pcfg_pull_none>, + /*cif_clkin*/ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/rk3399-box-rev1.dts b/rk3399-box-rev1.dts new file mode 100644 index 0000000..2a7d5a6 --- /dev/null +++ b/rk3399-box-rev1.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3399-box.dtsi" + +/ { + model = "Rockchip RK3399 Board rev1 (BOX)"; + compatible = "rockchip-box-rev1","rockchip,rk3399-box"; +}; + +&pinctrl { + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>, + <4 RK_PB1 1 &pcfg_pull_up_8ma>, + <4 RK_PB2 1 &pcfg_pull_up_8ma>, + <4 RK_PB3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&i2c4 { + status = "okay"; + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&dp_in_vopb { + status = "disabled"; +}; diff --git a/rk3399-box-rev2.dts b/rk3399-box-rev2.dts new file mode 100644 index 0000000..8e66b23 --- /dev/null +++ b/rk3399-box-rev2.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3399-box.dtsi" + +/ { + model = "Rockchip RK3399 Board rev2 (BOX)"; + compatible = "rockchip-box-rev2","rockchip,rk3399-box"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&cpt_gpio>; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>, + <4 RK_PB1 1 &pcfg_pull_up_8ma>, + <4 RK_PB2 1 &pcfg_pull_up_8ma>, + <4 RK_PB3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + compat { + cpt_gpio: cpt-gpio { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; +}; + +&i2c4 { + status = "okay"; + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x019d>, + <000000000 0x0000 0x0000 0x0000>; +}; diff --git a/rk3399-box.dtsi b/rk3399-box.dtsi new file mode 100644 index 0000000..e8c75eb --- /dev/null +++ b/rk3399-box.dtsi @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3399.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-opp.dtsi" + +/ { + compatible = "rockchip,rk3399-box","rockchip,rk3399"; + + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + /* for rockchip boot on */ + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + + vin-supply = <&vcc_sys>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + /* wifi-bt-power-toggle; */ + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + /* BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&hdmi_dp_sound { + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>; +}; + +&sdmmc { + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + card-detect-delay = <800>; + status = "okay"; +}; + +&sdio0 { + clock-frequency = <100000000>; + clock-freq-min-max = <200000 100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; +}; + +&spdif { + pinctrl-0 = <&spdif_bus_1>; + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&threshold { + temperature = <85000>; +}; + +&target { + temperature = <100000>; +}; + +&soc_crit { + temperature = <115000>; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <120000>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&pwm3 { + status = "okay"; + + interrupts = ; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&rgmii_pins>; + pinctrl-1 = <&rgmii_sleep_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; +}; + +&pvtm { + status = "okay"; +}; + +&pmu_pvtm { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; diff --git a/rk3399-dram-default-timing.dtsi b/rk3399-dram-default-timing.dtsi new file mode 100644 index 0000000..c1ca2f3 --- /dev/null +++ b/rk3399-dram-default-timing.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include + +/ { + ddr_timing: ddr_timing { + compatible = "rockchip,ddr-timing"; + ddr3_speed_bin = <21>; + pd_idle = <0>; + sr_idle = <0>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + auto_lp_dis_freq = <666>; + ddr3_dll_dis_freq = <300>; + phy_dll_dis_freq = <260>; + + ddr3_odt_dis_freq = <666>; + ddr3_drv = ; + ddr3_odt = ; + phy_ddr3_ca_drv = ; + phy_ddr3_dq_drv = ; + phy_ddr3_odt = ; + + lpddr3_odt_dis_freq = <666>; + lpddr3_drv = ; + lpddr3_odt = ; + phy_lpddr3_ca_drv = ; + phy_lpddr3_dq_drv = ; + phy_lpddr3_odt = ; + + lpddr4_odt_dis_freq = <800>; + lpddr4_drv = ; + lpddr4_dq_odt = ; + lpddr4_ca_odt = ; + phy_lpddr4_ca_drv = ; + phy_lpddr4_ck_cs_drv = ; + phy_lpddr4_dq_drv = ; + phy_lpddr4_odt = ; + }; +}; diff --git a/rk3399-early-opp.dtsi b/rk3399-early-opp.dtsi new file mode 100644 index 0000000..8c31a29 --- /dev/null +++ b/rk3399-early-opp.dtsi @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/* + * NOTE: this file exists for the sake of early (pre-ES2) silicon. ES2 silicon + * will have different power characteristics. + */ + +/ { + /delete-node/ opp-table0; + /delete-node/ opp-table1; + /delete-node/ opp-table2; + + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1200000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1200000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1200000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <900000 900000 1200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000 950000 1200000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1050000 1050000 1200000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <900000 900000 1200000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1200000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1200000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <950000 950000 1200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000 1000000 1200000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <900000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + }; +}; diff --git a/rk3399-evb-cros.dtsi b/rk3399-evb-cros.dtsi new file mode 100644 index 0000000..54fed8e --- /dev/null +++ b/rk3399-evb-cros.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + model = "Rockchip RK3399 Evaluation Board (Chrome OS)"; + compatible = "google,rk3399evb", "rockchip,rk3399-evb", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "lg,lp097qx1-spa1", "panel-simple"; + backlight = <&backlight>; + power-supply = <&vcc3v3_s0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + hdmi_codec: hdmi-codec { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "HDMI-CODEC"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + sound { + compatible = "rockchip,cdndp-sound"; + rockchip,cpu = <&i2s2>; + rockchip,codec = <&cdn_dp>; + }; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>, <&fusb1>; + + ports { + /* Don't use vopl for dp, save it for edp */ + dp_in: port { + /delete-node/ endpoint@1; + }; + }; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="boe,tv080wum-nl0"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&edp { + status = "disabled"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; + + /* Don't use vopl for dp, save it for edp */ + vopl_out: port { + /delete-node/ endpoint@3; + }; +}; + +&vopl_mmu { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; diff --git a/rk3399-evb-ind-lpddr4-android-avb.dts b/rk3399-evb-ind-lpddr4-android-avb.dts new file mode 100644 index 0000000..34a9b66 --- /dev/null +++ b/rk3399-evb-ind-lpddr4-android-avb.dts @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3399-evb-ind.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-ind-lpddr4-android", "rockchip,rk3399"; + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; + }; + + iram: sram@ff8d0000 { + compatible = "mmio-sram"; + reg = <0x0 0xff8d0000 0x0 0x20000>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + test-power { + status = "okay"; + }; +}; + +&backlight { + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&dmac_bus { + iram = <&iram>; + rockchip,force-iram; +}; + +&dp_sound { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + sgm3784: sgm3784@30 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sgmicro,gsm3784"; + reg = <0x30>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + //enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + //strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + sgm3784_led0: led@0 { + reg = <0x0>; + led-max-microamp = <299200>; + flash-max-microamp = <1122000>; + flash-max-timeout-us = <1600000>; + }; + + sgm3784_led1: led@1 { + reg = <0x1>; + led-max-microamp = <299200>; + flash-max-microamp = <1122000>; + flash-max-timeout-us = <1600000>; + }; + }; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc2145: gc2145@3c{ + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + power-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + reset-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + lens-focus = <&vm149c>; + flash-leds = <&sgm3784_led0 &sgm3784_led1>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + //remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + ov4689: ov4689@36 { + compatible = "ovti,ov4689"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "JSD3425-C1"; + rockchip,camera-module-lens-name = "JSD3425-C1"; + port { + ucam_out1: endpoint { + //remote-endpoint = <&mipi_in_ucam0>; + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&rk809_sound { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout &isp_dvp_d0d7>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + dvp_in_fcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + }; +}; + +/* + * if enable dp_sound, should disable spdif_sound and spdif_out + */ +&spdif_out { + status = "disabled"; +}; + +&spdif_sound { + status = "disabled"; +}; + +&i2s0 { + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&tc358749x_sound { + status = "disabled"; +}; + +&pinctrl { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/rk3399-evb-ind-lpddr4-android.dts b/rk3399-evb-ind-lpddr4-android.dts new file mode 100644 index 0000000..bb53e27 --- /dev/null +++ b/rk3399-evb-ind-lpddr4-android.dts @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3399-evb-ind.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-ind-lpddr4-android", "rockchip,rk3399"; + + iram: sram@ff8d0000 { + compatible = "mmio-sram"; + reg = <0x0 0xff8d0000 0x0 0x20000>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + test-power { + status = "okay"; + }; +}; + +&backlight { + enable-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; +}; + +&dmac_bus { + iram = <&iram>; + rockchip,force-iram; +}; + +&dp_sound { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&rk809_sound { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +/* + * if enable dp_sound, should disable spdif_sound and spdif_out + */ +&spdif_out { + status = "disabled"; +}; + +&spdif_sound { + status = "disabled"; +}; + +&i2s0 { + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&tc358749x_sound { + status = "disabled"; +}; + +&pinctrl { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/rk3399-evb-ind-lpddr4-linux.dts b/rk3399-evb-ind-lpddr4-linux.dts new file mode 100644 index 0000000..bc82021 --- /dev/null +++ b/rk3399-evb-ind-lpddr4-linux.dts @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019-2020 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3399-evb-ind.dtsi" +#include "rk3399-linux.dtsi" + +/ { + model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Linux)"; + compatible = "rockchip,linux", "rockchip,rk3399-evb-ind-lpddr4-linux", "rockchip,rk3399"; + + iram: sram@ff8d0000 { + compatible = "mmio-sram"; + reg = <0x0 0xff8d0000 0x0 0x20000>; + }; + + hub_reset: hub-reset { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; + regulator-name = "hub_reset"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + test-power { + status = "okay"; + }; +}; + +&backlight { + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmac_bus { + iram = <&iram>; + rockchip,force-iram; +}; + +&dp_sound { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + + lens-focus = <&vm149c>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s0 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&rk809_sound { + status = "okay"; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&route_edp { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopb_out_hdmi>; +}; + +/* + * if enable dp_sound, should disable spdif_sound and spdif_out + */ +&spdif_out { + status = "disabled"; +}; + +&spdif_sound { + status = "disabled"; +}; + +&tc358749x_sound { + status = "disabled"; +}; + +&vcca_0v9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; +}; + +&vcc0v9_soc { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ + diff --git a/rk3399-evb-ind-lpddr4-v13-android-avb.dts b/rk3399-evb-ind-lpddr4-v13-android-avb.dts new file mode 100644 index 0000000..7509122 --- /dev/null +++ b/rk3399-evb-ind-lpddr4-v13-android-avb.dts @@ -0,0 +1,427 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3399-evb-ind.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 EVB IND LPDDR4 Board edp (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-ind-v13-lpddr4-android", "rockchip,rk3399"; + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; + }; + + iram: sram@ff8d0000 { + compatible = "mmio-sram"; + reg = <0x0 0xff8d0000 0x0 0x20000>; + }; + + hub_reset: hub_reset { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; + regulator-name = "hub_reset"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + test-power { + status = "okay"; + }; +}; + +&backlight { + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&dmac_bus { + iram = <&iram>; + rockchip,force-iram; +}; + +&dp_sound { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + sgm3784: sgm3784@30 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sgmicro,gsm3784"; + reg = <0x30>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + //enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + //strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + sgm3784_led0: led@0 { + reg = <0x0>; + led-max-microamp = <299200>; + flash-max-microamp = <1122000>; + flash-max-timeout-us = <1600000>; + }; + + sgm3784_led1: led@1 { + reg = <0x1>; + led-max-microamp = <299200>; + flash-max-microamp = <1122000>; + flash-max-timeout-us = <1600000>; + }; + }; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc2145: gc2145@3c{ + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + power-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + reset-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + lens-focus = <&vm149c>; + flash-leds = <&sgm3784_led0 &sgm3784_led1>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + //remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + ov4689: ov4689@36 { + compatible = "ovti,ov4689"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "JSD3425-C1"; + rockchip,camera-module-lens-name = "JSD3425-C1"; + port { + ucam_out1: endpoint { + //remote-endpoint = <&mipi_in_ucam0>; + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&rk809_sound { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout &isp_dvp_d0d7>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + dvp_in_fcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + }; +}; + + +&vcca_0v9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; +}; + +&vcc0v9_soc { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-off-in-suspend; + }; +}; + +/* + * if enable dp_sound, should disable spdif_sound and spdif_out + */ +&spdif_out { + status = "disabled"; +}; + +&spdif_sound { + status = "disabled"; +}; + +&i2s0 { + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&tc358749x_sound { + status = "disabled"; +}; + +&pinctrl { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/rk3399-evb-ind.dtsi b/rk3399-evb-ind.dtsi new file mode 100644 index 0000000..ddd3dcd --- /dev/null +++ b/rk3399-evb-ind.dtsi @@ -0,0 +1,1514 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "dt-bindings/pwm/pwm.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" +#include +#include "rk3399-vop-clk-set.dtsi" +#include +#include "dt-bindings/usb/pd.h" + +/ { + compatible = "rockchip,rk3399-evb-ind", "rockchip,rk3399"; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dw_hdmi_audio: dw-hdmi-audio { + status = "disabled"; + compatible = "rockchip,dw-hdmi-audio"; + #sound-dai-cells = <0>; + }; + + rk809_sound: rk809-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + io-channels = <&saradc 2>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + dp_sound: dp-sound { + status = "disabled"; + compatible = "rockchip,cdndp-sound"; + rockchip,cpu = <&spdif>; + rockchip,codec = <&cdn_dp 1>; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <256>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s2>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + spdif_sound: spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + BT,wake_host_irq = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* GPIO2_D3 */ + status = "okay"; + }; + + rk_modem: rk-modem { + compatible="4g-modem-platdata"; + pinctrl-names = "default"; + pinctrl-0 = <<e_vbat <e_power_en <e_reset>; + 4G,vbat-gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + 4G,power-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + 4G,reset-gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + tc358749x_sound:tc358749x-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rk,hdmiin-tc358749x-codec"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + sound0_master: simple-audio-card,codec { + sound-dai = <&tc358749x>; + }; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_usbnet: vcc5v0-usbnet { + compatible = "regulator-fixed"; + enable-active-high; + /*disabled r8152 usb net default*/ + //regulator-always-on; + //regulator-boot-on; + gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usbnet_pwr_drv>; + regulator-name = "vcc5v0_usbnet"; + startup-delay-us = <20000>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + status = "okay"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "regulator-fixed"; + regulator-name = "vdd_log"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 856000 + SYS_STATUS_REBOOT 856000 + SYS_STATUS_SUSPEND 328000 + SYS_STATUS_VIDEO_1080P 666000 + SYS_STATUS_VIDEO_4K 856000 + SYS_STATUS_VIDEO_4K_10B 856000 + SYS_STATUS_PERFORMANCE 856000 + SYS_STATUS_BOOST 856000 + SYS_STATUS_DUALVIEW 856000 + SYS_STATUS_ISP 856000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 416000 + 763 3012 666000 + 3013 99999 856000 + >; + + vop-pn-msch-readlatency = < + 0 0x20 + 4 0x20 + >; + + auto-min-freq = <328000>; + auto-freq-en = <0>; +}; + +&dmc_opp_table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <900000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-856000000 { + opp-hz = /bits/ 64 <856000000>; + opp-microvolt = <900000>; + }; + opp-928000000 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 150000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x22>; + rx_delay = <0x23>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; + reg = <0x10>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int_l>; + pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>,<&rk809_slppin_null>; + rockchip,system-power-controller; + #clock-cells = <1>; + pmic-reset-func = <0>; + wakeup-source; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk809_slppin_null: rk809_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk809_slppin_slp: rk809_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk809_slppin_pwrdn: rk809_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk809_slppin_rst: rk809_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_usb"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + /* + battery { + compatible = "rk817,battery"; + ocv_table = <7000 7250 7370 7384 7436 7470 7496 + 7520 7548 7576 7604 7632 7668 7706 + 7754 7816 7892 7950 8036 8142 8212>; + design_capacity = <2500>; + design_qmax = <2750>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <7000>; + zero_algorithm_vol = <7700>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + bat_res_up = <140>; + bat_res_down = <20>; + }; + */ + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + assigned-clocks = <&cru SCLK_I2SOUT_SRC>; + assigned-clock-parents = <&cru SCLK_I2S1_8CH>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + clock-frequency = <400000>; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + tc358749x: tc358749x@0f { + #sound-dai-cells = <0>; + compatible = "toshiba,tc358749x"; + reg = <0x0f>; + power-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + stanby-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmiin_gpios>; + status = "okay"; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <475>; + i2c-scl-falling-time-ns = <26>; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <0>; + orientation-y= <0>; + orientation-z= <0>; + mpu-debug = <1>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <8>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <8>; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + displayport = <&cdn_dp>; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&tcphy0_orientation_switch>; + }; + }; + port@1 { + reg = <1>; + dp_mode_sw: endpoint { + remote-endpoint = <&tcphy_dp_altmode_switch>; + }; + }; + }; + }; + }; + + sensor@0d { + status = "okay"; + compatible = "ak8963"; + pinctrl-names = "default"; + pinctrl-0 = <&ak8963_irq_gpio>; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio1 0 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + }; + + bq25700: bq25700@6b {//6a + compatible = "ti,bq25703"; + reg = <0x6b>; + + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok>; + ti,charge-current = <2500000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,max-charge-voltage = <8750000>; + ti,input-current = <500000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,minimum-sys-voltage = <7400000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + pd-charge-only = <0>; + status = "disabled"; + }; +}; + +&i2c6 { + cw2015@62 { + status = "disabled"; + compatible = "cw201x"; + reg = <0x62>; + bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 + 0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24 + 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 + 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E + 0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D + 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 + 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB + 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>; + monitor_sec = <5>; + virtual_power = <0>; + }; +}; + +&i2s0 { + status = "disabled"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s1 { + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + dmas = <&dmac_bus 4>; + dma-names = "tx"; + status = "disabled"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_3v0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca_1v8>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vccio_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pwm0 { + status = "disabled"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&pwm3 { + status = "okay"; + + interrupts = ; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <4>; + pinctrl-names = "default"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&saradc { + status = "okay"; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&sdio0 { + clock-frequency = <150000000>; + clock-freq-min-max = <200000 150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + clock-frequency = <150000000>; + clock-freq-min-max = <100000 150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&tcphy0 { + status = "okay"; + + svid = <0xff01>; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + tcphy_dp_altmode_switch: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_mode_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + status = "okay"; + }; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&pinctrl { + + ak8963 { + ak8963_irq_gpio: ak8963-irq-gpio { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + charger { + charger_ok: charge-ok { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + i2s0 { + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>; + }; + + i2s_8ch_mclk: i2s-8ch-mclk { + rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_2ch_bus: i2s1-2ch-bus { + rockchip,pins = + <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA5 1 &pcfg_pull_none>, + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmiin { + hdmiin_gpios: hdmiin_gpios { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = + <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rk-modem { + lte_vbat: lte-vbat { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lte_power_en: lte-power-en { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lte_reset: lte-reset { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usbnet { + usbnet_pwr_drv: usbnet-pwr-drv { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399-evb-rev1-android.dts b/rk3399-evb-rev1-android.dts new file mode 100644 index 0000000..e4c094e --- /dev/null +++ b/rk3399-evb-rev1-android.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev1.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v1 (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-rev1", "rockchip,rk3399"; +}; + +&vdd_log { + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; +}; + +&vdd_center { + rockchip,pwm_id= <3>; + rockchip,pwm_voltage = <900000>; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3399-evb-rev1-cros.dts b/rk3399-evb-rev1-cros.dts new file mode 100644 index 0000000..a333345 --- /dev/null +++ b/rk3399-evb-rev1-cros.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev1.dtsi" +#include "rk3399-evb-cros.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v1 (Chrome OS)"; + compatible = "google,rk3399evb-rev1", "rockchip,rk3399-evb-rev1", "rockchip,rk3399"; +}; diff --git a/rk3399-evb-rev1.dtsi b/rk3399-evb-rev1.dtsi new file mode 100644 index 0000000..afd652b --- /dev/null +++ b/rk3399-evb-rev1.dtsi @@ -0,0 +1,316 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3399-evb.dtsi" +#include "rk3399-early-opp.dtsi" + +/ { + compatible = "rockchip,rk3399-evb-rev1", "rockchip,rk3399"; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + rockchip,pwm_id = <2>; + rockchip,pwm_voltage = <900000>; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + rockchip,pwm_id = <3>; + rockchip,pwm_voltage = <900000>; + pwms = <&pwm3 0 25000 1>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&cpu_l0 { + dynamic-power-coefficient = <121>; +}; + +&cpu_b0 { + dynamic-power-coefficient = <1068>; +}; + +&soc_thermal { + sustainable-power = <1600>; /* milliwatts */ + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <10240>; + }; + map1 { + trip = <&target>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <10240>; + }; + }; +}; + +&gpu_power_model { + dynamic-power = <1780>; +}; + +&i2c0 { + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mp8865: mp8865@68 { + compatible = "mps,mp8865"; + reg = <0x68>; + regulators { + vdd_gpu: mp8865_dcdc1 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <8000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_cpu_b: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_b"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c4 { + fusb1: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-5v-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,utmi-avalid; +}; diff --git a/rk3399-evb-rev2-android.dts b/rk3399-evb-rev2-android.dts new file mode 100644 index 0000000..fa523cd --- /dev/null +++ b/rk3399-evb-rev2-android.dts @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev2.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v2 (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-rev2", "rockchip,rk3399"; +}; + +&vdd_center { + rockchip,pwm_id= <3>; + rockchip,pwm_voltage = <900000>; +}; + +&i2s2 { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&spdif_out { + status = "okay"; +}; + +&spdif_sound { + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3399-evb-rev2-cros.dts b/rk3399-evb-rev2-cros.dts new file mode 100644 index 0000000..cb45ed1 --- /dev/null +++ b/rk3399-evb-rev2-cros.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev2.dtsi" +#include "rk3399-evb-cros.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v2 (Chrome OS)"; + compatible = "google,rk3399evb-rev2", "rockchip,rk3399-evb-rev2", "rockchip,rk3399"; +}; diff --git a/rk3399-evb-rev2.dtsi b/rk3399-evb-rev2.dtsi new file mode 100644 index 0000000..9335df7 --- /dev/null +++ b/rk3399-evb-rev2.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3399-evb.dtsi" +#include "rk3399-early-opp.dtsi" + +/ { + compatible = "rockchip,rk3399-evb-rev2", "rockchip,rk3399"; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + rockchip,pwm_id = <3>; + rockchip,pwm_voltage = <900000>; + pwms = <&pwm3 0 25000 1>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; +}; + +&cpu_l0 { + dynamic-power-coefficient = <121>; +}; + +&cpu_b0 { + dynamic-power-coefficient = <1068>; +}; + +&soc_thermal { + sustainable-power = <1600>; /* milliwatts */ + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <10240>; + }; + map1 { + trip = <&target>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <10240>; + }; + }; +}; + +&gpu_power_model { + dynamic-power = <1780>; +}; + +&i2c0 { + fusb1: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-5v-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + lp8752: lp8752@60 { + compatible = "ti,lp8752"; + reg = <0x60>; + vin0-supply = <&vcc5v0_sys>; + regulators { + vdd_gpu: lp8752_buck0 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <6000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_log"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3a_pin_pull_down>; +}; + +&u2phy0_otg { + rockchip,utmi-avalid; +}; + +&i2c6 { + status = "okay"; + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; diff --git a/rk3399-evb-rev3-android-edp.dts b/rk3399-evb-rev3-android-edp.dts new file mode 100644 index 0000000..9421e9d --- /dev/null +++ b/rk3399-evb-rev3-android-edp.dts @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev3.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v3 edp (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-rev3", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "lg,lp079qx1-sp0v", "panel-simple"; + backlight = <&backlight>; + power-supply = <&vcc3v3_s0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&i2s2 { + status = "okay"; +}; + +>9xx { + status = "disabled"; +}; + +&i2c4 { + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; +}; + +&edp { + force-hpd; + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&route_edp { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3399-evb-rev3-android-lp4.dts b/rk3399-evb-rev3-android-lp4.dts new file mode 100644 index 0000000..85f4356 --- /dev/null +++ b/rk3399-evb-rev3-android-lp4.dts @@ -0,0 +1,233 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rk3399-evb-rev3.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v3 (Android) LPDDR4"; + compatible = "rockchip,android", "rockchip,rk3399-evb-rev3-android-lp4", "rockchip,rk3399"; + + /* first 64k(0xff8c0000~0xff8d0000) for ddr and suspend */ + iram: sram@ff8d0000 { + compatible = "mmio-sram"; + reg = <0x0 0xff8d0000 0x0 0x20000>; /* 128k */ + }; +}; + +&dmac_bus { + iram = <&iram>; + rockchip,force-iram; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + dsp_lut: dsp-lut { + gamma-lut = < + 0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 + 0x00080808 0x00090909 0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f + 0x00101010 0x00111111 0x00121212 0x00131313 0x00141414 0x00151515 0x00161616 0x00171717 + 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d 0x001e1e1e 0x001f1f1f + 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727 + 0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f + 0x00303030 0x00313131 0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 + 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b 0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f + 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545 0x00464646 0x00474747 + 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f + 0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 + 0x00585858 0x00595959 0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f + 0x00606060 0x00616161 0x00626262 0x00636363 0x00646464 0x00656565 0x00666666 0x00676767 + 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d 0x006e6e6e 0x006f6f6f + 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777 + 0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f + 0x00808080 0x00818181 0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 + 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b 0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f + 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595 0x00969696 0x00979797 + 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f + 0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 + 0x00a8a8a8 0x00a9a9a9 0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf + 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3 0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 + 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd 0x00bebebe 0x00bfbfbf + 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7 + 0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf + 0x00d0d0d0 0x00d1d1d1 0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 + 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb 0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf + 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5 0x00e6e6e6 0x00e7e7e7 + 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef + 0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 + 0x00f8f8f8 0x00f9f9f9 0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&cdn_dp { + extcon = <&fusb0>, <&fusb1>; + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 856000 + SYS_STATUS_REBOOT 416000 + SYS_STATUS_SUSPEND 416000 + SYS_STATUS_VIDEO_1080P 416000 + SYS_STATUS_VIDEO_4K 856000 + SYS_STATUS_VIDEO_4K_10B 856000 + SYS_STATUS_PERFORMANCE 856000 + SYS_STATUS_BOOST 856000 + SYS_STATUS_DUALVIEW 856000 + SYS_STATUS_ISP 856000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 577 416000 + 578 99999 856000 + >; + auto-min-freq = <416000>; + auto-freq-en = <1>; +}; + +&dmc_opp_table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-856000000 { + opp-hz = /bits/ 64 <856000000>; + opp-microvolt = <900000>; + }; + opp-928000000 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3399-evb-rev3-android-mipi-edp.dts b/rk3399-evb-rev3-android-mipi-edp.dts new file mode 100644 index 0000000..2672d1c --- /dev/null +++ b/rk3399-evb-rev3-android-mipi-edp.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev3.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v3 (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-rev3", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "lg,lp079qx1-sp0v", "panel-simple"; + backlight = <&backlight1>; + power-supply = <&vcc3v3_s0>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + + disp_timings: display-timings { + native-mode = <&F402>; + + F402: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&edp_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + dsp_lut: dsp-lut { + gamma-lut = < + 0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 + 0x00080808 0x00090909 0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f + 0x00101010 0x00111111 0x00121212 0x00131313 0x00141414 0x00151515 0x00161616 0x00171717 + 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d 0x001e1e1e 0x001f1f1f + 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727 + 0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f + 0x00303030 0x00313131 0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 + 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b 0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f + 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545 0x00464646 0x00474747 + 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f + 0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 + 0x00585858 0x00595959 0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f + 0x00606060 0x00616161 0x00626262 0x00636363 0x00646464 0x00656565 0x00666666 0x00676767 + 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d 0x006e6e6e 0x006f6f6f + 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777 + 0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f + 0x00808080 0x00818181 0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 + 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b 0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f + 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595 0x00969696 0x00979797 + 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f + 0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 + 0x00a8a8a8 0x00a9a9a9 0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf + 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3 0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 + 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd 0x00bebebe 0x00bfbfbf + 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7 + 0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf + 0x00d0d0d0 0x00d1d1d1 0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 + 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb 0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf + 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5 0x00e6e6e6 0x00e7e7e7 + 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef + 0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 + 0x00f8f8f8 0x00f9f9f9 0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&cdn_dp { + extcon = <&fusb0>, <&fusb1>; + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&edp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&route_edp { + status = "okay"; + connect = <&vopl_out_edp>; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +>9xx { + status = "disabled"; +}; diff --git a/rk3399-evb-rev3-android.dts b/rk3399-evb-rev3-android.dts new file mode 100644 index 0000000..a8514a7 --- /dev/null +++ b/rk3399-evb-rev3-android.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev3.dtsi" +#include "rk3399-android.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v3 (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-evb-rev3", "rockchip,rk3399"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <21>; + hfront-porch = <120>; + vback-porch = <18>; + vfront-porch = <21>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + dsp_lut: dsp-lut { + gamma-lut = < + 0x00000000 0x00010101 0x00020202 0x00030303 0x00040404 0x00050505 0x00060606 0x00070707 + 0x00080808 0x00090909 0x000a0a0a 0x000b0b0b 0x000c0c0c 0x000d0d0d 0x000e0e0e 0x000f0f0f + 0x00101010 0x00111111 0x00121212 0x00131313 0x00141414 0x00151515 0x00161616 0x00171717 + 0x00181818 0x00191919 0x001a1a1a 0x001b1b1b 0x001c1c1c 0x001d1d1d 0x001e1e1e 0x001f1f1f + 0x00202020 0x00212121 0x00222222 0x00232323 0x00242424 0x00252525 0x00262626 0x00272727 + 0x00282828 0x00292929 0x002a2a2a 0x002b2b2b 0x002c2c2c 0x002d2d2d 0x002e2e2e 0x002f2f2f + 0x00303030 0x00313131 0x00323232 0x00333333 0x00343434 0x00353535 0x00363636 0x00373737 + 0x00383838 0x00393939 0x003a3a3a 0x003b3b3b 0x003c3c3c 0x003d3d3d 0x003e3e3e 0x003f3f3f + 0x00404040 0x00414141 0x00424242 0x00434343 0x00444444 0x00454545 0x00464646 0x00474747 + 0x00484848 0x00494949 0x004a4a4a 0x004b4b4b 0x004c4c4c 0x004d4d4d 0x004e4e4e 0x004f4f4f + 0x00505050 0x00515151 0x00525252 0x00535353 0x00545454 0x00555555 0x00565656 0x00575757 + 0x00585858 0x00595959 0x005a5a5a 0x005b5b5b 0x005c5c5c 0x005d5d5d 0x005e5e5e 0x005f5f5f + 0x00606060 0x00616161 0x00626262 0x00636363 0x00646464 0x00656565 0x00666666 0x00676767 + 0x00686868 0x00696969 0x006a6a6a 0x006b6b6b 0x006c6c6c 0x006d6d6d 0x006e6e6e 0x006f6f6f + 0x00707070 0x00717171 0x00727272 0x00737373 0x00747474 0x00757575 0x00767676 0x00777777 + 0x00787878 0x00797979 0x007a7a7a 0x007b7b7b 0x007c7c7c 0x007d7d7d 0x007e7e7e 0x007f7f7f + 0x00808080 0x00818181 0x00828282 0x00838383 0x00848484 0x00858585 0x00868686 0x00878787 + 0x00888888 0x00898989 0x008a8a8a 0x008b8b8b 0x008c8c8c 0x008d8d8d 0x008e8e8e 0x008f8f8f + 0x00909090 0x00919191 0x00929292 0x00939393 0x00949494 0x00959595 0x00969696 0x00979797 + 0x00989898 0x00999999 0x009a9a9a 0x009b9b9b 0x009c9c9c 0x009d9d9d 0x009e9e9e 0x009f9f9f + 0x00a0a0a0 0x00a1a1a1 0x00a2a2a2 0x00a3a3a3 0x00a4a4a4 0x00a5a5a5 0x00a6a6a6 0x00a7a7a7 + 0x00a8a8a8 0x00a9a9a9 0x00aaaaaa 0x00ababab 0x00acacac 0x00adadad 0x00aeaeae 0x00afafaf + 0x00b0b0b0 0x00b1b1b1 0x00b2b2b2 0x00b3b3b3 0x00b4b4b4 0x00b5b5b5 0x00b6b6b6 0x00b7b7b7 + 0x00b8b8b8 0x00b9b9b9 0x00bababa 0x00bbbbbb 0x00bcbcbc 0x00bdbdbd 0x00bebebe 0x00bfbfbf + 0x00c0c0c0 0x00c1c1c1 0x00c2c2c2 0x00c3c3c3 0x00c4c4c4 0x00c5c5c5 0x00c6c6c6 0x00c7c7c7 + 0x00c8c8c8 0x00c9c9c9 0x00cacaca 0x00cbcbcb 0x00cccccc 0x00cdcdcd 0x00cecece 0x00cfcfcf + 0x00d0d0d0 0x00d1d1d1 0x00d2d2d2 0x00d3d3d3 0x00d4d4d4 0x00d5d5d5 0x00d6d6d6 0x00d7d7d7 + 0x00d8d8d8 0x00d9d9d9 0x00dadada 0x00dbdbdb 0x00dcdcdc 0x00dddddd 0x00dedede 0x00dfdfdf + 0x00e0e0e0 0x00e1e1e1 0x00e2e2e2 0x00e3e3e3 0x00e4e4e4 0x00e5e5e5 0x00e6e6e6 0x00e7e7e7 + 0x00e8e8e8 0x00e9e9e9 0x00eaeaea 0x00ebebeb 0x00ececec 0x00ededed 0x00eeeeee 0x00efefef + 0x00f0f0f0 0x00f1f1f1 0x00f2f2f2 0x00f3f3f3 0x00f4f4f4 0x00f5f5f5 0x00f6f6f6 0x00f7f7f7 + 0x00f8f8f8 0x00f9f9f9 0x00fafafa 0x00fbfbfb 0x00fcfcfc 0x00fdfdfd 0x00fefefe 0x00ffffff>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&cdn_dp { + extcon = <&fusb0>, <&fusb1>; + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; diff --git a/rk3399-evb-rev3-cros.dts b/rk3399-evb-rev3-cros.dts new file mode 100644 index 0000000..4fbc773 --- /dev/null +++ b/rk3399-evb-rev3-cros.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-evb-rev3.dtsi" +#include "rk3399-evb-cros.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board v3 (Chrome OS)"; + compatible = "google,rk3399evb-rev3", "rockchip,rk3399-evb-rev3", "rockchip,rk3399"; +}; diff --git a/rk3399-evb-rev3.dtsi b/rk3399-evb-rev3.dtsi new file mode 100644 index 0000000..64cd9c8 --- /dev/null +++ b/rk3399-evb-rev3.dtsi @@ -0,0 +1,317 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3399-evb.dtsi" +#include + +/ { + compatible = "rockchip,rk3399-evb-rev3", "rockchip,rk3399"; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + rockchip,pwm_id = <2>; + rockchip,pwm_voltage = <900000>; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3399"; + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c0 { + fusb1: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-5v-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_log"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&es8316 { + reg = <0x11>; +}; + +&i2c6 { + status = "okay"; + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; diff --git a/rk3399-evb.dts b/rk3399-evb.dts new file mode 100644 index 0000000..694b0d0 --- /dev/null +++ b/rk3399-evb.dts @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include "rk3399.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board"; + compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + }; + + edp_panel: edp-panel { + compatible ="lg,lp079qx1-sp0v"; + backlight = <&backlight>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + power-supply = <&vcc3v3_s0>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 25000 0>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + ep-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "disabled"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; diff --git a/rk3399-evb.dtsi b/rk3399-evb.dtsi new file mode 100644 index 0000000..9b39d2f --- /dev/null +++ b/rk3399-evb.dtsi @@ -0,0 +1,612 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + + home-key { + label = "home"; + linux,code = ; + press-threshold-microvolt = <621250>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + camera-key { + label = "camera"; + linux,code = ; + press-threshold-microvolt = <787500>; + }; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&es8316>; + }; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&dw_hdmi_audio>; + }; + }; + + dw_hdmi_audio: dw-hdmi-audio { + status = "disabled"; + compatible = "rockchip,dw-hdmi-audio"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&sdmmc { + clock-frequency = <150000000>; + clock-freq-min-max = <400000 150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&sdio0 { + clock-frequency = <150000000>; + clock-freq-min-max = <200000 150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&emmc_phy { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 800000 + SYS_STATUS_REBOOT 528000 + SYS_STATUS_SUSPEND 200000 + SYS_STATUS_VIDEO_1080P 200000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_VIDEO_4K_10B 800000 + SYS_STATUS_PERFORMANCE 800000 + SYS_STATUS_BOOST 400000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 600000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 577 200000 + 578 1701 300000 + 1702 99999 400000 + >; + auto-min-freq = <200000>; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; +}; + +&spdif { + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + es8316: es8316@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1900>; + tp-size = <911>; + tp-supply = <&vcc3v0_tp>; + }; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "disabled"; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy1 { + extcon = <&fusb1>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + extcon = <&fusb1>; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + extcon = <&fusb1>; +}; + +&pwm0 { + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + fusb1_int: fusb1-int { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pvtm { + status = "okay"; +}; + +&pmu_pvtm { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc1v8_pmu>; +}; + diff --git a/rk3399-excavator-sapphire.dtsi b/rk3399-excavator-sapphire.dtsi new file mode 100644 index 0000000..59cdade --- /dev/null +++ b/rk3399-excavator-sapphire.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3399-sapphire.dtsi" +#include +/ { + compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; + + rt5651_sound: rt5651-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "realtek,rt5651-codec"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0>; + rockchip,codec = <&rt5651>; + rockchip,audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "Speaker", "HPOL", + "Speaker", "HPOR", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "IN1P", "Main Mic", + "IN2P", "Headset Mic", + "IN2N", "Headset Mic", + "Headset Mic", "micbias1"; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 800000 + SYS_STATUS_REBOOT 528000 + SYS_STATUS_SUSPEND 200000 + SYS_STATUS_VIDEO_1080P 200000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_VIDEO_4K_10B 800000 + SYS_STATUS_PERFORMANCE 800000 + SYS_STATUS_BOOST 600000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 600000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 200000 + 763 1893 400000 + 1894 3012 528000 + 3013 99999 800000 + >; + auto-freq-en = <1>; + auto-min-freq = <200000>; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&i2s0 { + status = "okay"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5651: rt5651@1a { + #sound-dai-cells = <0>; + compatible = "rockchip,rt5651"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <0>; + mpu-debug = <1>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <2>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <2>; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&saradc { + status = "okay"; +}; + +&sdio0 { + max-frequency = <100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = + <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk3399-ficus.dts b/rk3399-ficus.dts new file mode 100644 index 0000000..1ce85a5 --- /dev/null +++ b/rk3399-ficus.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * + * Schematics available at https://dl.vamrs.com/products/ficus/docs/hw + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" + +/ { + model = "96boards RK3399 Ficus"; + compatible = "vamrs,ficus", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, + <&user_led3_pin>, <&user_led4_pin>, + <&wlan_led_pin>, <&bt_led_pin>; + + user_led1: led-1 { + label = "red:user1"; + gpios = <&gpio4 25 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2: led-2 { + label = "red:user2"; + gpios = <&gpio4 26 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3: led-3 { + label = "red:user3"; + gpios = <&gpio4 30 0>; + linux,default-trigger = "mmc1"; + }; + + user_led4: led-4 { + label = "red:user4"; + gpios = <&gpio1 0 0>; + panic-indicator; + linux,default-trigger = "none"; + }; + + wlan_active_led: led-5 { + label = "red:wlan"; + gpios = <&gpio1 1 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led: led-6 { + label = "red:bt"; + gpios = <&gpio1 4 0>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_sys>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led1_pin: user-led1-pin { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2_pin: user-led2-pin { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led3_pin: user-led3-pin { + rockchip,pins = + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led4_pin: user-led4-pin { + rockchip,pins = + <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led_pin: wlan-led-pin { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_led_pin: bt-led-pin { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&spi1 { + /* On both Low speed and High speed expansion */ + cs-gpios = <0>, <&gpio4 RK_PA6 0>, <&gpio4 RK_PA7 0>; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&vcc3v3_pcie { + gpio = <&gpio1 24 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; +}; diff --git a/rk3399-firefly-android.dts b/rk3399-firefly-android.dts new file mode 100644 index 0000000..1579231 --- /dev/null +++ b/rk3399-firefly-android.dts @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" +#include +#include +#include "rk3399-vop-clk-set.dtsi" + +/ { + model = "Rockchip RK3399 Firefly Board (Android)"; + compatible = "rockchip,rk3399-firefly-android", "rockchip,rk3399"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 coherent_pool=1m"; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&cpu_id>; + nvmem-cell-names = "id"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dw_hdmi_audio: dw-hdmi-audio { + status = "okay"; + compatible = "rockchip,dw-hdmi-audio"; + #sound-dai-cells = <0>; + }; + + edp_panel: edp-panel { + compatible = "sharp,lcd-f402", "panel-simple"; + status = "okay"; + + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <0>; + /* Only 115200 and 1500000 */ + rockchip,baudrate = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + interrupts = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + stb_devinfo: stb-devinfo@00000000 { + compatible = "rockchip,stb-devinfo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + }; + + rockchip-key { + compatible = "rockchip,key"; + status = "okay"; + + io-channels = <&saradc 1>; + power-key { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + }; + + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&dw_hdmi_audio>; + }; + }; + + hdmi_codec: hdmi-codec { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "HDMI-CODEC"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rga2"; + dev_mode = <1>; + reg = <0x0 0xff680000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3399_PD_RGA>; + dma-coherent; + status = "okay"; + }; + + spdif-sound { + compatible = "simple-audio-card"; + status = "okay"; + + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + status = "okay"; + + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-name = "vcc3v3_pcie"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + /* + * the firefly hardware using 3.0 v as APIO2_VDD + * voltage, but the pwm divider resistance is designed + * based on hardware which the APIO2_VDD is 1.8v, so we + * need to change the regulator-max-microvolt from 1.4v + * to 1.0v, so the pwm can output 0.9v voltage. + */ + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + /* for rockchip boot on */ + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_lcd: vcc-lcd-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + regulator-name = "vcc_lcd"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_edp: route-edp { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&edp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>; + hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 4>; + hp-det-adc-value = <500>; + status = "okay"; + }; +}; + +&i2c3 { + status = "okay"; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + gsl3680: gsl3680@41 { + compatible = "gslX680-pad"; + reg = <0x41>; + screen_max_x = <1536>; + screen_max_y = <2048>; + touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mpu6050: mpu@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <1>; + orientation-y= <1>; + orientation-z= <1>; + irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>; + mpu-debug = <1>; + status = "okay"; + }; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s1 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + lcd_en: lcd-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_3g_drv: pcie-3g-drv { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rt5640 { + rt5640_hpcon: rt5640-hpcon { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&rockchip_suspend { + rockchip,power-ctrl = + <&gpio1 18 GPIO_ACTIVE_LOW>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vccadc_ref>; +}; + +&sdhci { + bus-width = <8>; + keep-power-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; + no-sdio; + no-sd; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&sdio0 { + max-frequency = <50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus_1>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-firefly-linux.dts b/rk3399-firefly-linux.dts new file mode 100644 index 0000000..48bfaf0 --- /dev/null +++ b/rk3399-firefly-linux.dts @@ -0,0 +1,1039 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-linux.dtsi" +#include + +/ { + model = "Rockchip RK3399 Firefly Board (Linux Opensource)"; + compatible = "rockchip,rk3399-firefly-linux", "rockchip,rk3399"; + + backlight: backlight { + status = "disabled"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dw_hdmi_audio: dw-hdmi-audio { + status = "disabled"; + compatible = "rockchip,dw-hdmi-audio"; + #sound-dai-cells = <0>; + }; + + edp_panel: edp-panel { + status = "disabled"; + compatible = "sharp,lcd-f402", "panel-simple"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&dw_hdmi_audio>; + }; + }; + + hdmi_codec: hdmi-codec { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "HDMI-CODEC"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-name = "vcc3v3_pcie"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + /* + * the firefly hardware using 3.0 v as APIO2_VDD + * voltage, but the pwm divider resistance is designed + * based on hardware which the APIO2_VDD is 1.8v, so we + * need to change the regulator-max-microvolt from 1.4v + * to 1.0v, so the pwm can output 0.9v voltage. + */ + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + /* for rockchip boot on */ + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vcc_lcd: vcc-lcd-regulator { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + regulator-name = "vcc_lcd"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&display_subsystem { + status = "okay"; +}; + +&edp { + status = "disabled"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>; + hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 4>; + hp-det-adc-value = <500>; + }; + + camera0: ov13850@10 { + status = "okay"; + compatible = "omnivision,ov13850-v4l2-i2c-subdev"; + reg = < 0x10 >; + device_type = "v4l2-i2c-subdev"; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "clk_cif_out"; + + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + pinctrl-0 = <&cam0_default_pins>; + pinctrl-1 = <&cam0_sleep_pins>; + + rockchip,pd-gpio = <&gpio2 12 GPIO_ACTIVE_LOW>; + rockchip,pwr-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; + rockchip,pwr-2nd-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; + rockchip,rst-gpio = <&gpio0 8 GPIO_ACTIVE_LOW>; + + rockchip,camera-module-mclk-name = "clk_cif_out"; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "cmk-cb0695-fv1"; + rockchip,camera-module-len-name = "lg9569a2"; + rockchip,camera-module-fov-h = "66.0"; + rockchip,camera-module-fov-v = "50.1"; + rockchip,camera-module-orientation = <0>; + rockchip,camera-module-iq-flip = <0>; + rockchip,camera-module-iq-mirror = <0>; + rockchip,camera-module-flip = <1>; + rockchip,camera-module-mirror = <0>; + + rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>; + rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>; + rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>; + rockchip,camera-module-flash-support = <0>; + rockchip,camera-module-mipi-dphy-index = <0>; + }; +}; + +&i2c3 { + status = "okay"; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + gsl3680: gsl3680@41 { + status = "disabled"; + compatible = "gslX680-pad"; + reg = <0x41>; + screen_max_x = <1536>; + screen_max_y = <2048>; + touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + + mpu6050: mpu@68 { + status = "disabled"; + compatible = "invensense,mpu6050"; + reg = <0x68>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <1>; + orientation-y= <1>; + orientation-z= <1>; + irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>; + mpu-debug = <1>; + }; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s1 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + lcd_en: lcd-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + pcie_3g_drv: pcie-3g-drv { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rt5640 { + rt5640_hpcon: rt5640-hpcon { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&rockchip_suspend { + rockchip,power-ctrl = + <&gpio1 18 GPIO_ACTIVE_LOW>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&route_edp { + status = "disabled"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vccadc_ref>; +}; + +&sdhci { + bus-width = <8>; + keep-power-in-suspend; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; + no-sdio; + no-sd; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&sdio0 { + max-frequency = <50000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus_1>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&cif_isp0 { + rockchip,camera-modules-attached = <&camera0>; + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-firefly.dts b/rk3399-firefly.dts new file mode 100644 index 0000000..dc45ec3 --- /dev/null +++ b/rk3399-firefly.dts @@ -0,0 +1,807 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Firefly-RK3399 Board"; + compatible = "firefly,firefly-rk3399", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; + + work_led: led-0 { + label = "work"; + default-state = "on"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + + diy_led: led-1 { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + }; + + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <430000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG2 { + regulator-name = "vcc2v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <0>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + rt5640: rt5640@1c { + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rt5640_hpcon>; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + accelerometer@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = ; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_3g_drv: pcie-3g-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rt5640 { + rt5640_hpcon: rt5640-hpcon { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_pin: work-led-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + /* WiFi & BT combo module Ampak AP6356S */ + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + + /* Power supply */ + vqmmc-supply = <&vcc1v8_s3>; /* IO line */ + vmmc-supply = <&vcc_sdio>; /* card's power */ + + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-fpga.dts b/rk3399-fpga.dts new file mode 100644 index 0000000..4ad01f6 --- /dev/null +++ b/rk3399-fpga.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3399.dtsi" + +/ { + model = "Rockchip RK3399 FPGA Board"; + compatible = "rockchip,fpga", "rockchip,rk3399"; + + chosen { + bootargs = "init=/init console=uart,mmio32,0xff1a0000"; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x0 0x00000000 0x0 0x20000000>; + }; +}; + +&uart2 { + status = "okay"; + clocks = <&xin24m>, <&xin24m>; +}; + diff --git a/rk3399-gru-bob.dts b/rk3399-gru-bob.dts new file mode 100644 index 0000000..07737b6 --- /dev/null +++ b/rk3399-gru-bob.dts @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Bob Rev 4+ board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" + +/ { + model = "Google Bob"; + compatible = "google,bob-rev13", "google,bob-rev12", + "google,bob-rev11", "google,bob-rev10", + "google,bob-rev9", "google,bob-rev8", + "google,bob-rev7", "google,bob-rev6", + "google,bob-rev5", "google,bob-rev4", + "google,bob", "google,gru", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "boe,nv101wxmn51"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + }; +}; + +&ap_i2c_tp { + trackpad: trackpad@15 { + compatible = "elan,ekth3000"; + reg = <0x15>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + wakeup-source; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 0>; +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_alert1 { + temperature = <70000>; +}; + +&spi0 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + spi-max-frequency = <800000>; + }; +}; + +&pinctrl { + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&wlan_host_wake_l { + /* Kevin has an external pull up, but Bob does not. */ + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; +}; diff --git a/rk3399-gru-chromebook.dtsi b/rk3399-gru-chromebook.dtsi new file mode 100644 index 0000000..739937f --- /dev/null +++ b/rk3399-gru-chromebook.dtsi @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Chromebook shared properties + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/ { + pp900_ap: pp900-ap { + compatible = "regulator-fixed"; + regulator-name = "pp900_ap"; + + /* EC turns on w/ pp900_ap_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + /* EC turns on w/ pp900_usb_en */ + pp900_usb: pp900-ap { + }; + + /* EC turns on w/ pp900_pcie_en */ + pp900_pcie: pp900-ap { + }; + + pp3000: pp3000 { + compatible = "regulator-fixed"; + regulator-name = "pp3000"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3000_en>; + + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_centerlogic_pwm: ppvar-centerlogic-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_centerlogic_pwm"; + + pwms = <&pwm3 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ppvar_centerlogic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + }; + + ppvar_centerlogic: ppvar-centerlogic { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_centerlogic"; + + regulator-min-microvolt = <799434>; + regulator-max-microvolt = <1049925>; + + ctrl-supply = <&ppvar_centerlogic_pwm>; + ctrl-voltage-range = <799434 1049925>; + + regulator-settling-time-up-us = <378>; + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; + }; + + /* Schematics call this PPVAR even though it's fixed */ + ppvar_logic: ppvar-logic { + compatible = "regulator-fixed"; + regulator-name = "ppvar_logic"; + + /* EC turns on w/ ppvar_logic_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800_audio: pp1800-audio { + compatible = "regulator-fixed"; + regulator-name = "pp1800_audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1800_audio_en>; + + enable-active-high; + gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + + vin-supply = <&pp1800>; + }; + + /* gpio is shared with pp3300_wifi_bt */ + pp1800_pcie: pp1800-pcie { + compatible = "regulator-fixed"; + regulator-name = "pp1800_pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_pd_l>; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Need to wait 1ms + ramp-up time before we can power on WiFi. + * This has been approximated as 8ms total. + */ + regulator-enable-ramp-delay = <8000>; + + vin-supply = <&pp1800>; + }; + + /* Always on; plain and simple */ + pp3000_ap: pp3000_emmc: pp3000 { + }; + + pp1500_ap_io: pp1500-ap-io { + compatible = "regulator-fixed"; + regulator-name = "pp1500_ap_io"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1500_en>; + + enable-active-high; + gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>; + + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + vin-supply = <&pp1800>; + }; + + pp3300_disp: pp3300-disp { + compatible = "regulator-fixed"; + regulator-name = "pp3300_disp"; + pinctrl-names = "default"; + pinctrl-0 = <&pp3300_disp_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <2000>; + vin-supply = <&pp3300>; + }; + + /* EC turns on w/ pp3300_usb_en_l */ + pp3300_usb: pp3300 { + }; + + /* gpio is shared with pp1800_pcie and pinctrl is set there */ + pp3300_wifi_bt: pp3300-wifi-bt { + compatible = "regulator-fixed"; + regulator-name = "pp3300_wifi_bt"; + + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3300>; + }; + + /* + * This is a bit of a hack. The WiFi module should be reset at least + * 1ms after its regulators have ramped up (max rampup time is ~7ms). + * With some stretching of the imagination, we can call the 1.8V + * regulator a supply. + */ + wlan_pd_n: wlan-pd-n { + compatible = "regulator-fixed"; + regulator-name = "wlan_pd_n"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_module_reset_l>; + + enable-active-high; + gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp1800_pcie>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + power-supply = <&pp3300_disp>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwm-delay-us = <10000>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + + wake_on_bt: wake-on-bt { + label = "Wake-on-Bluetooth"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; +}; + +&ppvar_bigcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_litcpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&ppvar_gpu { + min-slew-down-rate = <225>; + ovp-threshold-percent = <16>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>, <&usbc_extcon1>; +}; + +&edp { + status = "okay"; + + /* + * eDP PHY/clk don't sync reliably at anything other than 24 MHz. Only + * set this here, because rk3399-gru.dtsi ensures we can generate this + * off GPLL=600MHz, whereas some other RK3399 boards may not. + */ + assigned-clocks = <&cru PCLK_EDP>; + assigned-clock-rates = <24000000>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +ap_i2c_mic: &i2c1 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + headsetcodec: rt5514@57 { + compatible = "realtek,rt5514"; + reg = <0x57>; + realtek,dmic-init-delay-ms = <20>; + }; +}; + +ap_i2c_tp: &i2c5 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* + * Note strange pullup enable. Apparently this avoids leakage but + * still allows us to get nice 4.7K pullups for high speed i2c + * transfers. Basically we want the pullup on whenever the ap is + * alive, so the "en" pin just gets set to output high. + */ + pinctrl-0 = <&i2c5_xfer &ap_i2c_tp_pu_en>; +}; + +&cros_ec { + cros_ec_pwm: ec-pwm { + compatible = "google,cros-ec-pwm"; + #pwm-cells = <1>; + }; + + usbc_extcon1: extcon1 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <1>; + }; +}; + +&sound { + rockchip,codec = <&max98357a &headsetcodec + &codec &wacky_spi_audio &cdn_dp>; +}; + +&spi2 { + wacky_spi_audio: spi2@0 { + compatible = "realtek,rt5514"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mic_int>; + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + wakeup-source; + }; +}; + +&pci_rootport { + mvl_wifi: wifi@0,0 { + compatible = "pci1b4b,2b42"; + reg = <0x83010000 0x0 0x00000000 0x0 0x00100000 + 0x83010000 0x0 0x00100000 0x0 0x00100000>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_host_wake_l>; + wakeup-source; + }; +}; + +&tcphy1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&u2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; + extcon = <&usbc_extcon1>; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&pinctrl { + discrete-regulators { + pp1500_en: pp1500-en { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp1800_audio_en: pp1800-audio-en { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + + pp3000_en: pp3000-en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + pp3300_disp_en: pp3300-disp-en { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + wlan_module_pd_l: wlan-module-pd-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO + &pcfg_pull_down>; + }; + }; +}; + +&wifi { + wifi_perst_l: wifi-perst-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + /* Kevin has an external pull up, but Bob does not */ + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; +}; diff --git a/rk3399-gru-gru.dts b/rk3399-gru-gru.dts new file mode 100644 index 0000000..e8d771e --- /dev/null +++ b/rk3399-gru-gru.dts @@ -0,0 +1,165 @@ +/* + * Google Gru-Gru Rev 0+ board device tree source + * + * Copyright 2016 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3399-gru.dtsi" + +/ { + model = "Google Gru"; + compatible = "google,gru-rev15", "google,gru-rev14", + "google,gru-rev13", "google,gru-rev12", + "google,gru-rev11", "google,gru-rev10", + "google,gru-rev9", "google,gru-rev8", + "google,gru-rev7", "google,gru-rev6", + "google,gru-rev5", "google,gru-rev4", + "google,gru-rev3", "google,gru-rev2", + "google,gru-rev1", "google,gru-rev0", + "google,gru", "rockchip,rk3399"; + + // TODO: Model: + // - pp1200_mipi_cam + // - pp1800_mipi_cam + // - pp2800_mipi_cam + + /* pp1800 children */ + + pp1800_fp: pp1800-fp { + compatible = "regulator-fixed"; + regulator-name = "pp1800_fp"; + pinctrl-names = "default"; + pinctrl-0 = <&fp_en>; + + enable-active-high; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + + regulator-always-on; // For bringup??? + regulator-boot-on; // For bringup??? + + vin-supply = <&pp1800>; + }; + + /* pp3300 children */ + + pp3300_fp: pp3300-fp { + compatible = "regulator-fixed"; + regulator-name = "pp3300_fp"; + /* NOTE: fp_en pinctrl in pp1800_fp */ + + enable-active-high; + gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + + regulator-always-on; // For bringup??? + regulator-boot-on; // For bringup??? + + vin-supply = <&pp3300>; + }; +}; + +ap_i2c_dvs: &i2c0 { + status = "okay"; + + // TODO: bus speed + // ...with no speed, it should just use 100kHz + // TODO: rise / fall times? + + /* LP8556 */ + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + // TODO: Where do we specify AP_BL_EN??? + + bl-name = "lcd-bl"; + dev-ctrl = /bits/ 8 <0x85>; // TODO: It depends on the device. + init-brt = /bits/ 8 <0x10>; // TODO: What should it be? + + power-supply = <&pp3300_disp>; + }; +}; + +ap_i2c_cam: &i2c2 { + status = "okay"; + + // TODO: bus speed + // ...with no speed, it should just use 100kHz + // TODO: rise / fall times? + + // TODO: I belive this is for the MIPI camera. +}; + +ap_i2c_nfc: &i2c7 { + status = "okay"; + + // TODO: bus speed + // ...with no speed, it should just use 100kHz + // TODO: rise / fall times? + + // TODO: Add the proper NFC reference... +}; + +&spi4 { + status = "okay"; + + // TODO: more properly. Hacky spidev for now??? + fingerprint@0 { + compatible = "spidev"; + spi-max-frequency = <10000000>; + reg = <0>; + }; +}; + +/* PINCTRL: always below everything else */ + +&pinctrl { + discrete-regulators { + fp_en: fp-en { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/rk3399-gru-kevin-r0.dts b/rk3399-gru-kevin-r0.dts new file mode 100644 index 0000000..7a1c36e --- /dev/null +++ b/rk3399-gru-kevin-r0.dts @@ -0,0 +1,118 @@ +/* + * Google Gru-Kevin Rev 0 board device tree source + * + * Copyright 2016 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3399-gru.dtsi" + +/ { + model = "Google Kevin Rev 0"; + compatible = "google,kevin-rev0", + "google,kevin", "google,gru", "rockchip,rk3399"; +}; + +&ap_i2c_tp { + trackpad@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = ; + }; +}; + +/* GPIO overrides for -r0; in same order as parent */ + +&pp3000 { + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; +}; + +&pp1800_audio { + gpio = <&gpio0 1 GPIO_ACTIVE_HIGH>; +}; + +&pp1800_pcie { + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; +}; + +&sdmmc { + cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; +}; + +&cros_ec { + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; +}; + +/* Pinctrl overrides for -r0; in same order as parent */ + +&ec_ap_int_l { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&pp1500_en { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&pp1800_audio_en { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO + &pcfg_pull_none>; +}; + +&pp3000_en { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO + &pcfg_pull_none>; +}; + +&wlan_module_pd_l { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO + &pcfg_pull_none>; +}; + +&sdmmc_cd_gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; +}; diff --git a/rk3399-gru-kevin-r1.dts b/rk3399-gru-kevin-r1.dts new file mode 100644 index 0000000..44b04e1 --- /dev/null +++ b/rk3399-gru-kevin-r1.dts @@ -0,0 +1,85 @@ +/* + * Google Gru-Kevin Rev 1+ board device tree source + * + * Copyright 2016 Google, Inc + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3399-gru.dtsi" + +/ { + model = "Google Kevin"; + compatible = "google,kevin-rev15", "google,kevin-rev14", + "google,kevin-rev13", "google,kevin-rev12", + "google,kevin-rev11", "google,kevin-rev10", + "google,kevin-rev9", "google,kevin-rev8", + "google,kevin-rev7", "google,kevin-rev6", + "google,kevin-rev5", "google,kevin-rev4", + "google,kevin-rev3", "google,kevin-rev2", + "google,kevin-rev1", "google,kevin", + "google,gru", "rockchip,rk3399"; +}; + +&ap_i2c_tp { + trackpad@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = ; + }; +}; + +/* PINCTRL: always below everything else */ + +&pinctrl { + pen-eject { + pen_eject_l: pen-eject-l { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO + &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399-gru-kevin.dts b/rk3399-gru-kevin.dts new file mode 100644 index 0000000..2bbef9f --- /dev/null +++ b/rk3399-gru-kevin.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Kevin Rev 6+ board device tree source + * + * Copyright 2016-2017 Google, Inc + */ + +/dts-v1/; +#include "rk3399-gru-chromebook.dtsi" +#include + +/* + * Kevin-specific things + * + * Things in this section should use names from Kevin schematic since no + * equivalent exists in Gru schematic. If referring to signals that exist + * in Gru we use the Gru names, though. Confusing enough for you? + */ +/ { + model = "Google Kevin"; + compatible = "google,kevin-rev15", "google,kevin-rev14", + "google,kevin-rev13", "google,kevin-rev12", + "google,kevin-rev11", "google,kevin-rev10", + "google,kevin-rev9", "google,kevin-rev8", + "google,kevin-rev7", "google,kevin-rev6", + "google,kevin", "google,gru", "rockchip,rk3399"; + + /* Power tree */ + + p3_3v_dig: p3-3v-dig { + compatible = "regulator-fixed"; + regulator-name = "p3.3v_dig"; + pinctrl-names = "default"; + pinctrl-0 = <&cpu3_pen_pwr_en>; + + enable-active-high; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300>; + }; + + edp_panel: edp-panel { + compatible = "sharp,lq123p1jx31"; + backlight = <&backlight>; + power-supply = <&pp3300_disp>; + + panel-timing { + clock-frequency = <266666667>; + hactive = <2400>; + hfront-porch = <48>; + hback-porch = <84>; + hsync-len = <32>; + hsync-active = <0>; + vactive = <1600>; + vfront-porch = <3>; + vback-porch = <120>; + vsync-len = <10>; + vsync-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + thermistor_ppvar_bigcpu: thermistor-ppvar-bigcpu { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <25500>; + pulldown-ohm = <0>; + io-channels = <&saradc 2>; + #thermal-sensor-cells = <0>; + }; + + thermistor_ppvar_litcpu: thermistor-ppvar-litcpu { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <25500>; + pulldown-ohm = <0>; + io-channels = <&saradc 3>; + #thermal-sensor-cells = <0>; + }; +}; + +&backlight { + pwms = <&cros_ec_pwm 1>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>, <&cpu1_pen_eject>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; +}; + +&thermal_zones { + bigcpu_reg_thermal: bigcpu-reg-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermistor_ppvar_bigcpu 0>; + sustainable-power = <4000>; + + ppvar_bigcpu_trips: trips { + ppvar_bigcpu_on: ppvar-bigcpu-on { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_bigcpu_alert: ppvar-bigcpu-alert { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_bigcpu_crit: ppvar-bigcpu-crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&ppvar_bigcpu_alert>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&ppvar_bigcpu_alert>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + litcpu_reg_thermal: litcpu-reg-thermal { + polling-delay-passive = <100>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermistor_ppvar_litcpu 0>; + sustainable-power = <4000>; + + ppvar_litcpu_trips: trips { + ppvar_litcpu_on: ppvar-litcpu-on { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_litcpu_alert: ppvar-litcpu-alert { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + + ppvar_litcpu_crit: ppvar-litcpu-crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + }; +}; + +ap_i2c_tpm: &i2c0 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + tpm: tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + powered-while-suspended; + }; +}; + +ap_i2c_dig: &i2c2 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + digitizer: digitizer@9 { + /* wacom,w9013 */ + compatible = "hid-over-i2c"; + reg = <0x9>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu1_dig_irq_l &cpu1_dig_pdct_l>; + + vdd-supply = <&p3_3v_dig>; + post-power-on-delay-ms = <100>; + + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + hid-descr-addr = <0x1>; + }; +}; + +/* Adjustments to things in the gru baseboard */ + +&ap_i2c_tp { + trackpad@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_int_l>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = ; + wakeup-source; + }; +}; + +&ap_i2c_ts { + touchscreen@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&ppvar_bigcpu_pwm { + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; +}; + +&ppvar_bigcpu { + regulator-min-microvolt = <798674>; + regulator-max-microvolt = <1302172>; + ctrl-voltage-range = <798674 1302172>; +}; + +&ppvar_litcpu_pwm { + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; +}; + +&ppvar_litcpu { + regulator-min-microvolt = <799065>; + regulator-max-microvolt = <1303738>; + ctrl-voltage-range = <799065 1303738>; +}; + +&ppvar_gpu_pwm { + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; +}; + +&ppvar_gpu { + regulator-min-microvolt = <785782>; + regulator-max-microvolt = <1217729>; + ctrl-voltage-range = <785782 1217729>; +}; + +&ppvar_centerlogic_pwm { + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; +}; + +&ppvar_centerlogic { + regulator-min-microvolt = <800069>; + regulator-max-microvolt = <1049692>; + ctrl-voltage-range = <800069 1049692>; +}; + +&saradc { + status = "okay"; + vref-supply = <&pp1800_ap_io>; +}; + +&mvl_wifi { + marvell,wakeup-pin = <14>; /* GPIO_14 on Marvell */ +}; + +&pinctrl { + digitizer { + /* Has external pullup */ + cpu1_dig_irq_l: cpu1-dig-irq-l { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* Has external pullup */ + cpu1_dig_pdct_l: cpu1-dig-pdct-l { + rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + discrete-regulators { + cpu3_pen_pwr_en: cpu3-pen-pwr-en { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + cpu1_pen_eject: cpu1-pen-eject { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399-gru-scarlet-inx.dts b/rk3399-gru-scarlet-inx.dts new file mode 100644 index 0000000..2d721a9 --- /dev/null +++ b/rk3399-gru-scarlet-inx.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Scarlet Rev4+ (SKU-6/Innolux) board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; + +#include "rk3399-gru-scarlet.dtsi" + +/ { + model = "Google Scarlet"; + compatible = "google,scarlet-rev15-sku6", "google,scarlet-rev15", + "google,scarlet-rev14-sku6", "google,scarlet-rev14", + "google,scarlet-rev13-sku6", "google,scarlet-rev13", + "google,scarlet-rev12-sku6", "google,scarlet-rev12", + "google,scarlet-rev11-sku6", "google,scarlet-rev11", + "google,scarlet-rev10-sku6", "google,scarlet-rev10", + "google,scarlet-rev9-sku6", "google,scarlet-rev9", + "google,scarlet-rev8-sku6", "google,scarlet-rev8", + "google,scarlet-rev7-sku6", "google,scarlet-rev7", + "google,scarlet-rev6-sku6", "google,scarlet-rev6", + "google,scarlet-rev5-sku6", "google,scarlet-rev5", + "google,scarlet-rev4-sku6", "google,scarlet-rev4", + "google,scarlet", "google,gru", "rockchip,rk3399"; +}; + +&mipi_panel { + compatible = "innolux,p097pfg"; + avdd-supply = <&ppvarp_lcd>; + avee-supply = <&ppvarn_lcd>; +}; diff --git a/rk3399-gru-scarlet-kd.dts b/rk3399-gru-scarlet-kd.dts new file mode 100644 index 0000000..bd75922 --- /dev/null +++ b/rk3399-gru-scarlet-kd.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-Scarlet Rev3+ (SKU-7/Kingdisplay) board device tree source + * + * Copyright 2018 Google, Inc + */ + +/dts-v1/; + +#include "rk3399-gru-scarlet.dtsi" + +/ { + model = "Google Scarlet"; + compatible = "google,scarlet-rev15-sku7", "google,scarlet-rev15", + "google,scarlet-rev14-sku7", "google,scarlet-rev14", + "google,scarlet-rev13-sku7", "google,scarlet-rev13", + "google,scarlet-rev12-sku7", "google,scarlet-rev12", + "google,scarlet-rev11-sku7", "google,scarlet-rev11", + "google,scarlet-rev10-sku7", "google,scarlet-rev10", + "google,scarlet-rev9-sku7", "google,scarlet-rev9", + "google,scarlet-rev8-sku7", "google,scarlet-rev8", + "google,scarlet-rev7-sku7", "google,scarlet-rev7", + "google,scarlet-rev6-sku7", "google,scarlet-rev6", + "google,scarlet-rev5-sku7", "google,scarlet-rev5", + "google,scarlet-rev4-sku7", "google,scarlet-rev4", + "google,scarlet-rev3-sku7", "google,scarlet-rev3", + "google,scarlet", "google,gru", "rockchip,rk3399"; +}; + +&mipi_panel { + compatible = "kingdisplay,kd097d04"; + power-supply = <&pp3300_s0>; +}; diff --git a/rk3399-gru-scarlet.dtsi b/rk3399-gru-scarlet.dtsi new file mode 100644 index 0000000..e9ecffc --- /dev/null +++ b/rk3399-gru-scarlet.dtsi @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru-scarlet board device tree source + * + * Copyright 2018 Google, Inc + */ + +#include "rk3399-gru.dtsi" + +/{ + /* Power tree */ + + /* ppvar_sys children, sorted by name */ + pp1250_s3: pp1250-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp1250_s3"; + + /* EC turns on w/ pp1250_s3_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1250_cam: pp1250-dvdd { + compatible = "regulator-fixed"; + regulator-name = "pp1250_dvdd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp1250_cam_en>; + + enable-active-high; + gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; + + /* 740us delay from gpio output high to pp1250 stable, + * rounding up to 1ms for safety. + */ + startup-delay-us = <1000>; + vin-supply = <&pp1250_s3>; + }; + + pp900_s0: pp900-s0 { + compatible = "regulator-fixed"; + regulator-name = "pp900_s0"; + + /* EC turns on w/ pp900_s0_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvarn_lcd: ppvarn-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarn_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarn_lcd_en>; + + enable-active-high; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + vin-supply = <&ppvar_sys>; + }; + + ppvarp_lcd: ppvarp-lcd { + compatible = "regulator-fixed"; + regulator-name = "ppvarp_lcd"; + pinctrl-names = "default"; + pinctrl-0 = <&ppvarp_lcd_en>; + + enable-active-high; + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + vin-supply = <&ppvar_sys>; + }; + + /* pp1800 children, sorted by name */ + pp900_s3: pp900-s3 { + compatible = "regulator-fixed"; + regulator-name = "pp900_s3"; + + /* EC turns on w/ pp900_s3_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + vin-supply = <&pp1800>; + }; + + /* EC turns on pp1800_s3_en */ + pp1800_s3: pp1800 { + }; + + /* pp3300 children, sorted by name */ + pp2800_cam: pp2800-avdd { + compatible = "regulator-fixed"; + regulator-name = "pp2800_avdd"; + pinctrl-names = "default"; + pinctrl-0 = <&pp2800_cam_en>; + + enable-active-high; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + vin-supply = <&pp3300>; + }; + + /* EC turns on pp3300_s0_en */ + pp3300_s0: pp3300 { + }; + + /* EC turns on pp3300_s3_en */ + pp3300_s3: pp3300 { + }; + + /* + * See b/66922012 + * + * This is a hack to make sure the Bluetooth part of the QCA6174A + * is reset at boot by toggling BT_EN. At boot BT_EN is first set + * to low when the bt_3v3 regulator is registered (in disabled + * state). The fake regulator is configured as a supply of the + * wlan_3v3 regulator below. When wlan_3v3 is enabled early in + * the boot process it also enables its supply regulator bt_3v3, + * which changes BT_EN to high. + */ + bt_3v3: bt-3v3 { + compatible = "regulator-fixed"; + regulator-name = "bt_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&bt_en_1v8_l>; + + enable-active-high; + gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; + vin-supply = <&pp3300_s3>; + }; + + wlan_3v3: wlan-3v3 { + compatible = "regulator-fixed"; + regulator-name = "wlan_3v3"; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_pd_1v8_l>; + + /* + * The WL_EN pin is driven low when the regulator is + * registered, and transitions to high when the PCIe bus + * is powered up. + */ + enable-active-high; + gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; + + /* + * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. + * TODO (b/64444991): how long to assert PD#? + */ + regulator-enable-ramp-delay = <10000>; + /* See bt_3v3 hack above */ + vin-supply = <&bt_3v3>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm1 0 1000000 0>; + pwm-delay-us = <10000>; + }; + + dmic: dmic { + compatible = "dmic-codec"; + dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dmic_en>; + wakeup-delay-ms = <250>; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pen_eject_odl>; + + pen-insert { + label = "Pen Insert"; + /* Insert = low, eject = high */ + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + }; +}; + +/* pp900_s0 aliases */ +pp900_ddrpll_ap: &pp900_s0 { +}; +pp900_pcie: &pp900_s0 { +}; +pp900_usb: &pp900_s0 { +}; + +/* pp900_s3 aliases */ +pp900_emmcpll: &pp900_s3 { +}; + +/* EC turns on; alias for pp1800_s0 */ +pp1800_pcie: &pp1800_s0 { +}; + +/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ +&ppvar_bigcpu { + ctrl-voltage-range = <800074 1299226>; + regulator-min-microvolt = <800074>; + regulator-max-microvolt = <1299226>; +}; + +&ppvar_bigcpu_pwm { + /* On scarlet ppvar big cpu use pwm3 */ + pwms = <&pwm3 0 3337 0>; + regulator-min-microvolt = <800074>; + regulator-max-microvolt = <1299226>; +}; + +&ppvar_litcpu { + ctrl-voltage-range = <802122 1199620>; + regulator-min-microvolt = <802122>; + regulator-max-microvolt = <1199620>; +}; + +&ppvar_litcpu_pwm { + regulator-min-microvolt = <802122>; + regulator-max-microvolt = <1199620>; +}; + +&ppvar_gpu { + ctrl-voltage-range = <799600 1099600>; + regulator-min-microvolt = <799600>; + regulator-max-microvolt = <1099600>; +}; + +&ppvar_gpu_pwm { + regulator-min-microvolt = <799600>; + regulator-max-microvolt = <1099600>; +}; + +&ppvar_sd_card_io { + states = <1800000 0x0>, <3300000 0x1>; + regulator-max-microvolt = <3300000>; +}; + +&pp3000_sd_slot { + vin-supply = <&pp3300>; +}; + +ap_i2c_dig: &i2c2 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times. */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + digitizer: digitizer@9 { + compatible = "hid-over-i2c"; + reg = <0x9>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + hid-descr-addr = <0x1>; + pinctrl-names = "default"; + pinctrl-0 = <&pen_int_odl &pen_reset_l>; + }; +}; + +&ap_i2c_ts { + touchscreen: touchscreen@10 { + compatible = "elan,ekth3500"; + reg = <0x10>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_int_l &touch_reset_l>; + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; +}; + +camera: &i2c7 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times; TODO: measure */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + /* 24M mclk is shared between world and user cameras */ + pinctrl-0 = <&i2c7_xfer &test_clkout1>; +}; + +&cdn_dp { + extcon = <&usbc_extcon0>; + phys = <&tcphy0_dp>; +}; + +&cpu_alert0 { + temperature = <66000>; +}; + +&cpu_alert1 { + temperature = <71000>; +}; + +&cros_ec { + interrupt-parent = <&gpio1>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; +}; + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>, + <&cru ACLK_HDCP>; + assigned-clock-rates = + <600000000>, <1600000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <800000000>, + <100000000>, <50000000>, + <400000000>, + <200000000>, + <200000000>, + <400000000>; +}; + +&i2c_tunnel { + google,remote-bus = <0>; +}; + +&io_domains { + bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ + audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ + gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ +}; + +&max98357a { + sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; +}; + +&mipi_dsi { + status = "okay"; + clock-master; + + ports { + mipi_out: port@1 { + reg = <1>; + + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; + }; + }; + + mipi_panel: panel@0 { + /* 2 different panels are used, compatibles are in dts files */ + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&display_rst_l>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + + port@1 { + reg = <1>; + + mipi1_in_panel: endpoint@1 { + remote-endpoint = <&mipi1_out_panel>; + }; + }; + }; + }; +}; + +&mipi_dsi1 { + status = "okay"; + + ports { + mipi1_out: port@1 { + reg = <1>; + + mipi1_out_panel: endpoint { + remote-endpoint = <&mipi1_in_panel>; + }; + }; + }; +}; + +&pcie0 { + ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + + /* PERST# asserted in S3 */ + pcie-reset-suspend = <1>; + + vpcie3v3-supply = <&wlan_3v3>; + vpcie1v8-supply = <&pp1800_pcie>; +}; + +&sdmmc { + cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; +}; + +&sound { + rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; +}; + +&spi2 { + status = "okay"; + + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&h1_int_od_l>; + spi-max-frequency = <800000>; + }; +}; + +&usb_host0_ohci { + #address-cells = <1>; + #size-cells = <0>; + + qca_bt: bluetooth@1 { + compatible = "usbcf3,e300", "usb4ca,301a"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "wakeup"; + }; +}; + +/* PINCTRL OVERRIDES */ +&ec_ap_int_l { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&ap_fw_wp { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&bl_en { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&bt_host_wake_l { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&ec_ap_int_l { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&headset_int_l { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&i2s0_8ch_bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none_6ma>, + <3 RK_PD1 1 &pcfg_pull_none_6ma>, + <3 RK_PD2 1 &pcfg_pull_none_6ma>, + <3 RK_PD3 1 &pcfg_pull_none_6ma>, + <3 RK_PD7 1 &pcfg_pull_none_6ma>, + <4 RK_PA0 1 &pcfg_pull_none_6ma>; +}; + +/* there is no external pull up, so need to set this pin pull up */ +&sdmmc_cd_pin { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&sd_pwr_1800_sel { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; +}; + +&sdmode_en { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&touch_reset_l { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&touch_int_l { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; +}; + +&pinctrl { + pinctrl-0 = < + &ap_pwroff /* AP will auto-assert this when in S3 */ + &clk_32k /* This pin is always 32k on gru boards */ + &wlan_rf_kill_1v8_l + >; + + pcfg_pull_none_6ma: pcfg-pull-none-6ma { + bias-disable; + drive-strength = <6>; + }; + + camera { + pp1250_cam_en: pp1250-dvdd { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pp2800_cam_en: pp2800-avdd { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ucam_rst: ucam_rst { + rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wcam_rst: wcam_rst { + rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + digitizer { + pen_int_odl: pen-int-odl { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pen_reset_l: pen-reset-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + discrete-regulators { + display_rst_l: display-rst-l { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + ppvarp_lcd_en: ppvarp-lcd-en { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + ppvarn_lcd_en: ppvarn-lcd-en { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dmic { + dmic_en: dmic-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pen { + pen_eject_odl: pen-eject-odl { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tpm { + h1_int_od_l: h1-int-od-l { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&wifi { + bt_en_1v8_l: bt-en-1v8-l { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_pd_1v8_l: wlan-pd-1v8-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + /* Default pull-up, but just to be clear */ + wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_perst_l: wifi-perst-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_host_wake_l: wlan-host-wake-l { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; +}; diff --git a/rk3399-gru.dtsi b/rk3399-gru.dtsi new file mode 100644 index 0000000..fb0a13c --- /dev/null +++ b/rk3399-gru.dtsi @@ -0,0 +1,831 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Gru (and derivatives) board device tree source + * + * Copyright 2016-2017 Google, Inc + */ + +#include +#include "rk3399.dtsi" +#include "rk3399-op1-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; + + /* + * Power Tree + * + * In general an attempt is made to include all rails called out by + * the schematic as long as those rails interact in some way with + * the AP. AKA: + * - Rails that only connect to the EC (or devices that the EC talks to) + * are not included. + * - Rails _are_ included if the rails go to the AP even if the AP + * doesn't currently care about them / they are always on. The idea + * here is that it makes it easier to map to the schematic or extend + * later. + * + * If two rails are substantially the same from the AP's point of + * view, though, we won't create a full fixed regulator. We'll just + * put the child rail as an alias of the parent rail. Sometimes rails + * look the same to the AP because one of these is true: + * - The EC controls the enable and the EC always enables a rail as + * long as the AP is running. + * - The rails are actually connected to each other by a jumper and + * the distinction is just there to add clarity/flexibility to the + * schematic. + */ + + ppvar_sys: ppvar-sys { + compatible = "regulator-fixed"; + regulator-name = "ppvar_sys"; + regulator-always-on; + regulator-boot-on; + }; + + pp1200_lpddr: pp1200-lpddr { + compatible = "regulator-fixed"; + regulator-name = "pp1200_lpddr"; + + /* EC turns on w/ lpddr_pwr_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + vin-supply = <&ppvar_sys>; + }; + + pp1800: pp1800 { + compatible = "regulator-fixed"; + regulator-name = "pp1800"; + + /* Always on when ppvar_sys shows power good */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + vin-supply = <&ppvar_sys>; + }; + + pp3300: pp3300 { + compatible = "regulator-fixed"; + regulator-name = "pp3300"; + + /* Always on; plain and simple */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&ppvar_sys>; + }; + + pp5000: pp5000 { + compatible = "regulator-fixed"; + regulator-name = "pp5000"; + + /* EC turns on w/ pp5000_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + vin-supply = <&ppvar_sys>; + }; + + ppvar_bigcpu_pwm: ppvar-bigcpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_bigcpu_pwm"; + + pwms = <&pwm1 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800107>; + regulator-max-microvolt = <1302232>; + }; + + ppvar_bigcpu: ppvar-bigcpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_bigcpu"; + + regulator-min-microvolt = <800107>; + regulator-max-microvolt = <1302232>; + + ctrl-supply = <&ppvar_bigcpu_pwm>; + ctrl-voltage-range = <800107 1302232>; + + regulator-settling-time-up-us = <322>; + }; + + ppvar_litcpu_pwm: ppvar-litcpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_litcpu_pwm"; + + pwms = <&pwm2 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <797743>; + regulator-max-microvolt = <1307837>; + }; + + ppvar_litcpu: ppvar-litcpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_litcpu"; + + regulator-min-microvolt = <797743>; + regulator-max-microvolt = <1307837>; + + ctrl-supply = <&ppvar_litcpu_pwm>; + ctrl-voltage-range = <797743 1307837>; + + regulator-settling-time-up-us = <384>; + }; + + ppvar_gpu_pwm: ppvar-gpu-pwm { + compatible = "pwm-regulator"; + regulator-name = "ppvar_gpu_pwm"; + + pwms = <&pwm0 0 3337 0>; + pwm-supply = <&ppvar_sys>; + pwm-dutycycle-range = <100 0>; + pwm-dutycycle-unit = <100>; + + /* EC turns on w/ ap_core_en; always on for AP */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <786384>; + regulator-max-microvolt = <1217747>; + }; + + ppvar_gpu: ppvar-gpu { + compatible = "vctrl-regulator"; + regulator-name = "ppvar_gpu"; + + regulator-min-microvolt = <786384>; + regulator-max-microvolt = <1217747>; + + ctrl-supply = <&ppvar_gpu_pwm>; + ctrl-voltage-range = <786384 1217747>; + + regulator-settling-time-up-us = <390>; + }; + + /* EC turns on w/ pp900_ddrpll_en */ + pp900_ddrpll: pp900-ap { + }; + + /* EC turns on w/ pp900_pll_en */ + pp900_pll: pp900-ap { + }; + + /* EC turns on w/ pp900_pmu_en */ + pp900_pmu: pp900-ap { + }; + + /* EC turns on w/ pp1800_s0_en_l */ + pp1800_ap_io: pp1800_emmc: pp1800_nfc: pp1800_s0: pp1800 { + }; + + /* EC turns on w/ pp1800_avdd_en_l */ + pp1800_avdd: pp1800 { + }; + + /* EC turns on w/ pp1800_lid_en_l */ + pp1800_lid: pp1800_mic: pp1800 { + }; + + /* EC turns on w/ lpddr_pwr_en */ + pp1800_lpddr: pp1800 { + }; + + /* EC turns on w/ pp1800_pmu_en_l */ + pp1800_pmu: pp1800 { + }; + + /* EC turns on w/ pp1800_usb_en_l */ + pp1800_usb: pp1800 { + }; + + pp3000_sd_slot: pp3000-sd-slot { + compatible = "regulator-fixed"; + regulator-name = "pp3000_sd_slot"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_slot_pwr_en>; + + enable-active-high; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + + vin-supply = <&pp3000>; + }; + + /* + * Technically, this is a small abuse of 'regulator-gpio'; this + * regulator is a mux between pp1800 and pp3300. pp1800 and pp3300 are + * always on though, so it is sufficient to simply control the mux + * here. + */ + ppvar_sd_card_io: ppvar-sd-card-io { + compatible = "regulator-gpio"; + regulator-name = "ppvar_sd_card_io"; + pinctrl-names = "default"; + pinctrl-0 = <&sd_io_pwr_en &sd_pwr_1800_sel>; + + enable-active-high; + enable-gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3000000 0x0>; + + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + /* EC turns on w/ pp3300_trackpad_en_l */ + pp3300_trackpad: pp3300-trackpad { + }; + + /* EC turns on w/ usb_a_en */ + pp5000_usb_a_vbus: pp5000 { + }; + + ap_rtc_clk: ap-rtc-clk { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + max98357a: max98357a { + compatible = "maxim,max98357a"; + pinctrl-names = "default"; + pinctrl-0 = <&sdmode_en>; + sdmode-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sdmode-delay = <2>; + #sound-dai-cells = <0>; + status = "okay"; + }; + + sound: sound { + compatible = "rockchip,rk3399-gru-sound"; + rockchip,cpu = <&i2s0 &spdif>; + }; +}; + +&cdn_dp { + status = "okay"; +}; + +/* + * Set some suspend operating points to avoid OVP in suspend + * + * When we go into S3 ARM Trusted Firmware will transition our PWM regulators + * from wherever they're at back to the "default" operating point (whatever + * voltage we get when we set the PWM pins to "input"). + * + * This quick transition under light load has the possibility to trigger the + * regulator "over voltage protection" (OVP). + * + * To make extra certain that we don't hit this OVP at suspend time, we'll + * transition to a voltage that's much closer to the default (~1.0 V) so that + * there will not be a big jump. Technically we only need to get within 200 mV + * of the default voltage, but the speed here should be fast enough and we need + * suspend/resume to be rock solid. + */ + +&cluster0_opp { + opp05 { + opp-suspend; + }; +}; + +&cluster1_opp { + opp06 { + opp-suspend; + }; +}; + +&cpu_l0 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l1 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l2 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_l3 { + cpu-supply = <&ppvar_litcpu>; +}; + +&cpu_b0 { + cpu-supply = <&ppvar_bigcpu>; +}; + +&cpu_b1 { + cpu-supply = <&ppvar_bigcpu>; +}; + + +&cru { + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; + assigned-clock-rates = + <600000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <800000000>, + <100000000>, <50000000>, + <400000000>, <400000000>, + <200000000>, + <200000000>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&ppvar_gpu>; + status = "okay"; +}; + +ap_i2c_ts: &i2c3 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; +}; + +ap_i2c_audio: &i2c8 { + status = "okay"; + + clock-frequency = <400000>; + + /* These are relatively safe rise/fall times */ + i2c-scl-falling-time-ns = <50>; + i2c-scl-rising-time-ns = <300>; + + codec: da7219@1a { + compatible = "dlg,da7219"; + reg = <0x1a>; + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + dlg,micbias-lvl = <2600>; + dlg,mic-amp-in-sel = "diff"; + pinctrl-names = "default"; + pinctrl-0 = <&headset_int_l>; + VDD-supply = <&pp1800>; + VDDMIC-supply = <&pp3300>; + VDDIO-supply = <&pp1800>; + + da7219_aad { + dlg,adc-1bit-rpt = <1>; + dlg,btn-avg = <4>; + dlg,btn-cfg = <50>; + dlg,mic-det-thr = <500>; + dlg,jack-ins-deb = <20>; + dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-rem-deb = <1>; + + dlg,a-d-btn-thr = <0xa>; + dlg,d-b-btn-thr = <0x16>; + dlg,b-c-btn-thr = <0x21>; + dlg,c-mic-btn-thr = <0x3E>; + }; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&pp1800_audio>; /* APIO5_VDD; 3d 4a */ + bt656-supply = <&pp1800_ap_io>; /* APIO2_VDD; 2a 2b */ + gpio1830-supply = <&pp3000_ap>; /* APIO4_VDD; 4c 4d */ + sdmmc-supply = <&ppvar_sd_card_io>; /* SDMMC0_VDD; 4b */ +}; + +&pcie0 { + status = "okay"; + + ep-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>, <&wifi_perst_l>; + vpcie3v3-supply = <&pp3300_wifi_bt>; + vpcie1v8-supply = <&wlan_pd_n>; /* HACK: see &wlan_pd_n */ + vpcie0v9-supply = <&pp900_pcie>; + + pci_rootport: pcie@0,0 { + reg = <0x83000000 0x0 0x00000000 0x0 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + + pmu1830-supply = <&pp1800_pmu>; /* PMUIO2_VDD */ +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdhci { + /* + * Signal integrity isn't great at 200 MHz and 150 MHz (DDR) gives the + * same (or nearly the same) performance for all eMMC that are intended + * to be used. + */ + assigned-clock-rates = <150000000>; + + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + + /* + * Note: configure "sdmmc_cd" as card detect even though it's actually + * hooked to ground. Because we specified "cd-gpios" below dw_mmc + * should be ignoring card detect anyway. Specifying the pin as + * sdmmc_cd means that even if you've got GRF_SOC_CON7[12] (force_jtag) + * turned on that the system will still make sure the port is + * configured as SDMMC and not JTAG. + */ + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_cd_pin + &sdmmc_bus4>; + + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&pp3000_sd_slot>; + vqmmc-supply = <&ppvar_sd_card_io>; +}; + +&spdif { + status = "okay"; + + /* + * SPDIF is routed internally to DP; we either don't use these pins, or + * mux them to something else. + */ + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +&spi1 { + status = "okay"; + + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&spi1_sleep>; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* May run faster once verified. */ + spi-max-frequency = <10000000>; + }; +}; + +&spi2 { + status = "okay"; +}; + +&spi5 { + status = "okay"; + + cros_ec: ec@0 { + compatible = "google,cros-ec-spi"; + reg = <0>; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ec_ap_int_l>; + spi-max-frequency = <3000000>; + + i2c_tunnel: i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + google,remote-bus = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + usbc_extcon0: extcon0 { + compatible = "google,extcon-usbc-cros-ec"; + google,usb-port-id = <0>; + }; + }; +}; + +&tsadc { + status = "okay"; + + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ +}; + +&tcphy0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; + extcon = <&usbc_extcon0>; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +#include +#include + +&pinctrl { + /* + * pinctrl settings for pins that have no real owners. + * + * At the moment settings are identical for S0 and S3, but if we later + * need to configure things differently for S3 we'll adjust here. + */ + pinctrl-names = "default"; + pinctrl-0 = < + &ap_pwroff /* AP will auto-assert this when in S3 */ + &clk_32k /* This pin is always 32k on gru boards */ + >; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_pull_none_8ma: pcfg-pull-none-8ma { + bias-disable; + drive-strength = <8>; + }; + + backlight-enable { + bl_en: bl-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cros-ec { + ec_ap_int_l: ec-ap-int-l { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + discrete-regulators { + sd_io_pwr_en: sd-io-pwr-en { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + sd_pwr_1800_sel: sd-pwr-1800-sel { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + + sd_slot_pwr_en: sd-slot-pwr-en { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO + &pcfg_pull_none>; + }; + }; + + codec { + /* Has external pullup */ + headset_int_l: headset-int-l { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mic_int: mic-int { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + max98357a { + sdmode_en: sdmode-en { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie_clkreqn_cpm: pci-clkreqn-cpm { + /* + * Since our pcie doesn't support ClockPM(CPM), we want + * to hack this as gpio, so the EP could be able to + * de-assert it along and make ClockPM(CPM) work. + */ + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * We run sdmmc at max speed; bump up drive strength. + * We also have external pulls, so disable the internal ones. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_none_8ma>, + <4 RK_PB1 1 &pcfg_pull_none_8ma>, + <4 RK_PB2 1 &pcfg_pull_none_8ma>, + <4 RK_PB3 1 &pcfg_pull_none_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_none_8ma>; + }; + + /* + * In our case the official card detect is hooked to ground + * to avoid getting access to JTAG just by sticking something + * in the SD card slot (see the force_jtag bit in the TRM). + * + * We still configure it as card detect because it doesn't + * hurt and dw_mmc will ignore it. We make sure to disable + * the pull though so we don't burn needless power. + */ + sdmmc_cd: sdmmc-cd { + rockchip,pins = + <0 RK_PA7 1 &pcfg_pull_none>; + }; + + /* This is where we actually hook up CD; has external pull */ + sdmmc_cd_pin: sdmmc-cd-pin { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + spi1 { + spi1_sleep: spi1-sleep { + /* + * Pull down SPI1 CLK/CS/RX/TX during suspend, to + * prevent leakage. + */ + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + touchscreen { + touch_int_l: touch-int-l { + rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + touch_reset_l: touch-reset-l { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + trackpad { + ap_i2c_tp_pu_en: ap-i2c-tp-pu-en { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; + }; + + trackpad_int_l: trackpad-int-l { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi: wifi { + wlan_module_reset_l: wlan-module-reset-l { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + /* Kevin has an external pull up, but Gru does not */ + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + write-protect { + ap_fw_wp: ap-fw-wp { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399-hugsun-x99.dts b/rk3399-hugsun-x99.dts new file mode 100644 index 0000000..341d074 --- /dev/null +++ b/rk3399-hugsun-x99.dts @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Hugsun X99 TV BOX"; + compatible = "hugsun,x99", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dc_5v: dc-5v { + compatible = "regulator-fixed"; + regulator-name = "dc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led_pin>; + + power_led: led-0 { + label = "blue:power"; + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "default-on"; + }; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&dc_5v>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_5v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + pwm-supply = <&vcc_sys>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-initial-mode = <1>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <40>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + audio-supply = <&vcc1v8_s0>; + bt656-supply = <&vcc1v8_s0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sd>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + ir { + ir_rx: ir-rx { + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + leds { + power_led_pin: power-led-pin { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&saradc { + vref-supply = <&vcc1v8_s0>; + status = "okay"; +}; + +&sdmmc { + clock-frequency = <150000000>; + max-frequency = <150000000>; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + card-detect-delay = <800>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus_1>; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <110000>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_typec>; + status = "okay"; + }; + + u2phy0_otg: otg-port { + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; + + u2phy1_otg: otg-port { + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; diff --git a/rk3399-khadas-edge-captain.dts b/rk3399-khadas-edge-captain.dts new file mode 100644 index 0000000..8302e51 --- /dev/null +++ b/rk3399-khadas-edge-captain.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-Captain"; + compatible = "khadas,edge-captain", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/rk3399-khadas-edge-v.dts b/rk3399-khadas-edge-v.dts new file mode 100644 index 0000000..f5dcb99 --- /dev/null +++ b/rk3399-khadas-edge-v.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge-V"; + compatible = "khadas,edge-v", "rockchip,rk3399"; +}; + +&gmac { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + status = "okay"; +}; diff --git a/rk3399-khadas-edge.dts b/rk3399-khadas-edge.dts new file mode 100644 index 0000000..31616e7 --- /dev/null +++ b/rk3399-khadas-edge.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include "rk3399-khadas-edge.dtsi" + +/ { + model = "Khadas Edge"; + compatible = "khadas,edge", "rockchip,rk3399"; +}; diff --git a/rk3399-khadas-edge.dtsi b/rk3399-khadas-edge.dtsi new file mode 100644 index 0000000..2c644ac --- /dev/null +++ b/rk3399-khadas-edge.dtsi @@ -0,0 +1,830 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Shenzhen Wesion Technology Co., Ltd. + * (https://www.khadas.com) + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys_3v3>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vsys_5v0>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vsys_3v3>; + }; + + vsys: vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + vsys_3v3: vsys-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vsys_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vsys>; + }; + + vsys_5v0: vsys-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vsys_5v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vsys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>; + linux,rc-map-name = "rc-khadas"; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&sys_led_pin>, <&user_led_pin>; + + sys_led: led-0 { + label = "sys_led"; + linux,default-trigger = "heartbeat"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + }; + + user_led: led-1 { + label = "user_led"; + default-state = "off"; + gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <0 150 200 255>; + #cooling-cells = <2>; + fan-supply = <&vsys_5v0>; + pwms = <&pwm0 0 40000 0>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_thermal { + trips { + gpu_warm: gpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + gpu_hot: gpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&gpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map2 { + trip = <&gpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vsys_3v3>; + vcc2-supply = <&vsys_3v3>; + vcc3-supply = <&vsys_3v3>; + vcc4-supply = <&vsys_3v3>; + vcc6-supply = <&vsys_3v3>; + vcc7-supply = <&vsys_3v3>; + vcc8-supply = <&vsys_3v3>; + vcc9-supply = <&vsys_3v3>; + vcc10-supply = <&vsys_3v3>; + vcc11-supply = <&vsys_3v3>; + vcc12-supply = <&vsys_3v3>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_apio2: LDO_REG1 { + regulator-name = "vcc1v8_apio2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_vldo2: LDO_REG2 { + regulator-name = "vcc_vldo2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_vldo5: LDO_REG5 { + regulator-name = "vcc_vldo5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_codec: LDO_REG7 { + regulator-name = "vcc1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vsys_3v3>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c8 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_apio2>; + audio-supply = <&vcc1v8_codec>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + ir { + ir_rx: ir-rx { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + sys_led_pin: sys-led-pin { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led_pin: user-led-pin { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + /* WiFi & BT combo module Ampak AP6356S */ + bus-width = <4>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + vqmmc-supply = <&vcc1v8_s3>; + vmmc-supply = <&vccio_sd>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + brcm,drive-strength = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + non-removable; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + spiflash: flash@0 { + compatible = "winbond,w25q128fw", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <104000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vsys_3v3>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-leez-p710.dts b/rk3399-leez-p710.dts new file mode 100644 index 0000000..88984b5 --- /dev/null +++ b/rk3399-leez-p710.dts @@ -0,0 +1,645 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Andy Yan + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Leez RK3399 P710"; + compatible = "leez,p710", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + dc5v_adp: dc5v-adp { + compatible = "regulator-fixed"; + regulator-name = "dc5v_adapter"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc3v3_lan: vcc3v3-lan { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host0: vcc5v0_host1: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host3: vcc5v0-host3 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host3"; + enable-active-high; + gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host3_en>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc5v_adp>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-name = "vcc0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb2 { + vcc5v0_host3_en: vcc5v0-host3-en { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; + + vref-supply = <&vcc_1v8>; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + status = "okay"; + + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host0>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host1>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-linux.dtsi b/rk3399-linux.dtsi new file mode 100644 index 0000000..41ed525 --- /dev/null +++ b/rk3399-linux.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,linux", "rockchip,rk3399"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio0; + }; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops_mem: region@110000 { + reg = <0x0 0x110000 0x0 0xf0000>; + reg-names = "ramoops_mem"; + }; + }; + + ramoops: ramoops { + compatible = "ramoops"; + record-size = <0x0 0x40000>; + console-size = <0x0 0x80000>; + ftrace-size = <0x0 0x00000>; + pmsg-size = <0x0 0x00000>; + memory-region = <&ramoops_mem>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + }; + + cif_isp0: cif_isp@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + rockchip,grf = <&grf>; + reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>; + reg-names = "register", "dsihost-register"; + clocks = + <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>, + <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>, + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_MIPIDPHY_REF>; + clock-names = + "aclk_isp0_noc", "aclk_isp0_wrapper", + "hclk_isp0_noc", "hclk_isp0_wrapper", + "clk_isp0", "pclk_dphyrx", + "clk_cif_out", "clk_cif_pll", + "pclk_dphy_ref"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + power-domains = <&power RK3399_PD_ISP0>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + + cif_isp1: cif_isp@ff920000 { + compatible = "rockchip,rk3399-cif-isp"; + rockchip,grf = <&grf>; + reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>; + reg-names = "register", "dsihost-register"; + clocks = + <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>, + <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>, + <&cru SCLK_ISP1>, <&cru PCLK_ISP1_WRAPPER>, + <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>, + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_MIPIDPHY_REF>; + clock-names = + "aclk_isp1_noc", "aclk_isp1_wrapper", + "hclk_isp1_noc", "hclk_isp1_wrapper", + "clk_isp1", "pclkin_isp1", + "pclk_dphytxrx", + "pclk_mipi_dsi","mipi_dphy_cfg", + "clk_cif_out", "clk_cif_pll", + "pclk_dphy_ref"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + power-domains = <&power RK3399_PD_ISP1>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rga2"; + dev_mode = <1>; + reg = <0x0 0xff680000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3399_PD_RGA>; + status = "okay"; + }; +}; + +&display_subsystem { + status = "disabled"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_edp>; + }; + }; +}; + +&edp { + /delete-property/pinctrl-names; + /delete-property/pinctrl-0; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pvtm { + status = "okay"; +}; + +&rkvdec { + status = "okay"; + /* 0 means ion, 1 means drm */ + //allocator = <0>; +}; + +&vdec_mmu { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vpu_mmu { + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&pinctrl { + isp { + cif_clkout: cif-clkout { + rockchip,pins = + /* cif_clkout */ + <2 RK_PB3 3 &pcfg_pull_none>; + }; + + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + /* cif_clkout */ + <2 RK_PB3 3 &pcfg_pull_none>, + /* cif_data0 */ + <2 RK_PA0 3 &pcfg_pull_none>, + /* cif_data1 */ + <2 RK_PA1 3 &pcfg_pull_none>, + /* cif_data2 */ + <2 RK_PA2 3 &pcfg_pull_none>, + /* cif_data3 */ + <2 RK_PA3 3 &pcfg_pull_none>, + /* cif_data4 */ + <2 RK_PA4 3 &pcfg_pull_none>, + /* cif_data5 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* cif_data6 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* cif_data7 */ + <2 RK_PA7 3 &pcfg_pull_none>, + /* cif_sync */ + <2 RK_PB0 3 &pcfg_pull_none>, + /* cif_href */ + <2 RK_PB1 3 &pcfg_pull_none>, + /* cif_clkin */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + isp_shutter: isp-shutter { + rockchip,pins = + /* SHUTTEREN */ + <1 RK_PA1 1 &pcfg_pull_none>, + /* SHUTTERTRIG */ + <1 RK_PA0 1 &pcfg_pull_none>; + }; + + isp_flash_trigger: isp-flash-trigger { + /* ISP_FLASHTRIGOU */ + rockchip,pins = <1 RK_PA3 1 &pcfg_pull_none>; + }; + + isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio { + /* ISP_FLASHTRIGOU */ + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam_pins { + cam0_default_pins: cam0-default-pins { + rockchip,pins = + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB3 3 &pcfg_pull_none>; + }; + cam0_sleep_pins: cam0-sleep-pins { + rockchip,pins = + <4 RK_PD3 3 &pcfg_pull_none>, + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399-mid-818-android.dts b/rk3399-mid-818-android.dts new file mode 100644 index 0000000..3eda89f --- /dev/null +++ b/rk3399-mid-818-android.dts @@ -0,0 +1,1086 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include +#include +#include +#include "rk3399.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,rk3399-mid", "rockchip,rk3399"; + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; + }; + + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <6700>; + rockchip,screen-on-voltage = <6800>; + status = "okay"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio1 2 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + edp_panel: edp-panel { + compatible = "lg,lp079qx1-sp0v", "panel-simple"; + bus-format = ; + bpc = <6>; + backlight = <&backlight>; + power-supply = <&vcc3v3_s0>; + enable-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 255 200 199 198 197 197 196 195 194 193 193 192 + 191 190 189 189 188 187 186 185 185 184 183 182 + 181 181 180 179 178 177 177 176 175 174 173 173 + 172 171 170 169 169 168 167 166 165 165 164 163 + 162 161 161 160 159 158 157 157 156 155 154 153 + 153 152 151 150 149 149 148 147 146 145 145 144 + 143 142 141 141 140 139 138 137 137 136 135 134 + 133 133 132 131 130 129 129 128 127 126 125 125 + 124 123 122 121 121 120 119 118 117 117 116 115 + 114 113 113 112 111 110 109 109 108 107 106 105 + 105 104 103 102 101 101 100 99 98 97 97 96 + 95 94 93 93 92 91 90 89 89 88 87 86 + 85 85 84 83 82 81 81 80 79 78 77 77 + 76 75 74 73 73 72 71 70 69 69 68 67 + 66 65 65 64 63 62 61 61 60 59 58 57 + 57 56 55 54 53 53 52 51 50 49 49 48 + 47 46 45 45 44 43 42 41 41 40 39 38 + 37 37 36 35 34 33 33 32 31 30 29 29 + 28 27 26 25 25 24 23 22 21 21 20 19 + 18 17 17 16 15 14 13 13 12 11 10 9 + 9 8 7 6 5 5 4 3 2 1 1 0 + 0 0 0 0>; + default-brightness-level = <200>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&es8316>; + }; + }; + + spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk818 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; + + vibrator { + compatible = "rk-vibrator-gpio"; + vibrator-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 800000 + SYS_STATUS_REBOOT 528000 + SYS_STATUS_SUSPEND 200000 + SYS_STATUS_VIDEO_1080P 200000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_VIDEO_4K_10B 800000 + SYS_STATUS_PERFORMANCE 800000 + SYS_STATUS_BOOST 600000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 600000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 200000 + 763 1893 400000 + 1894 3012 528000 + 3013 99999 800000 + >; + + auto-min-freq = <200000>; +}; + +&sdmmc { + clock-frequency = <50000000>; + clock-freq-min-max = <400000 150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&sdio0 { + clock-frequency = <150000000>; + clock-freq-min-max = <200000 150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; +}; + +&spdif { + status = "disabled"; + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu_b: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + status = "okay"; + reg = <0x41>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk818: pmic@1c { + compatible = "rockchip,rk818"; + status = "okay"; + reg = <0x1c>; + clock-output-names = "rk818-clkout1", "wifibt_32kin"; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + rk818,support_dc_chg = <1>;/*1: dc chg; 0:usb chg*/ + wakeup-source; + extcon = <&fusb0>; + #clock-cells = <1>; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_cpu_l: DCDC_REG1 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_center: DCDC_REG2 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca3v0_codec: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_codec: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_power_on: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_power_on"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_3v0: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcc1v8_dvp: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s3: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s0: SWITCH_REG { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + boost_otg: DCDC_BOOST { + regulator-name = "boost_otg"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + }; + }; + + battery { + compatible = "rk818-battery"; + ocv_table = <3400 3675 3689 3716 3740 3756 3768 3780 + 3793 3807 3827 3853 3896 3937 3974 4007 4066 + 4110 4161 4217 4308>; + design_capacity = <7916>; + design_qmax = <8708>; + bat_res = <65>; + max_input_current = <3000>; + max_chrg_current = <3000>; + max_chrg_voltage = <4350>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3950>; + fb_temperature = <105>; + sample_res = <20>; + max_soc_offset = <60>; + energy_mode = <0>; + monitor_sec = <5>; + virtual_power = <0>; + power_dc2otg = <0>; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + es8316: es8316@10 { + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <400000>; + + lsm330_accel@1e { + status = "okay"; + compatible = "lsm330_acc"; + pinctrl-names = "default"; + pinctrl-0 = <&lsm330a_irq_gpio>; + reg = <0x1e>; + irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>; + type = ; + irq_enable = <1>; + poll_delay_ms = <30>; + power-off-in-suspend = <1>; + layout = <4>; + }; + + lsm330_gyro@6a { + status = "okay"; + compatible = "lsm330_gyro"; + pinctrl-names = "default"; + pinctrl-0 = <&lsm330g_irq_gpio>; + reg = <0x6a>; + irq-gpio = <&gpio1 20 IRQ_TYPE_EDGE_RISING>; + type = ; + irq_enable = <0>; + power-off-in-suspend = <1>; + poll_delay_ms = <30>; + }; + + mpu6500@68 { + status = "disabled"; + compatible = "invensense,mpu6500"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + reg = <0x68>; + irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <1 0 0 0 1 0 0 0 1>; + orientation-x= <1>; + orientation-y= <1>; + orientation-z= <0>; + support-hw-poweroff = <1>; + mpu-debug = <1>; + }; + + sensor@0d { + status = "okay"; + compatible = "ak8963"; + pinctrl-names = "default"; + pinctrl-0 = <&ak8963_irq_gpio>; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio2 28 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <3>; + }; + + sensor@10 { + status = "okay"; + compatible = "capella,light_cm3218"; + pinctrl-names = "default"; + pinctrl-0 = <&cm3218_irq_gpio>; + reg = <0x10>; + type = ; + irq-gpio = <&gpio4 24 IRQ_TYPE_EDGE_FALLING>; + irq_enable = <1>; + poll_delay_ms = <30>; + }; + + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + int-n-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&i2c5 { + status = "okay"; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + touch-gpio = <&gpio3 12 IRQ_TYPE_LEVEL_LOW>; + reset-gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>; + max-x = <1536>; + max-y = <2048>; + tp-size = <970>; + tp-supply = <&vcc3v0_tp>; + }; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&spi1 { + status = "disabled"; + max-freq = <50000000>; + mpu6500@0 { + status = "disabled"; + compatible = "inv-spi,mpu6500"; + pinctrl-names = "default"; + pinctrl-0 = <&mpu6500_irq_gpio>; + irq-gpio = <&gpio2 27 IRQ_TYPE_EDGE_RISING>; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpha; + spi-cpol; + mpu-int_config = <0x00>; + mpu-level_shifter = <0>; + mpu-orientation = <1 0 0 0 1 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <1>; + support-hw-poweroff = <1>; + mpu-debug = <1>; + }; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&saradc { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + hallsensor { + mh248_irq_gpio: mh248-irq-gpio { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lsm330_a { + lsm330a_irq_gpio: lsm330a-irq-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lsm330_g { + lsm330g_irq_gpio: lsm330g-irq-gpio { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mpu6500 { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ak8963 { + ak8963_irq_gpio: ak8963-irq-gpio { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm3218 { + cm3218_irq_gpio: cm3218-irq-gpio { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&edp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; + phys = <&tcphy0_dp>; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&route_edp { + status = "okay"; + logo,mode = "center"; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; diff --git a/rk3399-nanopc-t4.dts b/rk3399-nanopc-t4.dts new file mode 100644 index 0000000..e0d7561 --- /dev/null +++ b/rk3399-nanopc-t4.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPC-T4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPC-T4"; + compatible = "friendlyarm,nanopc-t4", "rockchip,rk3399"; + + vcc12v0_sys: vcc12v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "vcc12v0_sys"; + }; + + vcc5v0_host0: vcc5v0-host0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_host0"; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_rx>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + /* + * With 20KHz PWM and an EVERCOOL EC4007H12SA fan, these levels + * work out to 0, ~1200, ~3000, and 5000RPM respectively. + */ + cooling-levels = <0 12 18 255>; + #cooling-cells = <2>; + fan-supply = <&vcc12v0_sys>; + pwms = <&pwm1 0 50000 0>; + }; +}; + +&cpu_thermal { + trips { + cpu_warm: cpu_warm { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_hot: cpu_hot { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + trip = <&cpu_warm>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map3 { + trip = <&cpu_hot>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + +&pcie0 { + num-lanes = <4>; + vpcie3v3-supply = <&vcc3v3_sys>; +}; + +&pinctrl { + ir { + ir_rx: ir-rx { + /* external pullup to VCC3V3_SYS, despite being 1.8V :/ */ + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host0>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host0>; +}; + +&vcc5v0_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vcc3v3_sys { + vin-supply = <&vcc12v0_sys>; +}; + +&vbus_typec { + enable-active-high; + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; +}; diff --git a/rk3399-nanopi-m4.dts b/rk3399-nanopi-m4.dts new file mode 100644 index 0000000..60358ab --- /dev/null +++ b/rk3399-nanopi-m4.dts @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * FriendlyElec NanoPi M4 board device tree source + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyElec NanoPi M4"; + compatible = "friendlyarm,nanopi-m4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb2: vcc5v0-usb2 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb2"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_usb2>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/rk3399-nanopi-neo4.dts b/rk3399-nanopi-neo4.dts new file mode 100644 index 0000000..195410b --- /dev/null +++ b/rk3399-nanopi-neo4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Amarula Solutions B.V. + * Author: Jagan Teki + */ + +/dts-v1/; + +#include "rk3399-nanopi4.dtsi" + +/ { + model = "FriendlyARM NanoPi NEO4"; + compatible = "friendlyarm,nanopi-neo4", "rockchip,rk3399"; + + vdd_5v: vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_core: vcc5v0-core { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_core"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_5v>; + }; + + vcc5v0_usb1: vcc5v0-usb1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb1"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&vcc3v3_sys { + vin-supply = <&vcc5v0_core>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_usb1>; +}; + +&vbus_typec { + regulator-always-on; + vin-supply = <&vdd_5v>; +}; diff --git a/rk3399-nanopi4.dtsi b/rk3399-nanopi4.dtsi new file mode 100644 index 0000000..76a8b40 --- /dev/null +++ b/rk3399-nanopi4.dtsi @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * RK3399-based FriendlyElec boards device tree source + * + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Copyright (c) 2018 FriendlyElec Computer Tech. Co., Ltd. + * (http://www.friendlyarm.com) + * + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2019 Arm Ltd. + */ + +/dts-v1/; +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vdd_5v>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_s3"; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + /* + * Really, this is supplied by vcc_1v8, and vcc1v8_s3 only + * drives the enable pin, but we can't quite model that. + */ + vcca0v9_s3: vcca0v9-s3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca0v9_s3"; + vin-supply = <&vcc1v8_s3>; + }; + + /* As above, actually supplied by vcc3v3_sys */ + vcca1v8_s3: vcca1v8-s3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_s3"; + vin-supply = <&vcc1v8_s3>; + }; + + vbus_typec: vbus-typec { + compatible = "regulator-fixed"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vbus_typec"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&power_key>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&status_led_pin>; + + status_led: led-0 { + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + label = "status_led"; + linux,default-trigger = "heartbeat"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clock-parents = <&clkin_gmac>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; + phy-handle = <&rtl8211e>; + phy-mode = "rgmii"; + phy-supply = <&vcc3v3_s3>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c7>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu_b"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_gpu"; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + clock-output-names = "xin32k", "rtc_clko_wifi"; + #clock-cells = <1>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_center"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_cpu_l"; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_cam: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_cam"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_touch"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmupll"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <3000000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <200000>; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <160>; + i2c-scl-falling-time-ns = <30>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vbus_typec>; + }; +}; + +&i2c7 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pcie_phy { + assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>; + assigned-clock-rates = <100000000>; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <2>; + vpcie0v9-supply = <&vcca0v9_s3>; + vpcie1v8-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&pinctrl { + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + status_led_pin: status-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gmac { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rockchip-key { + power_key: power-key { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio { + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reg_on_h: bt-reg-on-h { + /* external pullup to VCC1V8_PMUPLL */ + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_reg_on_h: wifi-reg_on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc0_det_l: sdmmc0-det-l { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc0_det_l>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_host { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_rts &uart0_cts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + max-speed = <4000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h &bt_host_wake_l &bt_wake_l>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-op1-opp.dtsi b/rk3399-op1-opp.dtsi new file mode 100644 index 0000000..69cc9b0 --- /dev/null +++ b/rk3399-op1-opp.dtsi @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <900000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <975000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1100000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <900000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <975000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1050000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1150000>; + }; + opp08 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1250000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + }; + opp03 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <850000>; + }; + opp04 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + }; + opp05 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1075000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/rk3399-opp.dtsi b/rk3399-opp.dtsi new file mode 100644 index 0000000..645c2d4 --- /dev/null +++ b/rk3399-opp.dtsi @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016-2017 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include "rk3399-sched-energy.dtsi" + +/ { + cluster0_opp: opp-table0 { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + nvmem-cells = <&cpul_leakage>, <&specification_serial_number>, + <&customer_demand>; + nvmem-cell-names = "cpu_leakage", + "specification_serial_number", + "customer_demand"; + clocks = <&cru PLL_APLLL>; + rockchip,avs-scale = <20>; + rockchip,bin-scaling-sel = < + 0 30 + 1 34 + >; + + rockchip,pvtm-voltage-sel = < + 0 143500 0 + 143501 148500 1 + 148501 152000 2 + 152001 999999 3 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <1000000>; + rockchip,pvtm-ch = <0 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <41>; + rockchip,pvtm-temp-prop = <115 66>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1250000>; + opp-microvolt-L0 = <825000 825000 1250000>; + opp-microvolt-L1 = <825000 825000 1250000>; + opp-microvolt-L2 = <825000 825000 1250000>; + opp-microvolt-L3 = <825000 825000 1250000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1250000>; + opp-microvolt-L0 = <825000 825000 1250000>; + opp-microvolt-L1 = <825000 825000 1250000>; + opp-microvolt-L2 = <825000 825000 1250000>; + opp-microvolt-L3 = <825000 825000 1250000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000 850000 1250000>; + opp-microvolt-L0 = <850000 850000 1250000>; + opp-microvolt-L1 = <825000 825000 1250000>; + opp-microvolt-L2 = <825000 825000 1250000>; + opp-microvolt-L3 = <825000 825000 1250000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <925000 925000 1250000>; + opp-microvolt-L0 = <925000 925000 1250000>; + opp-microvolt-L1 = <900000 900000 1250000>; + opp-microvolt-L2 = <875000 875000 1250000>; + opp-microvolt-L3 = <850000 850000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1000000 1000000 1250000>; + opp-microvolt-L0 = <1000000 1000000 1250000>; + opp-microvolt-L1 = <975000 975000 1250000>; + opp-microvolt-L2 = <950000 950000 1250000>; + opp-microvolt-L3 = <925000 925000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1125000 1125000 1250000>; + opp-microvolt-L0 = <1125000 1125000 1250000>; + opp-microvolt-L1 = <1100000 1100000 1250000>; + opp-microvolt-L2 = <1075000 1075000 1200000>; + opp-microvolt-L3 = <1050000 1050000 1250000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + nvmem-cells = <&cpub_leakage>, <&specification_serial_number>, + <&customer_demand>; + nvmem-cell-names = "cpu_leakage", + "specification_serial_number", + "customer_demand"; + clocks = <&cru PLL_APLLB>; + rockchip,avs-scale = <8>; + rockchip,bin-scaling-sel = < + 0 8 + 1 17 + >; + + rockchip,pvtm-voltage-sel = < + 0 149000 0 + 149001 155000 1 + 155001 159000 2 + 159001 161000 3 + 161001 999999 4 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <1000000>; + rockchip,pvtm-ch = <1 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <41>; + rockchip,pvtm-temp-prop = <71 35>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1250000>; + opp-microvolt-L0 = <825000 825000 1250000>; + opp-microvolt-L1 = <825000 825000 1250000>; + opp-microvolt-L2 = <825000 825000 1250000>; + opp-microvolt-L3 = <825000 825000 1250000>; + opp-microvolt-L4 = <825000 825000 1250000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1250000>; + opp-microvolt-L0 = <825000 825000 1250000>; + opp-microvolt-L1 = <825000 825000 1250000>; + opp-microvolt-L2 = <825000 825000 1250000>; + opp-microvolt-L3 = <825000 825000 1250000>; + opp-microvolt-L4 = <825000 825000 1250000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000 825000 1250000>; + opp-microvolt-L0 = <825000 825000 1250000>; + opp-microvolt-L1 = <825000 825000 1250000>; + opp-microvolt-L2 = <825000 825000 1250000>; + opp-microvolt-L3 = <825000 825000 1250000>; + opp-microvolt-L4 = <825000 825000 1250000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <875000 875000 1250000>; + opp-microvolt-L0 = <875000 875000 1250000>; + opp-microvolt-L1 = <850000 850000 1250000>; + opp-microvolt-L2 = <850000 850000 1250000>; + opp-microvolt-L3 = <850000 850000 1250000>; + opp-microvolt-L4 = <850000 850000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000 950000 1250000>; + opp-microvolt-L0 = <950000 950000 1250000>; + opp-microvolt-L1 = <925000 925000 1250000>; + opp-microvolt-L2 = <900000 900000 1250000>; + opp-microvolt-L3 = <875000 875000 1250000>; + opp-microvolt-L4 = <875000 875000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000 1025000 1250000>; + opp-microvolt-L0 = <1025000 1025000 1250000>; + opp-microvolt-L1 = <1000000 1000000 1250000>; + opp-microvolt-L2 = <1000000 1000000 1250000>; + opp-microvolt-L3 = <975000 975000 1250000>; + opp-microvolt-L4 = <975000 975000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000 1100000 1250000>; + opp-microvolt-L0 = <1100000 1100000 1250000>; + opp-microvolt-L1 = <1075000 1075000 1250000>; + opp-microvolt-L2 = <1050000 1050000 1250000>; + opp-microvolt-L3 = <1025000 1025000 1250000>; + opp-microvolt-L4 = <1025000 1025000 1250000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000 1200000 1250000>; + opp-microvolt-L0 = <1200000 1200000 1250000>; + opp-microvolt-L1 = <1175000 1175000 1250000>; + opp-microvolt-L2 = <1150000 1150000 1250000>; + opp-microvolt-L3 = <1125000 1125000 1250000>; + opp-microvolt-L4 = <1100000 1100000 1250000>; + clock-latency-ns = <40000>; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + nvmem-cells = <&gpu_leakage>; + nvmem-cell-names = "gpu_leakage"; + + rockchip,pvtm-voltage-sel = < + 0 121000 0 + 121001 125500 1 + 125501 128500 2 + 128501 999999 3 + >; + rockchip,pvtm-freq = <200000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ch = <3 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <41>; + rockchip,pvtm-temp-prop = <46 12>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + opp-microvolt-L0 = <825000>; + opp-microvolt-L1 = <825000>; + opp-microvolt-L2 = <825000>; + opp-microvolt-L3 = <825000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000>; + opp-microvolt-L0 = <825000>; + opp-microvolt-L1 = <825000>; + opp-microvolt-L2 = <825000>; + opp-microvolt-L3 = <825000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000>; + opp-microvolt-L0 = <825000>; + opp-microvolt-L1 = <825000>; + opp-microvolt-L2 = <825000>; + opp-microvolt-L3 = <825000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <925000>; + opp-microvolt-L0 = <925000>; + opp-microvolt-L1 = <925000>; + opp-microvolt-L2 = <900000>; + opp-microvolt-L3 = <900000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1100000>; + opp-microvolt-L0 = <1100000>; + opp-microvolt-L1 = <1075000>; + opp-microvolt-L2 = <1050000>; + opp-microvolt-L3 = <1025000>; + }; + }; + + dmc_opp_table: opp-table3 { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <900000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + }; +}; + +&cpu_l0 { + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; +}; + +&cpu_l1 { + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; +}; + +&cpu_l2 { + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; +}; + +&cpu_l3 { + operating-points-v2 = <&cluster0_opp>; + sched-energy-costs = <&RK3399_CPU_COST_0 &RK3399_CLUSTER_COST_0>; +}; + +&cpu_b0 { + operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; +}; + +&cpu_b1 { + operating-points-v2 = <&cluster1_opp>; + sched-energy-costs = <&RK3399_CPU_COST_1 &RK3399_CLUSTER_COST_1>; +}; + +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; + +&gpu { + operating-points-v2 = <&gpu_opp_table>; +}; diff --git a/rk3399-orangepi.dts b/rk3399-orangepi.dts new file mode 100644 index 0000000..6163ae8 --- /dev/null +++ b/rk3399-orangepi.dts @@ -0,0 +1,828 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Orange Pi RK3399 Board"; + compatible = "rockchip,rk3399-orangepi", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = ; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <1314000>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + linux,input-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_btn>; + wakeup-source; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_s3>; + phy-mode = "rgmii"; + phy-handle = <&rtl8211e>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_intb>, <&phy_rstb>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rtl8211e: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "rtc_clko_soc", "rtc_clko_wifi"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3400000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&cpu_b_sleep>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&gpu_sleep>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + ak09911@c { + compatible = "asahi-kasei,ak09911"; + reg = <0x0c>; + vdd-supply = <&vcc3v3_s3>; + vid-supply = <&vcc3v3_s3>; + }; + + mpu6500@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int_l>; + vddio-supply = <&vcc3v3_s3>; + }; + + lsm6ds3@6a { + compatible = "st,lsm6ds3"; + reg = <0x6a>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&gyr_int_l>; + vdd-supply = <&vcc3v3_s3>; + vddio-supply = <&vcc3v3_s3>; + }; + + cm32181@10 { + compatible = "capella,cm32181"; + reg = <0x10>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&light_int_l>; + vdd-supply = <&vcc3v3_s3>; + }; + + fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&chg_cc_int_l>; + vbus-supply = <&vbus_typec>; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; +}; + +&pinctrl { + buttons { + pwr_btn: pwr-btn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gmac { + phy_intb: phy-intb { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rstb: phy-rstb { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + cpu_b_sleep: cpu-b-sleep { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + gpu_sleep: gpu-sleep { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_typec_en: vcc5v0-typec-en { + rockchip,pins = + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + bluetooth { + bt_reg_on_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + mpu6500 { + gsensor_int_l: gsensor-int-l { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lsm6ds3 { + gyr_int_l: gyr-int-l { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cm32181 { + light_int_l: light-int-l { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb302 { + chg_cc_int_l: chg-cc-int-l { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + clock-frequency = <50000000>; + disable-wp; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + clock-frequency = <150000000>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vbus_typec>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_reg_on_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-pinebook-pro.dts b/rk3399-pinebook-pro.dts new file mode 100644 index 0000000..4297c1d --- /dev/null +++ b/rk3399-pinebook-pro.dts @@ -0,0 +1,1116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2020 Tobias Schramm + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Pine64 Pinebook Pro"; + compatible = "pine64,pinebook-pro", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: edp-backlight { + compatible = "pwm-backlight"; + power-supply = <&vcc_12v>; + pwms = <&pwm0 0 740740 0>; + }; + + bat: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <9800000>; + voltage-max-design-microvolt = <4350000>; + voltage-min-design-microvolt = <3000000>; + }; + + edp_panel: edp-panel { + compatible = "boe,nv140fhmn49"; + backlight = <&backlight>; + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_en_pin>; + power-supply = <&vcc3v3_panel>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + panel_in_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; + + /* + * Use separate nodes for gpio-keys to allow for selective deactivation + * of wakeup sources via sysfs without disabling the whole key + */ + gpio-key-lid { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&lidbtn_pin>; + + lid { + debounce-interval = <20>; + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + label = "Lid"; + linux,code = ; + linux,input-type = ; + wakeup-event-action = ; + wakeup-source; + }; + }; + + gpio-key-power { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn_pin>; + + power { + debounce-interval = <20>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_led_pin &slp_led_pin>; + + green_led: led-0 { + color = ; + default-state = "on"; + function = LED_FUNCTION_POWER; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + label = "green:power"; + }; + + red_led: led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_STANDBY; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + label = "red:standby"; + panic-indicator; + retain-state-suspended; + }; + }; + + /* Power sequence for SDIO WiFi module */ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h_pin>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <500000>; + + /* WL_REG_ON on module */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + /* Audio components */ + es8316-sound { + compatible = "simple-audio-card"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det_pin>; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "MIC1", "Mic Jack", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker Amplifier INL", "HPOL", + "Speaker Amplifier INR", "HPOR", + "Speaker", "Speaker Amplifier OUTL", + "Speaker", "Speaker Amplifier OUTR"; + + simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + simple-audio-card,aux-devs = <&speaker_amp>; + simple-audio-card,pin-switches = "Speaker"; + + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + + simple-audio-card,codec { + sound-dai = <&es8316>; + }; + }; + + speaker_amp: speaker-amplifier { + compatible = "simple-audio-amplifier"; + enable-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + sound-name-prefix = "Speaker Amplifier"; + VCC-supply = <&pa_5v>; + }; + + /* Power tree */ + /* Root power source */ + vcc_sysin: vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + }; + + /* Regulators supplied by vcc_sysin */ + /* LCD backlight supply */ + vcc_12v: vcc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Main 3.3 V supply */ + vcc3v3_sys: wifi_bat: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* 5 V USB power supply */ + vcc5v0_usb: pa_5v: vcc5v0-usb-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_5v_pin>; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* RK3399 logic supply */ + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sysin>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + /* Regulators supplied by vcc3v3_sys */ + /* 0.9 V supply, always on */ + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* S3 1.8 V supply, switched by vcc1v8_s3 */ + vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcca1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* micro SD card power */ + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h_pin>; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* LCD panel power, called VCC3V3_S0 in schematic */ + vcc3v3_panel: vcc3v3-panel { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcdvcc_en_pin>; + regulator-name = "vcc3v3_panel"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <100000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* M.2 adapter power, switched by vcc1v8_s3 */ + vcc3v3_ssd: vcc3v3-ssd { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ssd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* Regulators supplied by vcc5v0_usb */ + /* USB 3 port power supply regulator */ + vcc5v0_otg: vcc5v0-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en_pin>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Regulators supplied by vcc5v0_usb */ + /* Type C port power supply regulator */ + vbus_5vout: vbus_typec: vbus-5vout { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en_pin>; + regulator-name = "vbus_5vout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* Regulators supplied by vcc_1v8 */ + /* Primary 0.9 V LDO */ + vcca0v9_s3: vcca0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc0v9_s3"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_1v8>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + mains_charger: dc-charger { + compatible = "gpio-charger"; + charger-type = "mains"; + gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + + /* Also triggered by USB charger */ + pinctrl-names = "default"; + pinctrl-0 = <&dc_det_pin>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&edp { + force-hpd; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <4>; + i2c-scl-rising-time-ns = <168>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l_pin>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sysin>; + vcc2-supply = <&vcc_sysin>; + vcc3-supply = <&vcc_sysin>; + vcc4-supply = <&vcc_sysin>; + vcc6-supply = <&vcc_sysin>; + vcc7-supply = <&vcc_sysin>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sysin>; + vcc10-supply = <&vcc_sysin>; + vcc11-supply = <&vcc_sysin>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc_sysin>; + vcc14-supply = <&vcc_sysin>; + + regulators { + /* rk3399 center logic supply */ + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: vcc_wl: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + /* not used */ + LDO_REG1 { + }; + + /* not used */ + LDO_REG2 { + }; + + vcc1v8_pmupll: LDO_REG3 { + regulator-name = "vcc1v8_pmupll"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc_1v8>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + vin-supply = <&vcc_1v8>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + i2c-scl-falling-time-ns = <4>; + i2c-scl-rising-time-ns = <168>; + status = "okay"; + + es8316: es8316@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + }; +}; + +&i2c3 { + i2c-scl-falling-time-ns = <15>; + i2c-scl-rising-time-ns = <450>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-falling-time-ns = <20>; + i2c-scl-rising-time-ns = <600>; + status = "okay"; + + fusb0: fusb30x@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int_pin>; + vbus-supply = <&vbus_typec>; + + connector { + compatible = "usb-c-connector"; + data-role = "host"; + label = "USB-C"; + op-sink-microwatt = <1000000>; + power-role = "dual"; + sink-pdos = + ; + source-pdos = + ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc_hs: endpoint { + remote-endpoint = + <&u2phy0_typec_hs>; + }; + }; + + port@1 { + reg = <1>; + + usbc_ss: endpoint { + remote-endpoint = + <&tcphy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc_dp: endpoint { + remote-endpoint = + <&tcphy0_typec_dp>; + }; + }; + }; + }; + }; + + cw2015@62 { + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 < + 0x17 0x67 0x80 0x73 0x6E 0x6C 0x6B 0x63 + 0x77 0x51 0x5C 0x58 0x50 0x4C 0x48 0x36 + 0x15 0x0C 0x0C 0x19 0x5B 0x7D 0x6F 0x69 + 0x69 0x5B 0x0C 0x29 0x20 0x40 0x52 0x59 + 0x57 0x56 0x54 0x4F 0x3B 0x1F 0x7F 0x17 + 0x06 0x1A 0x30 0x5A 0x85 0x93 0x96 0x2D + 0x48 0x77 0x9C 0xB3 0x80 0x52 0x94 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x11 0xF0 0x11 + >; + cellwise,monitor-interval-ms = <5000>; + monitored-battery = <&bat>; + power-supplies = <&mains_charger>, <&fusb0>; + }; +}; + +&i2s1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk_pin>, <&i2s1_2ch_bus>; + rockchip,capture-channels = <8>; + rockchip,playback-channels = <8>; + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + bus-scan-delay-ms = <1000>; + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie0v9-supply = <&vcca0v9_s3>; + vpcie1v8-supply = <&vcca1v8_s3>; + vpcie3v3-supply = <&vcc3v3_ssd>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn_pin: pwrbtn-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + lidbtn_pin: lidbtn-pin { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dc-charger { + dc_det_pin: dc-det-pin { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + es8316 { + hp_det_pin: hp-det-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int_pin: fusb0-int-pin { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + i2s1 { + i2s_8ch_mclk_pin: i2s-8ch-mclk-pin { + rockchip,pins = <4 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + lcd-panel { + lcdvcc_en_pin: lcdvcc-en-pin { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + panel_en_pin: panel-en-pin { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_panel_reset_pin: lcd-panel-reset-pin { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + pwr_led_pin: pwr-led-pin { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + slp_led_pin: slp-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l_pin: pmic-int-l-pin { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdcard { + sdmmc0_pwr_h_pin: sdmmc0-pwr-h-pin { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + sdio-pwrseq { + wifi_enable_h_pin: wifi-enable-h-pin { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec0_en_pin: vcc5v0-typec0-en-pin { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + pwr_5v_pin: pwr-5v-pin { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host_en_pin: vcc5v0-host-en-pin { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_wake_pin: bt-wake-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_pin: bt-host-wake-pin { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_pin: bt-reset-pin { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&spi1 { + max-freq = <10000000>; + status = "okay"; + + spiflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy0_dp { + port { + tcphy0_typec_dp: endpoint { + remote-endpoint = <&usbc_dp>; + }; + }; +}; + +&tcphy0_usb3 { + port { + tcphy0_typec_ss: endpoint { + remote-endpoint = <&usbc_ss>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; + + port { + u2phy0_typec_hs: endpoint { + remote-endpoint = <&usbc_hs>; + }; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_otg>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + max-speed = <1500000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + vbat-supply = <&wifi_bat>; + vddio-supply = <&vcc_wl>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-puma-haikou.dts b/rk3399-puma-haikou.dts new file mode 100644 index 0000000..3fc761c --- /dev/null +++ b/rk3399-puma-haikou.dts @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + */ + +/dts-v1/; +#include "rk3399-puma.dtsi" + +/ { + model = "Theobroma Systems RK3399-Q7 SoM"; + compatible = "tsd,rk3399-puma-haikou", "rockchip,rk3399"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>; + + sd_card_led: led-1 { + label = "sd_card_led"; + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + }; + + i2s0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Haikou,I2S-codec"; + simple-audio-card,mclk-fs = <512>; + + simple-audio-card,codec { + clocks = <&sgtl5000_clk>; + sound-dai = <&sgtl5000>; + }; + + simple-audio-card,cpu { + bitclock-master; + frame-master; + sound-dai = <&i2s0>; + }; + }; + + sgtl5000_clk: sgtl5000-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_baseboard: vcc3v3-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_baseboard: vcc5v0-baseboard { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_baseboard"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-always-on; + }; + + vdda_codec: vdda-codec { + compatible = "regulator-fixed"; + regulator-name = "vdda_codec"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_baseboard>; + }; + + vddd_codec: vddd-codec { + compatible = "regulator-fixed"; + regulator-name = "vddd_codec"; + regulator-boot-on; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <1600000>; + vin-supply = <&vcc5v0_baseboard>; + }; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&sgtl5000_clk>; + #sound-dai-cells = <0>; + VDDA-supply = <&vdda_codec>; + VDDIO-supply = <&vdda_codec>; + VDDD-supply = <&vddd_codec>; + status = "okay"; + }; +}; + +&i2c6 { + status = "okay"; + clock-frequency = <400000>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&haikou_pin_hog>; + + hog { + haikou_pin_hog: haikou-pin-hog { + rockchip,pins = + /* LID_BTN */ + <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + /* BATLOW# */ + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* SLP_BTN# */ + <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + /* BIOS_DISABLE# */ + <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + sd_card_led_pin: sd-card-led-pin { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <40000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v3_baseboard>; + status = "okay"; +}; + +&spi5 { + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-puma.dtsi b/rk3399-puma.dtsi new file mode 100644 index 0000000..95bc7a5 --- /dev/null +++ b/rk3399-puma.dtsi @@ -0,0 +1,539 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH + */ + +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&module_led_pin>; + + module_led: led-0 { + label = "module_led"; + gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + panic-indicator; + }; + }; + + /* + * Overwrite the opp-table for CPUB as this board uses a different + * regulator (FAN53555) that only allows 10mV steps and therefore + * can't reach the operation point target voltages from rk3399-opp.dtsi + */ + /delete-node/ opp-table1; + cluster1_opp: opp-table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <800000>; + clock-latency-ns = <40000>; + }; + opp01 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <830000>; + opp-suspend; + }; + opp03 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <880000>; + }; + opp04 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <950000>; + }; + opp05 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1030000>; + }; + opp06 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1200000>; + }; + opp08 { + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1230000>; + turbo-mode; + }; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + vcc1v2_phy: vcc1v2-phy { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_phy"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; + drive-impedance-ohm = <33>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc1v2_phy>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x10>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_ldo1: LDO_REG1 { + regulator-name = "vcc_ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_ldo5: LDO_REG5 { + regulator-name = "vcc_ldo5"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo6: LDO_REG6 { + regulator-name = "vcc_ldo6"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc0v9_hdmi: LDO_REG7 { + regulator-name = "vcc0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_efuse: LDO_REG8 { + regulator-name = "vcc_efuse"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_gpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1230000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <400000>; + + fan: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #cooling-cells = <2>; + }; + + rtc_twi: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c8 { + status = "okay"; + clock-frequency = <400000>; + + vdd_cpu_b: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + vin-supply = <&vcc5v0_sys>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1230000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2s0 { + pinctrl-0 = <&i2s0_2ch_bus>; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +/* + * As Q7 does not specify neither a global nor a RX clock for I2S these + * signals are not used. Furthermore I2S0_LRCK_RX is used as GPIO. + * Therefore we have to redefine the i2s0_2ch_bus definition to prevent + * conflicts. + */ +&i2s0_2ch_bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_1v8>; + audio-supply = <&vcc_1v8>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_1v8>; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm2 { + status = "okay"; +}; + +&pinctrl { + i2c8 { + i2c8_xfer_a: i2c8-xfer { + rockchip,pins = + <1 RK_PC4 1 &pcfg_pull_up>, + <1 RK_PC5 1 &pcfg_pull_up>; + }; + }; + + leds { + module_led_pin: module-led-pin { + rockchip,pins = + <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdhci { + /* + * Signal integrity isn't great at 200MHz but 100MHz has proven stable + * enough. + */ + max-frequency = <100000000>; + + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + vqmmc-supply = <&vcc_sd>; +}; + +&spi1 { + status = "okay"; + + norflash: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; diff --git a/rk3399-roc-pc-mezzanine.dts b/rk3399-roc-pc-mezzanine.dts new file mode 100644 index 0000000..754627d --- /dev/null +++ b/rk3399-roc-pc-mezzanine.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + * Copyright (c) 2019 Markus Reichl + */ + +/dts-v1/; +#include "rk3399-roc-pc.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Mezzanine Board"; + compatible = "firefly,roc-rk3399-pc-mezzanine", "rockchip,rk3399"; + + /* MP8009 PoE PD */ + poe_12v: poe-12v { + compatible = "regulator-fixed"; + regulator-name = "poe_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_ngff: vcc3v3-ngff { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_ngff"; + enable-active-high; + gpio = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_ngff_en>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&sys_12v>; + }; + + vcc3v3_pcie: vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie_en>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&sys_12v>; + }; +}; + +&sys_12v { + vin-supply = <&poe_12v>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie3v3-supply = <&vcc3v3_pcie>; + vpcie1v8-supply = <&vcc1v8_pmu>; + vpcie0v9-supply = <&vcca_0v9>; + status = "okay"; +}; + +&pinctrl { + ngff { + vcc3v3_ngff_en: vcc3v3-ngff-en { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + vcc3v3_pcie_en: vcc3v3-pcie-en { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_perst: pcie-perst { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_ngff>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; +}; diff --git a/rk3399-roc-pc.dts b/rk3399-roc-pc.dts new file mode 100644 index 0000000..cd41954 --- /dev/null +++ b/rk3399-roc-pc.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include "rk3399-roc-pc.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Board"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; +}; diff --git a/rk3399-roc-pc.dtsi b/rk3399-roc-pc.dtsi new file mode 100644 index 0000000..35b7ab3 --- /dev/null +++ b/rk3399-roc-pc.dtsi @@ -0,0 +1,825 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 T-Chip Intelligent Technology Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + model = "Firefly ROC-RK3399-PC Board"; + compatible = "firefly,roc-rk3399-pc", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1500000>; + poll-interval = <100>; + + recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <18000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key_l>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>, <&yellow_led_pin>; + + work_led: led-0 { + label = "green:work"; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + diy_led: led-1 { + label = "red:diy"; + gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc2"; + }; + + yellow_led: led-2 { + label = "yellow:yellow-led"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + default-state = "off"; + linux,default-trigger = "mmc1"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_vbus_typec0: vcc-vbus-typec0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_vbus_typec0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + sys_12v: sys-12v { + compatible = "regulator-fixed"; + regulator-name = "sys_12v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&dc_12v>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v0_sd_en>; + regulator-name = "vcc3v0_sd"; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&sys_12v>; + }; + + vcca_0v9: vcca-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en &hub_rst>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc_sys>; + }; + + vcc_vbus_typec1: vcc-vbus-typec1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_vbus_typec1_en>; + regulator-name = "vcc_vbus_typec1"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sys_en>; + regulator-name = "vcc_sys"; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&sys_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <450000>; + regulator-max-microvolt = <1400000>; + pwm-supply = <&vcc3v3_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vcc13-supply = <&vcc3v3_sys>; + vcc14-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_hdmi: LDO_REG2 { + regulator-name = "vcc1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb1: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; +}; + +&i2c7 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: usb-typec@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; + + mp8859: regulator@66 { + compatible = "mps,mp8859"; + reg = <0x66>; + dc_12v: mp8859_dcdc { + regulator-name = "dc_12v"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_vbus_typec0>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_key_l: pwr-key-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led_pin: work-led-pin { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + yellow_led_pin: yellow-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + vcc3v0_sd_en: vcc3v0-sd-en { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc_sys_en: vcc-sys-en { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + hub_rst: hub-rst { + rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb-typec { + vcc_vbus_typec1_en: vcc-vbus-typec1-en { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + fusb1_int: fusb1-int { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vcc_vbus_typec0>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + phy-supply = <&vcc_vbus_typec1>; + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-rock-pi-4.dtsi b/rk3399-rock-pi-4.dtsi new file mode 100644 index 0000000..2f52b91 --- /dev/null +++ b/rk3399-rock-pi-4.dtsi @@ -0,0 +1,753 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "Analog"; + dais = <&i2s0_p0>; + }; + + sound-dit { + compatible = "audio-graph-card"; + label = "SPDIF"; + dais = <&spdif_p0>; + }; + + spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + + port { + dit_p0_0: endpoint { + remote-endpoint = <&spdif_p0_0>; + }; + }; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vbus_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc12v_dcin: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_lan: vcc3v3-lan-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lan"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc3v3_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_codec: LDO_REG1 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_cam: SWITCH_REG1 { + regulator-name = "vcc_cam"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_mipi: SWITCH_REG2 { + regulator-name = "vcc_mipi"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + es8316: codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s0_p0_0>; + }; + }; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; + + i2s0_p0: port { + i2s0_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + audio-supply = <&vcca1v8_codec>; + bt656-supply = <&vcc_3v0>; + gpio1830-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcc_1v8>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0-typec-en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + status = "okay"; + + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + max-frequency = <150000000>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&sdio0 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cd &sdmmc_cmd &sdmmc_bus4>; + status = "okay"; +}; + +&spdif { + + spdif_p0: port { + spdif_p0_0: endpoint { + remote-endpoint = <&dit_p0_0>; + }; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + status = "okay"; + + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-rock-pi-4a.dts b/rk3399-rock-pi-4a.dts new file mode 100644 index 0000000..89f2af5 --- /dev/null +++ b/rk3399-rock-pi-4a.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4A"; + compatible = "radxa,rockpi4a", "radxa,rockpi4", "rockchip,rk3399"; +}; diff --git a/rk3399-rock-pi-4b.dts b/rk3399-rock-pi-4b.dts new file mode 100644 index 0000000..f0055ce --- /dev/null +++ b/rk3399-rock-pi-4b.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Akash Gajjar + * Copyright (c) 2019 Pragnesh Patel + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4B"; + compatible = "radxa,rockpi4b", "radxa,rockpi4", "rockchip,rk3399"; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; diff --git a/rk3399-rock-pi-4c.dts b/rk3399-rock-pi-4c.dts new file mode 100644 index 0000000..4c7ebb1 --- /dev/null +++ b/rk3399-rock-pi-4c.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3399-rock-pi-4.dtsi" + +/ { + model = "Radxa ROCK Pi 4C"; + compatible = "radxa,rockpi4c", "radxa,rockpi4", "rockchip,rk3399"; +}; + +&sdio0 { + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&uart0 { + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + +&vcc5v0_host { + gpio = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host_en { + rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; +}; diff --git a/rk3399-rock960-ab.dts b/rk3399-rock960-ab.dts new file mode 100644 index 0000000..ea9c3e5 --- /dev/null +++ b/rk3399-rock960-ab.dts @@ -0,0 +1,1089 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include +#include +#include "rk3399.dtsi" +#include "rk3399-linux.dtsi" +#include "rk3399-opp.dtsi" + +/ { + + model = "ROCK960 - 96boards based on Rockchip RK3399"; + compatible = "rockchip,rock960","rockchip,rk3399"; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <182>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + }; + + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-always-on; + regulator-name = "vcc3v3_pcie"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + /* for rockchip boot on */ + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + + vin-supply = <&vcc_sys>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + hdmi_codec: hdmi-codec { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "HDMI-CODEC"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + /* wifi-bt-power-toggle; */ + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + /* BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 27 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sdmmc { + clock-frequency = <100000000>; + clock-freq-min-max = <100000 100000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + card-detect-delay = <800>; + status = "okay"; +}; + +&sdio0 { + clock-frequency = <100000000>; + clock-freq-min-max = <200000 100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&emmc_phy { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&spdif { + pinctrl-0 = <&spdif_bus_1>; + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + regulator-initial-mode = <1>; /* 1:force PWM 2:auto */ + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&i2c2 { + status = "okay"; + camera0: camera-module@10 { + status = "disabled"; + compatible = "omnivision,ov13850-v4l2-i2c-subdev"; + reg = < 0x10 >; + device_type = "v4l2-i2c-subdev"; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "clk_cif_out"; + pinctrl-names = "rockchip,camera_default", + "rockchip,camera_sleep"; + pinctrl-0 = <&cam0_default_pins>; + pinctrl-1 = <&cam0_sleep_pins>; + //rockchip,pd-gpio = <&gpio4 4 GPIO_ACTIVE_LOW>; + rockchip,pwr-gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + rockchip,rst-gpio = <&gpio3 29 GPIO_ACTIVE_LOW>; + rockchip,camera-module-mclk-name = "clk_cif_out"; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "cmk-cb0695-fv1"; + rockchip,camera-module-len-name = "lg9569a2"; + rockchip,camera-module-fov-h = "66.0"; + rockchip,camera-module-fov-v = "50.1"; + rockchip,camera-module-orientation = <0>; + rockchip,camera-module-iq-flip = <0>; + rockchip,camera-module-iq-mirror = <0>; + rockchip,camera-module-flip = <1>; + rockchip,camera-module-mirror = <0>; + + rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>; + rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>; + rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>; + rockchip,camera-module-flash-support = <1>; + rockchip,camera-module-mipi-dphy-index = <0>; + }; + + camera1: camera-module@36 { + status = "disabled"; + compatible = "omnivision,ov4690-v4l2-i2c-subdev"; + reg = <0x36>; + device_type = "v4l2-i2c-subdev"; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "clk_cif_out"; + pinctrl-names = "rockchip,camera_default", + "rockchip,camera_sleep"; + pinctrl-0 = <&cam0_default_pins>; + pinctrl-1 = <&cam0_sleep_pins>; + rockchip,pd-gpio = <&gpio3 4 GPIO_ACTIVE_LOW>; + //rockchip,pwr-gpio = <&gpio3 13 0>; + rockchip,rst-gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; + rockchip,camera-module-mclk-name = "clk_cif_out"; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "LA6111PA"; + rockchip,camera-module-len-name = "YM6011P"; + rockchip,camera-module-fov-h = "116"; + rockchip,camera-module-fov-v = "61"; + rockchip,camera-module-orientation = <0>; + rockchip,camera-module-iq-flip = <0>; + rockchip,camera-module-iq-mirror = <0>; + rockchip,camera-module-flip = <0>; + rockchip,camera-module-mirror = <1>; + + rockchip,camera-module-defrect0 = <2688 1520 0 0 2688 1520>; + rockchip,camera-module-flash-support = <0>; + rockchip,camera-module-mipi-dphy-index = <0>; + }; + +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&threshold { + temperature = <85000>; +}; + +&target { + temperature = <100000>; +}; + +&soc_crit { + temperature = <105000>; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <110000>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + dmas = <&dmac_peri 0>, <&dmac_peri 1>; + dma-names = "tx", "rx"; + status = "okay"; +}; + +&uart3 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + dmas = <&dmac_peri 6>, <&dmac_peri 7>; + dma-names = "tx", "rx"; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>; + status = "okay"; +}; + +&uart4 { + status = "okay"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; + dma-names = "tx", "rx"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + extcon = <&fusb0>; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&pwm3 { + status = "okay"; + + interrupts = ; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&rgmii_pins>; + pinctrl-1 = <&rgmii_sleep_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "disabled"; +}; + +&saradc { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pinctrl { + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>, + <4 RK_PB1 1 &pcfg_pull_up_8ma>, + <4 RK_PB2 1 &pcfg_pull_up_8ma>, + <4 RK_PB3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + gmac { + rgmii_sleep_pins: rgmii-sleep-pins { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pvtm { + status = "okay"; +}; + +&pmu_pvtm { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&cif_isp0 { + rockchip,camera-modules-attached = <&camera0>; + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&cif_isp1 { + rockchip,camera-modules-attached = <&camera1>; + status = "disabled"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&vpu { + status = "okay"; + /* 0 means ion, 1 means drm */ + //allocator = <0>; +}; + +&rkvdec { + status = "okay"; + /* 0 means ion, 1 means drm */ + //allocator = <0>; +}; + +&display_subsystem { + status = "okay"; +}; diff --git a/rk3399-rock960.dts b/rk3399-rock960.dts new file mode 100644 index 0000000..1a23e8f --- /dev/null +++ b/rk3399-rock960.dts @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Linaro Ltd. + */ + +/dts-v1/; +#include "rk3399-rock960.dtsi" + +/ { + model = "96boards Rock960"; + compatible = "vamrs,rock960", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led1_pin>, <&user_led2_pin>, + <&user_led3_pin>, <&user_led4_pin>, + <&wlan_led_pin>, <&bt_led_pin>; + + user_led1: led-1 { + label = "green:user1"; + gpios = <&gpio4 RK_PC2 0>; + linux,default-trigger = "heartbeat"; + }; + + user_led2: led-2 { + label = "green:user2"; + gpios = <&gpio4 RK_PC6 0>; + linux,default-trigger = "mmc0"; + }; + + user_led3: led-3 { + label = "green:user3"; + gpios = <&gpio4 RK_PD0 0>; + linux,default-trigger = "mmc1"; + }; + + user_led4: led-4 { + label = "green:user4"; + gpios = <&gpio4 RK_PD4 0>; + panic-indicator; + linux,default-trigger = "none"; + }; + + wlan_active_led: led-5 { + label = "yellow:wlan"; + gpios = <&gpio4 RK_PD5 0>; + linux,default-trigger = "phy0tx"; + default-state = "off"; + }; + + bt_active_led: led-6 { + label = "blue:bt"; + gpios = <&gpio4 RK_PD6 0>; + linux,default-trigger = "hci0-power"; + default-state = "off"; + }; + }; + +}; + +&cpu_alert0 { + temperature = <65000>; +}; + +&cpu_thermal { + sustainable-power = <1550>; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + }; + }; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + leds { + user_led1_pin: user-led1-pin { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led2_pin: user-led2-pin { + rockchip,pins = + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led3_pin: user-led3-pin { + rockchip,pins = + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + user_led4_pin: user-led4-pin { + rockchip,pins = + <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wlan_led_pin: wlan-led-pin { + rockchip,pins = + <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_led_pin: bt-led-pin { + rockchip,pins = + <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&spi0 { + /* On Low speed expansion (LS-SPI0) */ + status = "okay"; +}; + +&spi4 { + /* On High speed expansion (HS-SPI1) */ + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + +&vcc3v3_pcie { + gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>; +}; + +&vcc5v0_host { + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; +}; diff --git a/rk3399-rock960.dtsi b/rk3399-rock960.dtsi new file mode 100644 index 0000000..5e3ac58 --- /dev/null +++ b/rk3399-rock960.dtsi @@ -0,0 +1,664 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Collabora Ltd. + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Linaro Ltd. + */ + +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc1v8_s0: vcc1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-boot-on; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_0v9: vcc-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + status = "okay"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_hdmi: LDO_REG2 { + regulator-name = "vcca1v8_hdmi"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-name = "vcc_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v0_sd: LDO_REG5 { + regulator-name = "vcc3v0_sd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca0v9_hdmi: LDO_REG7 { + regulator-name = "vcca0v9_hdmi"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + vpcie0v9-supply = <&vcc_0v9>; + vpcie1v8-supply = <&vcca_1v8>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_1v8>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>, + <4 RK_PB1 1 &pcfg_pull_up_8ma>, + <4 RK_PB2 1 &pcfg_pull_up_8ma>, + <4 RK_PB3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_18ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + }; + + sdio0 { + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up_20ma>, + <2 RK_PC5 1 &pcfg_pull_up_20ma>, + <2 RK_PC6 1 &pcfg_pull_up_20ma>, + <2 RK_PC7 1 &pcfg_pull_up_20ma>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 RK_PD0 1 &pcfg_pull_up_20ma>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 RK_PD1 1 &pcfg_pull_none_20ma>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_host_wake_l: wifi-host-wake-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + clock-frequency = <50000000>; + cap-sdio-irq; + cap-sd-highspeed; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + interrupt-parent = <&gpio0>; + interrupts = ; + interrupt-names = "host-wake"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_l>; + }; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clock-frequency = <100000000>; + max-frequency = <100000000>; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + card-detect-delay = <800>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + rockchip,hw-tshut-temp = <110000>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-rockpro64-v2.dts b/rk3399-rockpro64-v2.dts new file mode 100644 index 0000000..304e3c5 --- /dev/null +++ b/rk3399-rockpro64-v2.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2019 Katsuhiro Suzuki + */ + +/dts-v1/; +#include "rk3399-rockpro64.dtsi" + +/ { + model = "Pine64 RockPro64 v2.0"; + compatible = "pine64,rockpro64-v2.0", "pine64,rockpro64", "rockchip,rk3399"; +}; + +&i2c1 { + es8316: codec@10 { + compatible = "everest,es8316"; + reg = <0x10>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; + }; +}; diff --git a/rk3399-rockpro64.dts b/rk3399-rockpro64.dts new file mode 100644 index 0000000..4b42717 --- /dev/null +++ b/rk3399-rockpro64.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + * Copyright (c) 2019 Katsuhiro Suzuki + */ + +/dts-v1/; +#include "rk3399-rockpro64.dtsi" + +/ { + model = "Pine64 RockPro64 v2.1"; + compatible = "pine64,rockpro64-v2.1", "pine64,rockpro64", "rockchip,rk3399"; +}; + +&i2c1 { + es8316: codec@11 { + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + + port { + es8316_p0_0: endpoint { + remote-endpoint = <&i2s1_p0_0>; + }; + }; + }; +}; diff --git a/rk3399-rockpro64.dtsi b/rk3399-rockpro64.dtsi new file mode 100644 index 0000000..6e553ff --- /dev/null +++ b/rk3399-rockpro64.dtsi @@ -0,0 +1,824 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2018 Akash Gajjar + */ + +#include +#include +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + chosen { + stdout-path = "serial2:1500000n8"; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_pin>, <&diy_led_pin>; + + work_led: led-0 { + label = "work"; + default-state = "on"; + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + }; + + diy_led: led-1 { + label = "diy"; + default-state = "off"; + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + fan-supply = <&vcc12v_dcin>; + pwms = <&pwm1 0 50000 0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "audio-graph-card"; + label = "rockchip,rk3399"; + dais = <&i2s1_p0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + /* micro SD card power */ + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-name = "vcc3v0_sd"; + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr_en>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /* Actually 3 regulators (host0, 1, 2) controlled by the same gpio */ + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_typec: vcc5v0-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec_en>; + regulator-name = "vcc5v0_typec"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1700000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio3>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca_1v8>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_touch: LDO_REG2 { + regulator-name = "vcc3v0_touch"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG3 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_pin>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_pin>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + fusb0: typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-supply = <&vcc5v0_typec>; + status = "okay"; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&i2s1 { + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + status = "okay"; + + i2s1_p0: port { + i2s1_p0_0: endpoint { + dai-format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&es8316_p0_0>; + }; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcc_3v0>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_perst>; + vpcie12v-supply = <&vcc12v_dcin>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb302x { + fusb0_int: fusb0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + work_led_pin: work-led-pin { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_pin: diy-led-pin { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_perst: pcie-perst { + rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwr_en: pcie-pwr-en { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdcard { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + vcc5v0_typec_en: vcc5v0_typec_en { + rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + status = "okay"; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk808 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-sapphire-excavator-box.dts b/rk3399-sapphire-excavator-box.dts new file mode 100644 index 0000000..f669206 --- /dev/null +++ b/rk3399-sapphire-excavator-box.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3399-excavator-sapphire.dtsi" +#include "rk3399-android.dtsi" + +/ { + compatible = "rockchip,rk3399-excavator-box", "rockchip,rk3399"; + + test-power { + status = "okay"; + }; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&hdmi_dp_sound { + status = "okay"; +}; + +&pwm3 { + status = "okay"; + interrupts = ; + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; diff --git a/rk3399-sapphire-excavator-edp-avb.dts b/rk3399-sapphire-excavator-edp-avb.dts new file mode 100644 index 0000000..c951691 --- /dev/null +++ b/rk3399-sapphire-excavator-edp-avb.dts @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3399-sapphire-excavator-edp.dtsi" + +/ { + model = "Rockchip RK3399 Excavator Board edp avb (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-excavator-edp-avb", "rockchip,rk3399"; + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init initrd=0x62000001,0x00800000 coherent_pool=1m"; + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "CLK_CAMERA_27MHZ"; + #clock-cells = <0>; + }; +}; + +&i2c1 { + status = "okay"; + + /delete-node/ tc358749x@f; + + tc35874x: tc35874x@f { + status = "disabled"; + reg = <0x0f>; + compatible = "toshiba,tc358749"; + clocks = <&ext_cam_clk>; + clock-names = "refclk"; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + /* interrupt-parent = <&gpio2>; */ + /* interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; */ + pinctrl-names = "default"; + pinctrl-0 = <&tc35874x_gpios>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TC358749XBG"; + rockchip,camera-module-lens-name = "NC"; + + port { + hdmiin_out0: endpoint { + remote-endpoint = <&hdmi_to_mipi_in>; + data-lanes = <1 2 3 4>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + + hdmi_to_mipi_in: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmiin_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "disabled"; +}; + +&pinctrl { + hdmiin { + tc35874x_gpios: tc35874x_gpios { + rockchip,pins = + /* PWREN_3.3 */ + <2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, + /* PWREN_1.2 */ + <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>, + /* HDMIIN_RST */ + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + /* HDMIIN_STBY */ + <2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>, + /* MIPI_RST */ + <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>, + /* CSI_CTL */ + <2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>, + /* HDMIIN_INT */ + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkisp1_0 { + status = "okay"; +}; + +&rkisp1_1 { + status = "disabled"; +}; + diff --git a/rk3399-sapphire-excavator-edp.dts b/rk3399-sapphire-excavator-edp.dts new file mode 100644 index 0000000..35caf66 --- /dev/null +++ b/rk3399-sapphire-excavator-edp.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3399-sapphire-excavator-edp.dtsi" + +/ { + model = "Rockchip RK3399 Excavator Board edp (Android)"; + compatible = "rockchip,android", "rockchip,rk3399-excavator-edp", "rockchip,rk3399"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&dp_sound { + status = "disabled"; +}; + +&hdmi_dp_sound { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; diff --git a/rk3399-sapphire-excavator-edp.dtsi b/rk3399-sapphire-excavator-edp.dtsi new file mode 100644 index 0000000..ab2a79b --- /dev/null +++ b/rk3399-sapphire-excavator-edp.dtsi @@ -0,0 +1,477 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-excavator-sapphire.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + test-power { + status = "okay"; + }; + + hdmiin_sound: hdmiin-sound { + compatible = "rockchip,rockchip-rt5651-sound"; + rockchip,cpu = <&i2s0>; + rockchip,codec = <&rt5651 &rt5651>; + status = "okay"; + }; +}; + + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&rt5651 { + status = "okay"; +}; + + +&hdmi_dp_sound { + status = "okay"; +}; + +&hdmiin_sound { + status = "disabled"; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&i2s2 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + + sgm3784: sgm3784@30 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sgmicro,gsm3784"; + reg = <0x30>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + sgm3784_led0: led@0 { + reg = <0x0>; + led-max-microamp = <299200>; + flash-max-microamp = <1122000>; + flash-max-timeout-us = <1600000>; + }; + + sgm3784_led1: led@1 { + reg = <0x1>; + led-max-microamp = <299200>; + flash-max-microamp = <1122000>; + flash-max-timeout-us = <1600000>; + }; + }; + + tc358749x: tc358749x@f { + compatible = "toshiba,tc358749x"; + reg = <0x0f>; + power-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + power18-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + power33-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + csi-ctl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + stanby-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmiin_gpios>; + status = "disabled"; + }; + + vm149c: vm149c@c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc2145: gc2145@3c{ + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout>; + + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + pwdn-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; //ok + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_fcam>; + }; + }; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; // conflict with csi-ctl-gpios + pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + lens-focus = <&vm149c>; + flash-leds = <&sgm3784_led0 &sgm3784_led1>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + //remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + ov4689: ov4689@36 { + compatible = "ovti,ov4689"; + status = "disabled"; + reg = <0x36>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; // conflict with backlight + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "JSD3425-C1"; + rockchip,camera-module-lens-name = "JSD3425-C1"; + port { + ucam_out1: endpoint { + //remote-endpoint = <&mipi_in_ucam0>; + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c6 { + cw2015@62 { + status = "disabled"; + compatible = "cw201x"; + reg = <0x62>; + bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 + 0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24 + 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 + 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E + 0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D + 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 + 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB + 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>; + monitor_sec = <5>; + virtual_power = <0>; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&mipi_dphy_rx0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&vopb { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopl { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&rkisp1_0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + dvp_in_fcam: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2145_out>; + }; + }; +}; + +&route_edp { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&rt5651_sound { + status = "okay"; +}; + +&pinctrl { + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmiin { + hdmiin_gpios: hdmiin_gpios { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3399-sapphire-excavator-linux-for-rk1808-cascade.dts b/rk3399-sapphire-excavator-linux-for-rk1808-cascade.dts new file mode 100644 index 0000000..e1e4829 --- /dev/null +++ b/rk3399-sapphire-excavator-linux-for-rk1808-cascade.dts @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3399-excavator-sapphire.dtsi" +#include "rk3399-linux.dtsi" +#include + +/ { + model = "Rockchip RK3399 Excavator Board (Linux Opensource)"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <182>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + }; + + edp_panel: edp-panel { + compatible = "lg,lp079qx1-sp0v", "panel-simple"; + backlight = <&backlight>; + power-supply = <&vcc3v3_s0>; + enable-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "CLK_CAMERA_27MHZ"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = ; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <1314000>; + }; + }; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&isp1_mmu { + status = "okay"; +}; + +&saradc { + vref-supply = <&vccadc_ref>; +}; + +&backlight { + status = "okay"; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; +}; + +&cdn_dp { + status = "disabled"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_in_vopl { + status = "okay"; +}; + +&dsi_in_vopb { + status = "disabled"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible ="simple-panel-dsi"; + reg = <0>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + dsi,format = ; + dsi,lanes = <4>; + + display-timings { + native-mode = <&timing0_720p_30hz>; + + timing0_720p_30hz: timing0-720p-30hz { + clock-frequency = <96000000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <200>; + hfront-porch = <1000>; + vback-porch = <100>; + vfront-porch = <200>; + hsync-len = <200>; + vsync-len = <200>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1_1080p_30hz: timing0-1080p-30hz { + clock-frequency = <76000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <200>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing2_1080p_87hz: timing1-1080p-87hz { + clock-frequency = <220000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <200>; + hfront-porch = <120>; + vback-porch = <20>; + vfront-porch = <2>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&edp_in_vopb { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&edp { + force-hpd; + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&hdmi { + /* remove the hdmi_cec, reused by edp_hpd */ + pinctrl-0 = <&hdmi_i2c_xfer>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + + tc358749x: tc358749x@f { + compatible = "toshiba,tc358749"; + reg = <0xf>; + clocks = <&ext_cam_clk>; + clock-names = "refclk"; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmiin_gpios>; + status = "disabled"; + port { + hdmiin_out0: endpoint { + /* Unlinked mipi dphy rx0 */ + //remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + lens-focus = <&vm149c>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmiin { + hdmiin_gpios: hdmiin-gpios { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/rk3399-sapphire-excavator-linux.dts b/rk3399-sapphire-excavator-linux.dts new file mode 100644 index 0000000..0dbe011 --- /dev/null +++ b/rk3399-sapphire-excavator-linux.dts @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3399-excavator-sapphire.dtsi" +#include "rk3399-linux.dtsi" +#include + +/ { + model = "Rockchip RK3399 Excavator Board (Linux Opensource)"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "CLK_CAMERA_27MHZ"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = ; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <1314000>; + }; + }; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&isp1_mmu { + status = "okay"; +}; + +&saradc { + vref-supply = <&vccadc_ref>; +}; + +&display_subsystem { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + + tc358749x: tc358749x@f { + compatible = "toshiba,tc358749"; + reg = <0xf>; + clocks = <&ext_cam_clk>; + clock-names = "refclk"; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmiin_gpios>; + status = "disabled"; + port { + hdmiin_out0: endpoint { + /* Unlinked mipi dphy rx0 */ + //remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + lens-focus = <&vm149c>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&vopb { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmiin { + hdmiin_gpios: hdmiin-gpios { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399-sapphire-excavator-lp4-linux.dts b/rk3399-sapphire-excavator-lp4-linux.dts new file mode 100644 index 0000000..5beab0f --- /dev/null +++ b/rk3399-sapphire-excavator-lp4-linux.dts @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd. + +/dts-v1/; + +#include "rk3399-excavator-sapphire.dtsi" +#include "rk3399-linux.dtsi" +#include + +/ { + model = "Rockchip RK3399 Excavator Board (Linux Opensource)"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + pwms = <&pwm0 0 25000 0>; + enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd: vcc-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc_lcd"; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + startup-delay-us = <20000>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc_lcd>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "CLK_CAMERA_27MHZ"; + #clock-cells = <0>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = ; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <1314000>; + }; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 856000 + SYS_STATUS_REBOOT 856000 + SYS_STATUS_SUSPEND 328000 + SYS_STATUS_VIDEO_1080P 666000 + SYS_STATUS_VIDEO_4K 856000 + SYS_STATUS_VIDEO_4K_10B 856000 + SYS_STATUS_PERFORMANCE 856000 + SYS_STATUS_BOOST 856000 + SYS_STATUS_DUALVIEW 856000 + SYS_STATUS_ISP 856000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 416000 + 763 3012 666000 + 3013 99999 856000 + >; + + vop-pn-msch-readlatency = < + 0 0x20 + 4 0x20 + >; + + auto-min-freq = <328000>; + auto-freq-en = <0>; +}; + +&dmc_opp_table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <900000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-856000000 { + opp-hz = /bits/ 64 <856000000>; + opp-microvolt = <900000>; + }; + opp-928000000 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&isp1_mmu { + status = "okay"; +}; + +&saradc { + vref-supply = <&vccadc_ref>; +}; + +&display_subsystem { + status = "okay"; +}; + +&route_edp { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + + tc358749x: tc358749x@f { + compatible = "toshiba,tc358749"; + reg = <0xf>; + clocks = <&ext_cam_clk>; + clock-names = "refclk"; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmiin_gpios>; + status = "disabled"; + port { + hdmiin_out0: endpoint { + /* Unlinked mipi dphy rx0 */ + //remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&vopb { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hdmiin { + hdmiin_gpios: hdmiin-gpios { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399-sapphire-excavator.dts b/rk3399-sapphire-excavator.dts new file mode 100644 index 0000000..73e269a --- /dev/null +++ b/rk3399-sapphire-excavator.dts @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3399-sapphire.dtsi" + +/ { + model = "Excavator-RK3399 Board"; + compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <100000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = ; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <1314000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm0 0 25000 0>; + status = "okay"; + }; + + edp_panel: edp-panel { + compatible ="lg,lp079qx1-sp0v"; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_panel_reset>; + power-supply = <&vcc3v3_s0>; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + rt5651-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "realtek,rt5651-codec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&rt5651>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&edp { + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; + + rt5651: rt5651@1a { + compatible = "rockchip,rt5651"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&i2c4 { + i2c-scl-rising-time-ns = <600>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + + accelerometer@68 { + compatible = "invensense,mpu6500"; + reg = <0x68>; + interrupt-parent = <&gpio1>; + interrupts = ; + }; +}; + +&i2s0 { + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd-panel { + lcd_panel_reset: lcd-panel-reset { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + clock-frequency = <50000000>; + keep-power-in-suspend; + max-frequency = <50000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; diff --git a/rk3399-sapphire.dts b/rk3399-sapphire.dts new file mode 100644 index 0000000..5a58060 --- /dev/null +++ b/rk3399-sapphire.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; +#include "rk3399-sapphire.dtsi" + +/ { + model = "Sapphire-RK3399 Board"; + compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; +}; diff --git a/rk3399-sapphire.dtsi b/rk3399-sapphire.dtsi new file mode 100644 index 0000000..06040f5 --- /dev/null +++ b/rk3399-sapphire.dtsi @@ -0,0 +1,797 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include "dt-bindings/usb/pd.h" +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" + +/ { + compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + + home-key { + label = "home"; + linux,code = ; + press-threshold-microvolt = <621250>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + camera-key { + label = "camera"; + linux,code = ; + press-threshold-microvolt = <787500>; + }; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* + * The fan power supply comes from the baseboard. + * For the standalone Sapphire one option is to connect a wire + * from R90030 DNP R0805 pin2 to C90002 10uF C0805 pin1 (vcc_sys). + */ + fan0: gpio-fan { + #cooling-cells = <2>; + compatible = "gpio-fan"; + gpio-fan,speed-map = <0 0 3000 1>; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + power { + debounce-interval = <100>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + linux,input-type = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_btn>; + wakeup-source; + }; + }; + + /* switched by pmic_sleep */ + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + vcc5v0_typec0: vcc5v0-typec0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vcc5v0_typec0"; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + hysteresis = <10000>; + temperature = <55000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + cooling-device = + <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&cpu_hot>; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-name = "vdd_center"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-name = "vcc1v8_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-name = "vcc3v0_tp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-name = "vcc_sdio"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-name = "vcca3v0_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-name = "vcca1v8_codec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-name = "vcc_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-name = "vcc3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-name = "vcc3v3_s0"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + vdd_cpu_b: regulator@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: regulator@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <475>; + i2c-scl-falling-time-ns = <26>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_typec0>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + displayport = <&cdn_dp>; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&tcphy0_orientation_switch>; + }; + }; + port@1 { + reg = <1>; + dp_mode_sw: endpoint { + remote-endpoint = <&tcphy_dp_altmode_switch>; + }; + }; + }; + }; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sdio>; + gpio1830-supply = <&vcc_3v0>; +}; + +&pmu_io_domains { + pmu1830-supply = <&vcc_3v0>; + status = "okay"; +}; + +&pinctrl { + buttons { + pwr_btn: pwr-btn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fan { + motor_pwr: motor-pwr { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vsel1_pin: vsel1-pin { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + vsel2_pin: vsel2-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb2 { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = + <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&saradc { + vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + clock-frequency = <150000000>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&tcphy0 { + status = "okay"; + svid = <0xff01>; + orientation-switch; + + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + tcphy_dp_altmode_switch: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_mode_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; \ No newline at end of file diff --git a/rk3399-sched-energy.dtsi b/rk3399-sched-energy.dtsi new file mode 100644 index 0000000..df3789f --- /dev/null +++ b/rk3399-sched-energy.dtsi @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + energy-costs { + RK3399_CPU_COST_0: rk3399-core-cost0 { + busy-cost-data = < + 108 46 /* 408M */ + 159 67 /* 600M */ + 216 90 /* 816M */ + 267 120 /* 1008M */ + 318 153 /* 1200M */ + 375 198 /* 1416M */ + 401 222 /* 1512M */ + >; + idle-cost-data = < + 6 + 6 + 0 + 0 + >; + }; + + RK3399_CPU_COST_1: rk3399-core-cost1 { + busy-cost-data = < + 210 129 /* 408MHz */ + 308 184 /* 600MHz */ + 419 246 /* 816MHz */ + 518 335 /* 1008MHz */ + 617 428 /* 1200MHz */ + 728 573 /* 1416MHz */ + 827 724 /* 1608MHz */ + 925 900 /* 1800MHz */ + 1024 1108 /* 1992MHz */ + >; + idle-cost-data = < + 15 + 15 + 0 + 0 + >; + }; + + RK3399_CLUSTER_COST_0: rk3399-cluster-cost0 { + busy-cost-data = < + 108 46 /* 408M */ + 159 67 /* 600M */ + 216 90 /* 816M */ + 267 120 /* 1008M */ + 318 153 /* 1200M */ + 375 198 /* 1416M */ + 401 222 /* 1512M */ + >; + idle-cost-data = < + 56 + 56 + 56 + 56 + >; + }; + + RK3399_CLUSTER_COST_1: rk3399-cluster-cost1 { + busy-cost-data = < + 210 129 /* 408MHz */ + 308 184 /* 600MHz */ + 419 246 /* 816MHz */ + 518 335 /* 1008MHz */ + 617 428 /* 1200MHz */ + 728 573 /* 1416MHz */ + 827 724 /* 1608MHz */ + 925 900 /* 1800MHz */ + 1024 1108 /* 1992MHz */ + >; + idle-cost-data = < + 65 + 65 + 65 + 65 + >; + }; + }; +}; diff --git a/rk3399-tve1030g-avb.dts b/rk3399-tve1030g-avb.dts new file mode 100644 index 0000000..eeca9cf --- /dev/null +++ b/rk3399-tve1030g-avb.dts @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include "rk3399-tve1030g.dtsi" + +/ { + compatible = "rockchip,rk3399-tve1030g-avb", "rockchip,rk3399"; +}; + +&i2c1 { + status = "okay"; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + lens-focus = <&vm149c>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + //remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + gc2355: gc2355@3c { + status = "okay"; + compatible = "galaxycore,gc2355"; + reg = <0x3c>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <>; */ + /* dvdd-supply = <>; */ + /* dovdd-supply = <>; */ + /* reset-gpios = <>; */ + pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-CW2392"; + rockchip,camera-module-lens-name = "M206A-201"; + port { + ucam_out1: endpoint { + //remote-endpoint = <&mipi_in_ucam0>; + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&rkisp1_0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + diff --git a/rk3399-tve1030g.dts b/rk3399-tve1030g.dts new file mode 100644 index 0000000..28f81ee --- /dev/null +++ b/rk3399-tve1030g.dts @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include "rk3399-tve1030g.dtsi" + +/ { + compatible = "rockchip,rk3399-tve1030g", "rockchip,rk3399"; + +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&isp0 { + status = "okay"; +}; + +&isp1 { + status = "okay"; +}; diff --git a/rk3399-tve1030g.dtsi b/rk3399-tve1030g.dtsi new file mode 100644 index 0000000..fb70043 --- /dev/null +++ b/rk3399-tve1030g.dtsi @@ -0,0 +1,1039 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; +#include +#include +#include "rk3399.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" +#include + +/ { + adc_keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <170000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + es8316-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,es8316-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + system-clock-frequency = <11289600>; + }; + simple-audio-card,codec { + sound-dai = <&es8316>; + system-clock-frequency = <11289600>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <6700>; + rockchip,screen-on-voltage = <6800>; + status = "okay"; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + enable-active-high; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <20>; + downdifferential = <10>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 856000 + SYS_STATUS_REBOOT 856000 + SYS_STATUS_SUSPEND 416000 + SYS_STATUS_VIDEO_1080P 416000 + SYS_STATUS_VIDEO_4K 666000 + SYS_STATUS_VIDEO_4K_10B 856000 + SYS_STATUS_PERFORMANCE 856000 + SYS_STATUS_BOOST 856000 + SYS_STATUS_DUALVIEW 856000 + SYS_STATUS_ISP 856000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 328000 + 763 3012 666000 + 3013 99999 856000 + >; + + auto-min-freq = <328000>; + auto-freq-en = <1>; +}; + +&dmc_opp_table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <900000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-856000000 { + opp-hz = /bits/ 64 <856000000>; + opp-microvolt = <900000>; + }; + opp-928000000 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; +}; +&dp_in_vopb { + status = "disabled"; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 15 05 02 8F A5 + 15 14 02 01 00 + 15 05 02 8F A5 + 15 00 02 83 AA + 15 00 02 84 11 + 15 00 02 A9 4B + 15 00 02 83 00 + 15 00 02 84 00 + 15 00 02 8F 00 + ]; + + disp_timings: display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <150000000>; + hactive = <1200>; + hfront-porch = <80>; + hback-porch = <60>; + hsync-len = <1>; + vactive = <1920>; + vfront-porch = <35>; + vback-porch = <25>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_dp_sound { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu_b: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + status = "okay"; + reg = <0x41>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + vcc3v3_s0: SWITCH_REG2 { + regulator-boot-on; + regulator-always-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + es8316: es8316@11 { + #sound-dai-cells = <0>; + compatible = "everest,es8316"; + reg = <0x11>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + spk-con-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + extcon = <&rk_headset>; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <100000>; + + bq25700: bq25700@6b { + compatible = "ti,bq25703"; + reg = <0x6b>; + extcon = <&fusb0>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok>; + ti,charge-current = <1500000>; + ti,max-charge-voltage = <8704000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,input-current-dc = <2000000>; + ti,minimum-sys-voltage = <6700000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + ti,input-current = <500000>; + pd-charge-only = <0>; + typec0-enable-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + cw2015: cw2015@62 { + status = "okay"; + compatible = "cw201x"; + reg = <0x62>; + bat_config_info = <0x15 0xA8 0x5D 0x5D 0x59 0x55 0x57 0x50 + 0x4B 0x4F 0x55 0x53 0x43 0x37 0x2F 0x28 + 0x21 0x18 0x15 0x17 0x27 0x43 0x57 0x4F + 0x13 0x5E 0x0A 0xE1 0x19 0x31 0x3C 0x46 + 0x4C 0x52 0x50 0x54 0x44 0x1E 0x7E 0x4C + 0x1C 0x4A 0x52 0x87 0x8F 0x91 0x94 0x52 + 0x82 0x8C 0x92 0x96 0x00 0xAD 0xFB 0xCB + 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x1C 0x09>; + monitor_sec = <2>; + virtual_power = <0>; + divider_res1 = <200>; + divider_res2 = <200>; + }; + + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + discharge-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + charge-dev = <&bq25700>; + support-uboot-charge = <1>; + port-num = <0>; + status = "okay"; + }; + + kxtj: kxtj2@0e { + status = "okay"; + compatible = "gs_kxtj9"; + pinctrl-names = "default"; + pinctrl-0 = <&kxtj2_irq_gpio>; + reg = <0x0e>; + irq-gpio = <&gpio1 RK_PC6 IRQ_TYPE_EDGE_RISING>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + power-off-in-suspend = <1>; + layout = <5>; + }; +}; + +&i2c5 { + status = "okay"; + i2c-scl-rising-time-ns = <150>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <100000>; + + gslx680: gslx680@40 { + compatible = "gslX680_tve"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_irq_gpio>; + touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_EDGE_RISING>; + reset-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + max-x = <1200>; + max-y = <1920>; + tp-size = <80>; + tp-supply = <&vcc3v0_tp>; + status = "okay"; + }; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc1v8_dvp>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&pinctrl { + + charger { + charger_ok: charge-ok { + rockchip,pins = + <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + kxtj2 { + kxtj2_irq_gpio: kxtj2-irq-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd_rst { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&route_dsi { + status = "okay"; + logo,mode = "center"; +}; + +&saradc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdio0 { + clock-frequency = <100000000>; + clock-freq-min-max = <200000 100000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + clock-frequency = <50000000>; + clock-freq-min-max = <400000 150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; diff --git a/rk3399-tve1205g.dts b/rk3399-tve1205g.dts new file mode 100644 index 0000000..4927686 --- /dev/null +++ b/rk3399-tve1205g.dts @@ -0,0 +1,1143 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include +#include "rk3399.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-opp.dtsi" +#include +#include + +/ { + compatible = "rockchip,rk3399-mid", "rockchip,rk3399"; + + edp_panel: edp-panel { + compatible = "auo,b125han03"; + backlight = <&backlight>; + power-supply = <&vcc3v3_s0>; + enable-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + bus-format = ; + bpc = <6>; + prepare-delay-ms = <50>; + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + usb_cam_gpio: usb-cam-gpio { + compatible = "usb-cam-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&usb_cam_on_gpio>; + hd-cam-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + ir-cam-gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3900000>; + regulator-max-microvolt = <3900000>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + rockchip,pwm_id= <2>; + rockchip,pwm_voltage = <900000>; + regulator-name = "vdd_log"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 51 52 52 53 53 54 + 54 55 55 56 56 57 57 58 + 58 59 59 60 61 61 62 63 + 63 64 65 65 66 67 67 68 + 69 69 70 71 71 72 73 73 + 74 75 75 76 77 77 78 79 + 79 80 80 81 81 82 83 83 + 84 85 86 86 87 88 89 89 + 90 91 92 92 93 94 95 95 + 96 97 98 98 99 100 101 101 + 102 103 104 104 105 106 107 107 + 108 109 110 110 111 112 113 113 + 114 115 116 116 117 118 119 119 + 120 121 122 122 123 124 125 125 + 126 127 128 128 129 130 131 131 + 132 133 134 134 135 136 137 137 + 138 139 140 140 141 142 143 143 + 144 145 146 146 147 148 149 149 + 150 151 152 152 153 154 155 155 + 156 157 158 158 159 160 161 161 + 162 163 164 164 165 166 167 167 + 168 169 170 170 171 172 173 173 + 174 175 176 176 177 178 179 179 + 180 181 182 182 183 184 185 185 + 186 187 188 188 189 190 191 191 + 216 217 218 218 219 220 221 221 + 222 223 224 224 225 226 227 227 + 228 229 230 230 231 232 233 233 + 234 235 236 236 237 238 239 239 + 240 241 242 242 243 244 245 245 + 246 247 248 248 249 250 251 251 + 252 253 254 254 255 255 255 255>; + default-brightness-level = <200>; + enable-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + cx2072x-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,cx2072x-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Line", "Microphone Headset", + "Headphone", "Headphone Jack", + "Speaker", "Speaker External"; + simple-audio-card,routing = + "PORTC", "Microphone Jack", + "PortD Mic Bias", "Microphone Headset", + "Headphone Jack", "PORTA", + "Speaker External", "PORTG"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&cx2072x>; + }; + }; + + sound { + compatible = "rockchip,cdndp-sound"; + rockchip,cpu = <&i2s2>; + rockchip,codec = <&cdn_dp>; + status = "okay"; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + label = "battery_led_amber"; + retain-state-suspended; + }; + + led@2 { + gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + label = "battery_led_white"; + retain-state-suspended; + }; + + led@3 { + gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + label = "call_answer_led"; + }; + + led@4 { + gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + label = "call_decline_led"; + }; + + led@5 { + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + label = "rec_mute_led"; + }; + + led@6 { + gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + label = "play_mute_led"; + }; + + led@7 { + gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + label = "wl_led"; + }; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; + + uboot-charge { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-exit-charge-level = <2>; + rockchip,uboot-low-power-level = <1>; + rockchip,uboot-charge-brightness = <0>; + max-input-voltage = <20000>; + max-input-current = <6000>; + }; + + vibrator { + compatible = "rk-vibrator-gpio"; + vibrator-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio0 RK_PA1 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; +}; + +&rk_key { + compatible = "rockchip,key"; + status = "okay"; + + io-channels = <&saradc 1>; + + vol-up-key { + linux,code = <114>; + label = "volume up"; + rockchip,adc_value = <1>; + }; + + vol-down-key { + linux,code = <115>; + label = "volume down"; + rockchip,adc_value = <170>; + }; + + power-key { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = <116>; + label = "power"; + gpio-key,wakeup; + }; + + menu-key { + linux,code = <59>; + label = "menu"; + rockchip,adc_value = <746>; + }; + + home-key { + linux,code = <102>; + label = "home"; + rockchip,adc_value = <355>; + }; + + back-key { + linux,code = <158>; + label = "back"; + rockchip,adc_value = <560>; + }; + + camera-key { + linux,code = <212>; + label = "camera"; + rockchip,adc_value = <450>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&edp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + edp_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "disabled"; +}; + +&cdn_dp { + status = "okay"; + extcon = <&fusb0>, <&fusb1>; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&i2s0 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + rockchip,bclk-fs = <32>; + #sound-dai-cells = <0>; +}; + +&i2s1 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&i2s2 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + vdd_cpu_b: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + status = "okay"; + reg = <0x41>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + cx2072x:cx2072x@33 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "cnxt,cx20723"; + reg = <0x33>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c3 { + status="okay"; + + hidkey@68 { + clock-frequency = <100000>; + compatible = "hid-over-i2c"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hidkey_irq_gpio>; + reg = <0x68>; + hid-descr-addr = <0x0001>; + hid-support-wakeup; + }; + + ec_battery@76 { + compatible = "rockchip,ec-battery"; + reg = <0x76>; + virtual_power = <0>; + monitor_sec = <5>; + ec-notify-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <400000>; + + touchpad: touchpad@2c { + compatible = "hid-over-i2c"; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touchpad_irq_gpio>; + reg = <0x2c>; + hid-descr-addr = <0x002c>; + }; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <100000>; + bq25700: bq25700@09 {//6a + compatible = "ti,bq25700"; + reg = <0x09>; + extcon = <&fusb0>, <&fusb1>; + + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok>; + ti,charge-current = <2500000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,max-charge-voltage = <8750000>; + ti,input-current = <500000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,minimum-sys-voltage = <7400000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + pd-charge-only = <1>; + typec0-enable-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + typec1-enable-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c6 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <400000>; + + fusb1: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb1_int>; + vbus-5v-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + discharge-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + charge-dev = <&bq25700>; + support-uboot-charge = <1>; + port-num = <1>; + status = "okay"; + }; +}; + +&i2c7 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <400000>; + + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + vbus-5v-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + discharge-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + charge-dev = <&bq25700>; + support-uboot-charge = <1>; + port-num = <0>; + status = "okay"; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_3v0>; + audio-supply = <&vcca1v8_codec>; + sdmmc-supply = <&vcc_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&dsi { + status = "disabled"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin_pull_down>; +}; + +&route_edp { + status = "okay"; + logo,mode = "center"; +}; + +&saradc { + status = "okay"; +}; + +&sdmmc { + clock-frequency = <50000000>; + clock-freq-min-max = <400000 150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + num-slots = <1>; + //sd-uhs-sdr104; + vqmmc-supply = <&vcc_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + +&sdio0 { + clock-frequency = <150000000>; + clock-freq-min-max = <200000 150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spdif { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&spi1 { + status = "disabled"; +}; + +&tcphy0 { + extcon = <&fusb0>; + status = "okay"; +}; + +&tcphy1 { + extcon = <&fusb1>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + extcon = <&fusb1>; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_host>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + extcon = <&fusb0>; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + extcon = <&fusb1>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hallsensor { + mh248_irq_gpio: mh248-irq-gpio { + rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hidkey { + hidkey_irq_gpio: hidkey-irq-gpio { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touchpad { + touchpad_irq_gpio: touchpad-irq-gpio { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + charger { + charger_ok: charge-ok { + rockchip,pins = + <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + gpio-leds { + leds_gpio: leds-gpio { + rockchip,pins = + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + host_vbus_drv: host-vbus-drv { + rockchip,pins = + <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_camera { + usb_cam_on_gpio: usb-cam-on-gpio { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + fusb30x { + fusb0_int: fusb0-int { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + fusb1_int: fusb1-int { + rockchip,pins = + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399-videostrong-linux.dts b/rk3399-videostrong-linux.dts new file mode 100644 index 0000000..142515e --- /dev/null +++ b/rk3399-videostrong-linux.dts @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: (GPL-2.0+ OR MIT) + */ + +/dts-v1/; + +#include "rk3399-sapphire.dtsi" +#include "rk3399-linux.dtsi" +#include + +/ { + model = "Rockchip RK3399 Videostrong Board (Linux Opensource)"; + compatible = "rockchip,rk3399-videostrong-linux", "rockchip,rk3399"; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,signal-irq = <182>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + }; + + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6354"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + status = "okay"; + }; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /* system status freq(KHz) */ + SYS_STATUS_NORMAL 800000 + SYS_STATUS_REBOOT 528000 + SYS_STATUS_SUSPEND 200000 + SYS_STATUS_VIDEO_1080P 200000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_VIDEO_4K_10B 800000 + SYS_STATUS_PERFORMANCE 800000 + SYS_STATUS_BOOST 400000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 600000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 577 200000 + 578 1701 300000 + 1702 99999 400000 + >; + auto-min-freq = <200000>; +}; + +&hdmi { + /* remove the hdmi_cec, reused by edp_hpd */ + pinctrl-0 = <&hdmi_i2c_xfer>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + }; +}; + +&i2s1 { + status = "okay"; + rockchip,i2s-broken-burst-len; + rockchip,playback-channels = <2>; + rockchip,capture-channels = <2>; + #sound-dai-cells = <0>; +}; + +&rkvdec { + status = "okay"; + /* 0 means ion, 1 means drm */ + //allocator = <0>; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399-vop-clk-set.dtsi b/rk3399-vop-clk-set.dtsi new file mode 100644 index 0000000..b09cb3a --- /dev/null +++ b/rk3399-vop-clk-set.dtsi @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/* + * This define is for support double show any dclk frequency. + * dclk_vop will have a exclusive pll as parent. + * set dclk_vop will change the pll rate as well. + */ + +#ifdef RK3399_TWO_PLL_FOR_VOP + +&sdhci { + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-parents = <&cru PLL_GPLL>; + assigned-clock-rates = <200000000>; +}; + +&uart0 { + assigned-clocks = <&cru SCLK_UART0_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&uart1 { + assigned-clocks = <&cru SCLK_UART_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&uart2 { + assigned-clocks = <&cru SCLK_UART_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&uart3 { + assigned-clocks = <&cru SCLK_UART_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&uart4 { + assigned-clocks = <&pmucru SCLK_UART4_SRC>; + assigned-clock-parents = <&pmucru PLL_PPLL>; +}; + +&spdif { + assigned-clocks = <&cru SCLK_SPDIF_DIV>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&i2s0{ + assigned-clocks = <&cru SCLK_I2S0_DIV>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&i2s1 { + assigned-clocks = <&cru SCLK_I2S1_DIV>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&i2s2 { + assigned-clocks = <&cru SCLK_I2S2_DIV>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&cru { + assigned-clocks = + <&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>, + <&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>, + <&cru ACLK_EMMC>, <&cru ACLK_CENTER>, + <&cru HCLK_SD>, <&cru SCLK_VDU_CA>, + <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>, + <&cru FCLK_CM0S>, <&cru ACLK_CCI>, + <&cru PCLK_ALIVE>, <&cru ACLK_GMAC>, + <&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>, + <&cru ARMCLKL>, <&cru ARMCLKB>, + <&cru PLL_NPLL>, <&cru ACLK_GPU>, + <&cru PLL_GPLL>, <&cru ACLK_PERIHP>, + <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>, + <&cru PCLK_PERILP1>, <&cru SCLK_I2C1>, + <&cru SCLK_I2C2>, <&cru SCLK_I2C3>, + <&cru SCLK_I2C5>, <&cru SCLK_I2C6>, + <&cru SCLK_I2C7>, <&cru SCLK_SPI0>, + <&cru SCLK_SPI1>, <&cru SCLK_SPI2>, + <&cru SCLK_SPI4>, <&cru SCLK_SPI5>, + <&cru ACLK_GIC>, <&cru ACLK_ISP0>, + <&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>, + <&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>, + <&cru ACLK_HDCP>, <&cru ACLK_VIO>, + <&cru HCLK_SD>, <&cru SCLK_CRYPTO0>, + <&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru ACLK_CENTER>, + <&cru ACLK_IEP>, <&cru ACLK_RGA>, + <&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>, + <&cru ACLK_VCODEC>, <&cru PCLK_DDR>, + <&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>, + <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>, + <&cru FCLK_CM0S>, <&cru ACLK_CCI>, + <&cru PCLK_ALIVE>, <&cru SCLK_CS>, + <&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>, + <&cru HCLK_VOP0>, <&cru ACLK_VOP1>, + <&cru HCLK_VOP1>; + assigned-clock-rates = + <75000000>, <50000000>, + <50000000>, <50000000>, + <50000000>, <100000000>, + <50000000>, <150000000>, + <150000000>, <150000000>, + <50000000>, <150000000>, + <50000000>, <100000000>, + <75000000>, <75000000>, + <816000000>, <816000000>, + <600000000>, <200000000>, + <800000000>, <150000000>, + <75000000>, <37500000>, + <300000000>, <100000000>, + <50000000>, <100000000>, + <50000000>, <100000000>, + <100000000>, <100000000>, + <100000000>, <100000000>, + <100000000>, <50000000>, + <50000000>, <50000000>, + <50000000>, <50000000>, + <200000000>, <400000000>, + <400000000>, <100000000>, + <100000000>, <100000000>, + <400000000>, <400000000>, + <200000000>, <100000000>, + <200000000>, <200000000>, + <100000000>, <400000000>, + <400000000>, <400000000>, + <400000000>, <300000000>, + <400000000>, <200000000>, + <400000000>, <300000000>, + <300000000>, <300000000>, + <300000000>, <600000000>,/* aclk_cci */ + <100000000>, <150000000>, + <150000000>, <400000000>, + <100000000>, <400000000>, + <100000000>; +}; +#endif + diff --git a/rk3399.dtsi b/rk3399.dtsi new file mode 100644 index 0000000..c50bacc --- /dev/null +++ b/rk3399.dtsi @@ -0,0 +1,3124 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "rk3399-dram-default-timing.dtsi" + +/ { + compatible = "rockchip,rk3399"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + dsi0 = &dsi; + dsi1 = &dsi1; + ethernet0 = &gmac; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + mmc0 = &sdio0; + mmc1 = &sdmmc; + mmc2 = &sdhci; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; + clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu_l1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; + clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu_l2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; + clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu_l3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <485>; + clocks = <&cru ARMCLKL>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <100>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0 0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&cru ARMCLKB>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <436>; + cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x1010000>; + entry-latency-us = <400>; + exit-latency-us = <500>; + min-residency-us = <2000>; + }; + }; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vopl_out>, <&vopb_out>; + clocks = <&cru PLL_VPLL>, <&cru PLL_CPLL>; + clock-names = "hdmi-tmds-pll", "default-vop-pll"; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + pmu_a72 { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + dummy_cpll: dummy_cpll { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "dummy_cpll"; + #clock-cells = <0>; + }; + + dummy_vpll: dummy_vpll { + compatible = "fixed-clock"; + clock-frequency = <0>; + clock-output-names = "dummy_vpll"; + #clock-cells = <0>; + }; + + amba: bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_bus: dma-controller@ff6d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6d0000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC0_PERILP>; + clock-names = "apb_pclk"; + }; + + dmac_peri: dma-controller@ff6e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6e0000 0x0 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC1_PERILP>; + clock-names = "apb_pclk"; + }; + }; + + pcie0: pcie@f8000000 { + compatible = "rockchip,rk3399-pcie"; + reg = <0x0 0xf8000000 0x0 0x2000000>, + <0x0 0xfd000000 0x0 0x1000000>; + reg-names = "axi-base", "apb-base"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + aspm-no-l0s; + bus-range = <0x0 0x1f>; + clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, + <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; + clock-names = "aclk", "aclk-perf", + "hclk", "pm"; + interrupts = , + , + ; + interrupt-names = "sys", "legacy", "client"; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie0_intc 0>, + <0 0 0 2 &pcie0_intc 1>, + <0 0 0 3 &pcie0_intc 2>, + <0 0 0 4 &pcie0_intc 3>; + max-link-speed = <1>; + msi-map = <0x0 &its 0x0 0x1000>; + phys = <&pcie_phy 0>, <&pcie_phy 1>, + <&pcie_phy 2>, <&pcie_phy 3>; + phy-names = "pcie-phy-0", "pcie-phy-1", + "pcie-phy-2", "pcie-phy-3"; + power-domains = <&power RK3399_PD_PERIHP>; + ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 + 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; + resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, + <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, + <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, + <&cru SRST_A_PCIE>; + reset-names = "core", "mgmt", "mgmt-sticky", "pipe", + "pm", "pclk", "aclk"; + status = "disabled"; + + pcie0_intc: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@fe300000 { + compatible = "rockchip,rk3399-gmac"; + reg = <0x0 0xfe300000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, + <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, + <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "clk_mac_refout", "aclk_mac", + "pclk_mac"; + power-domains = <&power RK3399_PD_GMAC>; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + rockchip,grf = <&grf>; + snps,txpbl = <0x4>; + status = "disabled"; + }; + + sdio0: mmc@fe310000 { + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe310000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + resets = <&cru SRST_SDIO0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc: mmc@fe320000 { + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe320000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + assigned-clocks = <&cru HCLK_SD>; + assigned-clock-rates = <200000000>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + power-domains = <&power RK3399_PD_SD>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = ; + arasan,soc-ctl-syscon = <&grf>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + power-domains = <&power RK3399_PD_EMMC>; + disable-cqe-dcmd; + disable-cqe; + status = "disabled"; + }; + + usb_host0_ehci: usb@fe380000 { + compatible = "generic-ehci"; + reg = <0x0 0xfe380000 0x0 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fe3a0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfe3a0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, + <&u2phy0>; + phys = <&u2phy0_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fe3c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xfe3c0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fe3e0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfe3e0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, + <&u2phy1>; + phys = <&u2phy1_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usbdrd3_0: usb@fe800000 { + compatible = "rockchip,rk3399-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + status = "disabled"; + + usbdrd_dwc3_0: usb@fe800000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe800000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, + <&cru SCLK_USB3OTG0_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + resets = <&cru SRST_A_USB3_OTG0>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + power-domains = <&power RK3399_PD_USB3>; + status = "disabled"; + }; + }; + + usbdrd3_1: usb@fe900000 { + compatible = "rockchip,rk3399-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, + <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "aclk_usb3_rksoc_axi_perf", + "aclk_usb3", "grf_clk"; + status = "disabled"; + + usbdrd_dwc3_1: usb@fe900000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe900000 0x0 0x100000>; + interrupts = ; + clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, + <&cru SCLK_USB3OTG1_SUSPEND>; + clock-names = "ref", "bus_early", "suspend"; + resets = <&cru SRST_A_USB3_OTG1>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + power-domains = <&power RK3399_PD_USB3>; + status = "disabled"; + }; + }; + + cdn_dp: dp@fec00000 { + compatible = "rockchip,rk3399-cdn-dp"; + reg = <0x0 0xfec00000 0x0 0x100000>; + interrupts = ; + assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; + assigned-clock-rates = <100000000>, <200000000>; + clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, + <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; + clock-names = "core-clk", "pclk", "spdif", "grf"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + power-domains = <&power RK3399_PD_HDCP>; + resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, + <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; + reset-names = "spdif", "dptx", "apb", "core"; + rockchip,grf = <&grf>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + dp_in: port { + #address-cells = <1>; + #size-cells = <0>; + + dp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dp>; + }; + + dp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dp>; + }; + }; + }; + }; + + gic: interrupt-controller@fee00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ + <0x0 0xfef00000 0 0xc0000>, /* GICR */ + <0x0 0xfff00000 0 0x10000>, /* GICC */ + <0x0 0xfff10000 0 0x10000>, /* GICH */ + <0x0 0xfff20000 0 0x10000>; /* GICV */ + interrupts = ; + its: interrupt-controller@fee20000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfee20000 0x0 0x20000>; + }; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu_b0 &cpu_b1>; + }; + }; + }; + + saradc: saradc@ff100000 { + compatible = "rockchip,rk3399-saradc"; + reg = <0x0 0xff100000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + i2c1: i2c@ff110000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff110000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C1>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ff120000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff120000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C2>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ff130000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff130000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C3>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ff140000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff140000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C5>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ff150000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff150000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C6>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ff160000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff160000 0x0 0x1000>; + assigned-clocks = <&cru SCLK_I2C7>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@ff1a0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1a0000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + spi0: spi@ff1c0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1c0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + dmas = <&dmac_peri 10>, <&dmac_peri 11>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff1d0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + dmas = <&dmac_peri 12>, <&dmac_peri 13>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff1e0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1e0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + dmas = <&dmac_peri 14>, <&dmac_peri 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@ff1f0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1f0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + dmas = <&dmac_peri 18>, <&dmac_peri 19>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@ff200000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff200000 0x0 0x1000>; + clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + dmas = <&dmac_bus 8>, <&dmac_bus 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + soc_thermal: cpu_thermal: cpu-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <1000>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: cpu_alert0: cpu_alert0 { + temperature = <70000>; + hysteresis = <2000>; + type = "passive"; + }; + target: cpu_alert1: cpu_alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: cpu_crit: cpu_crit { + temperature = <115000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&target>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <100>; + polling-delay = <1000>; + + thermal-sensors = <&tsadc 1>; + }; + }; + + tsadc: tsadc@ff260000 { + compatible = "rockchip,rk3399-tsadc"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <750000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <95000>; + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&otp_pin>; + pinctrl-1 = <&otp_out>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + qos_emmc: qos@ffa58000 { + compatible = "syscon"; + reg = <0x0 0xffa58000 0x0 0x20>; + }; + + qos_gmac: qos@ffa5c000 { + compatible = "syscon"; + reg = <0x0 0xffa5c000 0x0 0x20>; + }; + + qos_pcie: qos@ffa60080 { + compatible = "syscon"; + reg = <0x0 0xffa60080 0x0 0x20>; + }; + + qos_usb_host0: qos@ffa60100 { + compatible = "syscon"; + reg = <0x0 0xffa60100 0x0 0x20>; + }; + + qos_usb_host1: qos@ffa60180 { + compatible = "syscon"; + reg = <0x0 0xffa60180 0x0 0x20>; + }; + + qos_usb_otg0: qos@ffa70000 { + compatible = "syscon"; + reg = <0x0 0xffa70000 0x0 0x20>; + }; + + qos_usb_otg1: qos@ffa70080 { + compatible = "syscon"; + reg = <0x0 0xffa70080 0x0 0x20>; + }; + + qos_sd: qos@ffa74000 { + compatible = "syscon"; + reg = <0x0 0xffa74000 0x0 0x20>; + }; + + qos_sdioaudio: qos@ffa76000 { + compatible = "syscon"; + reg = <0x0 0xffa76000 0x0 0x20>; + }; + + qos_hdcp: qos@ffa90000 { + compatible = "syscon"; + reg = <0x0 0xffa90000 0x0 0x20>; + }; + + qos_iep: qos@ffa98000 { + compatible = "syscon"; + reg = <0x0 0xffa98000 0x0 0x20>; + }; + + qos_isp0_m0: qos@ffaa0000 { + compatible = "syscon"; + reg = <0x0 0xffaa0000 0x0 0x20>; + }; + + qos_isp0_m1: qos@ffaa0080 { + compatible = "syscon"; + reg = <0x0 0xffaa0080 0x0 0x20>; + }; + + qos_isp1_m0: qos@ffaa8000 { + compatible = "syscon"; + reg = <0x0 0xffaa8000 0x0 0x20>; + }; + + qos_isp1_m1: qos@ffaa8080 { + compatible = "syscon"; + reg = <0x0 0xffaa8080 0x0 0x20>; + }; + + qos_rga_r: qos@ffab0000 { + compatible = "syscon"; + reg = <0x0 0xffab0000 0x0 0x20>; + }; + + qos_rga_w: qos@ffab0080 { + compatible = "syscon"; + reg = <0x0 0xffab0080 0x0 0x20>; + }; + + qos_video_m0: qos@ffab8000 { + compatible = "syscon"; + reg = <0x0 0xffab8000 0x0 0x20>; + }; + + qos_video_m1_r: qos@ffac0000 { + compatible = "syscon"; + reg = <0x0 0xffac0000 0x0 0x20>; + }; + + qos_video_m1_w: qos@ffac0080 { + compatible = "syscon"; + reg = <0x0 0xffac0080 0x0 0x20>; + }; + + qos_vop_big_r: qos@ffac8000 { + compatible = "syscon"; + reg = <0x0 0xffac8000 0x0 0x20>; + }; + + qos_vop_big_w: qos@ffac8080 { + compatible = "syscon"; + reg = <0x0 0xffac8080 0x0 0x20>; + }; + + qos_vop_little: qos@ffad0000 { + compatible = "syscon"; + reg = <0x0 0xffad0000 0x0 0x20>; + }; + + qos_perihp: qos@ffad8080 { + compatible = "syscon"; + reg = <0x0 0xffad8080 0x0 0x20>; + }; + + qos_gpu: qos@ffae0000 { + compatible = "syscon"; + reg = <0x0 0xffae0000 0x0 0x20>; + }; + + pmu: power-management@ff310000 { + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; + + /* + * Note: RK3399 supports 6 voltage domains including VD_CORE_L, + * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. + * Some of the power domains are grouped together for every + * voltage domain. + * The detail contents as below. + */ + power: power-controller { + compatible = "rockchip,rk3399-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* These power domains are grouped by VD_CENTER */ + power-domain@RK3399_PD_IEP { + reg = ; + clocks = <&cru ACLK_IEP>, + <&cru HCLK_IEP>; + pm_qos = <&qos_iep>; + }; + power-domain@RK3399_PD_RGA { + reg = ; + clocks = <&cru ACLK_RGA>, + <&cru HCLK_RGA>; + pm_qos = <&qos_rga_r>, + <&qos_rga_w>; + }; + power-domain@RK3399_PD_VCODEC { + reg = ; + clocks = <&cru ACLK_VCODEC>, + <&cru HCLK_VCODEC>; + pm_qos = <&qos_video_m0>; + }; + power-domain@RK3399_PD_VDU { + reg = ; + clocks = <&cru ACLK_VDU>, + <&cru HCLK_VDU>; + pm_qos = <&qos_video_m1_r>, + <&qos_video_m1_w>; + }; + + /* These power domains are grouped by VD_GPU */ + power-domain@RK3399_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU>; + pm_qos = <&qos_gpu>; + }; + + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3399_PD_EDP { + reg = ; + clocks = <&cru PCLK_EDP_CTRL>; + }; + power-domain@RK3399_PD_EMMC { + reg = ; + clocks = <&cru ACLK_EMMC>; + pm_qos = <&qos_emmc>; + }; + power-domain@RK3399_PD_GMAC { + reg = ; + clocks = <&cru ACLK_GMAC>, + <&cru PCLK_GMAC>; + pm_qos = <&qos_gmac>; + }; + power-domain@RK3399_PD_PERIHP { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru ACLK_PERIHP>; + pm_qos = <&qos_perihp>, + <&qos_pcie>, + <&qos_usb_host0>, + <&qos_usb_host1>; + + power-domain@RK3399_PD_SD { + reg = ; + clocks = <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC>; + pm_qos = <&qos_sd>; + }; + }; + power-domain@RK3399_PD_SDIOAUDIO { + reg = ; + clocks = <&cru HCLK_SDIO>; + pm_qos = <&qos_sdioaudio>; + }; + power-domain@RK3399_PD_TCPD0 { + reg = ; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + }; + power-domain@RK3399_PD_TCPD1 { + reg = ; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + }; + power-domain@RK3399_PD_USB3 { + reg = ; + clocks = <&cru ACLK_USB3>; + pm_qos = <&qos_usb_otg0>, + <&qos_usb_otg1>; + }; + power-domain@RK3399_PD_VIO { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3399_PD_HDCP { + reg = ; + clocks = <&cru ACLK_HDCP>, + <&cru HCLK_HDCP>, + <&cru PCLK_HDCP>; + pm_qos = <&qos_hdcp>; + }; + power-domain@RK3399_PD_ISP0 { + reg = ; + clocks = <&cru ACLK_ISP0>, + <&cru HCLK_ISP0>; + pm_qos = <&qos_isp0_m0>, + <&qos_isp0_m1>; + }; + power-domain@RK3399_PD_ISP1 { + reg = ; + clocks = <&cru ACLK_ISP1>, + <&cru HCLK_ISP1>; + pm_qos = <&qos_isp1_m0>, + <&qos_isp1_m1>; + }; + power-domain@RK3399_PD_VO { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3399_PD_VOPB { + reg = ; + clocks = <&cru ACLK_VOP0>, + <&cru HCLK_VOP0>; + pm_qos = <&qos_vop_big_r>, + <&qos_vop_big_w>; + }; + power-domain@RK3399_PD_VOPL { + reg = ; + clocks = <&cru ACLK_VOP1>, + <&cru HCLK_VOP1>; + pm_qos = <&qos_vop_little>; + }; + }; + }; + }; + }; + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xff320000 0x0 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3399-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x300>; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-panic = ; + mode-recovery = ; + mode-ums = ; + }; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk3399-pmu-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pvtm@4 { + reg = <4>; + clocks = <&pmucru SCLK_PVTM_PMU>; + clock-names = "clk"; + resets = <&pmucru SRST_PVTM>; + reset-names = "rst"; + }; + }; + }; + + spi3: spi@ff350000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff350000 0x0 0x1000>; + clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; + clock-names = "spiclk", "apb_pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@ff370000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff370000 0x0 0x100>; + clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; + clock-names = "baudclk", "apb_pclk"; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "disabled"; + }; + + i2c0: i2c@ff3c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3c0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C0_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ff3d0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3d0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C4_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@ff3e0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff3e0000 0x0 0x1000>; + assigned-clocks = <&pmucru SCLK_I2C8_PMU>; + assigned-clock-rates = <200000000>; + clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@ff420000 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff420010 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff420020 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff420030 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3a_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = ; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + ddr_timing = <&ddr_timing>; + status = "disabled"; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <2>; + rockchip,resetgroup-count = <2>; + status = "disabled"; + }; + + vpu: video-codec@ff650000 { + compatible = "rockchip,rk3399-vpu"; + reg = <0x0 0xff650000 0x0 0x800>; + interrupts = , + ; + interrupt-names = "vepu", "vdpu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "hclk"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3399_PD_VCODEC>; + status = "disabled"; + }; + + vepu: vepu@ff650000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xff650000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_enc"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; + reset-names = "shared_video_h", "shared_video_a"; + iommus = <&vpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + power-domains = <&power RK3399_PD_VCODEC>; + status = "disabled"; + }; + + vdpu: vdpu@ff650400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xff650400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>; + reset-names = "shared_video_h", "shared_video_a"; + iommus = <&vpu_mmu>; + power-domains = <&power RK3399_PD_VCODEC>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + vpu_mmu: iommu@ff650800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff650800 0x0 0x40>; + interrupts = ; + interrupt-names = "vpu_mmu"; + clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3399_PD_VCODEC>; + status = "disabled"; + }; + + vdec: video-codec@ff660000 { + compatible = "rockchip,rk3399-vdec"; + reg = <0x0 0xff660000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + iommus = <&vdec_mmu>; + power-domains = <&power RK3399_PD_VDU>; + status = "disabled"; + }; + + rkvdec: rkvdec@ff660000 { + compatible = "rockchip,rkv-decoder-rk3399"; + reg = <0x0 0xff660000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, + <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", + "clk_cabac", "clk_core"; + resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>, + <&cru SRST_H_VDU_NOC>, <&cru SRST_A_VDU_NOC>, + <&cru SRST_VDU_CA>, <&cru SRST_VDU_CORE>; + reset-names = "video_h", "video_a", "niu_h", "niu_a", + "video_cabac", "video_core"; + iommus = <&vdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + power-domains = <&power RK3399_PD_VDU>; + status = "disabled"; + }; + + vdec_mmu: iommu@ff660480 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; + interrupts = ; + interrupt-names = "vdec_mmu"; + clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VDU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep: iep@ff670000 { + compatible = "rockchip,iep"; + iommu_enabled = <1>; + iommus = <&iep_mmu>; + reg = <0x0 0xff670000 0x0 0x800>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk_iep", "hclk_iep"; + power-domains = <&power RK3399_PD_IEP>; + allocator = <1>; + version = <2>; + status = "disabled"; + }; + + iep_mmu: iommu@ff670800 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff670800 0x0 0x40>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_IEP>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rk3399-rga"; + reg = <0x0 0xff680000 0x0 0x10000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3399_PD_RGA>; + }; + + efuse0: efuse@ff690000 { + compatible = "rockchip,rk3399-efuse"; + reg = <0x0 0xff690000 0x0 0x80>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru PCLK_EFUSE1024NS>; + clock-names = "pclk_efuse"; + + /* Data cells */ + specification_serial_number: specification-serial-number@6 { + reg = <0x06 0x1>; + bits = <0 5>; + }; + cpu_id: cpu-id@7 { + reg = <0x07 0x10>; + }; + cpub_leakage: cpu-leakage@17 { + reg = <0x17 0x1>; + }; + gpu_leakage: gpu-leakage@18 { + reg = <0x18 0x1>; + }; + center_leakage: center-leakage@19 { + reg = <0x19 0x1>; + }; + cpul_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + logic_leakage: logic-leakage@1b { + reg = <0x1b 0x1>; + }; + wafer_info: wafer-info@1c { + reg = <0x1c 0x1>; + }; + customer_demand: customer-demand@22 { + reg = <0x22 0x1>; + bits = <4 4>; + }; + }; + + pmucru: pmu-clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0x0 0xff750000 0x0 0x1000>; + rockchip,grf = <&pmugrf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&pmucru PLL_PPLL>; + assigned-clock-rates = <676000000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, + <&cru ACLK_VIO>, <&cru ACLK_HDCP>, + <&cru ACLK_GIC_PRE>, + <&cru PCLK_DDR>; + assigned-clock-rates = + <594000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, <600000000>, + <100000000>, <50000000>, + <400000000>, <400000000>, + <200000000>, + <200000000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3399-io-voltage-domain"; + status = "disabled"; + }; + + mipi_dphy_rx0: mipi-dphy-rx0 { + compatible = "rockchip,rk3399-mipi-dphy"; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_RX0_CFG>, + <&cru PCLK_VIO_GRF>; + clock-names = "dphy-ref", "dphy-cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0: usb2-phy@e450 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe450 0x10>; + clocks = <&cru SCLK_USB2PHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy0_480m"; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + + u2phy1: usb2-phy@e460 { + compatible = "rockchip,rk3399-usb2phy"; + reg = <0xe460 0x10>; + clocks = <&cru SCLK_USB2PHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy1_480m"; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + clocks = <&sdhci>; + clock-names = "emmcclk"; + drive-impedance-ohm = <50>; + #phy-cells = <0>; + status = "disabled"; + }; + + pcie_phy: pcie-phy { + compatible = "rockchip,rk3399-pcie-phy"; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + #phy-cells = <1>; + resets = <&cru SRST_PCIEPHY>; + reset-names = "phy"; + status = "disabled"; + }; + + pvtm: pvtm { + compatible = "rockchip,rk3399-pvtm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + pvtm@0 { + reg = <0>; + clocks = <&cru SCLK_PVTM_CORE_L>; + clock-names = "clk"; + resets = <&cru SRST_PVTM_CORE_L>; + reset-names = "rst"; + }; + pvtm@1 { + reg = <1>; + clocks = <&cru SCLK_PVTM_CORE_B>; + clock-names = "clk"; + resets = <&cru SRST_PVTM_CORE_B>; + reset-names = "rst"; + }; + pvtm@2 { + reg = <2>; + clocks = <&cru SCLK_PVTM_DDR>; + clock-names = "clk"; + resets = <&cru SRST_PVTM_DDR>; + reset-names = "rst"; + }; + pvtm@3 { + reg = <3>; + clocks = <&cru SCLK_PVTM_GPU>; + clock-names = "clk"; + resets = <&cru SRST_PVTM_GPU>; + reset-names = "rst"; + }; + }; + }; + + tcphy0: phy@ff7c0000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff7c0000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY0_TCPDCORE>, + <&cru SCLK_UPHY0_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD0>; + resets = <&cru SRST_UPHY0>, + <&cru SRST_UPHY0_PIPE_L00>, + <&cru SRST_P_UPHY0_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + status = "disabled"; + + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + tcphy1: phy@ff800000 { + compatible = "rockchip,rk3399-typec-phy"; + reg = <0x0 0xff800000 0x0 0x40000>; + clocks = <&cru SCLK_UPHY1_TCPDCORE>, + <&cru SCLK_UPHY1_TCPDPHY_REF>; + clock-names = "tcpdcore", "tcpdphy-ref"; + assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; + assigned-clock-rates = <50000000>; + power-domains = <&power RK3399_PD_TCPD1>; + resets = <&cru SRST_UPHY1>, + <&cru SRST_UPHY1_PIPE_L00>, + <&cru SRST_P_UPHY1_TCPHY>; + reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; + rockchip,grf = <&grf>; + status = "disabled"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; + }; + + watchdog@ff848000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff848000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = ; + }; + + rktimer: rktimer@ff850000 { + compatible = "rockchip,rk3399-timer"; + reg = <0x0 0xff850000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; + clock-names = "pclk", "timer"; + }; + + spdif: spdif@ff870000 { + compatible = "rockchip,rk3399-spdif"; + reg = <0x0 0xff870000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac_bus 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s0: i2s@ff880000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff880000 0x0 0x1000>; + rockchip,grf = <&grf>; + interrupts = ; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; + resets = <&cru SRST_I2S0_8CH>, <&cru SRST_H_I2S0_8CH>; + reset-names = "reset-m", "reset-h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1: i2s@ff890000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac_bus 2>, <&dmac_bus 3>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; + resets = <&cru SRST_I2S1_8CH>, <&cru SRST_H_I2S1_8CH>; + reset-names = "reset-m", "reset-h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_bus>; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2: i2s@ff8a0000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff8a0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac_bus 4>, <&dmac_bus 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + resets = <&cru SRST_I2S2_8CH>, <&cru SRST_H_I2S2_8CH>; + reset-names = "reset-m", "reset-h"; + power-domains = <&power RK3399_PD_SDIOAUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + rng: rng@ff8b8000 { + compatible = "rockchip,cryptov1-rng"; + reg = <0x0 0xff8b8000 0x0 0x1000>; + clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; + clock-names = "clk_crypto", "hclk_crypto"; + assigned-clocks = <&cru SCLK_CRYPTO1>, <&cru HCLK_S_CRYPTO1>; + assigned-clock-rates = <150000000>, <100000000>; + status = "disabled"; + }; + + vopl: vop@ff8f0000 { + compatible = "rockchip,rk3399-vop-lit"; + reg = <0x0 0xff8f0000 0x0 0x600>, + <0x0 0xff8f1c00 0x0 0x200>, + <0x0 0xff8f2000 0x0 0x400>; + reg-names = "regs", "cabc_lut", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>, <&cru DCLK_VOP1_DIV>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; + iommus = <&vopl_mmu>; + power-domains = <&power RK3399_PD_VOPL>; + resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vopl_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopl_out_dsi: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi_in_vopl>; + }; + + vopl_out_edp: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp_in_vopl>; + }; + + vopl_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_vopl>; + }; + + vopl_out_dsi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&dsi1_in_vopl>; + }; + + vopl_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopl>; + }; + }; + }; + + vop1_pwm: voppwm@ff8f01a0 { + compatible = "rockchip,vop-pwm"; + reg = <0x0 0xff8f01a0 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&vop1_pwm_pin>; + clocks = <&cru SCLK_VOP1_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + vopl_mmu: iommu@ff8f3f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff8f3f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopl_mmu"; + clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPL>; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + vopb: vop@ff900000 { + compatible = "rockchip,rk3399-vop-big"; + reg = <0x0 0xff900000 0x0 0x600>, + <0x0 0xff901c00 0x0 0x200>, + <0x0 0xff902000 0x0 0x1000>; + reg-names = "regs", "cabc_lut", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>, <&cru DCLK_VOP0_DIV>; + clock-names = "aclk_vop", "dclk_vop", "hclk_vop", "dclk_source"; + iommus = <&vopb_mmu>; + power-domains = <&power RK3399_PD_VOPB>; + resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; + reset-names = "axi", "ahb", "dclk"; + status = "disabled"; + + vopb_out: port { + #address-cells = <1>; + #size-cells = <0>; + + vopb_out_edp: endpoint@0 { + reg = <0>; + remote-endpoint = <&edp_in_vopb>; + }; + + vopb_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vopb>; + }; + + vopb_out_hdmi: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi_in_vopb>; + }; + + vopb_out_dsi1: endpoint@3 { + reg = <3>; + remote-endpoint = <&dsi1_in_vopb>; + }; + + vopb_out_dp: endpoint@4 { + reg = <4>; + remote-endpoint = <&dp_in_vopb>; + }; + }; + }; + + vop0_pwm: voppwm@ff9001a0 { + compatible = "rockchip,vop-pwm"; + reg = <0x0 0xff9001a0 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&vop0_pwm_pin>; + clocks = <&cru SCLK_VOP0_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + vopb_mmu: iommu@ff903f00 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff903f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vopb_mmu"; + clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3399_PD_VOPB>; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + rkisp1_0: rkisp1@ff910000 { + compatible = "rockchip,rk3399-rkisp1"; + reg = <0x0 0xff910000 0x0 0x4000>; + interrupts = ; + interrupt-names = "isp_irq"; + clocks = <&cru SCLK_ISP0>, + <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, + <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "hclk_isp", + "aclk_isp_wrap", "hclk_isp_wrap"; + devfreq = <&dmc>; + power-domains = <&power RK3399_PD_ISP0>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + + isp0_mmu: iommu@ff914000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkisp1_1: rkisp1@ff920000 { + compatible = "rockchip,rk3399-rkisp1"; + reg = <0x0 0xff920000 0x0 0x4000>; + interrupts = ; + interrupt-names = "isp_irq"; + clocks = <&cru SCLK_ISP1>, + <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, + <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>, + <&cru PCLK_ISP1_WRAPPER>; + clock-names = "clk_isp", + "aclk_isp", "hclk_isp", + "aclk_isp_wrap", "hclk_isp_wrap", + "pclk_isp_wrap"; + devfreq = <&dmc>; + power-domains = <&power RK3399_PD_ISP1>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + + isp1_mmu: iommu@ff924000 { + compatible = "rockchip,iommu"; + reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; + interrupts = ; + interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3399_PD_ISP1>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "hdmi-sound"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + hdmi: hdmi@ff940000 { + compatible = "rockchip,rk3399-dw-hdmi"; + reg = <0x0 0xff940000 0x0 0x20000>; + interrupts = ; + clocks = <&cru PCLK_HDMI_CTRL>, + <&cru SCLK_HDMI_SFR>, + <&cru SCLK_HDMI_CEC>, + <&cru PCLK_VIO_GRF>, + <&cru PLL_VPLL>; + clock-names = "iahb", "isfr", "cec", "grf", "vpll"; + power-domains = <&power RK3399_PD_HDCP>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; + status = "disabled"; + + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; + }; + }; + }; + }; + + dsi: mipi_dsi: dsi@ff960000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff960000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, + <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI0>; + reset-names = "apb"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dsi>; + }; + dsi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dsi>; + }; + }; + }; + }; + + dsi1: mipi_dsi1: dsi@ff968000 { + compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x0 0xff968000 0x0 0x8000>; + interrupts = ; + clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, + <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; + clock-names = "ref", "pclk", "phy_cfg", "grf"; + power-domains = <&power RK3399_PD_VIO>; + resets = <&cru SRST_P_MIPI_DSI1>; + reset-names = "apb"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_dsi1>; + }; + + dsi1_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_dsi1>; + }; + }; + }; + }; + + mipi_dphy_tx1rx1: mipi-dphy-tx1rx1@ff968000 { + compatible = "rockchip,rk3399-mipi-dphy"; + reg = <0x0 0xff968000 0x0 0x8000>; + clocks = <&cru SCLK_MIPIDPHY_REF>, + <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru PCLK_VIO_GRF>, + <&cru PCLK_MIPI_DSI1>; + clock-names = "dphy-ref", "dphy-cfg", + "grf", "pclk_mipi_dsi"; + rockchip,grf = <&grf>; + power-domains = <&power RK3399_PD_VIO>; + status = "disabled"; + }; + + edp: edp@ff970000 { + compatible = "rockchip,rk3399-edp"; + reg = <0x0 0xff970000 0x0 0x8000>; + interrupts = ; + clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; + clock-names = "dp", "pclk", "grf"; + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; + power-domains = <&power RK3399_PD_EDP>; + resets = <&cru SRST_P_EDP_CTRL>; + reset-names = "dp"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_edp>; + }; + + edp_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + gpu: gpu@ff9a0000 { + compatible = "arm,malit860", + "arm,malit86x", + "arm,malit8xx", + "arm,mali-midgard"; + reg = <0x0 0xff9a0000 0x0 0x10000>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + clocks = <&cru ACLK_GPU>; + clock-names = "clk_mali"; + #cooling-cells = <2>; + power-domains = <&power RK3399_PD_GPU>; + power-off-delay-ms = <200>; + upthreshold = <40>; + downdifferential = <10>; + status = "disabled"; + + gpu_power_model: power_model { + compatible = "arm,mali-simple-power-model"; + static-coefficient = <411000>; + dynamic-coefficient = <733>; + ts = <32000 4700 (-80) 2>; + thermal-zone = "gpu-thermal"; + }; + }; + + nocp_cci_msch0: nocp-cci-msch0@ffa86000 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa86000 0x0 0x400>; + }; + + nocp_gpu_msch0: nocp-gpu-msch0@ffa86400 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa86400 0x0 0x400>; + }; + + nocp_hp_msch0: nocp-hp-msch0@ffa86800 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa86800 0x0 0x400>; + }; + + nocp_lp_msch0: nocp-lp-msch0@ffa86c00 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa86c00 0x0 0x400>; + }; + + nocp_video_msch0: nocp-video-msch0@ffa87000 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa87000 0x0 0x400>; + }; + + nocp_vio0_msch0: nocp-vio0-msch0@ffa87400 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa87400 0x0 0x400>; + }; + + nocp_vio1_msch0: nocp-vio1-msch0@ffa87800 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa87800 0x0 0x400>; + }; + + nocp_cci_msch1: nocp-cci-msch1@ffa8e000 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8e000 0x0 0x400>; + }; + + nocp_gpu_msch1: nocp-gpu-msch1@ffa8e400 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8e400 0x0 0x400>; + }; + + nocp_hp_msch1: nocp-hp-msch1@ffa8e800 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8e800 0x0 0x400>; + }; + + nocp_lp_msch1: nocp-lp-msch1@ffa8ec00 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8ec00 0x0 0x400>; + }; + + nocp_video_msch1: nocp-video-msch1@ffa8f000 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8f000 0x0 0x400>; + }; + + nocp_vio0_msch1: nocp-vio0-msch1@ffa8f400 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8f400 0x0 0x400>; + }; + + nocp_vio1_msch1: nocp-vio1-msch1@ffa8f800 { + compatible = "rockchip,rk3399-nocp"; + reg = <0x0 0xffa8f800 0x0 0x400>; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,polling-delay = <200>; /* milliseconds */ + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3399-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff720000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff720000 0x0 0x100>; + clocks = <&pmucru PCLK_GPIO0_PMU>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1@ff730000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff730000 0x0 0x100>; + clocks = <&pmucru PCLK_GPIO1_PMU>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3@ff788000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff788000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio4: gpio4@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO4>; + interrupts = ; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_10ma: pcfg-pull-none-10ma { + bias-disable; + drive-strength = <10>; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + + pcfg_pull_none_18ma: pcfg-pull-none-18ma { + bias-disable; + drive-strength = <18>; + }; + + pcfg_pull_none_20ma: pcfg-pull-none-20ma { + bias-disable; + drive-strength = <20>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_up_10ma: pcfg-pull-up-10ma { + bias-pull-up; + drive-strength = <10>; + }; + + pcfg_pull_up_18ma: pcfg-pull-up-18ma { + bias-pull-up; + drive-strength = <18>; + }; + + pcfg_pull_up_20ma: pcfg-pull-up-20ma { + bias-pull-up; + drive-strength = <20>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_down_8ma: pcfg-pull-down-8ma { + bias-pull-down; + drive-strength = <8>; + }; + + pcfg_pull_down_12ma: pcfg-pull-down-12ma { + bias-pull-down; + drive-strength = <12>; + }; + + pcfg_pull_down_18ma: pcfg-pull-down-18ma { + bias-pull-down; + drive-strength = <18>; + }; + + pcfg_pull_down_20ma: pcfg-pull-down-20ma { + bias-pull-down; + drive-strength = <20>; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + clock { + clk_32k: clk-32k { + rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp-hpd { + rockchip,pins = + <4 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = + /* mac_txclk */ + <3 RK_PC1 1 &pcfg_pull_none_13ma>, + /* mac_rxclk */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* mac_mdio */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* mac_txen */ + <3 RK_PB4 1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* mac_mdc */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* mac_rxd1 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 RK_PA5 1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 RK_PA4 1 &pcfg_pull_none_13ma>, + /* mac_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* mac_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* mac_txd3 */ + <3 RK_PA1 1 &pcfg_pull_none_13ma>, + /* mac_txd2 */ + <3 RK_PA0 1 &pcfg_pull_none_13ma>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = + /* mac_mdio */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* mac_txen */ + <3 RK_PB4 1 &pcfg_pull_none_13ma>, + /* mac_clk */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* mac_rxer */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* mac_rxdv */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* mac_mdc */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* mac_rxd1 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* mac_rxd0 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* mac_txd1 */ + <3 RK_PA5 1 &pcfg_pull_none_13ma>, + /* mac_txd0 */ + <3 RK_PA4 1 &pcfg_pull_none_13ma>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <1 RK_PB7 2 &pcfg_pull_none>, + <1 RK_PC0 2 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <4 RK_PA2 1 &pcfg_pull_none>, + <4 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 RK_PA1 2 &pcfg_pull_none_12ma>, + <2 RK_PA0 2 &pcfg_pull_none_12ma>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <4 RK_PC1 1 &pcfg_pull_none>, + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + i2c3_gpio: i2c3_gpio { + rockchip,pins = + <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = + <1 RK_PB4 1 &pcfg_pull_none>, + <1 RK_PB3 1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = + <3 RK_PB3 2 &pcfg_pull_none>, + <3 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + i2c6 { + i2c6_xfer: i2c6-xfer { + rockchip,pins = + <2 RK_PB2 2 &pcfg_pull_none>, + <2 RK_PB1 2 &pcfg_pull_none>; + }; + }; + + i2c7 { + i2c7_xfer: i2c7-xfer { + rockchip,pins = + <2 RK_PB0 2 &pcfg_pull_none>, + <2 RK_PA7 2 &pcfg_pull_none>; + }; + }; + + i2c8 { + i2c8_xfer: i2c8-xfer { + rockchip,pins = + <1 RK_PC5 1 &pcfg_pull_none>, + <1 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_2ch_bus: i2s0-2ch-bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>, + <4 RK_PA0 1 &pcfg_pull_none>; + }; + + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 RK_PD0 1 &pcfg_pull_none>, + <3 RK_PD1 1 &pcfg_pull_none>, + <3 RK_PD2 1 &pcfg_pull_none>, + <3 RK_PD3 1 &pcfg_pull_none>, + <3 RK_PD4 1 &pcfg_pull_none>, + <3 RK_PD5 1 &pcfg_pull_none>, + <3 RK_PD6 1 &pcfg_pull_none>, + <3 RK_PD7 1 &pcfg_pull_none>; + }; + + i2s_8ch_mclk: i2s-8ch-mclk { + rockchip,pins = + <4 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_2ch_bus: i2s1-2ch-bus { + rockchip,pins = + <4 RK_PA3 1 &pcfg_pull_none>, + <4 RK_PA4 1 &pcfg_pull_none>, + <4 RK_PA5 1 &pcfg_pull_none>, + <4 RK_PA6 1 &pcfg_pull_none>, + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + <2 RK_PC4 1 &pcfg_pull_up>, + <2 RK_PC5 1 &pcfg_pull_up>, + <2 RK_PC6 1 &pcfg_pull_up>, + <2 RK_PC7 1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = + <2 RK_PD0 1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = + <2 RK_PD1 1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = + <2 RK_PD2 1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = + <2 RK_PD3 1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = + <2 RK_PD4 1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = + <0 RK_PA4 1 &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up>, + <4 RK_PB1 1 &pcfg_pull_up>, + <4 RK_PB2 1 &pcfg_pull_up>, + <4 RK_PB3 1 &pcfg_pull_up>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up>; + }; + + sdmmc_cd: sdmmc-cd { + rockchip,pins = + <0 RK_PA7 1 &pcfg_pull_up>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = + <0 RK_PB0 1 &pcfg_pull_up>; + }; + }; + + suspend { + ap_pwroff: ap-pwroff { + rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; + }; + + ddrio_pwroff: ddrio-pwroff { + rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_bus: spdif-bus { + rockchip,pins = + <4 RK_PC5 1 &pcfg_pull_none>; + }; + + spdif_bus_1: spdif-bus-1 { + rockchip,pins = + <3 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <3 RK_PA6 2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = + <3 RK_PA7 2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = + <3 RK_PB0 2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = + <3 RK_PA5 2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = + <3 RK_PA4 2 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <1 RK_PB1 2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = + <1 RK_PB2 2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = + <1 RK_PA7 2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = + <1 RK_PB0 2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = + <2 RK_PB3 1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = + <2 RK_PB4 1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = + <2 RK_PB1 1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = + <2 RK_PB2 1 &pcfg_pull_up>; + }; + }; + + spi3 { + spi3_clk: spi3-clk { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_up>; + }; + spi3_cs0: spi3-cs0 { + rockchip,pins = + <1 RK_PC2 1 &pcfg_pull_up>; + }; + spi3_rx: spi3-rx { + rockchip,pins = + <1 RK_PB7 1 &pcfg_pull_up>; + }; + spi3_tx: spi3-tx { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_up>; + }; + }; + + spi4 { + spi4_clk: spi4-clk { + rockchip,pins = + <3 RK_PA2 2 &pcfg_pull_up>; + }; + spi4_cs0: spi4-cs0 { + rockchip,pins = + <3 RK_PA3 2 &pcfg_pull_up>; + }; + spi4_rx: spi4-rx { + rockchip,pins = + <3 RK_PA0 2 &pcfg_pull_up>; + }; + spi4_tx: spi4-tx { + rockchip,pins = + <3 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + spi5 { + spi5_clk: spi5-clk { + rockchip,pins = + <2 RK_PC6 2 &pcfg_pull_up>; + }; + spi5_cs0: spi5-cs0 { + rockchip,pins = + <2 RK_PC7 2 &pcfg_pull_up>; + }; + spi5_rx: spi5-rx { + rockchip,pins = + <2 RK_PC4 2 &pcfg_pull_up>; + }; + spi5_tx: spi5-tx { + rockchip,pins = + <2 RK_PC5 2 &pcfg_pull_up>; + }; + }; + + testclk { + test_clkout0: test-clkout0 { + rockchip,pins = + <0 RK_PA0 1 &pcfg_pull_none>; + }; + + test_clkout1: test-clkout1 { + rockchip,pins = + <2 RK_PD1 2 &pcfg_pull_none>; + }; + + test_clkout2: test-clkout2 { + rockchip,pins = + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + tsadc { + otp_pin: otp-pin { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + otp_out: otp-out { + rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <2 RK_PC0 1 &pcfg_pull_up>, + <2 RK_PC1 1 &pcfg_pull_up>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <2 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <3 RK_PB4 2 &pcfg_pull_up>, + <3 RK_PB5 2 &pcfg_pull_up>; + }; + }; + + uart2a { + uart2a_xfer: uart2a-xfer { + rockchip,pins = + <4 RK_PB0 2 &pcfg_pull_up>, + <4 RK_PB1 2 &pcfg_pull_up>; + }; + }; + + uart2b { + uart2b_xfer: uart2b-xfer { + rockchip,pins = + <4 RK_PC0 2 &pcfg_pull_up>, + <4 RK_PC1 2 &pcfg_pull_up>; + }; + }; + + uart2c { + uart2c_xfer: uart2c-xfer { + rockchip,pins = + <4 RK_PC3 1 &pcfg_pull_up>, + <4 RK_PC4 1 &pcfg_pull_up>; + }; + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = + <3 RK_PB6 2 &pcfg_pull_up>, + <3 RK_PB7 2 &pcfg_pull_up>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = + <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + <1 RK_PA7 1 &pcfg_pull_up>, + <1 RK_PB0 1 &pcfg_pull_up>; + }; + }; + + uarthdcp { + uarthdcp_xfer: uarthdcp-xfer { + rockchip,pins = + <4 RK_PC5 2 &pcfg_pull_up>, + <4 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + pwm0_pin_pull_down: pwm0-pin-pull-down { + rockchip,pins = + <4 RK_PC2 1 &pcfg_pull_down>; + }; + + vop0_pwm_pin: vop0-pwm-pin { + rockchip,pins = + <4 RK_PC2 2 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 RK_PC2 3 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <4 RK_PC6 1 &pcfg_pull_none>; + }; + + pwm1_pin_pull_down: pwm1-pin-pull-down { + rockchip,pins = + <4 RK_PC6 1 &pcfg_pull_down>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <1 RK_PC3 1 &pcfg_pull_none>; + }; + + pwm2_pin_pull_down: pwm2-pin-pull-down { + rockchip,pins = + <1 RK_PC3 1 &pcfg_pull_down>; + }; + }; + + pwm3a { + pwm3a_pin: pwm3a-pin { + rockchip,pins = + <0 RK_PA6 1 &pcfg_pull_none>; + }; + + pwm3a_pin_pull_down: pwm3a-pin-pull-down { + rockchip,pins = + <0 RK_PA6 1 &pcfg_pull_down>; + }; + }; + + pwm3b { + pwm3b_pin: pwm3b-pin { + rockchip,pins = + <1 RK_PB6 1 &pcfg_pull_none>; + }; + + pwm3b_pin_pull_down: pwm3b-pin-pull-down { + rockchip,pins = + <1 RK_PB6 1 &pcfg_pull_down>; + }; + }; + + hdmi { + hdmi_i2c_xfer: hdmi-i2c-xfer { + rockchip,pins = + <4 RK_PC1 3 &pcfg_pull_none>, + <4 RK_PC0 3 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = + <4 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + pcie { + pcie_clkreqn_cpm: pci-clkreqn-cpm { + rockchip,pins = + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_clkreqnb_cpm: pci-clkreqnb-cpm { + rockchip,pins = + <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3399"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,virtual-poweroff = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + }; +}; diff --git a/rk3399/king-rk3399.dts b/rk3399/king-rk3399.dts new file mode 100755 index 0000000..56f8307 --- /dev/null +++ b/rk3399/king-rk3399.dts @@ -0,0 +1,202 @@ +/dts-v1/; + +#include "rp-rk3399-board.dtsi" + +#include "rp-usb2-host0.dtsi" +#include "rp-usb2-host1.dtsi" +//#include "rp-usb3-otg-typeA.dtsi" +#include "rp-usb3-otg-typeC.dtsi" +#include "rp-usb3_1-host.dtsi" + + +#include "rp-audio-rt5651.dtsi" +#include "rp-pmu-rk808.dtsi" + + +#include "rp-gpio-key.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-mipi-ov13850-camera.dtsi" +//#include "rp-hdmiin.dtsi" + +#include "rp-wifi-sdio.dtsi" +#include "rp-bt-uart0.dtsi" + +#include "rp-sdcard-mmc1.dtsi" +#include "rp-gmac.dtsi" + +#include "rp-lcd-hdmi.dtsi" +//#include "rp-lcd-mipi-5-720-1280.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-800-1280.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280.dtsi" +//#include "rp-lcd-mipi-8-800-1280-new.dtsi" +//#include "rp-lcd-mipi-10-800-1280.dtsi" +//#include "rp-lcd-mipi-10-1920-1200.dtsi" +//#include "rp-lcd-edp-13.3-1920-1080.dtsi" + + + +/ { + + model = "king-rk3399"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "cpu-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + compatible = "rp_power"; + + rp_not_deep_sleep = <1>; + status = "okay"; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + * + *If you want to set the uboot to high level, add the lower properties + * regulator_uboot_on + */ + + breathe-led { //run led + gpio_num = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + regulator_uboot_on; + }; + + power_en { + gpio_num = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + hub_rst { + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + //fan_open { + // gpio_num = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // regulator_uboot_on; + // }; + + gsm_power_en { + gpio_num = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + base_value = <0>; //3288_5.1 = 0 3288_7.1.2 = 992 3288_ubuntu = 992 3399_7.1.2 = 1000 3399_ubuntu = 0 + + gpio4c5 { + gpio_num = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio4d5 { + gpio_num = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; +}; + +&spi1 { + status = "disabled"; + max-freq = <50000000>; + spi_test:spi_test@0 { + status = "okay"; + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-cpha; + spi-cpol; + cs-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + }; + }; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; //king usb +}; + +//used to bluetooth +//&uart0 { +// status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +//}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; + + + diff --git a/rk3399/nano-rk3399.dts b/rk3399/nano-rk3399.dts new file mode 100755 index 0000000..e933df8 --- /dev/null +++ b/rk3399/nano-rk3399.dts @@ -0,0 +1,273 @@ +/dts-v1/; + +#include "rp-rk3399-board.dtsi" + +#include "rp-usb2-host0.dtsi" +#include "rp-usb2-host1.dtsi" +#include "rp-usb3-otg-typeA.dtsi" +//#include "rp-usb3-otg-typeC.dtsi" +#include "rp-usb3_1-host.dtsi" + +#include "rp-audio-rt5640.dtsi" +#include "rp-pmu-rk808.dtsi" + +#include "rp-gpio-key.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-gmac.dtsi" + +#include "rp-wifi-sdio.dtsi" +#include "rp-bt-uart0.dtsi" + +#include "rp-mipi-ov13850-camera.dtsi" +//#include "rp-hdmiin.dtsi" + +#include "rp-sdcard-mmc1.dtsi" + +//#include "rp-lcd-hdmi.dtsi" +//#include "rp-lcd-mipi-5-720-1280.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-800-1280.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280.dtsi" +//#include "rp-lcd-mipi-8-800-1280-new.dtsi" +//#include "rp-lcd-mipi-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-8-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-800-1280.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-10-1920-1200.dtsi" +//#include "rp-lcd-edp-13.3-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-mipi2lvds-10-1024-600.dtsi" +//#include "rp-lcd-mipi2Duallvds-1920-1080.dtsi" + + +/ { + + model = "nano-rk3399"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "cpu-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + status = "okay"; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + * + *If you want to set the uboot to high level, add the lower properties + * regulator_uboot_on + */ + + vdd_en { //vdd5v and vdd_io power en + gpio_num = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + host_en { //usb2.0 and 3.0 host 5v power en + gpio_num = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + //fan { //fan en + // gpio_num = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // regulator_uboot_on; + //}; + + vdd_3g { //vdd 3G power en + gpio_num = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + run_led { //LED for indicate system is runing + gpio_num = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + regulator_uboot_on; + }; + + }; + + rp_gpio { + status = "okay"; + compatible = "rp_gpio"; + base_value = <0>; //3288_5.1 = 0 3288_7.1.2 = 992 3288_ubuntu = 992 3399_7.1.2 = 1000 3399_ubuntu = 0 + + gpio1a1 { + gpio_num = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio1a2 { + gpio_num = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio1a3 { + gpio_num = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio1c7 { + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + }; + + rp-keys { + compatible = "rp-keys"; + name = "rp-keys"; + status = "disabled"; + + gpio1a1 { + gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + }; + gpio1a2 { + label = "gpio1a1_key"; + gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + wakeup; + debounce_interval = <10>; + press_type = <1>; + code = ; + }; + }; + + /* wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + /* pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>,<&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + // BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + // BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + // BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + // status = "okay"; + // }; + + +}; + + + +&spi1 { + status = "okay"; + spi_wk2xxx: spi_wk2xxx@0{ + status = "okay"; + compatible = "spi-wk2xxx"; + reg = <0>; + spi-max-frequency = <10000000>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio1 20 IRQ_TYPE_EDGE_FALLING>; + cs-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + +}; + + + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_3v0>; //nano usb +}; + +//used to bluetooth +//&uart0 { +// status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +//}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "disabled";//okay + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; + +&vcc_otg_vbus { + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; +}; + + + +&pinctrl { + usb{ + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + + diff --git a/rk3399/rd-box-h-rk3399.dts b/rk3399/rd-box-h-rk3399.dts new file mode 100755 index 0000000..d107554 --- /dev/null +++ b/rk3399/rd-box-h-rk3399.dts @@ -0,0 +1,612 @@ +#include "../rk3399-sapphire-excavator-linux.dts" + +//#include "" +#include "rp-usb-typea.dtsi" + + +/** lcd configuration */ +//#include "rp-lcd-hdmi.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +#include "rp-lcd-mipi-7-720-1280-jc070hd005-v1.dtsi" +//#include "rp-lcd-mipi-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-8-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v3.dtsi" +//#include "rp-rd-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + +/ { + + model = "rd-box-h-rk3399"; + compatible = "rpdzkj,rd-box-h-rk3399", "rockchip,rk3399"; + + + rp_power{ + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + status = "okay"; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + */ + + fan_en { //fan + gpio_num = <&gpio1 18 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { // usb hub reset pin + gpio_num = <&gpio1 24 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + breath-led { //run led + gpio_num = <&gpio4 24 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + vdd-en { //vdd_5v, vdd_io power en + gpio_num = <&gpio4 30 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd_3g { // 4g module power enable + gpio_num = <&gpio4 22 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host_en { //usb port power enable + gpio_num = <&gpio4 25 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_host_en { /* usb3.0 otg port host power en, + * refer to Schematic diagram, + * the default status is needed + * by host active, such as below + * GPIO_ACTIVE_LOW + */ + gpio_num = <&gpio4 26 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /** + * GPIO example, place you want to control as below + * + * gpioxxx { // the node name will display on /proc/rp_gpio, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio: 0 output, 1 input, 3 blink per 2S + * gpio_event = ; // optional property used to define gpio report event such as KEY_F14, only works in case of gpio_function = <1>; + * }; + */ + + gpio0a2 { + gpio_num = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1a2 { + gpio_num = <&gpio1 2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1c7 { + gpio_num = <&gpio1 23 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio0b3 { + gpio_num = <&gpio0 11 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d4 { + gpio_num = <&gpio3 28 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d5 { + gpio_num = <&gpio3 29 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d6 { + gpio_num = <&gpio3 30 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4c5 { + gpio_num = <&gpio4 21 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4d3 { + gpio_num = <&gpio4 27 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + }; + + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + //"Headphone", "Headphone Jack", //fix for headphone dapm name to match drivers + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + //"Headphone Jack", "HPOL", //fix for headphone dapm name to match drivers + //"Headphone Jack", "HPOR", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPOLP", + "Speaker", "SPOLN", + "Speaker", "SPORP", + "Speaker", "SPORN"; + pinctrl-names = "default"; + pinctrl-0 = <&rt5640_hp_det_gpio>; + simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + wireless-bluetooth { + /** redefine for fix real used gpio */ + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; // GPIO2_C3 + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; // GPIOx_xx + BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; // GPIO0_B1 + BT,wake_gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; // GPIO0_B4 + BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; // GPIO0_A4 + status = "okay"; + }; + + /** spi2can mcp2515 configuration */ + clkin_24m: osci_24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + //clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; //wifi +/* + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + +*/ + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcca-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + //regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vccio_sd>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&gmac { + /***** redefine delay value for rtl8211f */ + status = "okay"; + tx_delay = <0x21>; + rx_delay = <0x23>; + //max-speed = <100>; /* set eth maximal speed, default utomatically adapt */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; //nano usb +}; + +&rk808 { + rtc { + /****** disable rtc-rk808 for use hym8563 */ + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + io-channels = <&saradc 4>; + //hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + hp-det-adc-value = <500>; + status = "okay"; + }; + rtc-hym8563@51 { + status = "okay"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + }; + +#if 0 + rk628_hdmi2csi: rk628_hdmi2csi@50 { + reg = <0x50>; + compatible = "rockchip,rk628-hdmi2csi"; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; //gpio2_a7 + enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +#else + rk628_hdmi2csi_v4l2: rk628_hdmi2csi_v4l2@50 { + reg = <0x50>; + compatible = "rockchip,rk628-csi-v4l2"; + interrupt-parent = <&gpio2>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; //gpio2_a7 + enable-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK628-CSI"; + rockchip,camera-module-lens-name = "NC"; + + port { + hdmiin_out1: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +#endif +}; + +&hdmi_sound { + status = "disabled"; +}; + +&spi1 { + status = "okay"; + spi_wk2xxx: spi_wk2xxx@00{ + status = "okay"; + compatible = "spi-wk2xxx"; + reg = <0>; + spi-max-frequency = <10000000>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio0 8 IRQ_TYPE_EDGE_FALLING>; + cs-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + +}; + +/*spi2 to can :gpio_irq conflict ov13850f in i2c1 define*/ +&ov13850f{ + status = "disabled"; +}; +/** for rk628 v4l2 link */ +&ov13850b { + status = "disabled"; +}; +&mipi_in_ucam0 { + remote-endpoint = <&hdmiin_out1>; + data-lanes = <1 2 3 4>; +}; + +&spi2{ + status = "okay"; + can0: mcp251x@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clkin_24m>; + //interrupt-parent = <&gpio1>; + //interrupts = <30 GPIO_ACTIVE_LOW>; + //interrupts = ; + gpio_irq = <&gpio2 8 GPIO_ACTIVE_LOW>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + + +&pinctrl { + rt5640 { + rt5640_hp_det_gpio: rt5640_hp_det_gpio { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + /** redefine for sdo1, sdo2 and sdo3 to be gpio */ + i2s0 { + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>, + <3 31 RK_FUNC_1 &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3399/rd-box-lcd-edp-13.3-15.6-1920-1080.dtsi b/rk3399/rd-box-lcd-edp-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..c90e862 --- /dev/null +++ b/rk3399/rd-box-lcd-edp-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,293 @@ + + +/ { + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_sys>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <200>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 {//EDP compatible with 13.3 and 15.6 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>;//160 + hsync-len = <8>;//32 + hback-porch = <130>;//160 + vfront-porch = <3>;//3 + vsync-len = <5>;//5 + vback-porch = <23>;//23 + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; +// enable-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; +// secure-memory-region = <&secure_memory>; + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + //status = "okay"; + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&edp_in_vopl { + status = "disabled"; +}; +&edp_in_vopb { + status = "okay"; +}; + + +&hdmi_in_vopb { + status = "disabled"; +}; +&hdmi_in_vopl { + status = "okay"; +}; + + +&route_edp { + status = "okay"; + //status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + //status = "disabled"; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + // gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; + }; + +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rd-box-rk3399.dts b/rk3399/rd-box-rk3399.dts new file mode 100755 index 0000000..d07954d --- /dev/null +++ b/rk3399/rd-box-rk3399.dts @@ -0,0 +1,294 @@ +/dts-v1/; + +#include "rp-rk3399-board.dtsi" + +#include "rp-pmu-rk808.dtsi" +#include "rp-audio-rt5640.dtsi" + +#include "rp-usb2-host0.dtsi" +#include "rp-usb2-host1.dtsi" +#include "rp-usb3-otg-typeA.dtsi" +//#include "rp-usb3-otg-typeC.dtsi" +#include "rp-usb3_1-host.dtsi" + +#include "rp-gpio-key.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-gmac.dtsi" + +#include "rp-mipi-ov13850-camera.dtsi" +//#include "rp-hdmiin.dtsi" + +#include "rp-pcie.dtsi" + +#include "rp-wifi-sdio.dtsi" + +#include "rp-bt-uart0.dtsi" + +#include "rp-sdcard-mmc1.dtsi" + +/** lcd configuration */ +//#include "rp-lcd-hdmi.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +#include "rp-lcd-mipi-7-720-1280-jc070hd005-v1.dtsi" +//#include "rp-lcd-mipi-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-8-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v3.dtsi" +//#include "rd-box-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + +/ { + + model = "rd-box-rk3399"; + compatible = "rpdzkj,rd-box-rk3399", "rockchip,rk3399"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "cpu-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + status = "okay"; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + * + *If you want to set the uboot to high level, add the lower properties + * regulator_uboot_on + */ + + // fan_en { //fan + // gpio_num = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // regulator_uboot_on; + // }; + + hub_rst { // usb hub reset pin + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + breath-led { //run led + gpio_num = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + regulator_uboot_on; + }; + + vdd-en { //vdd_5v, vdd_io power en + gpio_num = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + vdd_3g { // 4g module power enable + gpio_num = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + host_en { //usb port power enable + gpio_num = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /** + * GPIO example, place you want to control as below + * + * gpioxxx { // the node name will display on /proc/rp_gpio, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio: 0 output, 1 input, 3 blink per 2S + * gpio_event = ; // optional property used to define gpio report event such as KEY_F14, only works in case of gpio_function = <1>; + * }; + */ + + gpio0a2 { + gpio_num = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1a2 { + gpio_num = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1c7 { + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio0b3 { + gpio_num = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d4 { + gpio_num = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d5 { + gpio_num = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d6 { + gpio_num = <&gpio3 RK_PD6 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4c5 { + gpio_num = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4d3 { + gpio_num = <&gpio4 RK_PD3 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + }; + +wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + //BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + //BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; + + +}; + + + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; //nano usb +}; + + +&rk808 { + rtc { + /****** disable rtc-rk808 for use hym8563 */ + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rtc-hym8563@51 { + status = "okay"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + }; +}; + +//used to bluetooth +//&uart0 { +// status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +//}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; + +/* +&spi_wk2xxx{ + status = "okay"; + reset-gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_EDGE_FALLING>;//modify + cs-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; +*/ + +&pinctrl { + wireless-bluetooth { + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3399/rd-rk3399.dts b/rk3399/rd-rk3399.dts new file mode 100755 index 0000000..a80016a --- /dev/null +++ b/rk3399/rd-rk3399.dts @@ -0,0 +1,239 @@ +/dts-v1/; + +#include "rp-rk3399-board.dtsi" + + +#include "rp-pmu-rk808.dtsi" +#include "rp-audio-rt5651.dtsi" + +#include "rp-gpio-key.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-gmac.dtsi" + +#include "rp-mipi-ov13850-camera.dtsi" +//#include "rp-hdmiin.dtsi" + +#include "rp-pcie.dtsi" + +#include "rp-usb2-host0.dtsi" +#include "rp-usb2-host1.dtsi" +#include "rp-usb3-otg-typeA.dtsi" +//#include "rp-usb3-otg-typeC.dtsi" +#include "rp-usb3_1-host.dtsi" + +#include "rp-wifi-sdio.dtsi" +#include "rp-bt-uart0.dtsi" + +#include "rp-sdcard-mmc1.dtsi" + +#include "rp-lcd-hdmi.dtsi" +//#include "rp-lcd-mipi-5-720-1280.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5.5-1080-1920.dtsi" +#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-800-1280.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280.dtsi" +//#include "rp-lcd-mipi-8-800-1280-new.dtsi" +//#include "rp-lcd-mipi-10-800-1280.dtsi" +//#include "rp-lcd-mipi-10-1920-1200.dtsi" +//#include "rp-lcd-edp-13.3-1920-1080.dtsi" + + + +/ { + + model = "rd-rk3399"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "cpu-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + compatible = "rp_power"; + + rp_not_deep_sleep = <1>; + status = "okay"; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + * + *If you want to set the uboot to high level, add the lower properties + * regulator_uboot_on + */ + + breathe-led { //usb hub reset pin + gpio_num = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + regulator_uboot_on; + }; + + power_en-gpio { //usb hub reset pin + gpio_num = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + 3v3_power_en { //usb hub reset pin + gpio_num = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + hub_rst { //usb hub reset pin + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + //fan_open { //fan + // gpio_num = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // regulator_uboot_on; + //}; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + base_value = <0>; + + gpio4c5 { + gpio_num = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio4d1 { + gpio_num = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio4d3 { + gpio_num = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + }; + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + //BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + //BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; +}; + + +&io_domains { + status = "okay"; + + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; //nano usb +}; + + +/*&spi_wk2xxx{ + status = "okay"; + reset-gpio = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_EDGE_FALLING>;//modify + cs-gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +};*/ + +&spi1 { + status = "okay"; + spi_wk2xxx: spi_wk2xxx@0{ + status = "okay"; + compatible = "spi-wk2xxx"; + reg = <0>; + spi-max-frequency = <10000000>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio0 8 IRQ_TYPE_EDGE_FALLING>; + cs-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + + +//used to bluetooth +&uart0 { + status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; +&pinctrl { + wireless-bluetooth { + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3399/rd3399-enable-i2s1-gpio.dtsi b/rk3399/rd3399-enable-i2s1-gpio.dtsi new file mode 100755 index 0000000..2b7d7b2 --- /dev/null +++ b/rk3399/rd3399-enable-i2s1-gpio.dtsi @@ -0,0 +1,35 @@ + + +&rp_gpio { + + gpio10 { + gpio_num = <&gpio4 3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio11 { + gpio_num = <&gpio4 4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio12 { + gpio_num = <&gpio4 5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio13 { + gpio_num = <&gpio4 6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + + gpio14 { + gpio_num = <&gpio4 7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; +}; + + +&i2s1 { + status = "okay"; +}; + diff --git a/rk3399/rk3399-linux.dtsi b/rk3399/rk3399-linux.dtsi new file mode 100755 index 0000000..cb6ba95 --- /dev/null +++ b/rk3399/rk3399-linux.dtsi @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,linux", "rockchip,rk3399"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops_mem: region@110000 { + reg = <0x0 0x110000 0x0 0xf0000>; + reg-names = "ramoops_mem"; + }; + }; + + ramoops: ramoops { + compatible = "ramoops"; + record-size = <0x0 0x40000>; + console-size = <0x0 0x80000>; + ftrace-size = <0x0 0x00000>; + pmsg-size = <0x0 0x00000>; + memory-region = <&ramoops_mem>; + }; + + cif_isp0: cif_isp@ff910000 { + compatible = "rockchip,rk3399-cif-isp"; + rockchip,grf = <&grf>; + reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>; + reg-names = "register", "dsihost-register"; + clocks = + <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>, + <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>, + <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>, + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_MIPIDPHY_REF>; + clock-names = + "aclk_isp0_noc", "aclk_isp0_wrapper", + "hclk_isp0_noc", "hclk_isp0_wrapper", + "clk_isp0", "pclk_dphyrx", + "clk_cif_out", "clk_cif_pll", + "pclk_dphy_ref"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + power-domains = <&power RK3399_PD_ISP0>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + + cif_isp1: cif_isp@ff920000 { + compatible = "rockchip,rk3399-cif-isp"; + rockchip,grf = <&grf>; + reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>; + reg-names = "register", "dsihost-register"; + clocks = + <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>, + <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>, + <&cru SCLK_ISP1>, <&cru PCLK_ISP1_WRAPPER>, + <&cru SCLK_DPHY_TX1RX1_CFG>, + <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>, + <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>, + <&cru SCLK_MIPIDPHY_REF>; + clock-names = + "aclk_isp1_noc", "aclk_isp1_wrapper", + "hclk_isp1_noc", "hclk_isp1_wrapper", + "clk_isp1", "pclkin_isp1", + "pclk_dphytxrx", + "pclk_mipi_dsi","mipi_dphy_cfg", + "clk_cif_out", "clk_cif_pll", + "pclk_dphy_ref"; + interrupts = ; + interrupt-names = "cif_isp10_irq"; + power-domains = <&power RK3399_PD_ISP1>; + rockchip,isp,iommu-enable = <1>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + + rga: rga@ff680000 { + compatible = "rockchip,rga2"; + dev_mode = <1>; + reg = <0x0 0xff680000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3399_PD_RGA>; + dma-coherent; + status = "okay"; + }; +}; + + +/* HACK: keep MALI version on linux */ +&gpu_power_model { + // for DDK r14. + voltage = <900>; + frequency = <500>; + static-power = <300>; + dynamic-power = <396>; +}; + +&pvtm { + status = "okay"; +}; + +&pinctrl { + isp { + cif_clkout: cif-clkout { + rockchip,pins = + /* cif_clkout */ + <2 11 RK_FUNC_3 &pcfg_pull_none>; + }; + + isp_dvp_d0d7: isp-dvp-d0d7 { + rockchip,pins = + <4 27 RK_FUNC_GPIO &pcfg_pull_none>, + /* cif_clkout */ + <2 11 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data0 */ + <2 0 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data1 */ + <2 1 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data2 */ + <2 2 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data3 */ + <2 3 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data4 */ + <2 4 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data5 */ + <2 5 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data6 */ + <2 6 RK_FUNC_3 &pcfg_pull_none>, + /* cif_data7 */ + <2 7 RK_FUNC_3 &pcfg_pull_none>, + /* cif_sync */ + <2 8 RK_FUNC_3 &pcfg_pull_none>, + /* cif_href */ + <2 9 RK_FUNC_3 &pcfg_pull_none>, + /* cif_clkin */ + <2 10 RK_FUNC_3 &pcfg_pull_none>; + }; + + isp_shutter: isp-shutter { + rockchip,pins = + /* SHUTTEREN */ + <1 1 RK_FUNC_1 &pcfg_pull_none>, + /* SHUTTERTRIG */ + <1 0 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_flash_trigger: isp-flash-trigger { + /* ISP_FLASHTRIGOU */ + rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>; + }; + + isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio { + /* ISP_FLASHTRIGOU */ + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + cam_pins { + cam0_default_pins: cam0-default-pins { + rockchip,pins = + <4 27 RK_FUNC_GPIO &pcfg_pull_none>, + <2 11 RK_FUNC_3 &pcfg_pull_none>; + }; + cam0_sleep_pins: cam0-sleep-pins { + rockchip,pins = + <4 27 RK_FUNC_3 &pcfg_pull_none>, + <2 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-adc-key.dtsi b/rk3399/rp-adc-key.dtsi new file mode 100755 index 0000000..17b2888 --- /dev/null +++ b/rk3399/rp-adc-key.dtsi @@ -0,0 +1,53 @@ +/ { + + + vccadc_ref: vccadc-ref { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + adc_keys:adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + button-up { + label = "Volume Up"; + linux,code = ; + press-threshold-microvolt = <20000>; + }; + + button-down { + label = "Volume Down"; + linux,code = ; + press-threshold-microvolt = <300000>; + }; + + back { + label = "Back"; + linux,code = ; + press-threshold-microvolt = <985000>; + }; + + menu { + label = "Menu"; + linux,code = ; + press-threshold-microvolt = <1314000>; + }; + }; + +}; + + + +&saradc { + status = "okay"; + vref-supply = <&vcca1v8_s3>; + }; diff --git a/rk3399/rp-audio-rt5640-rp-box.dtsi b/rk3399/rp-audio-rt5640-rp-box.dtsi new file mode 100755 index 0000000..aeaa448 --- /dev/null +++ b/rk3399/rp-audio-rt5640-rp-box.dtsi @@ -0,0 +1,85 @@ + +/ { + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + //"Headphone", "Headphone Jack", //fix for headphone dapm name to match drivers + "Headphone", "Headphones", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + //"Headphone Jack", "HPOL", //fix for headphone dapm name to match drivers + //"Headphone Jack", "HPOR", + "Headphones", "HPOL", + "Headphones", "HPOR", + "Speaker", "SPOLP", + "Speaker", "SPOLN", + "Speaker", "SPORP", + "Speaker", "SPORN"; + pinctrl-names = "default"; + pinctrl-0 = <&rt5640_hp_det_gpio>; + simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; +}; + + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + io-channels = <&saradc 4>; + //hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + hp-det-adc-value = <500>; + status = "okay"; + }; +}; + +&i2s0 { + status = "okay"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&pinctrl { + rt5640 { + rt5640_hp_det_gpio: rt5640_hp_det_gpio { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + /** redefine for sdo1, sdo2 and sdo3 to be gpio */ + i2s0 { + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>, + <3 31 RK_FUNC_1 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-audio-rt5640.dtsi b/rk3399/rp-audio-rt5640.dtsi new file mode 100755 index 0000000..e426513 --- /dev/null +++ b/rk3399/rp-audio-rt5640.dtsi @@ -0,0 +1,69 @@ + +/ { + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack", + "Speaker", "Speaker"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR", + "Speaker", "SPOLP", + "Speaker", "SPOLN", + "Speaker", "SPORP", + "Speaker", "SPORN"; + pinctrl-names = "default"; + pinctrl-0 = <&rt5640_hp_det_gpio>; + simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + io-channels = <&saradc 4>; + //hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + hp-det-adc-value = <500>; + status = "okay"; + }; +}; + + +&i2s0 { + status = "okay"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&pinctrl { + rt5640 { + rt5640_hp_det_gpio: rt5640_hp_det_gpio { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-audio-rt5651-king.dtsi b/rk3399/rp-audio-rt5651-king.dtsi new file mode 100755 index 0000000..33cbdd1 --- /dev/null +++ b/rk3399/rp-audio-rt5651-king.dtsi @@ -0,0 +1,50 @@ + +/ { + rt5651-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "realtek,rt5651-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&rt5651>; + }; + }; +}; + + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5651: rt5651@1a { + #sound-dai-cells = <0>; + compatible = "realtek,rt5651"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + }; +}; + + +&i2s0 { + status = "okay"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; \ No newline at end of file diff --git a/rk3399/rp-audio-rt5651.dtsi b/rk3399/rp-audio-rt5651.dtsi new file mode 100755 index 0000000..86084a2 --- /dev/null +++ b/rk3399/rp-audio-rt5651.dtsi @@ -0,0 +1,63 @@ + +/ { + rt5651-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5651-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "micbias1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + pinctrl-names = "default"; + pinctrl-0 = <&rt5651_hp_det_gpio>; + simple-audio-card,hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + simple-audio-card,codec { + sound-dai = <&rt5651>; + }; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <300>; + i2c-scl-falling-time-ns = <15>; + + rt5651: rt5651@1a { + #sound-dai-cells = <0>; + compatible = "realtek,rt5651"; + reg = <0x1a>; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + io-channels = <&saradc 4>; + spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; +// hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; + hp-det-adc-value = <500>; + status = "okay"; + }; + +}; + +&i2s0 { + status = "okay"; + rockchip,playback-channels = <8>; + rockchip,capture-channels = <8>; + #sound-dai-cells = <0>; +}; + +&pinctrl { + rt5651 { + rt5651_hp_det_gpio: rt5651_hp_det_gpio { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-box-lcd-edp-13.3-15.6-1920-1080.dtsi b/rk3399/rp-box-lcd-edp-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..6e3db09 --- /dev/null +++ b/rk3399/rp-box-lcd-edp-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,293 @@ + + +/ { + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_sys>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <200>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 {//EDP compatible with 13.3 and 15.6 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>;//160 + hsync-len = <8>;//32 + hback-porch = <130>;//160 + vfront-porch = <3>;//3 + vsync-len = <5>;//5 + vback-porch = <23>;//23 + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; +// enable-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; +// secure-memory-region = <&secure_memory>; + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + //status = "okay"; + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&edp_in_vopl { + status = "disabled"; +}; +&edp_in_vopb { + status = "okay"; +}; + + +&hdmi_in_vopb { + status = "disabled"; +}; +&hdmi_in_vopl { + status = "okay"; +}; + + +&route_edp { + status = "okay"; + //status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + //status = "disabled"; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + // gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; + }; + +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-box-rk3399.dts b/rk3399/rp-box-rk3399.dts new file mode 100755 index 0000000..9d537ca --- /dev/null +++ b/rk3399/rp-box-rk3399.dts @@ -0,0 +1,273 @@ +/dts-v1/; + +#include "rp-rk3399-board.dtsi" + +#include "rp-pmu-rk808.dtsi" +#include "rp-audio-rt5640.dtsi" + +#include "rp-usb2-host0.dtsi" +#include "rp-usb2-host1.dtsi" +#include "rp-usb3-otg-typeA.dtsi" +//#include "rp-usb3-otg-typeC.dtsi" +#include "rp-usb3_1-host.dtsi" + +#include "rp-gpio-key.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-gmac.dtsi" +#include "rp-mipi-ov13850-camera.dtsi" +//#include "rp-hdmiin.dtsi" + +#include "rp-wifi-sdio.dtsi" +#include "rp-bt-uart0.dtsi" + +#include "rp-sdcard-mmc1.dtsi" + +#include "rp-lcd-hdmi.dtsi" +#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-7-720-1280-jc070hd005-v1.dtsi" +//#include "rp-lcd-mipi-10-1200-1920-jc101fh107-v1.dtsi" +//#include "rp-lcd-mipi2lvds-gm8775-singlelvds-10-1024-600.dtsi" +//#include "rp-lcd-mipi2lvds-gm8775-duallvds-1920-1080.dtsi" +//#include "rp-box-lcd-edp-13.3-15.6-1920-1080.dtsi" + +/ { + model = "rp-box-rk3399"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "cpu-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + //pinctrl-0 = <&rp_power_gpio>; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + * + *If you want to set the uboot to high level, add the lower properties + * regulator_uboot_on + */ + vdd_en { //vdd5v and vdd_io power en + gpio_num = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + hub_rst { //usb hub reset pin + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + host_en { //usb2.0 and 3.0 host 5v power en + gpio_num = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + //fan { //fan en + // gpio_num = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //regulator_uboot_on; + //}; + + vdd_3g { //vdd 3G power en + gpio_num = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + run_led { //LED for indicate system is runing + gpio_num = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + regulator_uboot_on; + + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + gpio3c0 { + gpio_num = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + /* gpio_event = ; */ /** define this property if you want to report + * event such as KEY_F14, but this only works + * in case of gpio_function = <1>; + */ + }; + + gpio0a6 { //ir_rx + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1b1 { + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1b2 { + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4c5 { + gpio_num = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4d5 { + gpio_num = <&gpio4 RK_PD5 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1c7 { + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio0b3 { + gpio_num = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio1a2 { + gpio_num = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + }; +}; + +&spi2 { + status = "okay"; + max-freq = <50000000>; + spi_test:spi_test@00 { + status = "okay"; + compatible = "rockchip,spi_test_bus2_cs0"; + id = <2>; + reg = <0>; + spi-max-frequency = <24000000>; + spi-cpha; + spi-cpol; + }; +}; + + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; //king usb +}; + +&dsi { + pinctrl-names="default"; + pinctrl-0=<&pwr_en>; +}; + +&i2s0 { + status = "okay"; +}; + +&rk808 { + rtc { + /****** disabled rtc-rk808 for use hym8563 */ + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "haoyu,hym8563"; + reg = <0x51>; + }; +}; + +&gmac { + tx_delay = <0x25>; + rx_delay = <0x25>; +}; + +&uart0 { + status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + + + diff --git a/rk3399/rp-bt-uart0.dtsi b/rk3399/rp-bt-uart0.dtsi new file mode 100755 index 0000000..be89071 --- /dev/null +++ b/rk3399/rp-bt-uart0.dtsi @@ -0,0 +1,45 @@ +/ { + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ + BT,reset_gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ + BT,wake_host_irq = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ + status = "okay"; + }; + +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&pinctrl { + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = + <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = + <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk3399/rp-gmac.dtsi b/rk3399/rp-gmac.dtsi new file mode 100755 index 0000000..f334b56 --- /dev/null +++ b/rk3399/rp-gmac.dtsi @@ -0,0 +1,27 @@ + + +/ { + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + clock_in_out = "input"; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; \ No newline at end of file diff --git a/rk3399/rp-gpio-key.dtsi b/rk3399/rp-gpio-key.dtsi new file mode 100755 index 0000000..5dc08bc --- /dev/null +++ b/rk3399/rp-gpio-key.dtsi @@ -0,0 +1,34 @@ +/ { + + gpio_keys:gpio-keys { + status = "okay"; + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + wakeup-source; + }; + }; + + +}; + + +&pinctrl { + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-hdmiin.dtsi b/rk3399/rp-hdmiin.dtsi new file mode 100755 index 0000000..20192de --- /dev/null +++ b/rk3399/rp-hdmiin.dtsi @@ -0,0 +1,103 @@ + +/ { + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <27000000>; + clock-output-names = "CLK_CAMERA_27MHZ"; + #clock-cells = <0>; + }; + + +}; + + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + + +&i2c1 { + status = "okay"; + + tc358749x: tc358749x@f { + status = "disabled"; + compatible = "toshiba,tc358749"; + reg = <0xf>; + clocks = <&ext_cam_clk>; + clock-names = "refclk"; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmiin_gpios>; + port { + hdmiin_out0: endpoint { + // Unlinked mipi dphy rx0 + // remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + clock-noncontinuous; + link-frequencies = + /bits/ 64 <297000000>; + }; + }; + }; +}; +&pinctrl { + hdmiin { + hdmiin_gpios: hdmiin-gpios { + rockchip,pins = + <2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>, + <2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>, + <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-lcd-edp-13.3-15.6-1920-1080.dtsi b/rk3399/rp-lcd-edp-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..ebbffe2 --- /dev/null +++ b/rk3399/rp-lcd-edp-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,293 @@ + + +/ { + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_sys>; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + //reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <200>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 {//EDP compatible with 13.3 and 15.6 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < +// 0 1 2 3 4 5 6 7 +// 8 9 10 11 12 13 14 15 +// 16 17 18 19 20 21 22 23 +// 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; +// enable-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; +// secure-memory-region = <&secure_memory>; + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + //status = "okay"; + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&edp_in_vopl { + status = "disabled"; +}; +&edp_in_vopb { + status = "okay"; +}; + + +&hdmi_in_vopb { + status = "disabled"; +}; +&hdmi_in_vopl { + status = "okay"; +}; + + +&route_edp { + status = "okay"; + connect = <&vopb_out_edp>; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + // gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; + }; + +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-edp-13.3-1920-1080.dtsi b/rk3399/rp-lcd-edp-13.3-1920-1080.dtsi new file mode 100755 index 0000000..d1c0da4 --- /dev/null +++ b/rk3399/rp-lcd-edp-13.3-1920-1080.dtsi @@ -0,0 +1,276 @@ + +/ { + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_sys>; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + //reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <200>; + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 {//EDP 13.3 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 {// EDP 15.6 LP156WF6 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + brightness-levels = < + + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + + + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&edp_in_vopl { + status = "disabled"; +}; +&edp_in_vopb { + status = "okay"; +}; + + +&hdmi_in_vopb { + status = "disabled"; +}; +&hdmi_in_vopl { + status = "okay"; +}; + + +&route_edp { + status = "okay"; + connect = <&vopb_out_edp>; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + goodix,cfg-group0 = [ + + 64 80 07 38 04 0A 3D 00 01 C8 28 0F + 55 37 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 90 30 AA 25 27 0F 0A 00 00 + 00 5A 03 11 00 00 00 00 00 00 00 00 + 00 25 00 19 37 94 D5 02 08 14 00 04 + 9B 1B 00 8E 1F 00 80 25 00 76 2B 00 + 6E 32 00 6E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 10 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + 00 00 00 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 19 1B 1C 1E 1F 20 21 22 23 24 + 25 26 27 28 29 2A 00 00 00 00 00 00 + 00 00 00 00 B7 01]; + }; + +}; + diff --git a/rk3399/rp-lcd-hdmi.dtsi b/rk3399/rp-lcd-hdmi.dtsi new file mode 100755 index 0000000..d7e883e --- /dev/null +++ b/rk3399/rp-lcd-hdmi.dtsi @@ -0,0 +1,79 @@ +&hdmi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_i2c_xfer>; + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2s2 { + status = "okay"; +}; + + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; +}; + +}; + + + + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + + +&hdmi_in_vopl { + status = "disabled"; +}; + +&hdmi_in_vopb { + status = "okay"; +}; diff --git a/rk3399/rp-lcd-mipi-10-1200-1920-jc101fh107-v1.dtsi b/rk3399/rp-lcd-mipi-10-1200-1920-jc101fh107-v1.dtsi new file mode 100755 index 0000000..8cc69fd --- /dev/null +++ b/rk3399/rp-lcd-mipi-10-1200-1920-jc101fh107-v1.dtsi @@ -0,0 +1,328 @@ + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "240";//320 + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + //not_status_bar = "true"; + default_launcher = "true"; + //default_launcher = "false"; + has_root = "true"; //true + //has_root = "false"; //false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + //usb_camera_only_front = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS6"; /* + * UART*, please check board + * whether have this uart, + * otherwish system may not run + */ + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; + }; + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; +// rockchip,lane-rate = <800>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + // MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; /** 7inch 720x1280 must this mode */ + dsi,format = ; + // bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <100>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + panel-init-sequence = [ + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + + goodix,cfg-group0 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01]; + }; + +}; + + diff --git a/rk3399/rp-lcd-mipi-10-1920-1200.dtsi b/rk3399/rp-lcd-mipi-10-1920-1200.dtsi new file mode 100755 index 0000000..a4e6124 --- /dev/null +++ b/rk3399/rp-lcd-mipi-10-1920-1200.dtsi @@ -0,0 +1,328 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1200>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + +//new + goodix,cfg-group0 = [ + 55 80 07 B0 04 0A 3D 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 8E 2F 99 17 15 31 + 0D 00 00 02 9B 03 1D 00 00 00 00 + 00 00 00 00 00 00 00 1E 78 94 C5 + 02 08 00 00 00 5B 22 00 4C 2D 00 + 41 3C 00 38 4F 00 32 69 00 32 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 0C + 0D 0E 0F 10 11 14 15 16 17 FF FF + 00 00 00 00 00 00 00 00 00 00 00 + 02 04 06 07 08 0A 0C 0D 0F 10 11 + 12 13 19 1B 1C 1E 1F 20 21 22 23 + 24 25 26 27 28 29 FF FF FF 00 00 + 00 00 00 00 00 00 00 00 6B 01]; + + }; + +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + //rockchip,lane-rate = <1000>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + display-timings { + native-mode = <&timing1>; + timing0: timing0 { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <60>; + hfront-porch = <16>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + de-active = <0>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + }; + timing1: timing1{ + clock-frequency = <140000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <60>; + hfront-porch = <16>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + de-active = <0>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&route_dsi { + status = "okay"; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-10-800-1280-v2.dtsi b/rk3399/rp-lcd-mipi-10-800-1280-v2.dtsi new file mode 100755 index 0000000..e01ae80 --- /dev/null +++ b/rk3399/rp-lcd-mipi-10-800-1280-v2.dtsi @@ -0,0 +1,598 @@ + + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + //bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + //=========_1===========// + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 53 + 39 00 02 04 13 + 39 00 02 05 00 + 39 00 02 06 04 + 39 00 02 07 00 + 39 00 02 08 00 + 39 00 02 09 22 + 39 00 02 0a 22 + 39 00 02 0b 00 + 39 00 02 0c 01 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 23 + 39 00 02 10 23 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 44 + 39 00 02 1f 80 + 39 00 02 20 02 + 39 00 02 21 03 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 03 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 04 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 3C + 39 00 02 39 00 + 39 00 02 3a 40 + 39 00 02 3b 40 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + + + + //=========_2===========// + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + //=========_3===========// + 39 00 02 5e 11 + + 39 00 02 5f 01 + 39 00 02 60 00 + 39 00 02 61 15 + 39 00 02 62 14 + 39 00 02 63 0C + 39 00 02 64 0D + 39 00 02 65 0E + 39 00 02 66 0F + 39 00 02 67 06 + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 08 + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 02 + 39 00 02 72 02 + 39 00 02 73 02 + 39 00 02 74 02 + + 39 00 02 75 01 + 39 00 02 76 00 + 39 00 02 77 15 + 39 00 02 78 14 + 39 00 02 79 0C + 39 00 02 7a 0D + 39 00 02 7b 0E + 39 00 02 7c 0F + 39 00 02 7D 08 + 39 00 02 7E 02 + 39 00 02 7F 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 06 + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 02 + 39 00 02 88 02 + 39 00 02 89 02 + 39 00 02 8A 02 + + + //CMD_Page + 39 00 04 FF 98 81 04 + 39 00 02 6C 15 + 39 00 02 6E 3B + 39 00 02 6F 73 + 39 00 02 3A 24 + 39 00 02 8D 14 + 39 00 02 87 BA + 39 00 02 26 76 + 39 00 02 B2 D1 + 39 00 02 B5 27 + 39 00 02 31 75 + 39 00 02 30 03 + 39 00 02 3B 98 + 39 00 02 35 1f + 39 00 02 33 14 + 39 00 02 7A 0F + 39 00 02 38 02 + 39 00 02 39 00 + + + //CMD_Page + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 0A + 39 00 02 35 07 + 39 00 02 52 00 + 39 00 02 53 5A + 39 00 02 54 00 + 39 00 02 55 59 + 39 00 02 50 83 + 39 00 02 51 80 + 39 00 02 60 20 + 39 00 02 61 01 + 39 00 02 62 07 + 39 00 02 63 00 + + //GammaP + 39 00 02 A0 08 + 39 00 02 A1 0F + 39 00 02 A2 15 + 39 00 02 A3 0E + 39 00 02 A4 0D + 39 00 02 A5 1B + 39 00 02 A6 0F + 39 00 02 A7 14 + 39 00 02 A8 33 + 39 00 02 A9 17 + 39 00 02 AA 23 + 39 00 02 AB 3F + 39 00 02 AC 22 + 39 00 02 AD 24 + 39 00 02 AE 59 + 39 00 02 AF 2B + 39 00 02 B0 2E + 39 00 02 B1 4C + 39 00 02 B2 5C + 39 00 02 B3 33 + + //GammaN + 39 00 02 C0 08 + 39 00 02 C1 0F + 39 00 02 C2 15 + 39 00 02 C3 0E + 39 00 02 C4 0D + 39 00 02 C5 1B + 39 00 02 C6 0F + 39 00 02 C7 14 + 39 00 02 C8 33 + 39 00 02 C9 17 + 39 00 02 CA 23 + 39 00 02 CB 3F + 39 00 02 CC 22 + 39 00 02 CD 24 + 39 00 02 CE 59 + 39 00 02 CF 2B + 39 00 02 D0 2E + 39 00 02 D1 4C + 39 00 02 D2 5C + 39 00 02 D3 33 + + + //CMD_Page + 39 00 04 FF 98 81 00 + 05 78 01 11 //sleep out + + 05 00 01 29 //display on + 05 00 01 35 //TE on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + +#if 0 + /* old touchscreen sensor_id0, reserve for some customer maybe using */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +#endif + /** ic 9271_1020 sensor_id0, v3 add 20211104 */ + goodix,cfg-group0 = [ + 59 20 03 00 05 0A 05 00 01 08 + 28 05 5A 46 03 05 00 00 00 00 + 00 00 00 17 19 1B 14 8E 2E 99 + 37 39 D3 07 00 00 01 81 02 2D + 00 00 00 00 00 00 00 00 00 00 + 00 28 78 94 C5 02 07 00 00 04 + 9A 2C 00 80 37 00 6B 45 00 5C + 56 00 50 6C 00 50 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 17 16 15 14 11 10 0F 0E + 0D 0C 09 08 07 06 05 04 01 00 + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0D 0F 10 11 12 28 27 26 25 24 + 23 22 21 20 1F 1E 1C 1B 19 13 + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 BF 01 + ]; + + + /* touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; + }; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-10-800-1280-v3.dtsi b/rk3399/rp-lcd-mipi-10-800-1280-v3.dtsi new file mode 100755 index 0000000..030c1c7 --- /dev/null +++ b/rk3399/rp-lcd-mipi-10-800-1280-v3.dtsi @@ -0,0 +1,318 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + //rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + //bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; + }; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-lcd-mipi-10-800-1280.dtsi b/rk3399/rp-lcd-mipi-10-800-1280.dtsi new file mode 100755 index 0000000..9dd1972 --- /dev/null +++ b/rk3399/rp-lcd-mipi-10-800-1280.dtsi @@ -0,0 +1,583 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; +/* old touchscreen sensor_id0 */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +/* new touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; + + }; +}; + +&display_subsystem { + status = "okay"; + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + prepare-delay-ms = <100>; + reset-delay-ms = <10>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 E0 04 + 15 00 02 2D 03 + 15 00 02 E0 00 + 15 00 02 80 03 + 15 00 02 70 02 + 15 00 02 71 23 + 15 00 02 72 06 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 66 + 15 00 02 03 00 + 15 00 02 04 6D + 15 00 02 17 00 + 15 00 02 18 BF + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B BF + 15 00 02 1C 00 + 15 00 02 1F 3E + 15 00 02 20 28 + 15 00 02 21 28 + 15 00 02 22 0E + 15 00 02 37 09 + 15 00 02 38 04 + 15 00 02 39 08 + 15 00 02 3A 12 + 15 00 02 3C 78 + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F 7F + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 55 0F + 15 00 02 56 01 + 15 00 02 57 69 + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 29 + 15 00 02 5B 15 + 15 00 02 5D 7C + 15 00 02 5E 65 + 15 00 02 5F 55 + 15 00 02 60 49 + 15 00 02 61 44 + 15 00 02 62 35 + 15 00 02 63 3A + 15 00 02 64 23 + 15 00 02 65 3D + 15 00 02 66 3C + 15 00 02 67 3D + 15 00 02 68 5D + 15 00 02 69 4D + 15 00 02 6A 56 + 15 00 02 6B 48 + 15 00 02 6C 45 + 15 00 02 6D 38 + 15 00 02 6E 25 + 15 00 02 6F 00 + 15 00 02 70 7C + 15 00 02 71 65 + 15 00 02 72 55 + 15 00 02 73 49 + 15 00 02 74 44 + 15 00 02 75 35 + 15 00 02 76 3A + 15 00 02 77 23 + 15 00 02 78 3D + 15 00 02 79 3C + 15 00 02 7A 3D + 15 00 02 7B 5D + 15 00 02 7C 4D + 15 00 02 7D 56 + 15 00 02 7E 48 + 15 00 02 7F 45 + 15 00 02 80 38 + 15 00 02 81 25 + 15 00 02 82 00 + 15 00 02 E0 02 + 15 00 02 00 1E + 15 00 02 01 1E + 15 00 02 02 41 + 15 00 02 03 41 + 15 00 02 04 43 + 15 00 02 05 43 + 15 00 02 06 1F + 15 00 02 07 1F + 15 00 02 08 1F + 15 00 02 09 1F + 15 00 02 0A 1E + 15 00 02 0B 1E + 15 00 02 0C 1F + 15 00 02 0D 47 + 15 00 02 0E 47 + 15 00 02 0F 45 + 15 00 02 10 45 + 15 00 02 11 4B + 15 00 02 12 4B + 15 00 02 13 49 + 15 00 02 14 49 + 15 00 02 15 1F + 15 00 02 16 1E + 15 00 02 17 1E + 15 00 02 18 40 + 15 00 02 19 40 + 15 00 02 1A 42 + 15 00 02 1B 42 + 15 00 02 1C 1F + 15 00 02 1D 1F + 15 00 02 1E 1F + 15 00 02 1F 1f + 15 00 02 20 1E + 15 00 02 21 1E + 15 00 02 22 1f + 15 00 02 23 46 + 15 00 02 24 46 + 15 00 02 25 44 + 15 00 02 26 44 + 15 00 02 27 4A + 15 00 02 28 4A + 15 00 02 29 48 + 15 00 02 2A 48 + 15 00 02 2B 1f + 15 00 02 2C 1F + 15 00 02 2D 1F + 15 00 02 2E 42 + 15 00 02 2F 42 + 15 00 02 30 40 + 15 00 02 31 40 + 15 00 02 32 1E + 15 00 02 33 1E + 15 00 02 34 1F + 15 00 02 35 1F + 15 00 02 36 1E + 15 00 02 37 1E + 15 00 02 38 1F + 15 00 02 39 48 + 15 00 02 3A 48 + 15 00 02 3B 4A + 15 00 02 3C 4A + 15 00 02 3D 44 + 15 00 02 3E 44 + 15 00 02 3F 46 + 15 00 02 40 46 + 15 00 02 41 1F + 15 00 02 42 1F + 15 00 02 43 1F + 15 00 02 44 43 + 15 00 02 45 43 + 15 00 02 46 41 + 15 00 02 47 41 + 15 00 02 48 1E + 15 00 02 49 1E + 15 00 02 4A 1E + 15 00 02 4B 1F + 15 00 02 4C 1E + 15 00 02 4D 1E + 15 00 02 4E 1F + 15 00 02 4F 49 + 15 00 02 50 49 + 15 00 02 51 4B + 15 00 02 52 4B + 15 00 02 53 45 + 15 00 02 54 45 + 15 00 02 55 47 + 15 00 02 56 47 + 15 00 02 57 1F + 15 00 02 58 10 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 30 + 15 00 02 5C 02 + 15 00 02 5D 40 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 30 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 6A + 15 00 02 64 6A + 15 00 02 65 05 + 15 00 02 66 12 + 15 00 02 67 74 + 15 00 02 68 04 + 15 00 02 69 6A + 15 00 02 6A 6A + 15 00 02 6B 08 + 15 00 02 6C 00 + 15 00 02 6D 06 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 07 + 15 00 02 76 00 + 15 00 02 77 5D + 15 00 02 78 17 + 15 00 02 79 1F + 15 00 02 7A 00 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 04 + 15 00 02 2B 2B + 15 00 02 2E 44 + 15 00 02 E0 01 + 15 00 02 0E 01 + 15 00 02 E0 03 + 15 00 02 98 2F + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 02 + + 05 78 01 11 + 05 05 01 29 + 15 0a 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <18>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<6 5 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi b/rk3399/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi new file mode 100755 index 0000000..9103858 --- /dev/null +++ b/rk3399/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi @@ -0,0 +1,341 @@ +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "270"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "190"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + /* + * UART*, please check board + * whether have this uart, + * otherwish system may not run + */ + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "true"; + home_apk = "null"; + + status = "okay"; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + // status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; +// rockchip,lane-rate = <410>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + // MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; /** 7inch 720x1280 must this mode */ + dsi,format = ; + // bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <100>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + panel-init-sequence = [ + //test + 05 78 01 01 + 39 00 04 B9 F1 12 83 + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + 39 00 02 B8 26 + 39 00 04 BF 02 10 00 + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + 39 00 02 BC 46 + 39 00 02 CC 0B + 39 00 02 B4 80 + 39 00 04 B2 C8 12 A0 + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + 39 00 03 B5 09 09 + 39 00 03 B6 B7 B7 + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + 05 ff 01 11 ////Sleep Out + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_FALLING>; + + goodix,cfg-group0 = [ + 4D D0 02 00 05 05 35 00 01 08 32 + 08 5A 3C 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 29 0A 55 57 B5 + 06 00 00 00 41 22 10 00 01 00 0F + 00 2A 00 00 19 50 32 3C 78 94 D5 + 02 08 00 00 04 A2 40 00 8F 4A 00 + 80 55 00 73 61 00 67 70 00 67 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 + 06 08 0A 0F 10 12 FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF 8D 01 + ]; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-lcd-mipi-5-720-1280-v2.dtsi b/rk3399/rp-lcd-mipi-5-720-1280-v2.dtsi new file mode 100755 index 0000000..14e7ca7 --- /dev/null +++ b/rk3399/rp-lcd-mipi-5-720-1280-v2.dtsi @@ -0,0 +1,339 @@ +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "270"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "190"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + /* + * UART*, please check board + * whether have this uart, + * otherwish system may not run + */ + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "true"; + home_apk = "null"; + + status = "okay"; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + // status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; +// rockchip,lane-rate = <410>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + // MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; /** 7inch 720x1280 must this mode */ + dsi,format = ; + // bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <100>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + panel-init-sequence = [ + //test + 05 78 01 01 + 39 00 04 B9 F1 12 83 + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + 39 00 02 B8 26 + 39 00 04 BF 02 10 00 + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + 39 00 02 BC 46 + 39 00 02 CC 0B + 39 00 02 B4 80 + 39 00 04 B2 C8 12 A0 + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + 39 00 03 B5 09 09 + 39 00 03 B6 B7 B7 + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + 05 ff 01 11 ////Sleep Out + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_FALLING>; + + goodix,cfg-group0 = [ + 46 D0 02 00 05 05 35 01 01 08 1E 0F 5A 3C + 03 05 00 00 00 00 11 11 00 19 1B 1E 14 89 + 29 0A 41 43 D3 07 00 00 00 9A 02 11 00 01 + 05 00 00 00 00 09 11 00 00 36 4A 94 45 00 + 00 00 00 00 94 37 00 8B 3B 00 83 3F 00 7C + 43 00 76 47 00 76 10 30 48 00 F0 4A 3A FF + FF 27 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 08 0A 0C 0E 10 12 14 16 18 1A 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 0E 0C 0A 08 06 05 04 02 00 1D 1E 1F + 20 22 24 28 29 2A 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 84 01]; + + + }; +}; diff --git a/rk3399/rp-lcd-mipi-5-720-1280.dtsi b/rk3399/rp-lcd-mipi-5-720-1280.dtsi new file mode 100755 index 0000000..529947a --- /dev/null +++ b/rk3399/rp-lcd-mipi-5-720-1280.dtsi @@ -0,0 +1,569 @@ +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 46 D0 02 00 05 05 35 01 01 08 1E 0F 5A 3C + 03 05 00 00 00 00 11 11 00 19 1B 1E 14 89 + 29 0A 41 43 D3 07 00 00 00 9A 02 11 00 01 + 05 00 00 00 00 09 11 00 00 36 4A 94 45 00 + 00 00 00 00 94 37 00 8B 3B 00 83 3F 00 7C + 43 00 76 47 00 76 10 30 48 00 F0 4A 3A FF + FF 27 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 08 0A 0C 0E 10 12 14 16 18 1A 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 0E 0C 0A 08 06 05 04 02 00 1D 1E 1F + 20 22 24 28 29 2A 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 84 01]; + goodix,cfg-group1 = [ + 46 D0 02 00 05 05 35 01 01 08 1E 0F 5A 3C + 03 05 00 00 00 00 11 11 00 19 1B 1E 14 89 + 29 0A 41 43 D3 07 00 00 00 9A 02 11 00 01 + 05 00 00 00 00 09 11 00 00 36 4A 94 45 00 + 00 00 00 00 94 37 00 8B 3B 00 83 3F 00 7C + 43 00 76 47 00 76 10 30 48 00 F0 4A 3A FF + FF 27 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 08 0A 0C 0E 10 12 14 16 18 1A 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 0E 0C 0A 08 06 05 04 02 00 1D 1E 1F + 20 22 24 28 29 2A 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 84 01]; + }; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; +// rockchip,lane-rate = <410>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 39 00 02 FE 01 + 39 00 02 24 00 + 39 00 02 25 53 + 39 00 02 26 00 + 39 00 02 27 0A + 39 00 02 29 0A + 39 00 02 2B E5 + 39 00 02 16 52 + 39 00 02 2F 54 + 39 00 02 34 59 + 39 00 02 1B 50 + 39 00 02 12 02 + 39 00 02 1A 06 + 39 00 02 46 5F + 39 00 02 52 70 + 39 00 02 53 00 + 39 00 02 54 70 + 39 00 02 55 00 + 39 00 02 5F 13 + 39 00 02 FE 03 + 39 00 02 00 05 + 39 00 02 01 16 + 39 00 02 02 0B + 39 00 02 03 0F + 39 00 02 04 7D + 39 00 02 05 00 + 39 00 02 06 50 + 39 00 02 07 05 + 39 00 02 08 16 + 39 00 02 09 0D + 39 00 02 0A 11 + 39 00 02 0B 7D + 39 00 02 0C 00 + 39 00 02 0D 50 + 39 00 02 0E 07 + 39 00 02 0F 08 + 39 00 02 10 01 + 39 00 02 11 02 + 39 00 02 12 00 + 39 00 02 13 7D + 39 00 02 14 00 + 39 00 02 15 85 + 39 00 02 16 08 + 39 00 02 17 03 + 39 00 02 18 04 + 39 00 02 19 05 + 39 00 02 1A 06 + 39 00 02 1B 00 + 39 00 02 1C 7D + 39 00 02 1D 00 + 39 00 02 1E 85 + 39 00 02 1F 08 + 39 00 02 20 00 + 39 00 02 21 00 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 00 + 39 00 02 29 00 + 39 00 02 2A 07 + 39 00 02 2B 08 + 39 00 02 2D 01 + 39 00 02 2F 02 + 39 00 02 30 00 + 39 00 02 31 40 + 39 00 02 32 05 + 39 00 02 33 08 + 39 00 02 34 54 + 39 00 02 35 7D + 39 00 02 36 00 + 39 00 02 37 03 + 39 00 02 38 04 + 39 00 02 39 05 + 39 00 02 3A 06 + 39 00 02 3B 00 + 39 00 02 3D 40 + 39 00 02 3F 05 + 39 00 02 40 08 + 39 00 02 41 54 + 39 00 02 42 7D + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 45 00 + 39 00 02 46 00 + 39 00 02 47 00 + 39 00 02 48 00 + 39 00 02 49 00 + 39 00 02 4A 00 + 39 00 02 4B 00 + 39 00 02 4C 00 + 39 00 02 4D 00 + 39 00 02 4E 00 + 39 00 02 4F 00 + 39 00 02 50 00 + 39 00 02 51 00 + 39 00 02 52 00 + 39 00 02 53 00 + 39 00 02 54 00 + 39 00 02 55 00 + 39 00 02 56 00 + 39 00 02 58 00 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 00 + 39 00 02 5C 00 + 39 00 02 5D 00 + 39 00 02 5E 00 + 39 00 02 5F 00 + 39 00 02 60 00 + 39 00 02 61 00 + 39 00 02 62 00 + 39 00 02 63 00 + 39 00 02 64 00 + 39 00 02 65 00 + 39 00 02 66 00 + 39 00 02 67 00 + 39 00 02 68 00 + 39 00 02 69 00 + 39 00 02 6A 00 + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 20 + 39 00 02 73 00 + 39 00 02 74 08 + 39 00 02 75 08 + 39 00 02 76 08 + 39 00 02 77 08 + 39 00 02 78 08 + 39 00 02 79 08 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 00 + 39 00 02 7E BF + 39 00 02 7F 3F + 39 00 02 80 3F + 39 00 02 81 3F + 39 00 02 82 3F + 39 00 02 83 3F + 39 00 02 84 3F + 39 00 02 85 02 + 39 00 02 86 06 + 39 00 02 87 3F + 39 00 02 88 14 + 39 00 02 89 10 + 39 00 02 8A 16 + 39 00 02 8B 12 + 39 00 02 8C 08 + 39 00 02 8D 0C + 39 00 02 8E 0A + 39 00 02 8F 0E + 39 00 02 90 00 + 39 00 02 91 04 + 39 00 02 92 3F + 39 00 02 93 3F + 39 00 02 94 3F + 39 00 02 95 3F + 39 00 02 96 05 + 39 00 02 97 01 + 39 00 02 98 0F + 39 00 02 99 0B + 39 00 02 9A 0D + 39 00 02 9B 09 + 39 00 02 9C 13 + 39 00 02 9D 17 + 39 00 02 9E 11 + 39 00 02 9F 15 + 39 00 02 A0 3F + 39 00 02 A2 07 + 39 00 02 A3 03 + 39 00 02 A4 3F + 39 00 02 A5 3F + 39 00 02 A6 3F + 39 00 02 A7 3F + 39 00 02 A9 3F + 39 00 02 AA 3F + 39 00 02 AB 3F + 39 00 02 AC 3F + 39 00 02 AD 3F + 39 00 02 AE 3F + 39 00 02 AF 3F + 39 00 02 B0 3F + 39 00 02 B1 3F + 39 00 02 B2 3F + 39 00 02 B3 05 + 39 00 02 B4 01 + 39 00 02 B5 3F + 39 00 02 B6 17 + 39 00 02 B7 13 + 39 00 02 B8 15 + 39 00 02 B9 11 + 39 00 02 BA 0F + 39 00 02 BB 0B + 39 00 02 BC 0D + 39 00 02 BD 09 + 39 00 02 BE 07 + 39 00 02 BF 03 + 39 00 02 C0 3F + 39 00 02 C1 3F + 39 00 02 C2 3F + 39 00 02 C3 3F + 39 00 02 C4 02 + 39 00 02 C5 06 + 39 00 02 C6 08 + 39 00 02 C7 0C + 39 00 02 C8 0A + 39 00 02 C9 0E + 39 00 02 CA 10 + 39 00 02 CB 14 + 39 00 02 CC 12 + 39 00 02 CD 16 + 39 00 02 CE 3F + 39 00 02 CF 00 + 39 00 02 D0 04 + 39 00 02 D1 3F + 39 00 02 D2 3F + 39 00 02 D3 3F + 39 00 02 D4 3F + 39 00 02 D5 3F + 39 00 02 D6 3F + 39 00 02 D7 3F + 39 00 02 DC 02 + 39 00 02 DE 12 + 39 00 02 FE 0E + 39 00 02 01 75 + 39 00 02 FE 04 + 39 00 02 60 00 + 39 00 02 61 08 + 39 00 02 62 0E + 39 00 02 63 0D + 39 00 02 64 05 + 39 00 02 65 10 + 39 00 02 66 0E + 39 00 02 67 0A + 39 00 02 68 16 + 39 00 02 69 0C + 39 00 02 6A 10 + 39 00 02 6B 07 + 39 00 02 6C 0E + 39 00 02 6D 13 + 39 00 02 6E 0C + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 08 + 39 00 02 72 0E + 39 00 02 73 0D + 39 00 02 74 05 + 39 00 02 75 10 + 39 00 02 76 0E + 39 00 02 77 0A + 39 00 02 78 16 + 39 00 02 79 0C + 39 00 02 7A 10 + 39 00 02 7B 07 + 39 00 02 7C 0E + 39 00 02 7D 13 + 39 00 02 7E 0C + 39 78 02 7F 00 + + 39 00 02 FE 00 + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <30>; + hfront-porch = <64>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-5.5-1080-1920.dtsi b/rk3399/rp-lcd-mipi-5.5-1080-1920.dtsi new file mode 100755 index 0000000..0eb0921 --- /dev/null +++ b/rk3399/rp-lcd-mipi-5.5-1080-1920.dtsi @@ -0,0 +1,315 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1080>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 47 38 04 80 07 0A 05 00 + 01 08 28 05 50 32 03 05 + 00 00 00 00 00 00 00 00 + 00 00 00 8B 2B 0D 17 15 + 31 0D 00 00 00 9A 03 2D + 00 00 00 00 00 03 64 32 + 00 00 00 0F 2C 94 C5 02 + 07 00 00 04 9E 10 00 82 + 14 00 6B 19 00 57 20 00 + 4A 27 00 4A 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 FF 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 0F 10 12 + 13 26 24 22 21 20 1F 1E + 1D 1C 18 16 FF FF FF FF + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 8C 01 + ]; + }; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; +// rockchip,lane-rate = <480>; + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + prepare-delay-ms = <100>; + reset-delay-ms = <10>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 15 00 02 FE 00 + 15 00 02 C2 08 + 15 00 02 35 00 + 15 00 02 53 20 + 15 00 02 51 FF + + 05 78 01 29 + 05 78 01 11 + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <138000000>; + hactive = <1080>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <36>; + vback-porch = <6>; + vfront-porch = <6>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-5.5-720-1280-v2.dtsi b/rk3399/rp-lcd-mipi-5.5-720-1280-v2.dtsi new file mode 100755 index 0000000..bb043dd --- /dev/null +++ b/rk3399/rp-lcd-mipi-5.5-720-1280-v2.dtsi @@ -0,0 +1,305 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt1x"; + reg = <0x5d>; + goodix,rst-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio1 22 IRQ_TYPE_EDGE_FALLING>; + + }; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + prepare-delay-ms = <100>; + reset-delay-ms = <10>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + 39 00 05 B8 26 22 20 03 + 39 00 04 BF 02 11 00 + 39 00 0B B3 0C 10 0A 50 03 FF 00 00 00 00 + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + 39 00 02 BC 46 + 39 00 02 CC 0B + 39 00 02 B4 80 + 39 00 04 B2 C8 12 30 + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 00 C0 10 + 39 00 0D C1 53 00 1E 1E 77 C1 FF FF AF AF 7F 7F + 39 00 03 B5 07 07 + 39 00 03 B6 70 70 + 39 00 07 C6 00 00 FF FF 01 FF + 39 00 40 E9 C2 10 05 04 FE 02 81 12 31 45 3F 83 12 91 3B 2A 08 05 00 00 00 00 08 05 00 00 00 00 FF 02 46 02 48 68 88 88 88 80 88 FF 13 57 13 58 78 88 88 88 81 88 00 00 00 00 00 12 B1 3B 00 00 00 00 00 + 39 00 3E EA 00 1A 00 00 00 00 00 00 00 00 00 00 FF 31 75 31 18 78 88 88 88 85 88 FF 20 64 20 08 68 88 88 88 84 88 20 10 00 00 54 00 00 00 00 00 00 00 C0 00 00 0C 00 00 00 00 30 02 A1 00 00 00 00 + 39 00 23 E0 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A + 05 ff 01 11 + 05 78 01 29 + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <42>; + hfront-porch = <44>; + vback-porch = <10>; + vfront-porch = <14>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-5.5-720-1280.dtsi b/rk3399/rp-lcd-mipi-5.5-720-1280.dtsi new file mode 100755 index 0000000..c3a50cf --- /dev/null +++ b/rk3399/rp-lcd-mipi-5.5-720-1280.dtsi @@ -0,0 +1,576 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS5"; //UART4 + status = "okay"; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt1x"; + reg = <0x5d>; + goodix,rst-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio1 22 IRQ_TYPE_EDGE_FALLING>; + + }; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 39 00 02 FE 01 + 39 00 02 24 C0 + 39 00 02 25 53 + 39 00 02 26 00 + 39 00 02 2B E5 + 39 00 02 27 0A + 39 00 02 29 0A + 39 00 02 16 52 + 39 00 02 2F 53 + 39 00 02 34 5A + 39 00 02 1B 00 + 39 00 02 12 0A + 39 00 02 1A 06 + 39 00 02 46 4F + 39 00 02 52 A0 + 39 00 02 53 00 + 39 00 02 54 A0 + 39 00 02 55 00 + 39 00 02 FE 03 + 39 00 02 00 05 + 39 00 02 01 16 + 39 00 02 02 0B + 39 00 02 03 0F + 39 00 02 04 7D + 39 00 02 05 00 + 39 00 02 06 50 + 39 00 02 07 05 + 39 00 02 08 16 + 39 00 02 09 0D + 39 00 02 0A 11 + 39 00 02 0B 7D + 39 00 02 0C 00 + 39 00 02 0D 50 + 39 00 02 0E 07 + 39 00 02 0F 08 + 39 00 02 10 01 + 39 00 02 11 02 + 39 00 02 12 00 + 39 00 02 13 7D + 39 00 02 14 00 + 39 00 02 15 85 + 39 00 02 16 08 + 39 00 02 17 03 + 39 00 02 18 04 + 39 00 02 19 05 + 39 00 02 1A 06 + 39 00 02 1B 00 + 39 00 02 1C 7D + 39 00 02 1D 00 + 39 00 02 1E 85 + 39 00 02 1F 08 + 39 00 02 20 00 + 39 00 02 21 00 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 00 + 39 00 02 29 00 + 39 00 02 2A 07 + 39 00 02 2B 08 + 39 00 02 2D 01 + 39 00 02 2F 02 + 39 00 02 30 00 + 39 00 02 31 40 + 39 00 02 32 05 + 39 00 02 33 08 + 39 00 02 34 54 + 39 00 02 35 7D + 39 00 02 36 00 + 39 00 02 37 03 + 39 00 02 38 04 + 39 00 02 39 05 + 39 00 02 3A 06 + 39 00 02 3B 00 + 39 00 02 3D 40 + 39 00 02 3F 05 + 39 00 02 40 08 + 39 00 02 41 54 + 39 00 02 42 7D + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 45 00 + 39 00 02 46 00 + 39 00 02 47 00 + 39 00 02 48 00 + 39 00 02 49 00 + 39 00 02 4A 00 + 39 00 02 4B 00 + 39 00 02 4C 00 + 39 00 02 4D 00 + 39 00 02 4E 00 + 39 00 02 4F 00 + 39 00 02 50 00 + 39 00 02 51 00 + 39 00 02 52 00 + 39 00 02 53 00 + 39 00 02 54 00 + 39 00 02 55 00 + 39 00 02 56 00 + 39 00 02 58 00 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 00 + 39 00 02 5C 00 + 39 00 02 5D 00 + 39 00 02 5E 00 + 39 00 02 5F 00 + 39 00 02 60 00 + 39 00 02 61 00 + 39 00 02 62 00 + 39 00 02 63 00 + 39 00 02 64 00 + 39 00 02 65 00 + 39 00 02 66 00 + 39 00 02 67 00 + 39 00 02 68 00 + 39 00 02 69 00 + 39 00 02 6A 00 + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 20 + 39 00 02 73 00 + 39 00 02 74 08 + 39 00 02 75 08 + 39 00 02 76 08 + 39 00 02 77 08 + 39 00 02 78 08 + 39 00 02 79 08 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 00 + 39 00 02 7E BF + 39 00 02 7F 02 + 39 00 02 80 06 + 39 00 02 81 14 + 39 00 02 82 10 + 39 00 02 83 16 + 39 00 02 84 12 + 39 00 02 85 08 + 39 00 02 86 3F + 39 00 02 87 3F + 39 00 02 88 3F + 39 00 02 89 3F + 39 00 02 8A 3F + 39 00 02 8B 0C + 39 00 02 8C 0A + 39 00 02 8D 0E + 39 00 02 8E 3F + 39 00 02 8F 3F + 39 00 02 90 00 + 39 00 02 91 04 + 39 00 02 92 3F + 39 00 02 93 3F + 39 00 02 94 3F + 39 00 02 95 3F + 39 00 02 96 05 + 39 00 02 97 01 + 39 00 02 98 3F + 39 00 02 99 3F + 39 00 02 9A 0F + 39 00 02 9B 0B + 39 00 02 9C 0D + 39 00 02 9D 3F + 39 00 02 9E 3F + 39 00 02 9F 3F + 39 00 02 A0 3F + 39 00 02 A2 3F + 39 00 02 A3 09 + 39 00 02 A4 13 + 39 00 02 A5 17 + 39 00 02 A6 11 + 39 00 02 A7 15 + 39 00 02 A9 07 + 39 00 02 AA 03 + 39 00 02 AB 3F + 39 00 02 AC 3F + 39 00 02 AD 05 + 39 00 02 AE 01 + 39 00 02 AF 17 + 39 00 02 B0 13 + 39 00 02 B1 15 + 39 00 02 B2 11 + 39 00 02 B3 0F + 39 00 02 B4 3F + 39 00 02 B5 3F + 39 00 02 B6 3F + 39 00 02 B7 3F + 39 00 02 B8 3F + 39 00 02 B9 0B + 39 00 02 BA 0D + 39 00 02 BB 09 + 39 00 02 BC 3F + 39 00 02 BD 3F + 39 00 02 BE 07 + 39 00 02 BF 03 + 39 00 02 C0 3F + 39 00 02 C1 3F + 39 00 02 C2 3F + 39 00 02 C3 3F + 39 00 02 C4 02 + 39 00 02 C5 06 + 39 00 02 C6 3F + 39 00 02 C7 3F + 39 00 02 C8 08 + 39 00 02 C9 0C + 39 00 02 CA 0A + 39 00 02 CB 3F + 39 00 02 CC 3F + 39 00 02 CD 3F + 39 00 02 CE 3F + 39 00 02 CF 3F + 39 00 02 D0 0E + 39 00 02 D1 10 + 39 00 02 D2 14 + 39 00 02 D3 12 + 39 00 02 D4 16 + 39 00 02 D5 00 + 39 00 02 D6 04 + 39 00 02 D7 3F + 39 00 02 DC 02 + 39 00 02 DE 12 + 39 00 02 FE 0E + 39 00 02 01 75 + 39 00 02 54 01 + 39 00 02 FE 04 + 39 00 02 60 00 + 39 00 02 61 0C + 39 00 02 62 12 + 39 00 02 63 0E + 39 00 02 64 06 + 39 00 02 65 12 + 39 00 02 66 0E + 39 00 02 67 0B + 39 00 02 68 15 + 39 00 02 69 0B + 39 00 02 6A 10 + 39 00 02 6B 07 + 39 00 02 6C 0F + 39 00 02 6D 12 + 39 00 02 6E 0C + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 0C + 39 00 02 72 12 + 39 00 02 73 0E + 39 00 02 74 06 + 39 00 02 75 12 + 39 00 02 76 0E + 39 00 02 77 0B + 39 00 02 78 15 + 39 00 02 79 0B + 39 00 02 7A 10 + 39 00 02 7B 07 + 39 00 02 7C 0F + 39 00 02 7D 12 + 39 00 02 7E 0C + 39 00 02 7F 00 + 39 00 02 FE 00 + 39 00 02 58 AD + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <32>; + hfront-porch = <32>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-lcd-mipi-7-1024-600.dtsi b/rk3399/rp-lcd-mipi-7-1024-600.dtsi new file mode 100755 index 0000000..5b9396d --- /dev/null +++ b/rk3399/rp-lcd-mipi-7-1024-600.dtsi @@ -0,0 +1,325 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ //old touch + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + goodix,cfg-group5 = [ //new touch + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; + }; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + prepare-delay-ms = <100>; + reset-delay-ms = <10>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; +&route_dsi { + status = "okay"; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-7-1200-1920.dtsi b/rk3399/rp-lcd-mipi-7-1200-1920.dtsi new file mode 100755 index 0000000..d591570 --- /dev/null +++ b/rk3399/rp-lcd-mipi-7-1200-1920.dtsi @@ -0,0 +1,505 @@ +#include +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "280"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "true"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; +}; + + + + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01]; + goodix,cfg-group1 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01]; + goodix,cfg-group2 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01]; + goodix,cfg-group3 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01]; + + goodix,cfg-group4 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01]; + + + goodix,cfg-group5 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01]; + + }; +}; +&display_subsystem { + status = "okay"; + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + + +&dsi { + status = "okay"; + rockchip,lane-rate = <880>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 14 42 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 de 03 00 + 39 60 03 c9 02 23 + + 39 00 02 b0 00 + 39 00 06 14 08 b0 00 22 00 + 39 30 02 b4 0c + 39 40 03 b6 3a d3 + 39 50 02 51 e6 + 39 30 02 53 2c + + 05 78 01 29 + 05 78 01 11 + + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 8c 83 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 c9 02 23 + 39 60 03 ca 01 23 + 39 10 03 cb 10 05 + 39 10 03 cc 05 10 + 39 10 03 d0 00 00 + + + 39 10 03 b6 03 00 + 39 10 03 de 03 00 + 39 10 03 d6 05 00 + 39 60 03 b7 4b 02 + + 05 00 01 2c + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + timing2: timing2 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <130>; + hfront-porch = <160>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + + +&pwm0 { + status = "okay"; +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + + + &hdmi_in_vopb { + status = "disabled"; + }; + +&hdmi_in_vopl { + status = "okay"; +}; + + + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-7-720-1280-jc070hd005-v1.dtsi b/rk3399/rp-lcd-mipi-7-720-1280-jc070hd005-v1.dtsi new file mode 100755 index 0000000..66106df --- /dev/null +++ b/rk3399/rp-lcd-mipi-7-720-1280-jc070hd005-v1.dtsi @@ -0,0 +1,545 @@ +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + // status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + // MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; /** 7inch 720x1280 must this mode */ + dsi,format = ; + // bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <100>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + + panel-init-sequence = [ + 39 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 75 03 + + 39 00 02 E0 01 + //39 00 02 4A 30 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 0A 07 + 39 00 02 0C 74 + 39 00 02 17 00 + 39 00 02 18 D7 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B D7 + 39 00 02 1C 01 + 39 00 02 1F 74 + 39 00 02 20 19 + 39 00 02 21 19 + 39 00 02 22 0E + 39 00 02 27 43 + + 39 00 02 37 09 + 39 00 02 38 04 + 39 00 02 39 08 + 39 00 02 3A 18 + 39 00 02 3B 18 + 39 00 02 3C 72 + 39 00 02 3E FF + 39 00 02 3E FF + 39 00 02 3F FF + 39 00 02 40 04 + 39 00 02 41 A0 + 39 00 02 43 08 + 39 00 02 44 07 + 39 00 02 45 30 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 65 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 0F + + 39 00 02 5D 7C + 39 00 02 5E 5F + 39 00 02 5F 4D + 39 00 02 60 3F + 39 00 02 61 39 + 39 00 02 62 29 + 39 00 02 63 2B + 39 00 02 64 12 + 39 00 02 65 28 + 39 00 02 66 24 + 39 00 02 67 22 + 39 00 02 68 3E + 39 00 02 69 2C + 39 00 02 6A 33 + 39 00 02 6B 26 + 39 00 02 6C 23 + 39 00 02 6D 18 + 39 00 02 6E 09 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 5F + 39 00 02 72 4D + 39 00 02 73 3F + 39 00 02 74 39 + 39 00 02 75 29 + 39 00 02 76 2B + 39 00 02 77 12 + 39 00 02 78 28 + 39 00 02 79 24 + 39 00 02 7A 22 + 39 00 02 7B 3E + 39 00 02 7C 2C + 39 00 02 7D 33 + 39 00 02 7E 26 + 39 00 02 7F 23 + 39 00 02 80 18 + 39 00 02 81 09 + 39 00 02 82 00 + + 39 00 02 E0 02 + 39 00 02 00 37 + 39 00 02 01 17 + 39 00 02 02 0A + 39 00 02 03 06 + 39 00 02 04 08 + 39 00 02 05 04 + 39 00 02 06 00 + 39 00 02 07 1F + 39 00 02 08 1F + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 1F + 39 00 02 10 3F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1E + 39 00 02 14 10 + 39 00 02 15 1F + + 39 00 02 16 37 + 39 00 02 17 17 + 39 00 02 18 0B + 39 00 02 19 07 + 39 00 02 1A 09 + 39 00 02 1B 05 + 39 00 02 1C 01 + 39 00 02 1D 1F + 39 00 02 1E 1F + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 1F + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1E + 39 00 02 2A 11 + 39 00 02 2B 1F + 39 00 02 2C 37 + 39 00 02 2D 17 + 39 00 02 2E 05 + 39 00 02 2F 09 + 39 00 02 30 07 + 39 00 02 31 0B + 39 00 02 32 11 + 39 00 02 33 1F + 39 00 02 34 1F + 39 00 02 35 1F + 39 00 02 36 1F + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 3F + 39 00 02 3D 1F + 39 00 02 3E 1E + 39 00 02 3F 1F + 39 00 02 40 01 + + 39 00 02 41 1F + 39 00 02 42 38 + 39 00 02 43 18 + 39 00 02 44 04 + 39 00 02 45 08 + 39 00 02 46 06 + 39 00 02 47 0A + 39 00 02 48 10 + 39 00 02 49 1F + 39 00 02 4A 1F + 39 00 02 4B 1F + 39 00 02 4C 1F + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1E + 39 00 02 55 1F + 39 00 02 56 00 + 39 00 02 57 1F + 39 00 02 58 10 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 10 + 39 00 02 5C 01 + 39 00 02 5D 50 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 30 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 06 + 39 00 02 64 6A + 39 00 02 65 55 + 39 00 02 66 08 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 08 + 39 00 02 6A 6E + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 80 + 39 00 02 76 00 + 39 00 02 77 0D + 39 00 02 78 18 + 39 00 02 79 00 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 04 + 39 00 02 04 01 + 39 00 02 0E 38 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E6 02 + //39 00 02 36 00 + 39 C8 02 11 00 + 39 C8 02 29 00 + 05 78 01 11//delay 120MS + 05 78 01 29 + //39 C8 02 35 00 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <70000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <34>; + hfront-porch = <34>; + vback-porch = <6>; + vfront-porch = <20>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +//TP +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_FALLING>; + + goodix,cfg-group0 = [ + 57 58 02 00 04 05 35 00 01 08 32 0F + 5A 32 03 05 00 00 00 00 02 00 00 18 + 1A 1E 14 8A 2A 0C 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 2B FF 7F + 19 46 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 40 30 FF + FF 27 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 24 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0F 10 12 13 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 81 01]; + + goodix,cfg-group5 = [ + 57 58 02 00 04 05 35 00 01 08 32 0F + 5A 32 03 05 00 00 00 00 02 00 00 18 + 1A 1E 14 8A 2A 0C 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 2B FF 7F + 19 46 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 40 30 FF + FF 27 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 24 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0F 10 12 13 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 81 01]; + + }; +}; diff --git a/rk3399/rp-lcd-mipi-7-800-1280.dtsi b/rk3399/rp-lcd-mipi-7-800-1280.dtsi new file mode 100755 index 0000000..5baeb0a --- /dev/null +++ b/rk3399/rp-lcd-mipi-7-800-1280.dtsi @@ -0,0 +1,265 @@ +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + gslx680@40 { + compatible = "gslx680"; + reg = <0x40>; + touch-gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + reset-gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + }; +}; + +&display_subsystem { + status = "okay"; + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + //rockchip,lane-rate = <470>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + //MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <70000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <22>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-lcd-mipi-8-1200-1920.dtsi b/rk3399/rp-lcd-mipi-8-1200-1920.dtsi new file mode 100755 index 0000000..3f5d261 --- /dev/null +++ b/rk3399/rp-lcd-mipi-8-1200-1920.dtsi @@ -0,0 +1,325 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <940>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_EOT_PACKET)>; + //MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; // + vsync-len = <1>; // + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 5E B0 04 80 07 05 05 00 01 0F 28 05 + 50 32 03 05 00 00 00 00 00 00 00 00 + 00 00 00 8C 2C 0E 52 54 31 0D 00 00 + 01 80 04 1C 00 00 00 00 00 03 64 32 + 00 00 00 52 66 94 C5 02 07 00 00 04 + 83 53 00 82 57 00 80 5B 00 7F 5F 00 + 7E 63 00 7E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 08 0A 0C 0F 10 12 13 14 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 22 01 + ]; + + /** jc */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + }; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-8-800-1280-new.dtsi b/rk3399/rp-lcd-mipi-8-800-1280-new.dtsi new file mode 100755 index 0000000..ecf83c7 --- /dev/null +++ b/rk3399/rp-lcd-mipi-8-800-1280-new.dtsi @@ -0,0 +1,544 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS5"; //UART4 + status = "okay"; + }; + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01]; + }; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 73 + 39 00 02 04 D7 + 39 00 02 05 00 + 39 00 02 06 08 + 39 00 02 07 11 + 39 00 02 08 00 + 39 00 02 09 3F + 39 00 02 0a 00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F + 39 00 02 10 3F + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 00 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 44 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + 39 00 02 5e 00 + 39 00 02 5f 0C + 39 00 02 60 0C + 39 00 02 61 0F + 39 00 02 62 0F + 39 00 02 63 0E + 39 00 02 64 0E + 39 00 02 65 06 + 39 00 02 66 07 + 39 00 02 67 0D + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 0D + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 05 + 39 00 02 72 01 + 39 00 02 73 08 + 39 00 02 74 00 + 39 00 02 75 0C + 39 00 02 76 0C + 39 00 02 77 0F + 39 00 02 78 0F + 39 00 02 79 0E + 39 00 02 7a 0E + 39 00 02 7b 06 + 39 00 02 7c 07 + 39 00 02 7d 0D + 39 00 02 7e 02 + 39 00 02 7f 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 0D + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 05 + 39 00 02 88 01 + 39 00 02 89 08 + 39 00 02 8A 00 + + 39 00 04 FF 98 81 04 + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 7B + 39 00 02 55 40 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 27 + 39 00 02 62 20 + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 20 + 39 00 02 A3 13 + 39 00 02 A4 14 + 39 00 02 A5 27 + 39 00 02 A6 1D + 39 00 02 A7 1F + 39 00 02 A8 7C + 39 00 02 A9 1D + 39 00 02 AA 2A + 39 00 02 AB 6B + 39 00 02 AC 1A + 39 00 02 AD 18 + 39 00 02 AE 4E + 39 00 02 AF 24 + 39 00 02 B0 2A + 39 00 02 B1 4D + 39 00 02 B2 5B + 39 00 02 B3 23 + 39 00 02 C0 00 + 39 00 02 C1 13 + 39 00 02 C2 20 + 39 00 02 C3 12 + 39 00 02 C4 15 + 39 00 02 C5 28 + 39 00 02 C6 1C + 39 00 02 C7 1E + 39 00 02 C8 7B + 39 00 02 C9 1E + 39 00 02 CA 29 + 39 00 02 CB 6C + 39 00 02 CC 1A + 39 00 02 CD 19 + 39 00 02 CE 4D + 39 00 02 CF 22 + 39 00 02 D0 2A + 39 00 02 D1 4D + 39 00 02 D2 5B + 39 00 02 D3 23 + 39 00 04 FF 98 81 00 + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <80000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <6>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi-8-800-1280-v2.dtsi b/rk3399/rp-lcd-mipi-8-800-1280-v2.dtsi new file mode 100755 index 0000000..5723d78 --- /dev/null +++ b/rk3399/rp-lcd-mipi-8-800-1280-v2.dtsi @@ -0,0 +1,514 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "true"; + home_apk = "null"; + status = "okay"; + }; + +}; +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; +// rockchip,lane-rate = <480>; + + panel: panel { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + //power-supply = <&vcc_lcd>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + status = "okay"; + panel-init-sequence = [ + + 39 00 04 FF 98 81 03 + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 73 + 39 00 02 04 D7 + 39 00 02 05 00 + 39 00 02 06 08 + 39 00 02 07 11 + 39 00 02 08 00 + 39 00 02 09 3F + 39 00 02 0a 00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F + 39 00 02 10 3F + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 00 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 44 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + 39 00 02 5e 00 + 39 00 02 5f 0C + 39 00 02 60 0C + 39 00 02 61 0F + 39 00 02 62 0F + 39 00 02 63 0E + 39 00 02 64 0E + 39 00 02 65 06 + 39 00 02 66 07 + 39 00 02 67 0D + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 0D + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 05 + 39 00 02 72 01 + 39 00 02 73 08 + 39 00 02 74 00 + 39 00 02 75 0C + 39 00 02 76 0C + 39 00 02 77 0F + 39 00 02 78 0F + 39 00 02 79 0E + 39 00 02 7a 0E + 39 00 02 7b 06 + 39 00 02 7c 07 + 39 00 02 7d 0D + 39 00 02 7e 02 + 39 00 02 7f 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 0D + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 05 + 39 00 02 88 01 + 39 00 02 89 08 + 39 00 02 8A 00 + + 39 00 04 FF 98 81 04 + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 7B + 39 00 02 55 40 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 27 + 39 00 02 62 20 + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 20 + 39 00 02 A3 13 + 39 00 02 A4 14 + 39 00 02 A5 27 + 39 00 02 A6 1D + 39 00 02 A7 1F + 39 00 02 A8 7C + 39 00 02 A9 1D + 39 00 02 AA 2A + 39 00 02 AB 6B + 39 00 02 AC 1A + 39 00 02 AD 18 + 39 00 02 AE 4E + 39 00 02 AF 24 + 39 00 02 B0 2A + 39 00 02 B1 4D + 39 00 02 B2 5B + 39 00 02 B3 23 + 39 00 02 C0 00 + 39 00 02 C1 13 + 39 00 02 C2 20 + 39 00 02 C3 12 + 39 00 02 C4 15 + 39 00 02 C5 28 + 39 00 02 C6 1C + 39 00 02 C7 1E + 39 00 02 C8 7B + 39 00 02 C9 1E + 39 00 02 CA 29 + 39 00 02 CB 6C + 39 00 02 CC 1A + 39 00 02 CD 19 + 39 00 02 CE 4D + 39 00 02 CF 22 + 39 00 02 D0 2A + 39 00 02 D1 4D + 39 00 02 D2 5B + 39 00 02 D3 23 + 39 00 04 FF 98 81 00 + + 05 78 01 11 + 05 78 01 29 + ]; + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + + disp_timings: display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <80000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <6>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +//TP +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_FALLING>; + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01]; + + }; +}; + diff --git a/rk3399/rp-lcd-mipi-8-800-1280-v3.dtsi b/rk3399/rp-lcd-mipi-8-800-1280-v3.dtsi new file mode 100755 index 0000000..b08f856 --- /dev/null +++ b/rk3399/rp-lcd-mipi-8-800-1280-v3.dtsi @@ -0,0 +1,559 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 57 //54 + 39 00 02 04 D3 //D4 + 39 00 02 05 00 + 39 00 02 06 11 + 39 00 02 07 08 //09 + 39 00 02 08 00 + 39 00 02 09 00 + 39 00 02 0a 3F //00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F //00 + 39 00 02 10 3F //00 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 78 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 //GCH/L + 39 00 02 44 00 + + + 39 00 02 50 00 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + 39 00 02 5e 00 + 39 00 02 5f 0D //FW_CGOUT_L[1] + 39 00 02 60 0D //FW_CGOUT_L[2] + 39 00 02 61 0C //FW_CGOUT_L[3] + 39 00 02 62 0C //FW_CGOUT_L[4] + 39 00 02 63 0F //FW_CGOUT_L[5] + 39 00 02 64 0F //FW_CGOUT_L[6] + 39 00 02 65 0E //FW_CGOUT_L[7] + 39 00 02 66 0E //FW_CGOUT_L[8] + 39 00 02 67 08 //FW_CGOUT_L[9] + 39 00 02 68 02 //FW_CGOUT_L[10] + 39 00 02 69 02 //FW_CGOUT_L[11] + 39 00 02 6a 02 //FW_CGOUT_L[12] + 39 00 02 6b 02 //FW_CGOUT_L[13] + 39 00 02 6c 02 //FW_CGOUT_L[14] + 39 00 02 6d 02 //FW_CGOUT_L[15] + 39 00 02 6e 02 //FW_CGOUT_L[16] + 39 00 02 6f 02 //FW_CGOUT_L[17] + 39 00 02 70 14 //FW_CGOUT_L[18] + 39 00 02 71 15 //FW_CGOUT_L[19] + 39 00 02 72 06 //FW_CGOUT_L[20] + 39 00 02 73 02 //FW_CGOUT_L[21] + 39 00 02 74 02 //FW_CGOUT_L[22] + + 39 00 02 75 0D //BW_CGOUT_L[1] + 39 00 02 76 0D //BW_CGOUT_L[2] + 39 00 02 77 0C //BW_CGOUT_L[3] + 39 00 02 78 0C //BW_CGOUT_L[4] + 39 00 02 79 0F //BW_CGOUT_L[5] + 39 00 02 7a 0F //BW_CGOUT_L[6] + 39 00 02 7b 0E //BW_CGOUT_L[7] + 39 00 02 7c 0E //BW_CGOUT_L[8] + 39 00 02 7d 08 //BW_CGOUT_L[9] + 39 00 02 7e 02 //BW_CGOUT_L[10] + 39 00 02 7f 02 //BW_CGOUT_L[11] + 39 00 02 80 02 //BW_CGOUT_L[12] + 39 00 02 81 02 //BW_CGOUT_L[13] + 39 00 02 82 02 //BW_CGOUT_L[14] + 39 00 02 83 02 //BW_CGOUT_L[15] + 39 00 02 84 02 //BW_CGOUT_L[16] + 39 00 02 85 02 //BW_CGOUT_L[17] + 39 00 02 86 14 //BW_CGOUT_L[18] + 39 00 02 87 15 //BW_CGOUT_L[19] + 39 00 02 88 06 //BW_CGOUT_L[20] + 39 00 02 89 02 //BW_CGOUT_L[21] + 39 00 02 8A 02 //BW_CGOUT_L[22] + + + + 39 00 04 FF 98 81 04 + + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 87 + 39 00 02 55 84 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 10 + 39 00 02 62 00 + + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 1F + 39 00 02 A3 12 + 39 00 02 A4 16 + 39 00 02 A5 29 + 39 00 02 A6 1E + 39 00 02 A7 1F + 39 00 02 A8 7E + 39 00 02 A9 1B + 39 00 02 AA 28 + 39 00 02 AB 6D + 39 00 02 AC 19 + 39 00 02 AD 18 + 39 00 02 AE 4C + 39 00 02 AF 1E + 39 00 02 B0 23 + 39 00 02 B1 52 + 39 00 02 B2 6D + 39 00 02 B3 3F + + 39 00 02 C0 00 + 39 00 02 C1 12 + 39 00 02 C2 20 + 39 00 02 C3 10 + 39 00 02 C4 13 + 39 00 02 C5 27 + 39 00 02 C6 1B + 39 00 02 C7 1D + 39 00 02 C8 75 + 39 00 02 C9 1F + 39 00 02 CA 28 + 39 00 02 CB 68 + 39 00 02 CC 1A + 39 00 02 CD 18 + 39 00 02 CE 4D + 39 00 02 CF 25 + 39 00 02 D0 2E + 39 00 02 D1 53 + 39 00 02 D2 60 + 39 00 02 D3 3F + + 39 00 04 FF 98 81 00 + 39 00 02 35 00 + 05 80 01 11 + 05 20 01 29 + ]; + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <70>; + hfront-porch = <70>; + vback-porch = <22>; + vfront-porch = <16>; + hsync-len = <20>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + /** jc */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01]; + }; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-lcd-mipi-8-800-1280.dtsi b/rk3399/rp-lcd-mipi-8-800-1280.dtsi new file mode 100755 index 0000000..a58788d --- /dev/null +++ b/rk3399/rp-lcd-mipi-8-800-1280.dtsi @@ -0,0 +1,567 @@ + +/ { + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS5"; //UART4 + status = "okay"; + }; + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01]; + }; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + panel-init-sequence = [ + 15 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 01 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 17 00 + 39 00 02 18 B1 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B B1 + 39 00 02 1C 01 + 39 00 02 1F 3E + 39 00 02 20 2D + 39 00 02 21 2D + 39 00 02 22 0E + 39 00 02 37 19 + 39 00 02 38 05 + 39 00 02 39 08 + 39 00 02 3A 12 + 39 00 02 3C 78 + 39 00 02 3E 80 + 39 00 02 3F 80 + 39 00 02 40 06 + 39 00 02 41 A0 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 69 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 19 + 39 00 02 5D 7C + 39 00 02 5E 65 + 39 00 02 5F 53 + 39 00 02 60 48 + 39 00 02 61 43 + 39 00 02 62 35 + 39 00 02 63 39 + 39 00 02 64 23 + 39 00 02 65 3D + 39 00 02 66 3C + 39 00 02 67 3D + 39 00 02 68 5A + 39 00 02 69 46 + 39 00 02 6A 57 + 39 00 02 6B 4B + 39 00 02 6C 49 + 39 00 02 6D 2F + 39 00 02 6E 03 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 65 + 39 00 02 72 53 + 39 00 02 73 48 + 39 00 02 74 43 + 39 00 02 75 35 + 39 00 02 76 39 + 39 00 02 77 23 + 39 00 02 78 3D + 39 00 02 79 3C + 39 00 02 7A 3D + 39 00 02 7B 5A + 39 00 02 7C 46 + 39 00 02 7D 57 + 39 00 02 7E 4B + 39 00 02 7F 49 + 39 00 02 80 2F + 39 00 02 81 03 + 39 00 02 82 00 + 39 00 02 E0 02 + 39 00 02 00 47 + 39 00 02 01 47 + 39 00 02 02 45 + 39 00 02 03 45 + 39 00 02 04 4B + 39 00 02 05 4B + 39 00 02 06 49 + 39 00 02 07 49 + 39 00 02 08 41 + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 43 + 39 00 02 10 1F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1F + 39 00 02 14 1F + 39 00 02 15 1F + 39 00 02 16 46 + 39 00 02 17 46 + 39 00 02 18 44 + 39 00 02 19 44 + 39 00 02 1A 4A + 39 00 02 1B 4A + 39 00 02 1C 48 + 39 00 02 1D 48 + 39 00 02 1E 40 + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 42 + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1F + 39 00 02 2A 1F + 39 00 02 2B 1F + 39 00 02 2C 11 + 39 00 02 2D 0F + 39 00 02 2E 0D + 39 00 02 2F 0B + 39 00 02 30 09 + 39 00 02 31 07 + 39 00 02 32 05 + 39 00 02 33 18 + 39 00 02 34 17 + 39 00 02 35 1F + 39 00 02 36 01 + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 1F + 39 00 02 3D 1F + 39 00 02 3E 1F + 39 00 02 3F 13 + 39 00 02 40 1F + 39 00 02 41 1F + 39 00 02 42 10 + 39 00 02 43 0E + 39 00 02 44 0C + 39 00 02 45 0A + 39 00 02 46 08 + 39 00 02 47 06 + 39 00 02 48 04 + 39 00 02 49 18 + 39 00 02 4A 17 + 39 00 02 4B 1F + 39 00 02 4C 00 + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1F + 39 00 02 55 12 + 39 00 02 56 1F + 39 00 02 57 1F + 39 00 02 58 40 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 30 + 39 00 02 5C 03 + 39 00 02 5D 30 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 00 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 03 + 39 00 02 64 6B + 39 00 02 65 00 + 39 00 02 66 00 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 06 + 39 00 02 6A 6B + 39 00 02 6B 08 + 39 00 02 6C 00 + 39 00 02 6D 04 + 39 00 02 6E 04 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 07 + 39 00 02 76 00 + 39 00 02 77 5D + 39 00 02 78 17 + 39 00 02 79 1F + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 01 + 39 00 02 0E 01 + 39 00 02 E0 03 + 39 00 02 98 2F + 39 00 02 E0 04 + 39 00 02 09 10 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E7 02 + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <20>; + hfront-porch = <32>; + vback-porch = <4>; + vfront-porch = <8>; + hsync-len = <20>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 { + clock-frequency = <148000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-lcd-mipi2Duallvds-1920-1080.dtsi b/rk3399/rp-lcd-mipi2Duallvds-1920-1080.dtsi new file mode 100755 index 0000000..dbf72ad --- /dev/null +++ b/rk3399/rp-lcd-mipi2Duallvds-1920-1080.dtsi @@ -0,0 +1,291 @@ +/** + * rpdzkj lcd configuration for mipi2lvds tc358775 + * + */ + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + rpdzkj_config { // linux donot use + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160";//320 + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + //not_status_bar = "true"; + default_launcher = "true"; + //default_launcher = "false"; + has_root = "true"; //true + //has_root = "false"; //false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + //usb_camera_only_front = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + //compatible = "rockchip,rk3399-dsi"; //no longer need that + //reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + panel { + compatible = "simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + + enable-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; /** note that needed status in real situation, there is low */ + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 29 00 06 14 01 08 00 00 00 + 29 00 06 3c 01 0c 00 0a 00 + 29 00 06 64 01 0c 00 00 00 + 29 00 06 68 01 0c 00 00 00 + 29 00 06 6c 01 0c 00 00 00 + 29 00 06 70 01 0c 00 00 00 + 29 00 06 34 01 1f 00 00 00 + 29 00 06 10 02 1f 00 00 00 + 29 00 06 04 01 01 00 00 00 + 29 00 06 04 02 01 00 00 00 + 29 00 06 50 04 00 01 f0 03 + 29 00 06 54 04 14 00 64 00 + 29 00 06 58 04 80 07 a0 00 + 29 00 06 5c 04 0a 00 19 00 + 29 00 06 60 04 38 04 0a 00 + 29 00 06 64 04 01 00 00 00 + 29 00 06 a0 04 06 c0 00 00 + 29 00 06 04 05 04 00 00 00 + 29 00 06 80 04 00 01 02 03 + 29 00 06 84 04 04 07 05 08 + 29 00 06 88 04 09 0a 0e 0f + 29 00 06 8c 04 0b 0c 0d 10 + 29 00 06 90 04 16 17 11 12 + 29 00 06 94 04 13 14 15 1b + 29 14 06 98 04 18 19 1a 06 + 29 78 06 9c 04 33 04 00 00 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <100>; + hsync-len = <20>; + hfront-porch = <160>; + vback-porch = <25>; + vfront-porch = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; +&dsi1_in_vopb { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; diff --git a/rk3399/rp-lcd-mipi2lvds-10-1024-600.dtsi b/rk3399/rp-lcd-mipi2lvds-10-1024-600.dtsi new file mode 100755 index 0000000..b65b374 --- /dev/null +++ b/rk3399/rp-lcd-mipi2lvds-10-1024-600.dtsi @@ -0,0 +1,297 @@ +/** + * rpdzkj lcd configuration for mipi2lvds tc358775 + * + */ + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + rpdzkj_config { // linux donot use + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160";//320 + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + //not_status_bar = "true"; + default_launcher = "true"; + //default_launcher = "false"; + has_root = "true"; //true + //has_root = "false"; //false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + //usb_camera_only_front = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + //status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + //compatible = "rockchip,rk3399-dsi"; //no longer need that + //reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + panel { + compatible = "simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + + enable-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; /** note that needed status in real situation, there is low */ + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + 29 00 06 3c 01 0c 00 0a 00 + 29 00 06 14 01 08 00 00 00 + 29 00 06 64 01 0d 00 00 00 + 29 00 06 68 01 0d 00 00 00 + 29 00 06 6c 01 0d 00 00 00 + 29 00 06 70 01 0d 00 00 00 + 29 00 06 34 01 1f 00 00 00 + 29 00 06 10 02 1f 00 00 00 + 29 00 06 04 01 01 00 00 00 + 29 00 06 04 02 01 00 00 00 + 29 00 06 50 04 00 01 f0 03 + 29 00 06 54 04 14 00 a0 00 + 29 00 06 58 04 00 04 a0 00 + 29 00 06 5c 04 03 00 17 00 + 29 00 06 60 04 58 02 0c 00 + 29 00 06 64 04 01 00 00 00 + 29 64 06 a0 04 06 80 44 00 + 29 00 06 a0 04 06 80 04 00 + 29 00 06 04 05 04 00 00 00 + /* data-mapping:jeida, default vesa + 29 00 06 80 04 00 01 02 03 + 29 00 06 84 04 04 07 05 08 + 29 00 06 88 04 09 0a 0e 0f + 29 00 06 8c 04 0b 0c 0d 10 + 29 00 06 90 04 16 17 11 12 + 29 00 06 94 04 13 14 15 1b + 29 14 06 98 04 18 19 1a 06 + */ + 29 78 06 9c 04 31 00 00 00 + + + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hsync-len = <20>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopl { + status = "disabled"; +}; +&dsi1_in_vopb { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; diff --git a/rk3399/rp-lcd-mipi2lvds-gm8775-duallvds-1920-1080.dtsi b/rk3399/rp-lcd-mipi2lvds-gm8775-duallvds-1920-1080.dtsi new file mode 100755 index 0000000..eb1fba9 --- /dev/null +++ b/rk3399/rp-lcd-mipi2lvds-gm8775-duallvds-1920-1080.dtsi @@ -0,0 +1,428 @@ + + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <255>; + }; + + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160";//320 + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + //not_status_bar = "true"; + default_launcher = "true"; + //default_launcher = "false"; + has_root = "true"; //true + //has_root = "false"; //false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + //usb_camera_only_front = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + primary_device = "LVDS"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "true"; + home_apk = "null"; + status = "okay"; + }; + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + // status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + // rockchip,lane-rate = <480>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <100>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + panel-init-sequence = [ +/* //26MHz +23 08 02 27 AA +23 08 02 48 02 +23 08 02 B6 20 +23 08 02 01 80 +23 08 02 02 38 +23 08 02 03 47 +23 08 02 04 50 +23 08 02 05 12 +23 08 02 06 50 +23 08 02 07 00 +23 08 02 08 18 +23 08 02 09 04 +23 08 02 0A 18 +23 08 02 0B 02 +23 08 02 0C 53 +23 08 02 0D 01 +23 08 02 0E 80 +23 08 02 0F 20 +23 08 02 10 20 +23 08 02 11 03 +23 08 02 12 1B +23 08 02 13 63 +23 08 02 14 34 +23 08 02 15 20 +23 08 02 16 10 +23 08 02 17 00 +23 08 02 18 34 +23 08 02 19 20 +23 08 02 1A 10 +23 08 02 1B 00 +23 08 02 1E 46 +23 08 02 51 30 +23 08 02 1F 10 +23 08 02 2A 01 +*/ + +//mipi clk +23 08 02 27 AA +23 08 02 48 02 +23 08 02 B6 20 +23 08 02 01 80 +23 08 02 02 38 +23 08 02 03 47 +23 08 02 04 50 +23 08 02 05 12 +23 08 02 06 50 +23 08 02 07 00 +23 08 02 08 18 +23 08 02 09 04 +23 08 02 0A 18 +23 08 02 0B 82 +23 08 02 0C 13 +23 08 02 0D 01 +23 08 02 0E 80 +23 08 02 0F 20 +23 08 02 10 20 +23 08 02 11 03 +23 08 02 12 1B +23 08 02 13 63 +23 08 02 14 34 +23 08 02 15 20 +23 08 02 16 10 +23 08 02 17 00 +23 08 02 18 34 +23 08 02 19 20 +23 08 02 1A 10 +23 08 02 1B 00 +23 08 02 1E 46 +23 08 02 51 30 +23 08 02 1F 10 +23 08 02 2A 01 + + + + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&route_dsi { + status = "okay"; +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + +/* old touchscreen sensor_id0 */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +/* new touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; + + }; +}; diff --git a/rk3399/rp-lcd-mipi2lvds-gm8775-singlelvds-10-1024-600.dtsi b/rk3399/rp-lcd-mipi2lvds-gm8775-singlelvds-10-1024-600.dtsi new file mode 100755 index 0000000..468cd31 --- /dev/null +++ b/rk3399/rp-lcd-mipi2lvds-gm8775-singlelvds-10-1024-600.dtsi @@ -0,0 +1,388 @@ + + +/ { + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <255>; + }; + + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160";//320 + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + //not_status_bar = "true"; + default_launcher = "true"; + //default_launcher = "false"; + has_root = "true"; //true + //has_root = "false"; //false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + //usb_camera_only_front = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + primary_device = "LVDS"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "true"; + home_apk = "null"; + status = "okay"; + }; + +}; + + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + + status = "okay"; + // status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&dsi { + status = "okay"; + rockchip,lane-rate = <360>; + + panel { + compatible ="simple-panel-dsi"; + status = "okay"; + reg = <0>; + power-supply = <&vcc3v3_sys>; + backlight = <&backlight>; + cmd_later_reset = <0>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; +// bus-format = ; + dsi,lanes = <4>; + reset-delay-ms = <100>; + init-delay-ms = <100>; + enable-delay-ms = <120>; + disable-delay-ms = <50>; + unprepare-delay-ms = <20>; + + width-mm = <68>; + height-mm = <121>; + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&dsi_in_vopl { + status = "disabled"; +}; + +&dsi_in_vopb { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "okay"; +}; + + +&edp_in_vopb { + status = "disabled"; +}; +&edp_in_vopl { + status = "disabled"; +}; + +&dsi1_in_vopb { + status = "disabled"; +}; +&dsi1_in_vopl { + status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vopl_out_hdmi>; +}; + +&route_dsi { + status = "okay"; + connect = <&vopb_out_dsi>; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + +/* old touchscreen sensor_id0 */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +/* new touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; + + }; +}; diff --git a/rk3399/rp-mipi-ov13850-camera.dtsi b/rk3399/rp-mipi-ov13850-camera.dtsi new file mode 100755 index 0000000..9b5cd5c --- /dev/null +++ b/rk3399/rp-mipi-ov13850-camera.dtsi @@ -0,0 +1,175 @@ + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + // Unlinked camera + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&isp1_mmu { + status = "okay"; +}; + + + +&i2c1 { + status = "okay"; + ov13850b: ov13850b@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&pinctrl_ov13850b>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + ov13850f: ov13850f@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + //pinctrl-names = "rockchip,camera_default"; + //pinctrl-0 = <&pinctrl_ov13850f>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + + port { + ucam_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&pinctrl { + camera { + pinctrl_ov13850b: pinctrl-ov13850b { + rockchip,pins = + /* cif_clkout */ + <2 RK_PB3 3 &pcfg_pull_none>, + <1 RK_PA3 0 &pcfg_pull_none>, + <2 RK_PD4 0 &pcfg_pull_none>; + }; + pinctrl_ov13850f: pinctrl-ov13850f { + rockchip,pins = + /* cif_clkout */ + <2 RK_PB3 3 &pcfg_pull_none>, + <2 RK_PD3 0 &pcfg_pull_none>, + <2 RK_PB4 0 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-pcie.dtsi b/rk3399/rp-pcie.dtsi new file mode 100755 index 0000000..b3dffe0 --- /dev/null +++ b/rk3399/rp-pcie.dtsi @@ -0,0 +1,40 @@ +/** + * rpdzkj configure for pcie + * + * Only pcie related configuration is placed here. + */ + +/ { + vcc3v3_pcie: vcc3v3-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_drv>; + regulator-name = "vcc3v3_pcie"; + }; +}; + +&pcie0 { + ep-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + phy-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pinctrl { + pcie { + pcie_drv: pcie-drv { + rockchip,pins = + <1 20 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-pmu-rk808-king.dtsi b/rk3399/rp-pmu-rk808-king.dtsi new file mode 100644 index 0000000..caeeed6 --- /dev/null +++ b/rk3399/rp-pmu-rk808-king.dtsi @@ -0,0 +1,259 @@ + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + // clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; //wifi + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + //regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-pmu-rk808-rd-box.dtsi b/rk3399/rp-pmu-rk808-rd-box.dtsi new file mode 100644 index 0000000..e70ee78 --- /dev/null +++ b/rk3399/rp-pmu-rk808-rd-box.dtsi @@ -0,0 +1,253 @@ + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + //clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; //wifi +/* + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + +*/ + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcca-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + //regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + diff --git a/rk3399/rp-pmu-rk808-rp-box.dtsi b/rk3399/rp-pmu-rk808-rp-box.dtsi new file mode 100644 index 0000000..b5c847d --- /dev/null +++ b/rk3399/rp-pmu-rk808-rp-box.dtsi @@ -0,0 +1,252 @@ + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + // clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; //wifi +/* + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + +*/ + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcca-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + //regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/rk3399/rp-pmu-rk808-rp.dtsi b/rk3399/rp-pmu-rk808-rp.dtsi new file mode 100644 index 0000000..b5c847d --- /dev/null +++ b/rk3399/rp-pmu-rk808-rp.dtsi @@ -0,0 +1,252 @@ + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + // clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; //wifi +/* + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + vcc10-supply = <&vcc3v3_sys>; + vcc11-supply = <&vcc3v3_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_3v0>; + +*/ + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcca-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc5v0_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + //regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/rk3399/rp-pmu-rk808.dtsi b/rk3399/rp-pmu-rk808.dtsi new file mode 100755 index 0000000..f97b9cf --- /dev/null +++ b/rk3399/rp-pmu-rk808.dtsi @@ -0,0 +1,259 @@ + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <168>; + i2c-scl-falling-time-ns = <4>; + clock-frequency = <400000>; + + vdd_cpu_b: syr827@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + reg = <0x41>; + vin-supply = <&vcc_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-names = "default"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio1>; + interrupts = <21 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &pmic_dvs2>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + //clock-output-names = "xin32k", "rk808-clkout2"; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; //wifi + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc1v8_pmu>; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v0_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc3v0_tp"; + regulator-state-mem { + //regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc1v8_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sdio: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_sdio"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <3000000>; + }; + }; + + vcca3v0_codec: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcca3v0_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1500000>; + }; + }; + + vcca1v8_codec: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_codec"; + regulator-state-mem { + regulator-off-in-suspend; + // regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v0: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc3v3_s3: vcc_lan: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_s0: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 17 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 14 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-rd-lcd-edp-13.3-1920-1080.dtsi b/rk3399/rp-rd-lcd-edp-13.3-1920-1080.dtsi new file mode 100755 index 0000000..4255c5a --- /dev/null +++ b/rk3399/rp-rd-lcd-edp-13.3-1920-1080.dtsi @@ -0,0 +1,288 @@ + +/ { + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_sys>; + enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + //reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <200>; + + //for king/rp/rd board cannot enable boot logo + pinctrl-names = "default"; + pinctrl-0 = <&pwr_en>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 {//EDP 13.3 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + timing1: timing1 {// EDP 15.6 LP156WF6 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + backlight: backlight { + status = "okay"; + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + brightness-levels = < + + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + + + default-brightness-level = <255>; + }; + + //bill + rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + back_camera_rotate = "0"; + front_camera_rotate = "0"; + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +0 + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; //true//false + usb_not_permission = "true"; + usb_camera_only_front = "false"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; //UART4 + status = "okay"; + }; + +}; + +&hdmi { + #address-cells = <1>; + #size-cells = <0>; + #sound-dai-cells = <0>; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; + ports = <&vopb_out>, <&vopl_out>; + logo-memory-region = <&drm_logo>; + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopl_out_hdmi>; + }; + + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_dsi>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "fullscreen"; + charge_logo,mode = "center"; + connect = <&vopl_out_dsi1>; + }; + + route_edp: route-edp { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vopb_out_edp>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; + //assigned-clock-parents = <&cru PLL_VPLL>; + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; + //assigned-clock-parents = <&cru PLL_CPLL>; + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&edp_in_vopl { + status = "disabled"; +}; +&edp_in_vopb { + status = "okay"; +}; + + +&hdmi_in_vopb { + status = "disabled"; +}; +&hdmi_in_vopl { + status = "okay"; +}; + + +&route_edp { + status = "okay"; + //status = "disabled"; +}; + +&route_hdmi { + status = "okay"; + //status = "disabled"; +}; + + +&i2c4 { + status = "okay"; + + goodix_ts@5d { + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; + goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>; + goodix,cfg-group0 = [ + + 64 80 07 38 04 0A 3D 00 01 C8 28 0F + 55 37 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 90 30 AA 25 27 0F 0A 00 00 + 00 5A 03 11 00 00 00 00 00 00 00 00 + 00 25 00 19 37 94 D5 02 08 14 00 04 + 9B 1B 00 8E 1F 00 80 25 00 76 2B 00 + 6E 32 00 6E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 10 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + 00 00 00 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 19 1B 1C 1E 1F 20 21 22 23 24 + 25 26 27 28 29 2A 00 00 00 00 00 00 + 00 00 00 00 B7 01]; + }; + +}; + +&pinctrl{ + pwr_5v { + pwr_en: pwr-en { + rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>, + <4 30 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3399/rp-rk3399-board.dtsi b/rk3399/rp-rk3399-board.dtsi new file mode 100755 index 0000000..edc32f6 --- /dev/null +++ b/rk3399/rp-rk3399-board.dtsi @@ -0,0 +1,323 @@ + +#include "dt-bindings/pwm/pwm.h" +#include "dt-bindings/input/input.h" +#include "../rk3399.dtsi" +#include "../rk3399-opp.dtsi" +#include "../rk3399-linux.dtsi" + +#include + +/ { + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v8_s3: vcca1v8_s3: vcc1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + }; + + vcc3v0_sd: vcc3v0-sd { + status = "disabled"; + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vdd_log: vdd-log { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 25000 1>; + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + vin-supply = <&vcc_sys>; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + +}; + +&pwm2 { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_thermal { + trips { + cpu_hot: cpu_hot { + hysteresis = <10000>; + temperature = <55000>; + type = "active"; + }; + }; + + cooling-maps { + map2 { + //cooling-device = + // <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&cpu_hot>; + }; + }; +}; + +&emmc_phy { + status = "okay"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&dfi { + status = "disabled"; +}; + +&dmc { + status = "disabled"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 800000 + SYS_STATUS_REBOOT 528000 + SYS_STATUS_SUSPEND 200000 + SYS_STATUS_VIDEO_1080P 200000 + SYS_STATUS_VIDEO_4K 600000 + SYS_STATUS_VIDEO_4K_10B 800000 + SYS_STATUS_PERFORMANCE 800000 + SYS_STATUS_BOOST 600000 + SYS_STATUS_DUALVIEW 600000 + SYS_STATUS_ISP 600000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 200000 + 763 1893 400000 + 1894 3012 528000 + 3013 99999 800000 + >; + auto-freq-en = <1>; + auto-min-freq = <200000>; +}; + +&spdif { + status = "disabled"; + pinctrl-0 = <&spdif_bus>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&i2c4 { + status = "okay"; +}; + + +&sdmmc { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + sd-uhs-sdr104; + clock-frequency = <150000000>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "disabled"; +}; + + +&saradc { +// vref-supply = <&vcca1v8_s3>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + + +&tsadc { + /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-mode = <1>; + /* tshut polarity 0:LOW 1:HIGH */ + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&uart4 { + status = "disabled"; +}; + +&uart3 { + status = "disabled"; +}; + +&uart2 { + status = "disabled"; +}; + +&uart1 { + status = "disabled"; +}; + +&uart0 { + status = "disabled"; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; + +&hdmi{ + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + +&i2s2 { + status = "disabled"; +}; + +&route_hdmi { + status = "disabled"; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + | RKPM_PWM_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | PWM2_REGULATOR_EN + ) + >; + rockchip,power-ctrl = + <&gpio1 17 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>; +}; diff --git a/rk3399/rp-rk3399.dts b/rk3399/rp-rk3399.dts new file mode 100755 index 0000000..3d730ef --- /dev/null +++ b/rk3399/rp-rk3399.dts @@ -0,0 +1,211 @@ +/dts-v1/; + +#include "rp-rk3399-board.dtsi" + +#include "rp-audio-rt5651.dtsi" +#include "rp-pmu-rk808.dtsi" + +#include "rp-usb2-host0.dtsi" +#include "rp-usb2-host1.dtsi" +//#include "rp-usb3-otg-typeA.dtsi" +#include "rp-usb3-otg-typeC.dtsi" +#include "rp-usb3_1-host.dtsi" + +#include "rp-gpio-key.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-mipi-ov13850-camera.dtsi" +//#include "rp-hdmiin.dtsi" + +#include "rp-wifi-sdio.dtsi" + +#include "rp-bt-uart0.dtsi" + +#include "rp-sdcard-mmc1.dtsi" +#include "rp-gmac.dtsi" + +#include "rp-lcd-hdmi.dtsi" +//#include "rp-lcd-mipi-5-720-1280.dtsi" +#include "rp-lcd-mipi-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-800-1280.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280.dtsi" +//#include "rp-lcd-mipi-8-800-1280-new.dtsi" +//#include "rp-lcd-mipi-10-800-1280.dtsi" +//#include "rp-lcd-mipi-10-1920-1200.dtsi" +//#include "rp-lcd-edp-13.3-1920-1080.dtsi" + + + +/ { + + model = "rp-rk3399"; + compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "cpu-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + compatible = "rp_power"; + + rp_not_deep_sleep = <1>; + status = "okay"; + + /* + * #define GPIO_FUNCTION_OUTPUT 0 + * #define GPIO_FUNCTION_INPUT 1 + * #define GPIO_FUNCTION_IRQ 2 + * #define GPIO_FUNCTION_FLASH 3 + * #define GPIO_FUNCTION_OUTPUT_CTRL 4 //output and creat proc ctrl + * + * you can define the gpio function as above + * on gpio_function = <>; + * + *If you want to set the uboot to high level, add the lower properties + * regulator_uboot_on + */ + + vddio_en { + gpio_num = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + power_en { + gpio_num = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + gsm_power_en { + gpio_num = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + uart5_en { + gpio_num = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + hub_rst { + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + regulator_uboot_on; + }; + + //fan_open { + // gpio_num = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // regulator_uboot_on; + //}; + + run_led { + gpio_num = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + regulator_uboot_on; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + base_value = <0>; //3288_5.1 = 0 3288_7.1.2 = 992 3288_ubuntu = 992 3399_7.1.2 = 1000 3399_ubuntu = 0 + + gpio4c5 { + gpio_num = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; //0:output，1:input + }; + }; +}; + + +&spi1 { + status = "disabled"; + status = "okay"; + max-freq = <50000000>; + spi_test:spi_test@0 { + status = "okay"; + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-cpha; + spi-cpol; + cs-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + }; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcc_1v8>; /* bt656_gpio2ab_ms */ + audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ + sdmmc-supply = <&vcc_sdio>; /* sdmmc_gpio4b_ms */ + gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; //king usb +}; + +//used to bluetooth +&uart0 { + status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; + + + + diff --git a/rk3399/rp-sdcard-mmc1.dtsi b/rk3399/rp-sdcard-mmc1.dtsi new file mode 100755 index 0000000..ba54c58 --- /dev/null +++ b/rk3399/rp-sdcard-mmc1.dtsi @@ -0,0 +1,65 @@ +/{ + vcc3v0_sd: vcc3v0-sd { + status = "okay"; + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwr_h>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc3v0_sd"; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&sdmmc { + broken-cd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + sd-uhs-sdr104; + clock-frequency = <150000000>; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk_rp &sdmmc_cmd_rp &sdmmc_cd_rp &sdmmc_bus4_rp>; + vmmc-supply = <&vcc3v0_sd>; + vqmmc-supply = <&vcc_sdio>; + status = "okay"; +}; + +&pinctrl { + + sd { + sdmmc0_pwr_h: sdmmc0-pwr-h { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + sdmmc_bus4_rp: sdmmc-bus4-rp { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_8ma>, + <4 RK_PB1 1 &pcfg_pull_up_8ma>, + <4 RK_PB2 1 &pcfg_pull_up_8ma>, + <4 RK_PB3 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_clk_rp: sdmmc-clk-rp { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd_rp: sdmmc-cmd-rp { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_8ma>; + }; + + sdmmc_cd_rp: sdmmc-cd-rp { + rockchip,pins = + <0 RK_PA7 1 &pcfg_pull_up_8ma>; + }; + }; + +}; diff --git a/rk3399/rp-spdif.dtsi b/rk3399/rp-spdif.dtsi new file mode 100755 index 0000000..824c0c3 --- /dev/null +++ b/rk3399/rp-spdif.dtsi @@ -0,0 +1,27 @@ +/{ + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; +}; + +&spdif { + status = "okay"; + pinctrl-0 = <&spdif_bus>; //<4 RK_PC5 1 &pcfg_pull_none>; + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + #sound-dai-cells = <0>; +}; + +&spdif_out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; +}; \ No newline at end of file diff --git a/rk3399/rp-spi1-uart.dtsi b/rk3399/rp-spi1-uart.dtsi new file mode 100755 index 0000000..1685bcc --- /dev/null +++ b/rk3399/rp-spi1-uart.dtsi @@ -0,0 +1,18 @@ + +&spi1 { + status = "okay"; + spi_wk2xxx: spi_wk2xxx@0{ + status = "okay"; + compatible = "spi-wk2xxx"; + reg = <0>; + spi-max-frequency = <10000000>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + irq-gpio = <&gpio1 20 IRQ_TYPE_EDGE_FALLING>; + cs-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; +}; + + +&uart4 { + status = "disabled"; +}; \ No newline at end of file diff --git a/rk3399/rp-uarts.dtsi b/rk3399/rp-uarts.dtsi new file mode 100755 index 0000000..6d2fe50 --- /dev/null +++ b/rk3399/rp-uarts.dtsi @@ -0,0 +1,45 @@ +//used to bluetooth +&uart0 { + status = "okay"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 0>, <&dmac_peri 1>; +}; + +//conflicts to ethernet +&uart1 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 2>, <&dmac_peri 3>; +}; + +//conflicts to debugger +&uart2 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 4>, <&dmac_peri 5>; +}; + +//conflicts to ethernet +&uart3 { + status = "disabled"; + //dma-names = "tx", "rx"; + //dmas = <&dmac_peri 6>, <&dmac_peri 7>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + dma-names = "tx", "rx"; + dmas = <&dmac_peri 8>, <&dmac_peri 9>; +}; + +&fiq_debugger { + rockchip,serial-id = <2>; //uart2 + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <1>; + compatible = "rockchip,fiq-debugger"; + rockchip,baudrate = <115200>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; +}; diff --git a/rk3399/rp-usb-typea.dtsi b/rk3399/rp-usb-typea.dtsi new file mode 100755 index 0000000..9f2c2dc --- /dev/null +++ b/rk3399/rp-usb-typea.dtsi @@ -0,0 +1,77 @@ + + + + +&cdn_dp { + status = "disabled"; + phys = <&tcphy0_dp>; +}; + +&tcphy0 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + status = "okay"; + }; +}; + + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "device"; + usb3-power-gpio = <&gpio0 6 GPIO_ACTIVE_HIGH>; //4 26 +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + diff --git a/rk3399/rp-usb-typec.dtsi b/rk3399/rp-usb-typec.dtsi new file mode 100755 index 0000000..e6f5791 --- /dev/null +++ b/rk3399/rp-usb-typec.dtsi @@ -0,0 +1,177 @@ +#include "dt-bindings/usb/pd.h" + +/ { + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vbus_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + + + +&i2c4 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + }; + }; + }; +}; + + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + status = "okay"; + }; +}; + + + +&tcphy0 { + status = "okay"; + svid = <0xff01>; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + + +&pinctrl { + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3399/rp-usb2-host0.dtsi b/rk3399/rp-usb2-host0.dtsi new file mode 100755 index 0000000..279832f --- /dev/null +++ b/rk3399/rp-usb2-host0.dtsi @@ -0,0 +1,21 @@ +//USB2.0-host0 + +&u2phy0 { + status = "okay"; + + u2phy0_host: host-port { + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; + phys = <&u2phy0_host>; + phy-names = "usb"; +}; + +&usb_host0_ohci { + status = "okay"; + phys = <&u2phy0_host>; + phy-names = "usb"; +}; \ No newline at end of file diff --git a/rk3399/rp-usb2-host1.dtsi b/rk3399/rp-usb2-host1.dtsi new file mode 100755 index 0000000..7b51967 --- /dev/null +++ b/rk3399/rp-usb2-host1.dtsi @@ -0,0 +1,21 @@ +//USB2.0-host1 + +&u2phy1 { + status = "okay"; + + u2phy1_host: host-port { + status = "okay"; + }; +}; + +&usb_host1_ehci { + status = "okay"; + phys = <&u2phy1_host>; + phy-names = "usb"; +}; + +&usb_host1_ohci { + status = "okay"; + phys = <&u2phy1_host>; + phy-names = "usb"; +}; \ No newline at end of file diff --git a/rk3399/rp-usb3-otg-typeA.dtsi b/rk3399/rp-usb3-otg-typeA.dtsi new file mode 100755 index 0000000..a510492 --- /dev/null +++ b/rk3399/rp-usb3-otg-typeA.dtsi @@ -0,0 +1,72 @@ +//USB3.0-otg-typec + +/ { + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_otg_vbus: otg-vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_otg_vbus"; + //regulator-min-microvolt = <5000000>; + //regulator-max-microvolt = <5000000>; + enable-active-low; + //regulator-always-on; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + }; + +}; + +&pinctrl { + usb{ + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + vbus-supply = <&vcc_otg_vbus>; + status = "okay"; + }; + +}; + +&tcphy0{ + status = "okay"; + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; +}; + +&cdn_dp { + compatible = "rockchip,rk3399-cdn-dp"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + status = "disabled"; +}; + + +&usbdrd3_0{ + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; //device or host + extcon = <&u2phy0>; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + status = "okay"; +}; + + diff --git a/rk3399/rp-usb3-otg-typeC.dtsi b/rk3399/rp-usb3-otg-typeC.dtsi new file mode 100755 index 0000000..45ab266 --- /dev/null +++ b/rk3399/rp-usb3-otg-typeC.dtsi @@ -0,0 +1,153 @@ +//USB3.0-otg-typec + +#include "dt-bindings/usb/pd.h" + +/ { + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vbus_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + +&i2c4 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + }; + }; + }; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; +}; + +&tcphy0 { + status = "okay"; + svid = <0xff01>; + orientation-switch; + tcphy0_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy0_usb3: usb3-port { + #phy-cells = <0>; + }; + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + phys = <&u2phy0_otg>, <&tcphy0_usb3>; + phy-names = "usb2-phy", "usb3-phy"; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&cdn_dp { + status = "disabled"; +}; + +&pinctrl { + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; \ No newline at end of file diff --git a/rk3399/rp-usb3_1-host.dtsi b/rk3399/rp-usb3_1-host.dtsi new file mode 100755 index 0000000..c97dd14 --- /dev/null +++ b/rk3399/rp-usb3_1-host.dtsi @@ -0,0 +1,37 @@ +//USB3.1 HOST +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&tcphy1 { + status = "okay"; + + tcphy1_dp: dp-port { + #phy-cells = <0>; + }; + + tcphy1_usb3: usb3-port { + #phy-cells = <0>; + }; +}; + +&cdn_dp { + compatible = "rockchip,rk3399-cdn-dp"; + phys = <&tcphy0_dp>, <&tcphy1_dp>; + status = "disabled"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; + dr_mode = "host"; + phy-names = "usb2-phy", "usb3-phy"; + phys = <&u2phy1_otg>, <&tcphy1_usb3>; +}; \ No newline at end of file diff --git a/rk3399/rp-wifi-sdio.dtsi b/rk3399/rp-wifi-sdio.dtsi new file mode 100755 index 0000000..9dd0326 --- /dev/null +++ b/rk3399/rp-wifi-sdio.dtsi @@ -0,0 +1,72 @@ +/ { + /*sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk808 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ +/* reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ +// }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6210"; + sdio_vref = <1800>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_enable_h>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ + WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + + +&sdio0 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + //mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +/*&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; +*/ +&pinctrl { + /*sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; +*/ + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; +}; diff --git a/rk3399k-opp.dtsi b/rk3399k-opp.dtsi new file mode 100644 index 0000000..59f200e --- /dev/null +++ b/rk3399k-opp.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +&cluster0_opp { + rockchip,high-temp = <70000>; + rockchip,high-temp-max-volt = <1125000>; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <1150000 1150000 1250000>; + clock-latency-ns = <40000>; + }; +}; + +&cluster1_opp { + rockchip,high-temp = <70000>; + rockchip,high-temp-max-volt = <1200000>; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1250000 1250000 1250000>; + clock-latency-ns = <40000>; + }; +}; diff --git a/rk3399pro-evb-lp4-v11-linux.dts b/rk3399pro-evb-lp4-v11-linux.dts new file mode 100644 index 0000000..0277a18 --- /dev/null +++ b/rk3399pro-evb-lp4-v11-linux.dts @@ -0,0 +1,1323 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3399pro.dtsi" +#include "rk3399-linux.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,rk3399pro-evb-v11-linux", "rockchip,rk3399pro"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + interrupts = ; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + rk809_sound: rk809-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk809-codec"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1>; + rockchip,codec = <&rk809_codec>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + usbacm_video_control: usbacm-video-control { + compatible = "rockchip,usbacm-video-control"; + status = "disabled"; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; + upthreshold = <40>; + downdifferential = <20>; + system-status-freq = < + /*system status freq(KHz)*/ + SYS_STATUS_NORMAL 856000 + SYS_STATUS_REBOOT 856000 + SYS_STATUS_SUSPEND 328000 + SYS_STATUS_VIDEO_1080P 666000 + SYS_STATUS_VIDEO_4K 856000 + SYS_STATUS_VIDEO_4K_10B 856000 + SYS_STATUS_PERFORMANCE 856000 + SYS_STATUS_BOOST 856000 + SYS_STATUS_DUALVIEW 856000 + SYS_STATUS_ISP 856000 + >; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 762 416000 + 763 3012 666000 + 3013 99999 856000 + >; + + vop-pn-msch-readlatency = < + 0 0x20 + 4 0x20 + >; + + auto-min-freq = <328000>; + auto-freq-en = <0>; +}; + +&dmc_opp_table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-328000000 { + opp-hz = /bits/ 64 <328000000>; + opp-microvolt = <900000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-416000000 { + opp-hz = /bits/ 64 <416000000>; + opp-microvolt = <900000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-666000000 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; + opp-856000000 { + opp-hz = /bits/ 64 <856000000>; + opp-microvolt = <900000>; + }; + opp-928000000 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <900000>; + status = "disabled"; + }; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&fiq_debugger { + pinctrl-0 = <&uart2a_xfer>; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int_l>; + pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk809_slppin_null>; + rockchip,system-power-controller; + pmic-reset-func = <0>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk809_slppin_null: rk809_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk809_slppin_slp: rk809_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk809_slppin_pwrdn: rk809_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk809_slppin_rst: rk809_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-name = "vcc5v0_usb"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; + + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; + reg = <0x10>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + bq25700: bq25700@6b { + compatible = "ti,bq25703"; + reg = <0x6b>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok_int>; + ti,charge-current = <1500000>; + ti,max-charge-voltage = <8704000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,input-current-dc = <2000000>; + ti,minimum-sys-voltage = <6700000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + ti,input-current = <500000>; + pd-charge-only = <0>; + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + mpu6500@68 { + status = "okay"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <0>; + mpu-debug = <1>; + }; + + sensor@d { + status = "okay"; + compatible = "ak8963"; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <3>; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx327: imx327@1a { + compatible = "sony,imx327"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ucam_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c8 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <100000>; + + fusb0: fusb30x@22 { + compatible = "fairchild,fusb302"; + reg = <0x22>; + pinctrl-names = "default"; + pinctrl-0 = <&fusb0_int>; + int-n-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + vbus-5v-gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + +}; + +&i2s1 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + audio-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + mipi_in_ucam2: endpoint@2 { + reg = <2>; + remote-endpoint = <&ucam_out2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rkisp1_0 { + status = "okay"; + assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <594000000>, <594000000>, <37125000>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = ; + rockchip,pwm-regulator-config = ; + rockchip,power-ctrl = + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&route_edp { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&spi1 { + status = "okay"; + max-freq = <48000000>; /* spi internal clk, don't modify */ + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&tcphy0 { + status = "okay"; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + extcon = <&fusb0>; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&npu_ref_clk>; + + bq2570 { + charger_ok_int: charger-ok-int { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd_rst { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + npu_clk { + npu_ref_clk: npu-ref-clk { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_down>; + }; + + soc_slppin_rst: soc-slppin-rst { + rockchip,pins = + <1 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>, + <4 RK_PB1 1 &pcfg_pull_up_10ma>, + <4 RK_PB2 1 &pcfg_pull_up_10ma>, + <4 RK_PB3 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_10ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_10ma>; + }; + }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/rk3399pro-evb-v10-linux.dts b/rk3399pro-evb-v10-linux.dts new file mode 100644 index 0000000..dbcc441 --- /dev/null +++ b/rk3399pro-evb-v10-linux.dts @@ -0,0 +1,1271 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3399pro.dtsi" +#include "rk3399-linux.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,rk3399pro-evb-v10-linux", "rockchip,rk3399pro"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + interrupts = ; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + rk809_sound: rk809-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk809-codec"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1>; + rockchip,codec = <&rk809_codec>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&fiq_debugger { + pinctrl-0 = <&uart2a_xfer>; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int_l>; + pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk809_slppin_rst>; + rockchip,system-power-controller; + pmic-reset-func = <0>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk809_slppin_null: rk809_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk809_slppin_slp: rk809_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk809_slppin_pwrdn: rk809_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk809_slppin_rst: rk809_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_log: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_log"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-name = "vcc5v0_usb"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; + + vdd_cpu_b: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + status = "okay"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + bq25700: bq25700@6b { + compatible = "ti,bq25703"; + reg = <0x6b>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok_int>; + ti,charge-current = <1500000>; + ti,max-charge-voltage = <8704000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,input-current-dc = <2000000>; + ti,minimum-sys-voltage = <6700000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + ti,input-current = <500000>; + pd-charge-only = <0>; + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + mpu6500@68 { + status = "okay"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <0>; + mpu-debug = <1>; + }; + + sensor@d { + status = "okay"; + compatible = "ak8963"; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <3>; + }; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "disabled"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + lens-focus = <&vm149c>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx327: imx327@1a { + compatible = "sony,imx327"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ucam_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c8 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <100000>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&tcphy0_orientation_switch>; + }; + }; + }; + }; + }; + +}; + +&i2s1 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + audio-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + + mipi_in_ucam2: endpoint@2 { + reg = <2>; + remote-endpoint = <&ucam_out2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rkisp1_0 { + status = "okay"; + assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <594000000>, <594000000>, <37125000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = ; + rockchip,pwm-regulator-config = ; + rockchip,power-ctrl = + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&route_edp { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&spi1 { + status = "okay"; + max-freq = <48000000>; /* spi internal clk, don't modify */ + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&tcphy0 { + status = "okay"; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&npu_ref_clk>; + + bq2570 { + charger_ok_int: charger-ok-int { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd_rst { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + npu_clk { + npu_ref_clk: npu-ref-clk { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc-slppin-rst { + rockchip,pins = + <1 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>, + <4 RK_PB1 1 &pcfg_pull_up_10ma>, + <4 RK_PB2 1 &pcfg_pull_up_10ma>, + <4 RK_PB3 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_10ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_10ma>; + }; + }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/rk3399pro-evb-v10.dts b/rk3399pro-evb-v10.dts new file mode 100644 index 0000000..80663f0 --- /dev/null +++ b/rk3399pro-evb-v10.dts @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "rk3399pro.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,rk3399pro-evb-v10", "rockchip,rk3399pro"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&fiq_debugger { + pinctrl-0 = <&uart2a_xfer>; +}; + +&firmware_android { + compatible = "android,firmware"; + fstab { + compatible = "android,fstab"; + system { + compatible = "android,system"; + dev = "/dev/block/by-name/system"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/by-name/vendor"; + type = "ext4"; + mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; + fsmgr_flags = "wait,verify"; + }; + }; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_dp_sound { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int_l>; + pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>,<&rk809_slppin_rst>; + rockchip,system-power-controller; + pmic-reset-func = <0>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk809_slppin_null: rk809_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk809_slppin_slp: rk809_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk809_slppin_pwrdn: rk809_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk809_slppin_rst: rk809_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_log: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_log"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_usb"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; + + vdd_cpu_b: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + status = "okay"; + reg = <0x41>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + bq25700: bq25700@6b { + compatible = "ti,bq25703"; + reg = <0x6b>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok_int>; + ti,charge-current = <1500000>; + ti,max-charge-voltage = <8704000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,input-current-dc = <2000000>; + ti,minimum-sys-voltage = <6700000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + ti,input-current = <500000>; + pd-charge-only = <0>; + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + mpu6500@68 { + status = "okay"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <0>; + orientation-y= <0>; + orientation-z= <1>; + mpu-debug = <1>; + }; + + sensor@d { + status = "okay"; + compatible = "ak8963"; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <3>; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c8 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <100000>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&tcphy0_orientation_switch>; + }; + }; + }; + }; + }; +}; + +&i2s1 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + audio-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + status = "disabled"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rk_key { + status = "disabled"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = ; + rockchip,pwm-regulator-config = ; + rockchip,power-ctrl = + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&route_edp { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&spi1 { + status = "okay"; + max-freq = <48000000>; /* spi internal clk, don't modify */ + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&tcphy0 { + status = "okay"; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&npu_ref_clk>; + + bq2570 { + charger_ok_int: charger-ok-int { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd_rst { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + npu_clk { + npu_ref_clk: npu-ref-clk { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>, + <4 RK_PB1 1 &pcfg_pull_up_10ma>, + <4 RK_PB2 1 &pcfg_pull_up_10ma>, + <4 RK_PB3 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_10ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_10ma>; + }; + }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk3399pro-evb-v11-linux.dts b/rk3399pro-evb-v11-linux.dts new file mode 100644 index 0000000..a1204d2 --- /dev/null +++ b/rk3399pro-evb-v11-linux.dts @@ -0,0 +1,1299 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3399pro.dtsi" +#include "rk3399-linux.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + compatible = "rockchip,rk3399pro-evb-v11-linux", "rockchip,rk3399pro"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */ + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + interrupts = ; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + rk809_sound: rk809-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk809-codec"; + rockchip,codec-hp-det; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1>; + rockchip,codec = <&rk809_codec>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + usbacm_video_control: usbacm-video-control { + compatible = "rockchip,usbacm-video-control"; + status = "disabled"; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopb { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&fiq_debugger { + pinctrl-0 = <&uart2a_xfer>; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vopl { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int_l>; + pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk809_slppin_null>; + rockchip,system-power-controller; + pmic-reset-func = <0>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk809_slppin_null: rk809_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk809_slppin_slp: rk809_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk809_slppin_pwrdn: rk809_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk809_slppin_rst: rk809_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-name = "vcc5v0_usb"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; + + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; + reg = <0x10>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <1000>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + bq25700: bq25700@6b { + compatible = "ti,bq25703"; + reg = <0x6b>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok_int>; + ti,charge-current = <1500000>; + ti,max-charge-voltage = <8704000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,input-current-dc = <2000000>; + ti,minimum-sys-voltage = <6700000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + ti,input-current = <500000>; + pd-charge-only = <0>; + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + mpu6500@68 { + status = "okay"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <1>; + orientation-y= <0>; + orientation-z= <0>; + mpu-debug = <1>; + }; + + sensor@d { + status = "okay"; + compatible = "ak8963"; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <3>; + }; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + + lens-focus = <&vm149c>; + + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx327: imx327@1a { + compatible = "sony,imx327"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ucam_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c8 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <100000>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&tcphy0_orientation_switch>; + }; + }; + }; + }; + }; +}; + +&i2s1 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + audio-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + /* Unlinked camera */ + //remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + + mipi_in_ucam2: endpoint@2 { + reg = <2>; + remote-endpoint = <&ucam_out2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + status = "okay"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rkisp1_0 { + status = "okay"; + assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>; + assigned-clock-rates = <594000000>, <594000000>, <37125000>; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&rkisp1_1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_tx1rx1_out>; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = ; + rockchip,pwm-regulator-config = ; + rockchip,power-ctrl = + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&route_edp { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&spi1 { + status = "okay"; + max-freq = <48000000>; /* spi internal clk, don't modify */ + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&tcphy0 { + status = "okay"; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&npu_ref_clk>; + + bq2570 { + charger_ok_int: charger-ok-int { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + camera { + cam_pwren_high: cam-pwren-high { + rockchip,pins = + <4 RK_PC5 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd_rst { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + npu_clk { + npu_ref_clk: npu-ref-clk { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_down>; + }; + + soc_slppin_rst: soc-slppin-rst { + rockchip,pins = + <1 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>, + <4 RK_PB1 1 &pcfg_pull_up_10ma>, + <4 RK_PB2 1 &pcfg_pull_up_10ma>, + <4 RK_PB3 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_10ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_10ma>; + }; + }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ +/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ diff --git a/rk3399pro-evb-v11.dts b/rk3399pro-evb-v11.dts new file mode 100644 index 0000000..32194fe --- /dev/null +++ b/rk3399pro-evb-v11.dts @@ -0,0 +1,1111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + +/dts-v1/; +#include +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3399pro.dtsi" +#include "rk3399-android.dtsi" +#include "rk3399-opp.dtsi" +#include "rk3399-vop-clk-set.dtsi" + +/ { + model = "Rockchip RK3399pro evb v11 board"; + compatible = "rockchip,rk3399pro-evb-v11", "rockchip,rk3399pro"; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 2>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + esc-key { + linux,code = ; + label = "esc"; + press-threshold-microvolt = <1310000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <987000>; + }; + + home-key { + linux,code = ; + label = "home"; + press-threshold-microvolt = <624000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <300000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + enable-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + }; + + clkin_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_gmac"; + #clock-cells = <0>; + }; + + hdmi_sound: hdmi-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,hdmi"; + + simple-audio-card,cpu { + sound-dai = <&i2s2>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + panel: panel { + compatible = "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + reset-delay-ms = <20>; + width-mm = <120>; + height-mm = <160>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in: endpoint { + remote-endpoint = <&edp_out>; + }; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s1>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + }; + + vbus_typec: vbus-typec-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 18 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_typec0_en>; + regulator-name = "vbus_typec"; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_sys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + sdio_vref = <1800>; + WIFI,host_wake_irq = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart0_rts>, <&bt_irq_gpio>; + pinctrl-1 = <&uart0_gpios>; + BT,reset_gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cdn_dp { + status = "okay"; + phys = <&tcphy0_dp>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_b>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_b>; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_center>; +}; + +&dp_in_vopb { + status = "disabled"; +}; + +&edp { + status = "okay"; + force-hpd; + + ports { + port@1 { + reg = <1>; + + edp_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&edp_in_vopl { + status = "disabled"; +}; + +&emmc_phy { + status = "okay"; +}; + +&fiq_debugger { + pinctrl-0 = <&uart2a_xfer>; +}; + +&gmac { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_RMII_SRC>; + assigned-clock-parents = <&clkin_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x28>; + rx_delay = <0x11>; + status = "okay"; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&hdmi { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,phy-table = + <74250000 0x8009 0x0004 0x0272>, + <165000000 0x802b 0x0004 0x0209>, + <297000000 0x8039 0x0005 0x028d>, + <594000000 0x8039 0x0000 0x00f6>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_dp_sound { + status = "okay"; +}; + +&hdmi_in_vopb { + status = "disabled"; +}; + +&i2s2 { + #sound-dai-cells = <0>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + i2c-scl-rising-time-ns = <180>; + i2c-scl-falling-time-ns = <30>; + clock-frequency = <400000>; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int_l>; + pinctrl-1 = <&soc_slppin_slp>, <&rk809_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk809_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>,<&rk809_slppin_null>; + rockchip,system-power-controller; + pmic-reset-func = <0>; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + rtc { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk809_slppin_null: rk809_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk809_slppin_slp: rk809_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk809_slppin_pwrdn: rk809_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk809_slppin_rst: rk809_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_center: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_center"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu_l"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-name = "vcc_buck5"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vcca_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc0v9_soc: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-name = "vcc0v9_soc"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1v5_dvp: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vdd1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + + regulator-name = "vcc_1v5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v0: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-name = "vcc_3v0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sd: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc5v0_usb"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru SCLK_I2S_8CH_OUT>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_8ch_mclk>; + hp-volume = <20>; + spk-volume = <3>; + status = "okay"; + }; + }; + + vdd_cpu_b: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu_b"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: tcs4526@10 { + compatible = "tcs,tcs4526"; + reg = <0x10>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel2_gpio>; + vsel-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <735000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + bq25700: bq25700@6b { + compatible = "ti,bq25703"; + reg = <0x6b>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok_int>; + ti,charge-current = <1500000>; + ti,max-charge-voltage = <8704000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,input-current-dc = <2000000>; + ti,minimum-sys-voltage = <6700000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <500000>; + ti,input-current = <500000>; + pd-charge-only = <0>; + status = "disabled"; + }; +}; + +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <140>; + i2c-scl-falling-time-ns = <30>; + + mpu6500@68 { + status = "okay"; + compatible = "invensense,mpu6500"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PD2 IRQ_TYPE_EDGE_RISING>; + mpu-int_config = <0x10>; + mpu-level_shifter = <0>; + mpu-orientation = <0 1 0 1 0 0 0 0 1>; + orientation-x= <0>; + orientation-y= <0>; + orientation-z= <1>; + mpu-debug = <1>; + }; + + sensor@d { + status = "okay"; + compatible = "ak8963"; + reg = <0x0d>; + type = ; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <3>; + }; +}; + +&i2c4 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PC3 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c8 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + clock-frequency = <100000>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&tcphy0_orientation_switch>; + }; + }; + }; + }; + }; +}; + +&i2s1 { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + audio-supply = <&vcca_1v8>; + sdmmc-supply = <&vccio_sd>; + gpio1830-supply = <&vcc_3v0>; +}; + +&isp0_mmu { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&pcie_phy { + status = "disabled"; +}; + +&pcie0 { + status = "disabled"; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + | RKPM_SLP_PERILPPD + | RKPM_SLP_DDR_RET + | RKPM_SLP_PLLPD + | RKPM_SLP_CENTER_PD + | RKPM_SLP_OSC_DIS + | RKPM_SLP_AP_PWROFF + ) + >; + rockchip,wakeup-config = ; + rockchip,pwm-regulator-config = ; + rockchip,power-ctrl = + <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>, + <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&route_edp { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdmmc { + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&spi1 { + status = "okay"; + max-freq = <48000000>; /* spi internal clk, don't modify */ + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&tcphy0 { + status = "okay"; + orientation-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + tcphy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&tcphy1 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&u2phy1 { + status = "okay"; + + u2phy1_otg: otg-port { + status = "okay"; + }; + + u2phy1_host: host-port { + phy-supply = <&vcc5v0_usb>; + status = "okay"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vopb { + assigned-clocks = <&cru DCLK_VOP0_DIV>; + assigned-clock-parents = <&cru PLL_CPLL>; +}; + +&vopl { + assigned-clocks = <&cru DCLK_VOP1_DIV>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&npu_ref_clk>; + + bq2570 { + charger_ok_int: charger-ok-int { + rockchip,pins = + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd_rst { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + npu_clk { + npu_ref_clk: npu-ref-clk { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + vsel2_gpio: vsel2-gpio { + rockchip,pins = + <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <1 RK_PA5 1 &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sdmmc_bus1: sdmmc-bus1 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + <4 RK_PB0 1 &pcfg_pull_up_10ma>, + <4 RK_PB1 1 &pcfg_pull_up_10ma>, + <4 RK_PB2 1 &pcfg_pull_up_10ma>, + <4 RK_PB3 1 &pcfg_pull_up_10ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = + <4 RK_PB4 1 &pcfg_pull_none_10ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + <4 RK_PB5 1 &pcfg_pull_up_10ma>; + }; + }; + + tp_irq { + tp_irq_gpio: tp-irq-gpio { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_typec0_en: vcc5v0-typec0-en { + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart0_gpios: uart0-gpios { + rockchip,pins = + <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk3399pro-evb-v14-linux.dts b/rk3399pro-evb-v14-linux.dts new file mode 100644 index 0000000..4f8546e --- /dev/null +++ b/rk3399pro-evb-v14-linux.dts @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3399pro-evb-v11-linux.dts" + +/ { + model = "Rockchip RK3399pro evb v14 board for linux"; + compatible = "rockchip,rk3399pro-evb-v14-linux", "rockchip,rk3399pro"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + + dma_trans: dma_trans@3c000000 { + //no-map; + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; +}; + +/delete-node/ &imx327; +/delete-node/ &ov13850; +/delete-node/ &vm149c; +&i2c1 { + status = "okay"; + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + pinctrl-0 = <&i2c1_xfer>, <&cam_pwren_high>; + + jaguar1: jaguar1@30 { + compatible = "jaguar1-v4l2"; + status = "okay"; + reg = <0x30>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* + * pd-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; // conflict with csi-ctl-gpios + * rst-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + */ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "jaguar1"; + rockchip,camera-module-lens-name = "jaguar1"; + port { + cam_out: endpoint { + remote-endpoint = <&usbacm_video_control_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + i2c-scl-rising-time-ns = <345>; + i2c-scl-falling-time-ns = <11>; + + vm149c: vm149c@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13850: ov13850@10 { + compatible = "ovti,ov13850"; + status = "okay"; + reg = <0x10>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-CT0116"; + rockchip,camera-module-lens-name = "Largan-50013A1"; + lens-focus = <&vm149c>; + + port { + ucam_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + imx327: imx327@1a { + compatible = "sony,imx327"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru SCLK_CIF_OUT>; + clock-names = "xvclk"; + /* conflict with csi-ctl-gpios */ + reset-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clkout>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ucam_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_dphy_rx0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbacm_video_control_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_rx0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_mipi_in>; + }; + }; + }; +}; + +&mipi_dphy_tx1rx1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy_tx1rx1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp1_mipi_in>; + }; + }; + }; +}; + +&pcie0 { + /delete-property/ ep-gpios; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + max-link-speed = <1>; + memory-region = <&dma_trans>; + busno = <0>; + rockchip,dma_trx_enabled = <1>; + rockchip,deferred = <1>; + status = "okay"; +}; + +&rkisp1_0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy_rx0_out>; + }; + }; +}; + +&usbacm_video_control { + status = "okay"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "usbacm_video_control"; + rockchip,camera-module-lens-name = "usbacm_video_control"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + usbacm_video_control_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&cam_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbacm_video_control_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; diff --git a/rk3399pro-npu-evb-v10.dts b/rk3399pro-npu-evb-v10.dts new file mode 100644 index 0000000..a7ce00c --- /dev/null +++ b/rk3399pro-npu-evb-v10.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + */ + +/dts-v1/; +#include +#include +#include "rk3399pro-npu.dtsi" + +/ { + model = "Rockchip RK3399pro-npu EVB V10 Board"; + compatible = "rockchip,rk3399pro-npu-evb-v10", "rockchip,rk3399pro-npu"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xff550000 console=ttyFIQ0 init=/init kpti=0"; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + + power { + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + label = "GPIO Power"; + linux,code = <116>; + wakeup-source; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <0>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "regulator-fixed"; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&i2c1 { + status = "okay"; + + vdd_npu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + pinctrl-0 = <&vsel_gpio>; + vsel-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&npu { + npu-supply = <&vdd_npu>; + status = "okay"; +}; + +&combphy { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usbdrd3 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "init", "default"; + pinctrl-0 = <&tsadc_otp_gpio>; + pinctrl-1 = <&tsadc_otp_out>; + status = "okay"; +}; + +&pinctrl { + vsel_gpio: vsel-gpio { + rockchip,pins = + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + pwr_key: pwr-key { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; +}; diff --git a/rk3399pro-npu.dtsi b/rk3399pro-npu.dtsi new file mode 100644 index 0000000..4e0781e --- /dev/null +++ b/rk3399pro-npu.dtsi @@ -0,0 +1,826 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd. + +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3399pro-npu"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + serial2 = &uart2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + dynamic-power-coefficient = <74>; + #cooling-cells = <2>; + power-model { + compatible = "simple-power-model"; + ref-leakage = <31>; + static-coefficient = <100000>; + ts = <597400 241050 (-2450) 70>; + thermal-zone = "soc-thermal"; + }; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + operating-points-v2 = <&cpu0_opp_table>; + dynamic-power-coefficient = <74>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&clkin_32k>; + }; + + usbdrd3: usb { + compatible = "rockchip,rk1808-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru SCLK_USB3_OTG0_REF>, <&cru ACLK_USB3OTG>, + <&cru SCLK_USB3_OTG0_SUSPEND>; + clock-names = "ref_clk", "bus_clk", + "suspend_clk"; + assigned-clocks = <&cru SCLK_USB3_OTG0_SUSPEND>; + assigned-clock-rates = <24000000>; + power-domains = <&power RK1808_PD_PCIE>; + resets = <&cru SRST_USB3_OTG_A>; + reset-names = "usb3-otg"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@fd000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x200000>; + interrupts = ; + dr_mode = "peripheral"; + phys = <&u2phy_otg>, <&combphy PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,tx-ipgap-linecheck-dis-quirk; + status = "disabled"; + }; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rk1808-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfe000000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + npu_pvtm: npu-pvtm { + compatible = "rockchip,rk1808-npu-pvtm"; + clocks = <&cru SCLK_PVTM_NPU>; + clock-names = "npu"; + status = "okay"; + }; + }; + + usb2phy_grf: syscon@fe010000 { + compatible = "rockchip,rk1808-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfe010000 0x0 0x8000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy: usb2-phy@100 { + compatible = "rockchip,rk1808-usb2phy"; + reg = <0x100 0x10>; + clocks = <&cru SCLK_USBPHY_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&u2phy>; + clock-output-names = "usb480m_phy"; + status = "disabled"; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + status = "disabled"; + }; + }; + }; + + combphy_grf: syscon@fe018000 { + compatible = "rockchip,usb3phy-grf", "syscon"; + reg = <0x0 0xfe018000 0x0 0x8000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rk1808-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfe020000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_pvtm: pmu-pvtm { + compatible = "rockchip,rk1808-pmu-pvtm"; + clocks = <&cru SCLK_PVTM_PMU>; + clock-names = "pmu"; + status = "okay"; + }; + }; + + usb_pcie_grf: syscon@fe040000 { + compatible = "rockchip,usb-pcie-grf", "syscon"; + reg = <0x0 0xfe040000 0x0 0x1000>; + }; + + coregrf: syscon@fe050000 { + compatible = "rockchip,rk1808-coregrf", "syscon", "simple-mfd"; + reg = <0x0 0xfe050000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pvtm: pvtm { + compatible = "rockchip,rk1808-pvtm"; + clocks = <&cru SCLK_PVTM_CORE>; + clock-names = "core"; + status = "okay"; + }; + }; + + qos_npu: qos@fe850000 { + compatible = "syscon"; + reg = <0x0 0xfe850000 0x0 0x20>; + }; + + qos_pcie: qos@fe880000 { + compatible = "syscon"; + reg = <0x0 0xfe880000 0x0 0x20>; + status = "disabled"; + }; + + qos_usb2: qos@fe890000 { + compatible = "syscon"; + reg = <0x0 0xfe890000 0x0 0x20>; + status = "disabled"; + }; + + qos_usb3: qos@fe890080 { + compatible = "syscon"; + reg = <0x0 0xfe890080 0x0 0x20>; + status = "disabled"; + }; + + qos_isp: qos@fe8a0000 { + compatible = "syscon"; + reg = <0x0 0xfe8a0000 0x0 0x20>; + }; + + qos_rga_rd: qos@fe8a0080 { + compatible = "syscon"; + reg = <0x0 0xfe8a0080 0x0 0x20>; + }; + + qos_rga_wr: qos@fe8a0100 { + compatible = "syscon"; + reg = <0x0 0xfe8a0100 0x0 0x20>; + }; + + qos_cif: qos@fe8a0180 { + compatible = "syscon"; + reg = <0x0 0xfe8a0180 0x0 0x20>; + }; + + qos_vop_raw: qos@fe8b0000 { + compatible = "syscon"; + reg = <0x0 0xfe8b0000 0x0 0x20>; + }; + + qos_vop_lite: qos@fe8b0080 { + compatible = "syscon"; + reg = <0x0 0xfe8b0080 0x0 0x20>; + }; + + qos_vpu: qos@fe8c0000 { + compatible = "syscon"; + reg = <0x0 0xfe8c0000 0x0 0x20>; + }; + + gic: interrupt-controller@ff100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xff100000 0 0x10000>, /* GICD */ + <0x0 0xff140000 0 0xc0000>, /* GICR */ + <0x0 0xff300000 0 0x10000>, /* GICC */ + <0x0 0xff310000 0 0x10000>, /* GICH */ + <0x0 0xff320000 0 0x10000>; /* GICV */ + interrupts = ; + its: interrupt-controller@ff120000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xff120000 0x0 0x20000>; + }; + }; + + cru: clock-controller@ff350000 { + compatible = "rockchip,rk1808-cru"; + reg = <0x0 0xff350000 0x0 0x5000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_PPLL>, <&cru ARMCLK>, + <&cru MSCLK_PERI>, <&cru LSCLK_PERI>, + <&cru HSCLK_BUS_PRE>, <&cru MSCLK_BUS_PRE>, + <&cru LSCLK_BUS_PRE>; + assigned-clock-rates = + <1188000000>, <1000000000>, + <100000000>, <1200000000>, + <200000000>, <100000000>, + <300000000>, <200000000>, + <100000000>; + }; + + combphy: phy@ff380000 { + compatible = "rockchip,rk1808-combphy"; + reg = <0x0 0xff380000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru SCLK_PCIEPHY_REF>; + clock-names = "refclk"; + assigned-clocks = <&cru SCLK_PCIEPHY_REF>; + assigned-clock-rates = <25000000>; + resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, + <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; + reset-names = "otg-rst", "combphy-por", + "combphy-apb", "combphy-pipe"; + rockchip,combphygrf = <&combphy_grf>; + rockchip,usbpciegrf = <&usb_pcie_grf>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <977>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point-0 { + /* millicelsius */ + temperature = <75000>; + /* millicelsius */ + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + /* millicelsius */ + temperature = <85000>; + /* millicelsius */ + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <4096>; + }; + map1 { + trip = <&target>; + cooling-device = + <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + }; + + tsadc: tsadc@ff3a0000 { + compatible = "rockchip,rk1808-tsadc"; + reg = <0x0 0xff3a0000 0x0 0x100>; + interrupts = ; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <650000>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + status = "disabled"; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rk1808-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff3e0000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk1808-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + pd_npu@RK1808_VD_NPU { + reg = ; + clocks = <&cru SCLK_NPU>, + <&cru ACLK_NPU>, + <&cru HCLK_NPU>; + pm_qos = <&qos_npu>; + }; + + /* These power domains are grouped by VD_LOGIC */ + pd_pcie@RK1808_PD_PCIE { + reg = ; + clocks = <&cru HSCLK_PCIE>, + <&cru LSCLK_PCIE>, + <&cru ACLK_PCIE>, + <&cru ACLK_PCIE_MST>, + <&cru ACLK_PCIE_SLV>, + <&cru PCLK_PCIE>, + <&cru SCLK_PCIE_AUX>, + <&cru SCLK_PCIE_AUX>, + <&cru ACLK_USB3OTG>, + <&cru HCLK_HOST>, + <&cru HCLK_HOST_ARB>, + <&cru SCLK_USB3_OTG0_REF>, + <&cru SCLK_USB3_OTG0_SUSPEND>; + pm_qos = <&qos_pcie>, + <&qos_usb2>, + <&qos_usb3>; + }; + pd_vpu@RK1808_PD_VPU { + reg = ; + clocks = <&cru ACLK_VPU>, + <&cru HCLK_VPU>; + pm_qos = <&qos_vpu>; + }; + pd_vio@RK1808_PD_VIO { + reg = ; + clocks = <&cru HSCLK_VIO>, + <&cru LSCLK_VIO>, + <&cru ACLK_VOPRAW>, + <&cru HCLK_VOPRAW>, + <&cru ACLK_VOPLITE>, + <&cru HCLK_VOPLITE>, + <&cru PCLK_DSI_TX>, + <&cru PCLK_CSI_TX>, + <&cru ACLK_RGA>, + <&cru HCLK_RGA>, + <&cru ACLK_ISP>, + <&cru HCLK_ISP>, + <&cru ACLK_CIF>, + <&cru HCLK_CIF>, + <&cru PCLK_CSI2HOST>, + <&cru DCLK_VOPRAW>, + <&cru DCLK_VOPLITE>; + pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, + <&qos_isp>, <&qos_cif>, + <&qos_vop_raw>, <&qos_vop_lite>; + }; + }; + }; + + i2c0: i2c@ff410000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff410000 0x0 0x1000>; + clocks = <&cru SCLK_PMU_I2C0>, <&cru PCLK_I2C0_PMU>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac: dmac@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff4e0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + i2c1: i2c@ff500000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xff500000 0x0 0x1000>; + clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart2: serial@ff550000 { + compatible = "rockchip,rk1808-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff550000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 4>, <&dmac 5>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + rktimer: rktimer@ff700000 { + compatible = "rockchip,rk3288-timer"; + reg = <0x0 0xff700000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + npu: npu@ffbc0000 { + compatible = "rockchip,npu"; + reg = <0x0 0xffbc0000 0x0 0x1000>; + clocks = <&cru SCLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; + clock-names = "sclk_npu", "aclk_npu", "hclk_npu"; + assigned-clocks = <&cru SCLK_NPU>; + assigned-clock-rates = <800000000>; + interrupts = ; + power-domains = <&power RK1808_VD_NPU>; + operating-points-v2 = <&npu_opp_table>; + #cooling-cells = <2>; + status = "disabled"; + + npu_power_model: power-model { + compatible = "simple-power-model"; + ref-leakage = <31>; + static-coefficient = <100000>; + dynamic-coefficient = <3080>; + ts = <88610 303120 (-5000) 100>; + thermal-zone = "soc-thermal"; + }; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + rockchip,max-volt = <880000>; + rockchip,evb-irdrop = <37500>; + + rockchip,pvtm-voltage-sel = < + 0 69000 0 + 69001 74000 1 + 74001 99999 2 + >; + rockchip,pvtm-freq = <200000>; + rockchip,pvtm-volt = <800000>; + rockchip,pvtm-ch = <0 0>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <(-20) (-26)>; + rockchip,thermal-zone = "soc-thermal"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-microvolt = <750000 750000 880000>; + }; + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <850000 850000 880000>; + opp-microvolt-L0 = <850000 850000 880000>; + opp-microvolt-L1 = <825000 825000 880000>; + opp-microvolt-L2 = <800000 800000 880000>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk1808-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff4c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff4c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0_PMU>, <&cru DBCLK_PMU_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff690000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff690000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff6a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff6b0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff6c0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + pcfg_pull_none_2ma_smt: pcfg-pull-none-2ma-smt { + bias-disable; + drive-strength = <2>; + input-schmitt-enable; + }; + + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_input_smt: pcfg-input-smt { + input-enable; + input-schmitt-enable; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_sda */ + <0 RK_PB1 1 &pcfg_pull_none_2ma_smt>, + /* i2c0_scl */ + <0 RK_PB0 1 &pcfg_pull_none_2ma_smt>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_sda */ + <0 RK_PC1 1 &pcfg_pull_none_2ma_smt>, + /* i2c1_scl */ + <0 RK_PC0 1 &pcfg_pull_none_2ma_smt>; + }; + }; + + pciusb { + pciusb_pins: pciusb-pins { + rockchip,pins = + /* pciusb_debug0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* pciusb_debug1 */ + <4 RK_PB5 3 &pcfg_pull_none>, + /* pciusb_debug2 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* pciusb_debug3 */ + <4 RK_PB7 3 &pcfg_pull_none>, + /* pciusb_debug4 */ + <4 RK_PC0 3 &pcfg_pull_none>, + /* pciusb_debug5 */ + <4 RK_PC1 3 &pcfg_pull_none>, + /* pciusb_debug6 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* pciusb_debug7 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <4 RK_PA3 2 &pcfg_pull_up_2ma>, + /* uart2_txm0 */ + <4 RK_PA2 2 &pcfg_pull_up_2ma>; + }; + + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <2 RK_PD1 2 &pcfg_pull_up_2ma>, + /* uart2_txm1 */ + <2 RK_PD0 2 &pcfg_pull_up_2ma>; + }; + + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rxm2 */ + <3 RK_PA4 2 &pcfg_pull_up_2ma>, + /* uart2_txm2 */ + <3 RK_PA3 2 &pcfg_pull_up_2ma>; + }; + }; + + tsadc { + tsadc_otp_gpio: tsadc-otp-gpio { + rockchip,pins = + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + tsadc_otp_out: tsadc-otp-out { + rockchip,pins = + <0 RK_PA6 2 &pcfg_pull_none>; + }; + }; + + xin32k { + clkin_32k: clkin-32k { + rockchip,pins = + <0 RK_PC2 1 &pcfg_input_smt>; + }; + + clkout_32k: clkout-32k { + rockchip,pins = + <0 RK_PC2 1 &pcfg_output_high>; + }; + }; + }; +}; diff --git a/rk3399pro-rock-pi-n10.dts b/rk3399pro-rock-pi-n10.dts new file mode 100644 index 0000000..369de5d --- /dev/null +++ b/rk3399pro-rock-pi-n10.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Radxa Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +/dts-v1/; +#include "rk3399.dtsi" +#include "rk3399-opp.dtsi" +#include +#include "rk3399pro-vmarc-som.dtsi" + +/ { + model = "Radxa ROCK Pi N10"; + compatible = "radxa,rockpi-n10", "vamrs,rk3399pro-vmarc-som", + "rockchip,rk3399pro"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; diff --git a/rk3399pro-vmarc-som.dtsi b/rk3399pro-vmarc-som.dtsi new file mode 100644 index 0000000..5d087be --- /dev/null +++ b/rk3399pro-vmarc-som.dtsi @@ -0,0 +1,457 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2019 Vamrs Limited + * Copyright (c) 2019 Amarula Solutions(India) + */ + +#include +#include +#include + +/ { + compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro"; + + vcc3v3_pcie: vcc-pcie-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwr>; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_l>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_l>; +}; + +&emmc_phy { + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_RMII_SRC>; + phy-supply = <&vcc_lan>; + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_cec>; +}; + +&i2c0 { + clock-frequency = <400000>; + i2c-scl-falling-time-ns = <30>; + i2c-scl-rising-time-ns = <180>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio1>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu_l: DCDC_REG2 { + regulator-name = "vdd_cpu_l"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcca_0v9: LDO_REG1 { + regulator-name = "vcca_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_1v8: LDO_REG2 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_0v9: LDO_REG3 { + regulator-name = "vcc_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcca_1v8: LDO_REG4 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1850000>; + }; + }; + + /* + * As per BSP, but schematic not showing any regulator + * pin for LD05. + */ + vdd1v5_dvp: LDO_REG5 { + regulator-name = "vdd1v5_dvp"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v5: LDO_REG6 { + regulator-name = "vcc_1v5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_3v0: LDO_REG7 { + regulator-name = "vccio_3v0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + /* + * As per BSP, but schematic not showing any regulator + * pin for LD09. + */ + vcc_sd: LDO_REG9 { + regulator-name = "vcc_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_usb2: SWITCH_REG1 { + regulator-name = "vcc5v0_usb2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + vccio_3v3: vcc_lan: SWITCH_REG2 { + regulator-name = "vccio_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + i2c-scl-falling-time-ns = <30>; + i2c-scl-rising-time-ns = <140>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <450>; + i2c-scl-falling-time-ns = <15>; + status = "okay"; +}; + +&io_domains { + status = "okay"; + bt656-supply = <&vcca_1v8>; + gpio1830-supply = <&vccio_3v0>; + sdmmc-supply = <&vccio_sd>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + max-link-speed = <2>; + num-lanes = <4>; + pinctrl-0 = <&pcie_clkreqnb_cpm>; + pinctrl-names = "default"; + vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */ + vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */ + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <4 RK_PD6 0 &pcfg_pull_up>; + }; + }; + + pcie { + pcie_pwr: pcie-pwr { + rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <1 RK_PC2 0 &pcfg_pull_up>; + }; + }; + + vbus_host { + usb1_en_oc: usb1-en-oc { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vbus_typec { + usb0_en_oc: usb0-en-oc { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmu1830-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&sdmmc { + cd-gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + max-frequency = <150000000>; +}; + +&tcphy0 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <1>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; + + u2phy0_otg: otg-port { + phy-supply = <&vbus_typec>; + status = "okay"; + }; + + u2phy0_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; +}; + + +&u2phy1 { + status = "okay"; + + u2phy1_host: host-port { + phy-supply = <&vbus_host>; + status = "okay"; + }; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + status = "okay"; +}; + +&vbus_host { + enable-active-high; + gpio = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; /* USB1_EN_OC# */ + pinctrl-names = "default"; + pinctrl-0 = <&usb1_en_oc>; +}; + +&vbus_typec { + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; /* USB0_EN_OC# */ + pinctrl-names = "default"; + pinctrl-0 = <&usb0_en_oc>; +}; diff --git a/rk3399pro.dtsi b/rk3399pro.dtsi new file mode 100644 index 0000000..bb5ebf6 --- /dev/null +++ b/rk3399pro.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + +#include "rk3399.dtsi" + +/ { + compatible = "rockchip,rk3399pro"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie_phy { + status = "okay"; +}; + +/* Default to enabled since AP talk to NPU part over pcie */ +&pcie0 { + ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + num-lanes = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clkreqn_cpm>; + status = "okay"; +}; diff --git a/rk3528-android.dtsi b/rk3528-android.dtsi new file mode 100644 index 0000000..9b53b1c --- /dev/null +++ b/rk3528-android.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 driver_async_probe=dwmmc_rockchip,rockchip-drm drm_kms_helper.fbdev_emulation=0"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x00800000>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi>; + }; + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_tve>; + }; + }; +}; + +&rng { + status = "okay"; +}; + +&vop { + /* + * VOP3_ESMART_8K_MODE = 0, + * VOP3_ESMART_4K_4K_MODE = 1, + * VOP3_ESMART_4K_2K_2K_MODE = 2, + * VOP3_ESMART_2K_2K_2K_2K_MODE = 3, + */ + esmart_lb_mode = /bits/ 8 <3>; + support-multi-area; +}; diff --git a/rk3528-demo.dtsi b/rk3528-demo.dtsi new file mode 100644 index 0000000..353e75c --- /dev/null +++ b/rk3528-demo.dtsi @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528.dtsi" +#include +#include +#include +#include "rk-stb-ir-keymap.dtsi" + +/ { + acodec_sound: acodec-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rk3528-acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; + + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + ir { + gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + net-red { + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + net-green { + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + }; + pwr-red { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "off"; + retain-state-suspended; + retain-state-shutdown; + }; + pwr-green { + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + default-state = "on"; + retain-state-suspended; + retain-state-shutdown; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&sai3>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <703000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&acodec { + pa-ctl-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rmii0_phy { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&sai0 { + pinctrl-0 = <&i2s0m0_lrck &i2s0m0_sclk &i2s0m0_sdi &i2s0m0_sdo>; + status = "disabled"; +}; + +&sai2 { + status = "okay"; +}; + +&sai3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + fixed-emmc-driver-type = <4>; + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&tve { + status = "okay"; +}; + +&tve_in_vp1 { + status = "okay"; +}; + +&u2phy_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + extcon = <&usb2phy>; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3528-demo1-lp4-v10.dts b/rk3528-demo1-lp4-v10.dts new file mode 100644 index 0000000..995ccfe --- /dev/null +++ b/rk3528-demo1-lp4-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-demo1-lp4-v10.dtsi" +#include "rk3528-android.dtsi" + diff --git a/rk3528-demo1-lp4-v10.dtsi b/rk3528-demo1-lp4-v10.dtsi new file mode 100644 index 0000000..c1f34d0 --- /dev/null +++ b/rk3528-demo1-lp4-v10.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-demo.dtsi" + +/ { + model = "Rockchip RK3528 DEMO1 LP4 V10 Board"; + compatible = "rockchip,rk3528-demo1-lp4-v10", "rockchip,rk3528"; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &wifi_reset &clkm0_32k_out>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m0_rtsn>; + pinctrl-1 = <&uart2m0_gpios>; + BT,reset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8822cs"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&sdio1 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_bus4 &sdio1_cmd &sdio1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer &uart2m0_ctsn>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_reset: wifi-reset { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + wireless-bluetooth { + uart2m0_gpios: uart2m0-gpios { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3528-demo4-ddr4-v10-linux.dts b/rk3528-demo4-ddr4-v10-linux.dts new file mode 100644 index 0000000..fc84bd5 --- /dev/null +++ b/rk3528-demo4-ddr4-v10-linux.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-demo4-ddr4-v10.dtsi" +#include "rk3528-linux.dtsi" + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; +}; + +&sdmmc { + status = "okay"; +}; diff --git a/rk3528-demo4-ddr4-v10.dts b/rk3528-demo4-ddr4-v10.dts new file mode 100644 index 0000000..a3f088c --- /dev/null +++ b/rk3528-demo4-ddr4-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-demo4-ddr4-v10.dtsi" +#include "rk3528-android.dtsi" + diff --git a/rk3528-demo4-ddr4-v10.dtsi b/rk3528-demo4-ddr4-v10.dtsi new file mode 100644 index 0000000..c2af2c2 --- /dev/null +++ b/rk3528-demo4-ddr4-v10.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-demo.dtsi" + +/ { + model = "Rockchip RK3528 DEMO4 DDR4 V10 Board"; + compatible = "rockchip,rk3528-demo4-ddr4-v10", "rockchip,rk3528"; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &wifi_reset>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m0_rtsn>; + pinctrl-1 = <&uart2m0_gpios>; + BT,reset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8822cs"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&sdio1 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio1_bus4 &sdio1_cmd &sdio1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer &uart2m0_ctsn>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_reset: wifi-reset { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + wireless-bluetooth { + uart2m0_gpios: uart2m0-gpios { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3528-demo6-ddr3-v10.dts b/rk3528-demo6-ddr3-v10.dts new file mode 100644 index 0000000..26f79a6 --- /dev/null +++ b/rk3528-demo6-ddr3-v10.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-demo6-ddr3-v10.dtsi" +#include "rk3528-android.dtsi" + +&pdm { + status = "okay"; + pinctrl-0 = <&pdm_clk1 + &pdm_sdi1>; +}; + +&pdmics { + status = "okay"; +}; + +&pdm_mic_array { + status = "okay"; +}; diff --git a/rk3528-demo6-ddr3-v10.dtsi b/rk3528-demo6-ddr3-v10.dtsi new file mode 100644 index 0000000..bf9b4ca --- /dev/null +++ b/rk3528-demo6-ddr3-v10.dtsi @@ -0,0 +1,337 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-demo.dtsi" + +/ { + model = "Rockchip RK3528 DEMO6 DDR3 V10 Board"; + compatible = "rockchip,rk3528-demo6-ddr3-v10", "rockchip,rk3528"; + + /delete-node/ vcc-ddr-s3; + /delete-node/ vcc-3v3-s3; + /delete-node/ vdd-cpu; + /delete-node/ vdd-logic; + /delete-node/ vdd-0v9-s3; + /delete-node/ vdd-1v8-s3; + + /omit-if-no-ref/ + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + regulator-boot-on; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn &bt_enable_h>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "aic8800"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq >; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + //WIFI,reset_gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&gmac0 { + status = "disabled"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus + ð_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + status = "okay"; + reg = <0x18>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + wakeup-source; + gpio-controller; + #gpio-cells = <2>; + #clock-cells = <1>; + clock-output-names = "rk805-clkout1", "rk805-clkout2"; + rockchip,system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_3v3_s3>; + vcc6-supply = <&vcc5v0_sys>; + + rtc { + status = "okay"; + }; + + pwrkey { + status = "disabled"; + }; + + gpio { + status = "okay"; + }; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-init-microvolt = <953000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic: DCDC_REG2 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x1>; + regulator-ramp-delay = <12500>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <712500>; + }; + }; + + vcc_ddr_s3: DCDC_REG3 { + regulator-name = "vcc_ddr_s3"; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + }; + }; + + vcc_3v3_s3: DCDC_REG4 { + regulator-name = "vcc_3v3_s3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-mode = <0x2>; + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_1v8_s3: LDO_REG1 { + regulator-name = "vdd_1v8_s3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_18emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v9_s3: LDO_REG3 { + regulator-name = "vdd_0v9_s3"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC1_VPU_25M>; + }; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_enable_h: bt-enable-h { + rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + |RKPM_SLP_ARMOFF + ) + >; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + post-power-on-delay-ms = <50>; + /delete-property/ rockchip,use-v2-tuning; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; diff --git a/rk3528-evb.dtsi b/rk3528-evb.dtsi new file mode 100644 index 0000000..5d39986 --- /dev/null +++ b/rk3528-evb.dtsi @@ -0,0 +1,676 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528.dtsi" +#include +#include +#include + +/ { + acodec_sound: acodec-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rk3528-acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; + + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + es7243_sound: es7243-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,es7243"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + simple-audio-card,codec { + sound-dai = <&es7243e>; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&sai3>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1148000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_0v9_s3: vdd-0v9-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8_s3: vdd-1v8-s3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_s3: vcc-3v3-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + /omit-if-no-ref/ + vcc_sd: vcc-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ddr_s3: vcc-ddr-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&acodec { + pa-ctl-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&combphy_pu { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&gmac0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&i2c6 { + status = "disabled"; + es7243e: es7243e@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7243E_MicArray_0"; + reg = <0x10>; + }; + + es7243e_11: es7243e@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7243E_MicArray_1"; + reg = <0x11>; + }; + + es7243e_12: es7243e@12 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7243E_MicArray_2"; + reg = <0x12>; + }; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM0_M0_REGULATOR_EN + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&sai0 { + pinctrl-0 = <&i2s0m1_lrck &i2s0m1_sclk &i2s0m1_sdi &i2s0m1_sdo>; + status = "disabled"; +}; + +&sai2 { + status = "okay"; +}; + +&sai3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8_s3>; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc_sd>; + status = "disabled"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&tve { + status = "okay"; +}; + +&tve_in_vp1 { + status = "okay"; +}; + +&u2phy_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy>; + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3528-evb1-ddr4-v10-linux.dts b/rk3528-evb1-ddr4-v10-linux.dts new file mode 100644 index 0000000..c173af5 --- /dev/null +++ b/rk3528-evb1-ddr4-v10-linux.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb1-ddr4-v10.dtsi" +#include "rk3528-linux.dtsi" + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; +}; + +&sdmmc { + status = "okay"; +}; diff --git a/rk3528-evb1-ddr4-v10-spi-nand-linux.dts b/rk3528-evb1-ddr4-v10-spi-nand-linux.dts new file mode 100644 index 0000000..5b87252 --- /dev/null +++ b/rk3528-evb1-ddr4-v10-spi-nand-linux.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb1-ddr4-v10.dtsi" +#include "rk3528-linux.dtsi" + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw rootwait"; + }; +}; + +&sdmmc { + status = "disabled"; +}; + +&sfc { + status = "okay"; + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/rk3528-evb1-ddr4-v10.dts b/rk3528-evb1-ddr4-v10.dts new file mode 100644 index 0000000..b0a5314 --- /dev/null +++ b/rk3528-evb1-ddr4-v10.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb1-ddr4-v10.dtsi" +#include "rk3528-android.dtsi" + +&sdmmc { + status = "okay"; +}; diff --git a/rk3528-evb1-ddr4-v10.dtsi b/rk3528-evb1-ddr4-v10.dtsi new file mode 100644 index 0000000..822d614 --- /dev/null +++ b/rk3528-evb1-ddr4-v10.dtsi @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-evb.dtsi" + +/ { + model = "Rockchip RK3528 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3528-evb1-ddr4-v10", "rockchip,rk3528"; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + +}; + +&es7243_sound { + status = "disabled"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x30>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&sai1 { + status = "okay"; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3528-evb2-ddr3-v10.dts b/rk3528-evb2-ddr3-v10.dts new file mode 100644 index 0000000..24dbe38 --- /dev/null +++ b/rk3528-evb2-ddr3-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb2-ddr3-v10.dtsi" +#include "rk3528-android.dtsi" + diff --git a/rk3528-evb2-ddr3-v10.dtsi b/rk3528-evb2-ddr3-v10.dtsi new file mode 100644 index 0000000..2cd94a6 --- /dev/null +++ b/rk3528-evb2-ddr3-v10.dtsi @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-evb.dtsi" + +/ { + model = "Rockchip RK3528 EVB2 DDR3 V10 Board"; + compatible = "rockchip,rk3528-evb2-ddr3-v10", "rockchip,rk3528"; + + pcie20_usb30_avdd0v9: pcie20-usb30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_usb30-avdd0v9"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vdd_0v9_s3>; + }; + + pcie20_usb30_avdd1v8: pcie20-usb30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_usb30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vdd_1v8_s3>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; + +&usbdrd_dwc3 { + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3528-evb3-lp4x-v10.dts b/rk3528-evb3-lp4x-v10.dts new file mode 100644 index 0000000..07b9218 --- /dev/null +++ b/rk3528-evb3-lp4x-v10.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb3-lp4x-v10.dtsi" +#include "rk3528-android.dtsi" + +&pdm { + status = "okay"; + pinctrl-0 = <&pdm_clk1 + &pdm_sdi0 + &pdm_sdi2>; +}; + +&pdmics { + status = "okay"; +}; + +&pdm_mic_array { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; diff --git a/rk3528-evb3-lp4x-v10.dtsi b/rk3528-evb3-lp4x-v10.dtsi new file mode 100644 index 0000000..a427da4 --- /dev/null +++ b/rk3528-evb3-lp4x-v10.dtsi @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-evb.dtsi" + +/ { + model = "Rockchip RK3528 EVB3 LP4X V10 Board"; + compatible = "rockchip,rk3528-evb3-lp4x-v10", "rockchip,rk3528"; + + vcc5v0_sys_s0: vcc5v0-sys-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v8_s0: vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys_s0>; + }; + + vcc_3v3_s0: vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s0>; + }; + + vdd_0v9_s0: vdd-0v9-s0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9_s0"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys_s0>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + uart_rts_gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m0_rtsn>; + pinctrl-1 = <&uart2m0_gpios>; + BT,reset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable &wifi_host_wake_irq &clkm0_32k_out>; + WIFI,reset_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_perst>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&sai0 { + pinctrl-0 = <&i2s0m0_lrck &i2s0m0_sclk &i2s0m0_sdi &i2s0m0_sdo>; + status = "disabled"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer &uart2m0_ctsn>; +}; + +&usbdrd_dwc3 { + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&pinctrl { + wireless-wlan { + wifi_perst: wifi-perst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + wifi_enable: wifi-enable { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_output_high>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart2m0_gpios: uart2m0-gpios { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&acodec { + pa-ctl-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk3528-evb4-ddr4-v10.dts b/rk3528-evb4-ddr4-v10.dts new file mode 100644 index 0000000..8b5c9e8 --- /dev/null +++ b/rk3528-evb4-ddr4-v10.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3528-evb1-ddr4-v10.dtsi" +#include "rk3528-android.dtsi" + +/ { + model = "Rockchip rk3528 evb4 board"; + compatible = "rockchip,rk3528-evb4-ddr4-v10", "rockchip,rk3528"; +}; + +&sdmmc { + status = "okay"; +}; diff --git a/rk3528-iotest-lp3-v10.dts b/rk3528-iotest-lp3-v10.dts new file mode 100644 index 0000000..62326ae --- /dev/null +++ b/rk3528-iotest-lp3-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3528.dtsi" +#include "rk3528-android.dtsi" + +/ { + model = "Rockchip rk3528 iotest board"; + compatible = "rockchip,rk3528-iotest-lp3-v10", "rockchip,rk3528"; +}; + diff --git a/rk3528-linux.dtsi b/rk3528-linux.dtsi new file mode 100644 index 0000000..47f2e98 --- /dev/null +++ b/rk3528-linux.dtsi @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_hdmi: route-hdmi { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi>; + }; + route_tve: route-tve { + status = "okay"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_tve>; + }; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/rk3528-pinctrl.dtsi b/rk3528-pinctrl.dtsi new file mode 100644 index 0000000..288b6ae --- /dev/null +++ b/rk3528-pinctrl.dtsi @@ -0,0 +1,1406 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + arm { + /omit-if-no-ref/ + arm_pins: arm-pins { + rockchip,pins = + /* arm_avs */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clkm0_32k_out: clkm0-32k-out { + rockchip,pins = + /* clkm0_32k_out */ + <3 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clkm1_32k_out: clkm1-32k-out { + rockchip,pins = + /* clkm1_32k_out */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PD6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + eth_pins: eth-pins { + rockchip,pins = + /* eth_clk_25m_out */ + <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + fephy { + /omit-if-no-ref/ + fephym0_led_dpx: fephym0-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_link: fephym0-led_link { + rockchip,pins = + /* fephy_led_link_m0 */ + <4 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_spd: fephym0-led_spd { + rockchip,pins = + /* fephy_led_spd_m0 */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_dpx: fephym1-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_link: fephym1-led_link { + rockchip,pins = + /* fephy_led_link_m1 */ + <2 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_spd: fephym1-led_spd { + rockchip,pins = + /* fephy_led_spd_m1 */ + <2 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD5 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmi_pins: hdmi-pins { + rockchip,pins = + /* hdmi_tx_cec */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* hdmi_tx_scl */ + <0 RK_PA4 1 &pcfg_pull_none>, + /* hdmi_tx_sda */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_pins_idle: hdmi-pins-idle { + rockchip,pins = + /* hdmi_tx_cec */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* hdmi_tx_scl */ + <0 RK_PA4 0 &pcfg_output_low_pull_down>, + /* hdmi_tx_sda */ + <0 RK_PA5 0 &pcfg_output_low_pull_down>; + }; + }; + + hsm { + /omit-if-no-ref/ + hsmm0_pins: hsmm0-pins { + rockchip,pins = + /* hsm_clk_out_m0 */ + <2 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hsmm1_pins: hsmm1-pins { + rockchip,pins = + /* hsm_clk_out_m1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <4 RK_PC4 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <4 RK_PC3 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PA1 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PA0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <4 RK_PA3 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <4 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PC5 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PC6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <1 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <1 RK_PA6 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PA0 2 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PA1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PC1 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4_xfer: i2c4-xfer { + rockchip,pins = + /* i2c4_scl */ + <2 RK_PA0 4 &pcfg_pull_none_smt>, + /* i2c4_sda */ + <2 RK_PA1 4 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <1 RK_PB2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <1 RK_PB3 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PD2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <3 RK_PB2 5 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <3 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PD4 3 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PD7 3 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7_xfer: i2c7-xfer { + rockchip,pins = + /* i2c7_scl */ + <2 RK_PA5 4 &pcfg_pull_none_smt>, + /* i2c7_sda */ + <2 RK_PA6 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi: i2s0m0-sdi { + rockchip,pins = + /* i2s0m0_sdi */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m0_sdo: i2s0m0-sdo { + rockchip,pins = + /* i2s0m0_sdo */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi: i2s0m1-sdi { + rockchip,pins = + /* i2s0m1_sdi */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m1_sdo: i2s0m1-sdo { + rockchip,pins = + /* i2s0m1_sdo */ + <1 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1_lrck: i2s1-lrck { + rockchip,pins = + /* i2s1_lrck */ + <4 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_mclk: i2s1-mclk { + rockchip,pins = + /* i2s1_mclk */ + <4 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sclk: i2s1-sclk { + rockchip,pins = + /* i2s1_sclk */ + <4 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sdi0: i2s1-sdi0 { + rockchip,pins = + /* i2s1_sdi0 */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi1: i2s1-sdi1 { + rockchip,pins = + /* i2s1_sdi1 */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi2: i2s1-sdi2 { + rockchip,pins = + /* i2s1_sdi2 */ + <4 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi3: i2s1-sdi3 { + rockchip,pins = + /* i2s1_sdi3 */ + <4 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo0: i2s1-sdo0 { + rockchip,pins = + /* i2s1_sdo0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo1: i2s1-sdo1 { + rockchip,pins = + /* i2s1_sdo1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo2: i2s1-sdo2 { + rockchip,pins = + /* i2s1_sdo2 */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo3: i2s1-sdo3 { + rockchip,pins = + /* i2s1_sdo3 */ + <4 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_tck_m0 */ + <2 RK_PA2 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m0 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* jtag_mcu_tms_m0 */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_tck_m1 */ + <4 RK_PD0 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m1 */ + <4 RK_PC7 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m1 */ + <4 RK_PD0 3 &pcfg_pull_none>, + /* jtag_mcu_tms_m1 */ + <4 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + pcie { + /omit-if-no-ref/ + pciem0_pins: pciem0-pins { + rockchip,pins = + /* pcie_clkreqn_m0 */ + <3 RK_PA6 5 &pcfg_pull_none>, + /* pcie_perstn_m0 */ + <3 RK_PB0 5 &pcfg_pull_none>, + /* pcie_waken_m0 */ + <3 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pciem1_pins: pciem1-pins { + rockchip,pins = + /* pcie_clkreqn_m1 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie_perstn_m1 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie_waken_m1 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdm_clk0: pdm-clk0 { + rockchip,pins = + /* pdm_clk0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_clk1: pdm-clk1 { + rockchip,pins = + /* pdm_clk1 */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi0: pdm-sdi0 { + rockchip,pins = + /* pdm_sdi0 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + /* pdm_sdi1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + /* pdm_sdi2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + /* pdm_sdi3 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <4 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + refm0_pins: refm0-pins { + rockchip,pins = + /* ref_clk_out_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + refm1_pins: refm1-pins { + rockchip,pins = + /* ref_clk_out_m1 */ + <3 RK_PC3 6 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmii_miim: rgmii-miim { + rockchip,pins = + /* rgmii_mdc */ + <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_mdio */ + <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rx_bus2: rgmii-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_rxd1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_rxdv_crs */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_tx_bus2: rgmii-tx_bus2 { + rockchip,pins = + /* rgmii_txd0 */ + <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd1 */ + <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txen */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_clk: rgmii-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_txclk */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_bus: rgmii-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_rxd3 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_txd2 */ + <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd3 */ + <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_clk: rgmii-clk { + rockchip,pins = + /* rgmii_clk */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmii_txer: rgmii-txer { + rockchip,pins = + /* rgmii_txer */ + <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scrm0_pins: scrm0-pins { + rockchip,pins = + /* scr_clk_m0 */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_data_m0 */ + <1 RK_PA1 3 &pcfg_pull_none>, + /* scr_detn_m0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* scr_rstn_m0 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + scrm1_pins: scrm1-pins { + rockchip,pins = + /* scr_clk_m1 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* scr_data_m1 */ + <2 RK_PA3 4 &pcfg_pull_none>, + /* scr_detn_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* scr_rstn_m1 */ + <2 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + sdio0 { + /omit-if-no-ref/ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + /* sdio0_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_clk: sdio0-clk { + rockchip,pins = + /* sdio0_clk */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_cmd: sdio0-cmd { + rockchip,pins = + /* sdio0_cmd */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_det: sdio0-det { + rockchip,pins = + /* sdio0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio0_pwren: sdio0-pwren { + rockchip,pins = + /* sdio0_pwren */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sdio1 { + /omit-if-no-ref/ + sdio1_bus4: sdio1-bus4 { + rockchip,pins = + /* sdio1_d0 */ + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d1 */ + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d2 */ + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d3 */ + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_clk: sdio1-clk { + rockchip,pins = + /* sdio1_clk */ + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_cmd: sdio1-cmd { + rockchip,pins = + /* sdio1_cmd */ + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_det: sdio1-det { + rockchip,pins = + /* sdio1_det */ + <3 RK_PB3 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio1_pwren: sdio1-pwren { + rockchip,pins = + /* sdio1_pwren */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_detn */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <4 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <4 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0_pins: spi0-pins { + rockchip,pins = + /* spi0_clk */ + <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>, + /* spi0_miso */ + <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>, + /* spi0_mosi */ + <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi0_csn0: spi0-csn0 { + rockchip,pins = + /* spi0_csn0 */ + <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi0_csn1: spi0-csn1 { + rockchip,pins = + /* spi0_csn1 */ + <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1_pins: spi1-pins { + rockchip,pins = + /* spi1_clk */ + <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* spi1_miso */ + <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>, + /* spi1_mosi */ + <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi1_csn0: spi1-csn0 { + rockchip,pins = + /* spi1_csn0 */ + <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi1_csn1: spi1-csn1 { + rockchip,pins = + /* spi1_csn1 */ + <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>; + }; + }; + + tsi0 { + /omit-if-no-ref/ + tsi0_pins: tsi0-pins { + rockchip,pins = + /* tsi0_clkin */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* tsi0_d0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* tsi0_d1 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* tsi0_d2 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* tsi0_d3 */ + <3 RK_PB7 3 &pcfg_pull_none>, + /* tsi0_d4 */ + <3 RK_PA3 3 &pcfg_pull_none>, + /* tsi0_d5 */ + <3 RK_PA2 3 &pcfg_pull_none>, + /* tsi0_d6 */ + <3 RK_PA1 3 &pcfg_pull_none>, + /* tsi0_d7 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* tsi0_fail */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* tsi0_sync */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* tsi0_valid */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + tsi1 { + /omit-if-no-ref/ + tsi1_pins: tsi1-pins { + rockchip,pins = + /* tsi1_clkin */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* tsi1_d0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* tsi1_sync */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* tsi1_valid */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <4 RK_PC7 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <4 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <2 RK_PA0 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <2 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <4 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <4 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PC6 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PC5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1_ctsn: uart1-ctsn { + rockchip,pins = + /* uart1_ctsn */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1_rtsn: uart1-rtsn { + rockchip,pins = + /* uart1_rtsn */ + <4 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <3 RK_PA0 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <3 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <3 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <1 RK_PB0 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <1 RK_PB1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB0 2 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <4 RK_PB7 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <4 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4_xfer: uart4-xfer { + rockchip,pins = + /* uart4_rx */ + <2 RK_PA2 3 &pcfg_pull_up>, + /* uart4_tx */ + <2 RK_PA3 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PA2 2 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PA3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PA6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <1 RK_PD4 2 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <1 RK_PD7 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <3 RK_PC1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6_ctsn: uart6-ctsn { + rockchip,pins = + /* uart6_ctsn */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6_rtsn: uart6-rtsn { + rockchip,pins = + /* uart6_rtsn */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <1 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3528.dtsi b/rk3528.dtsi new file mode 100644 index 0000000..68f2544 --- /dev/null +++ b/rk3528.dtsi @@ -0,0 +1,2506 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3528"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &sfc; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkout_sai0: mclkout-sai0@ff340014 { + compatible = "rockchip,clk-out"; + reg = <0 0xff340014 0 0x4>; + clocks = <&cru MCLK_SAI_I2S0>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <1>; + rockchip,bit-set-to-disable; + }; + + mclkout_sai1: mclkout-sai1@ff320004 { + compatible = "rockchip,clk-out"; + reg = <0 0xff320004 0 0x4>; + clocks = <&cru MCLK_SAI_I2S1>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <14>; + rockchip,bit-set-to-disable; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + #cooling-cells = <2>; /* min followed by max */ + dynamic-power-coefficient = <147>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP0>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP1>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP1>; + }; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP0: cpu-sleep0 { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + status = "disabled"; + }; + + CPU_SLEEP1: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + status = "okay"; + }; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + mbist-vmin = <825000 925000 975000>; + nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&cpu_mbist_vmin>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; + + rockchip,video-4k-freq = <1200000>; + rockchip,pvtm-voltage-sel = < + 0 1320 0 + 1321 1350 1 + 1351 1375 2 + 1376 1405 3 + 1406 1435 4 + 1436 1470 5 + 1471 1505 6 + 1506 1540 7 + 1541 1575 8 + 1576 1610 9 + 1611 1640 10 + 1641 9999 11 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&grf>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1100000>; + opp-microvolt-L0 = <875000 875000 1100000>; + opp-microvolt-L1 = <875000 875000 1100000>; + opp-microvolt-L2 = <875000 875000 1100000>; + opp-microvolt-L3 = <875000 875000 1100000>; + opp-microvolt-L4 = <875000 875000 1100000>; + opp-microvolt-L5 = <850000 850000 1100000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1100000>; + opp-microvolt-L0 = <875000 875000 1100000>; + opp-microvolt-L1 = <875000 875000 1100000>; + opp-microvolt-L2 = <875000 875000 1100000>; + opp-microvolt-L3 = <875000 875000 1100000>; + opp-microvolt-L4 = <875000 875000 1100000>; + opp-microvolt-L5 = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000 825000 1100000>; + opp-microvolt-L0 = <875000 875000 1100000>; + opp-microvolt-L1 = <875000 875000 1100000>; + opp-microvolt-L2 = <875000 875000 1100000>; + opp-microvolt-L3 = <875000 875000 1100000>; + opp-microvolt-L4 = <875000 875000 1100000>; + opp-microvolt-L5 = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <825000 825000 1100000>; + opp-microvolt-L0 = <875000 875000 1100000>; + opp-microvolt-L1 = <875000 875000 1100000>; + opp-microvolt-L2 = <875000 875000 1100000>; + opp-microvolt-L3 = <875000 875000 1100000>; + opp-microvolt-L4 = <875000 875000 1100000>; + opp-microvolt-L5 = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <825000 825000 1100000>; + opp-microvolt-L0 = <900000 900000 1100000>; + opp-microvolt-L1 = <887500 887500 1100000>; + opp-microvolt-L2 = <875000 875000 1100000>; + opp-microvolt-L3 = <875000 875000 1100000>; + opp-microvolt-L4 = <875000 875000 1100000>; + opp-microvolt-L5 = <862500 862500 1100000>; + opp-microvolt-L6 = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <962500 962500 1100000>; + opp-microvolt-L1 = <950000 950000 1100000>; + opp-microvolt-L2 = <950000 950000 1100000>; + opp-microvolt-L3 = <937500 937500 1100000>; + opp-microvolt-L4 = <925000 925000 1100000>; + opp-microvolt-L5 = <912500 912500 1100000>; + opp-microvolt-L6 = <900000 900000 1100000>; + opp-microvolt-L7 = <887500 887000 1100000>; + opp-microvolt-L8 = <875000 875000 1100000>; + opp-microvolt-L9 = <862500 862500 1100000>; + opp-microvolt-L10 = <850000 850000 1100000>; + opp-microvolt-L11 = <850000 850000 1100000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1012500 1012500 1100000>; + opp-microvolt-L2 = <1000000 1000000 1100000>; + opp-microvolt-L3 = <987500 987500 1100000>; + opp-microvolt-L4 = <975000 975000 1100000>; + opp-microvolt-L5 = <962500 962500 1100000>; + opp-microvolt-L6 = <950000 950000 1100000>; + opp-microvolt-L7 = <937500 937500 1100000>; + opp-microvolt-L8 = <925000 925000 1100000>; + opp-microvolt-L9 = <912500 912500 1100000>; + opp-microvolt-L10 = <900000 900000 1100000>; + opp-microvolt-L11 = <887500 887500 1100000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1062500 1062500 1100000>; + opp-microvolt-L1 = <1050000 1050000 1100000>; + opp-microvolt-L2 = <1037500 1037500 1100000>; + opp-microvolt-L3 = <1025000 1025000 1100000>; + opp-microvolt-L4 = <1012500 1012500 1100000>; + opp-microvolt-L5 = <1000000 1000000 1100000>; + opp-microvolt-L6 = <987500 987500 1100000>; + opp-microvolt-L7 = <975000 975000 1100000>; + opp-microvolt-L8 = <962500 962500 1100000>; + opp-microvolt-L9 = <950000 950000 1100000>; + opp-microvolt-L10 = <937500 937500 1100000>; + opp-microvolt-L11 = <925000 925000 1100000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1100000 1100000 1100000>; + opp-microvolt-L1 = <1087500 1087500 1100000>; + opp-microvolt-L2 = <1075000 1075000 1100000>; + opp-microvolt-L3 = <1062500 1062500 1100000>; + opp-microvolt-L4 = <1050000 1050000 1100000>; + opp-microvolt-L5 = <1037500 1037500 1100000>; + opp-microvolt-L6 = <1025000 1025000 1100000>; + opp-microvolt-L7 = <1012500 1012500 1100000>; + opp-microvolt-L8 = <1000000 1000000 1100000>; + opp-microvolt-L9 = <987500 987500 1100000>; + opp-microvolt-L10 = <975000 975000 1100000>; + opp-microvolt-L11 = <962500 962500 1100000>; + clock-latency-ns = <40000>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3528-dmc"; + interrupts = ; + interrupt-names = "complete"; + devfreq-events = <&dfi>; + clocks = <&scmi_clk SCMI_CLK_DDR>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + upthreshold = <40>; + downdifferential = <20>; + system-status-level = < + /* system status freq level */ + SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH + >; + auto-min-freq = <324000>; + auto-freq-en = <0>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <850000 900000>; + nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&logic_mbist_vmin>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + rockchip,leakage-voltage-sel = < + 1 10 0 + 11 14 1 + 15 22 2 + 23 28 3 + 29 254 4 + >; + + opp-920000000 { + opp-hz = /bits/ 64 <920000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <850000 850000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + opp-microvolt-L1 = <850000 850000 1000000>; + opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + }; + opp-1184000000 { + opp-hz = /bits/ 64 <1184000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <950000 950000 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + opp-microvolt-L4 = <862500 862500 1000000>; + status = "disabled"; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + + assigned-clocks = <&scmi_clk SCMI_CLK_CPU>; + assigned-clock-rates = <1200000000>; + }; + }; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <5>; + rockchip,resetgroup-count = <5>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkvtunnel: rkvtunnel { + compatible = "rockchip,video-tunnel"; + status = "disabled"; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3528"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + rockchip,polling-delay = <200>; /* milliseconds */ + rockchip,temp-hysteresis = <5000>; /* millicelsius */ + rockchip,offline-cpu-temp = <105000>; /* millicelsius */ + rockchip,temp-offline-cpus = "2-3"; + }; + + secure_otp: secure-otp { + compatible = "rockchip,secure-otp"; + rockchip,otp-size = <32>; + status = "disabled"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <638>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + + trips { + threshold: trip-point-0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + temperature = <120000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = + <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + scmi_shmem: scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + }; + + sram: sram@fe480000 { + compatible = "mmio-sram"; + reg = <0x0 0xfe480000 0x0 0xc000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xfe480000 0xc000>; + + /* start address and size should be 4k algin */ + rkvdec_sram: rkvdec-sram@0 { + reg = <0x0 0xc000>; + }; + }; + + pcie2x1: pcie@fe4f0000 { + compatible = "rockchip,rk3528-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, + <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>, + <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>, + <&cru PCLK_PCIE_PHY>; + clock-names = "aclk", "hclk_slv", + "hclk_dbi", "pclk_cru", + "aux", "pclk", + "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + num-lanes = <1>; + phys = <&combphy_pu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 + 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe4f0000 0x0 0x10000>, + <0x1 0x40000000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>, + <&cru SRST_PRESETN_CRU_PCIE>; + reset-names = "pcie", "periph", "preset_cru"; + status = "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + usbdrd30: usbdrd { + compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@fe500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_ARESETN_USB3OTG>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "disabled"; + }; + }; + + gic: interrupt-controller@fed01000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfed01000 0 0x1000>, + <0x0 0xfed02000 0 0x2000>, + <0x0 0xfed04000 0 0x2000>, + <0x0 0xfed06000 0 0x2000>; + interrupts = ; + }; + + usb_host0_ehci: usb@ff100000 { + compatible = "generic-ehci"; + reg = <0x0 0xff100000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBHOST>, + <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff140000 { + compatible = "generic-ohci"; + reg = <0x0 0xff140000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USBHOST>, + <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + debug: debug@ff190000 { + compatible = "rockchip,debug"; + reg = <0x0 0xff190000 0x0 0x1000>, + <0x0 0xff192000 0x0 0x1000>, + <0x0 0xff194000 0x0 0x1000>, + <0x0 0xff196000 0x0 0x1000>; + }; + + qos_crypto_a: qos@ff200000 { + compatible = "syscon"; + reg = <0x0 0xff200000 0x0 0x20>; + }; + + qos_crypto_p: qos@ff200080 { + compatible = "syscon"; + reg = <0x0 0xff200080 0x0 0x20>; + }; + + qos_dcf: qos@ff200100 { + compatible = "syscon"; + reg = <0x0 0xff200100 0x0 0x20>; + }; + + qos_dft2apb: qos@ff200200 { + compatible = "syscon"; + reg = <0x0 0xff200200 0x0 0x20>; + }; + + qos_dma2ddr: qos@ff200280 { + compatible = "syscon"; + reg = <0x0 0xff200280 0x0 0x20>; + }; + + qos_dmac: qos@ff200300 { + compatible = "syscon"; + reg = <0x0 0xff200300 0x0 0x20>; + }; + + qos_keyreader: qos@ff200380 { + compatible = "syscon"; + reg = <0x0 0xff200380 0x0 0x20>; + }; + + qos_cpu: qos@ff210000 { + compatible = "syscon"; + reg = <0x0 0xff210000 0x0 0x20>; + }; + + qos_debug: qos@ff210080 { + compatible = "syscon"; + reg = <0x0 0xff210080 0x0 0x20>; + }; + + qos_gpu_m0: qos@ff220000 { + compatible = "syscon"; + reg = <0x0 0xff220000 0x0 0x20>; + }; + + qos_gpu_m1: qos@ff220080 { + compatible = "syscon"; + reg = <0x0 0xff220080 0x0 0x20>; + }; + + qos_pmu_mcu: qos@ff240000 { + compatible = "syscon"; + reg = <0x0 0xff240000 0x0 0x20>; + }; + + qos_rkvdec: qos@ff250000 { + compatible = "syscon"; + reg = <0x0 0xff250000 0x0 0x20>; + }; + + qos_rkvenc: qos@ff260000 { + compatible = "syscon"; + reg = <0x0 0xff260000 0x0 0x20>; + }; + + qos_gmac0: qos@ff270000 { + compatible = "syscon"; + reg = <0x0 0xff270000 0x0 0x20>; + }; + + qos_hdcp: qos@ff270080 { + compatible = "syscon"; + reg = <0x0 0xff270080 0x0 0x20>; + }; + + qos_jpegdec: qos@ff270100 { + compatible = "syscon"; + reg = <0x0 0xff270100 0x0 0x20>; + }; + + qos_rga2_m0ro: qos@ff270200 { + compatible = "syscon"; + reg = <0x0 0xff270200 0x0 0x20>; + }; + + qos_rga2_m0wo: qos@ff270280 { + compatible = "syscon"; + reg = <0x0 0xff270280 0x0 0x20>; + }; + + qos_sdmmc0: qos@ff270300 { + compatible = "syscon"; + reg = <0x0 0xff270300 0x0 0x20>; + }; + + qos_usb2host: qos@ff270380 { + compatible = "syscon"; + reg = <0x0 0xff270380 0x0 0x20>; + }; + + qos_vdpp: qos@ff270480 { + compatible = "syscon"; + reg = <0x0 0xff270480 0x0 0x20>; + }; + + qos_vop: qos@ff270500 { + compatible = "syscon"; + reg = <0x0 0xff270500 0x0 0x20>; + }; + + qos_emmc: qos@ff280000 { + compatible = "syscon"; + reg = <0x0 0xff280000 0x0 0x20>; + }; + + qos_fspi: qos@ff280080 { + compatible = "syscon"; + reg = <0x0 0xff280080 0x0 0x20>; + }; + + qos_gmac1: qos@ff280100 { + compatible = "syscon"; + reg = <0x0 0xff280100 0x0 0x20>; + }; + + qos_pcie: qos@ff280180 { + compatible = "syscon"; + reg = <0x0 0xff280180 0x0 0x20>; + }; + + qos_sdio0: qos@ff280200 { + compatible = "syscon"; + reg = <0x0 0xff280200 0x0 0x20>; + }; + + qos_sdio1: qos@ff280280 { + compatible = "syscon"; + reg = <0x0 0xff280280 0x0 0x20>; + }; + + qos_tsp: qos@ff280300 { + compatible = "syscon"; + reg = <0x0 0xff280300 0x0 0x20>; + }; + + qos_usb3otg: qos@ff280380 { + compatible = "syscon"; + reg = <0x0 0xff280380 0x0 0x20>; + }; + + qos_vpu: qos@ff280400 { + compatible = "syscon"; + reg = <0x0 0xff280400 0x0 0x20>; + }; + + /* + * Merge all GRF, each independent GRF offset is shown as bellow: + * CORE_GRF: 0xff300000 + * GPU_GRF: 0xff310000 + * RKVENC_GRF: 0xff320000 + * DDR_GRF: 0xff330000 + * VPU_GRF: 0xff340000 + * COMBO_PIPE_PHY_GRF: 0xff348000 + * RKVDEC_GRF: 0xff350000 + * VO_GRF: 0xff360000 + * PMU_GRF: 0xff370000 + * SYS_GRF: 0xff380000 + */ + grf: syscon@ff300000 { + compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff300000 0x0 0x90000>; + + grf_cru: grf-clock-controller { + compatible = "rockchip,rk3528-grf-cru"; + #clock-cells = <1>; + }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x70200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + cru: clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0x0 0xff4a0000 0x0 0x30000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru XIN_OSC0_DIV>, + <&cru PLL_GPLL>, + <&cru PLL_PPLL>, + <&cru PLL_CPLL>, + <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>, + <&cru ACLK_VO_ROOT>, + <&cru ACLK_VPU_ROOT>, + <&cru ACLK_VPU_L_ROOT>; + + assigned-clock-rates = + <32768>, + <1188000000>, + <1000000000>, + <996000000>, + <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>, + <340000000>, + <300000000>, + <200000000>; + }; + + ioc_grf: syscon@ff540000 { + compatible = "rockchip,rk3528-ioc-grf", "syscon"; + reg = <0x0 0xff540000 0x0 0x40000>; + }; + + pmu: power-management@ff600000 { + compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff600000 0x0 0x2000>; + + power: power-controller { + compatible = "rockchip,rk3528-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3528_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU_MALI>, + <&cru PCLK_GPU_ROOT>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>; + }; + /* These power domains are grouped by VD_LOGIC */ + pd_rkvdec@RK3528_PD_RKVDEC { + reg = ; + }; + pd_rkvenc@RK3528_PD_RKVENC { + reg = ; + }; + pd_vo@RK3528_PD_VO { + reg = ; + }; + pd_vpu@RK3528_PD_VPU { + reg = ; + }; + }; + }; + + mailbox: mailbox@ff630000 { + compatible = "rockchip,rk3528-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xff630000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_PMU_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + gpu: gpu@ff700000 { + compatible = "arm,mali-450"; + reg = <0x0 0xff700000 0x0 0x40000>; + + interrupts = , + , + , + , + , + , + ; + interrupt-names = "Mali_GP_IRQ", + "Mali_GP_MMU_IRQ", + "IRQPP", + "Mali_PP0_IRQ", + "Mali_PP0_MMU_IRQ", + "Mali_PP1_IRQ", + "Mali_PP1_MMU_IRQ"; + clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>, + <&cru PCLK_GPU_ROOT>; + clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu"; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <300000000>; + power-domains = <&power RK3528_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + rockchip,grf = <&grf>; + status = "disabled"; + + gpu_power_model: power-model { + compatible = "simple-power-model"; + leakage-range= <1 3>; + ls = <(-15658) 67354 0>; + static-coefficient = <10000>; + dynamic-coefficient = <724>; + ts = <3156546 120154 (-2506) 39>; + thermal-zone = "soc-thermal"; + }; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 925000>; + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&gpu_mbist_vmin>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; + + rockchip,pvtm-voltage-sel = < + 0 750 0 + 751 770 1 + 771 790 2 + 791 810 3 + 811 830 4 + 831 850 5 + 851 870 6 + 871 890 7 + 891 9999 8 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x10018>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <800000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&grf>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <875000 875000 1000000>; + opp-microvolt-L5 = <850000 850000 1000000>; + opp-microvolt-L6 = <837500 837500 1000000>; + opp-microvolt-L7 = <825000 825000 1000000>; + opp-microvolt-L8 = <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <875000 875000 1000000>; + opp-microvolt-L5 = <850000 850000 1000000>; + opp-microvolt-L6 = <837500 837500 1000000>; + opp-microvolt-L7 = <825000 825000 1000000>; + opp-microvolt-L8 = <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <875000 875000 1000000>; + opp-microvolt-L5 = <850000 850000 1000000>; + opp-microvolt-L6 = <837500 837500 1000000>; + opp-microvolt-L7 = <825000 825000 1000000>; + opp-microvolt-L8 = <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L1 = <887500 887500 1000000>; + opp-microvolt-L2 = <875000 875000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + opp-microvolt-L4 = <875000 875000 1000000>; + opp-microvolt-L5 = <850000 850000 1000000>; + opp-microvolt-L6 = <837500 837500 1000000>; + opp-microvolt-L7 = <825000 825000 1000000>; + opp-microvolt-L8 = <825000 825000 1000000>; + clock-latency-ns = <40000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L1 = <937500 937500 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <912500 912500 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + opp-microvolt-L5 = <887500 887500 1000000>; + opp-microvolt-L6 = <875000 875000 1000000>; + opp-microvolt-L7 = <862500 862500 1000000>; + opp-microvolt-L8 = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + gpu_bus: gpu-bus { + compatible = "rockchip,rk3528-bus"; + rockchip,busfreq-policy = "clkfreq"; + clocks = <&scmi_clk SCMI_CLK_GPU>; + clock-names = "bus"; + operating-points-v2 = <&gpu_bus_opp_table>; + status = "disabled"; + }; + + gpu_bus_opp_table: gpu-bus-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&log_leakage>; + nvmem-cell-names = "leakage"; + + rockchip,leakage-voltage-sel = < + 1 22 0 + 23 254 1 + >; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <875000 875000 1000000>; + opp-microvolt-L1 = <850000 850000 1000000>; + }; + }; + + rkvdec: rkvdec@ff740100 { + compatible = "rockchip,rkv-decoder-rk3528", "rockchip,rkv-decoder-v2"; + reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; + clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; + rockchip,normal-rates = <340000000>, <0>, <600000000>; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; + assigned-clock-rates = <340000000>, <600000000>; + resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>, + <&cru SRST_RESETN_HEVC_CA_RKVDEC>; + reset-names = "video_a", "video_h", "video_hevc_cabac"; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + rockchip,task-capacity = <16>; + rockchip,sram = <&rkvdec_sram>; + /* rcb_iova: start and size */ + rockchip,rcb-iova = <0x10000000 65536>; + rockchip,rcb-min-width = <512>; + status = "disabled"; + }; + + rkvdec_mmu: iommu@ff740800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; + clock-names = "aclk", "iface", "clk_hevc_cabac"; + #iommu-cells = <0>; + rockchip,shootdown-entire; + status = "disabled"; + }; + + rkvenc: rkvenc@ff780000 { + compatible = "rockchip,rkv-encoder-rk3528", "rockchip,rkv-encoder-v2"; + reg = <0x0 0xff780000 0x0 0x6000>; + interrupts = ; + interrupt-names = "irq_rkvenc"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <300000000>, <0>, <300000000>; + resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>, + <&cru SRST_RESETN_CORE_RKVENC>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>; + assigned-clock-rates = <300000000>, <300000000>; + iommus = <&rkvenc_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,grf = <&grf>; + rockchip,grf-mem-offset = <0x20010>; + rockchip,grf-mem-values = <0x00000021>, <0xffff0021>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + status = "disabled"; + }; + + rkvenc_mmu: iommu@ff78f000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff78f000 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvenc_mmu"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,shootdown-entire; + status = "disabled"; + }; + + vdpu: vdpu@ff7c0400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xff7c0400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <300000000>, <0>; + assigned-clocks = <&cru ACLK_VPU>; + assigned-clock-rates = <300000000>; + resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vdpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,grf = <&grf>; + rockchip,grf-mem-offset = <0x40034>; + rockchip,grf-mem-values = <0x0f040000>, <0x0f040f04>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + rockchip,disable-auto-freq; + status = "disabled"; + }; + + vdpu_mmu: iommu@ff7c0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff7c0800 0x0 0x40>; + interrupts = ; + interrupt-names = "vdpu_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + #iommu-cells = <0>; + rockchip,shootdown-entire; + status = "disabled"; + }; + + avsd: avsd_plus@ff7c1000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xff7c1000 0x0 0x200>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <300000000>, <0>; + assigned-clocks = <&cru ACLK_VPU>; + assigned-clock-rates = <300000000>; + resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; + reset-names = "shared_video_a", "shared_video_h"; + iommus = <&vdpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + rockchip,disable-auto-freq; + status = "disabled"; + }; + + vop: vop@ff840000 { + compatible = "rockchip,rk3528-vop"; + reg = <0x0 0xff840000 0x0 0x3000>, + <0x0 0xff845000 0x0 0x1000>, + <0x0 0xff846400 0x0 0x800>; + reg-names = "regs", + "gamma_lut", + "acm_regs"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>; + clock-names = "aclk_vop", + "hclk_vop", + "dclk_vp0", + "dclk_vp1"; + assigned-clocks = <&cru DCLK_VOP0>; + assigned-clock-parents = <&inno_hdmiphy_clk>; + iommus = <&vop_mmu>; + rockchip,grf = <&grf>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_hdmi: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_in_vp0>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_tve: endpoint@0 { + reg = <0>; + remote-endpoint = <&tve_in_vp1>; + }; + }; + }; + }; + + vop_mmu: iommu@ff847e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff847e00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "disabled"; + }; + + rga2: rga@ff850000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xff850000 0x0 0x1000>; + interrupts = ; + interrupt-names = "rga2_irq"; + clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; + clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; + iommus = <&rga2_mmu>; + rockchip,grf = <&grf>; + rockchip,grf-offset = <0x600e0>; + rockchip,grf-values = <0x0ff10000>, <0x0ff10ff1>; + status = "disabled"; + }; + + rga2_mmu: iommu@ff850f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff850f00 0x0 0x100>; + interrupts = ; + interrupt-names = "rga2_mmu"; + clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep: iep@ff860000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xff860000 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; + clock-names = "aclk", "hclk", "sclk"; + rockchip,normal-rates = <340000000>, <0>, <340000000>; + assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>; + assigned-clock-rates = <340000000>, <340000000>; + resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, + <&cru SRST_RESETN_CORE_VDPP>; + reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <3>; + rockchip,resetgroup-node = <3>; + iommus = <&iep_mmu>; + status = "disabled"; + }; + + iep_mmu: iommu@ff860800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff860800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,shootdown-entire; + status = "disabled"; + }; + + vdpp: vdpp@ff861000 { + compatible = "rockchip,vdpp-v1"; + reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>; + reg-names = "vdpp_regs", "zme_regs"; + interrupts = ; + clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; + clock-names = "aclk", "hclk", "sclk"; + rockchip,normal-rates = <340000000>, <0>, <340000000>; + assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>; + assigned-clock-rates = <340000000>, <340000000>; + resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, + <&cru SRST_RESETN_CORE_VDPP>; + reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; + rockchip,srv = <&mpp_srv>; + rockchip,grf = <&grf>; + rockchip,grf-mem-offset = <0x600e0>; + rockchip,grf-mem-values = <0xf0040000>, <0xf004f004>; + rockchip,taskqueue-node = <3>; + rockchip,resetgroup-node = <3>; + rockchip,disable-auto-freq; + iommus = <&iep_mmu>; + status = "disabled"; + }; + + jpegd: jpegd@ff870000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xff870000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <340000000>, <0>; + assigned-clocks = <&cru ACLK_JPEG_DECODER>; + assigned-clock-rates = <340000000>; + rockchip,disable-auto-freq; + resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>; + reset-names = "video_a", "video_h"; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <4>; + rockchip,resetgroup-node = <4>; + status = "disabled"; + }; + + jpegd_mmu: iommu@ff870480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff870480 0x0 0x40>; + interrupts = ; + interrupt-names = "jpegd_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; + #iommu-cells = <0>; + rockchip,shootdown-entire; + status = "disabled"; + }; + + tve: tve@ff880000 { + compatible = "rockchip,rk3528-tve"; + reg = <0x0 0xff880000 0x0 0x4000>, + <0x0 0xffde0000 0x0 0x300>; + interrupts = ; + clocks = <&cru HCLK_CVBS>, + <&cru PCLK_VCDCPHY>, + <&cru DCLK_CVBS>, + <&cru DCLK_4X_CVBS>; + clock-names = "hclk", + "pclk_vdac", + "dclk", + "dclk_4x"; + rockchip,lumafilter0 = <0x0ff80006>; + rockchip,lumafilter1 = <0x00090010>; + rockchip,lumafilter2 = <0x0ffb0fd8>; + rockchip,lumafilter3 = <0x00080057>; + rockchip,lumafilter4 = <0x0fef0f64>; + rockchip,lumafilter5 = <0x0016010a>; + rockchip,lumafilter6 = <0x0f830df7>; + rockchip,lumafilter7 = <0x08de055f>; + rockchip,tve-upsample = ; + rockchip,grf = <&grf>; + nvmem-cells = <&vdac_out_current>, <&test_version>; + nvmem-cell-names = "out-current", "version"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tve_in_vp1: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp1_out_tve>; + status = "disabled"; + }; + }; + }; + }; + + hdcp2: hdcp2@ff8c0000 { + compatible = "rockchip,rk3528-hdmi-hdcp2"; + reg = <0x0 0xff8c0000 0x0 0x2000>; + interrupts = ; + clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>, + <&cru HCLK_HDCP>; + clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi"; + status = "disabled"; + }; + + hdmi: hdmi@ff8d0000 { + compatible = "rockchip,rk3528-dw-hdmi"; + reg = <0x0 0xff8d0000 0x0 0x20000>, + <0x0 0xff610000 0x0 0x200>; + interrupts = , + ; + interrupt-names = "hdmi", "hdmi_wakeup"; + clocks = <&cru PCLK_HDMI>, + <&cru CLK_SFR_HDMI>, + <&cru CLK_CEC_HDMI>, + <&inno_hdmiphy_clk>; + clock-names = "iahb", "isfr", "cec", "dclk_vp0"; + ddc-i2c-scl-high-time-ns = <9625>; + ddc-i2c-scl-low-time-ns = <10000>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pins>; + phys = <&hdmiphy>; + phy-names = "hdmi"; + #sound-dai-cells = <0>; + hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi>; + status = "disabled"; + }; + }; + }; + }; + + dfi: dfi@ff930000 { + reg = <0x0 0xff930000 0x0 0x400>; + compatible = "rockchip,rk3528-dfi"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + spi0: spi@ff9c0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff9c0000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>; + clock-names = "spiclk", "apb_pclk", "sclk_in"; + dmas = <&dmac 25>, <&dmac 24>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>; + status = "disabled"; + }; + + spi1: spi@ff9d0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff9d0000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>; + clock-names = "spiclk", "apb_pclk", "sclk_in"; + dmas = <&dmac 31>, <&dmac 30>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>; + status = "disabled"; + }; + + uart0: serial@ff9f0000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff9f0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 9>, <&dmac 8>; + status = "disabled"; + }; + + uart1: serial@ff9f8000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff9f8000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 11>, <&dmac 10>; + status = "disabled"; + }; + + uart2: serial@ffa00000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa00000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 13>, <&dmac 12>; + status = "disabled"; + }; + + uart3: serial@ffa08000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa08000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 15>, <&dmac 14>; + status = "disabled"; + }; + + uart4: serial@ffa10000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa10000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 17>, <&dmac 16>; + status = "disabled"; + }; + + uart5: serial@ffa18000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa18000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 19>, <&dmac 18>; + status = "disabled"; + }; + + uart6: serial@ffa20000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa20000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 21>, <&dmac 20>; + status = "disabled"; + }; + + uart7: serial@ffa28000 { + compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + reg = <0x0 0xffa28000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 23>, <&dmac 22>; + status = "disabled"; + }; + + i2c0: i2c@ffa50000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa50000 0x0 0x1000>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@ffa58000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa58000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa60000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa60000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa68000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa68000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa70000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa70000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa78000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa78000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@ffa80000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@ffa88000 { + compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa88000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pwm0: pwm@ffa90000 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@ffa90010 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@ffa90020 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@ffa90030 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa90030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm4: pwm@ffa98000 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@ffa98010 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@ffa98020 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@ffa98030 { + compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xffa98030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + rktimer: timer@ffab0000 { + compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xffab0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@ffac0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xffac0000 0x0 0x100>; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + tsadc: tsadc@ffad0000 { + compatible = "rockchip,rk3528-tsadc"; + reg = <0x0 0xffad0000 0x0 0x400>; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; + assigned-clock-rates = <1200000>, <12000000>; + resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + status = "disabled"; + }; + + saradc: saradc@ffae0000 { + compatible = "rockchip,rk3528-saradc"; + reg = <0x0 0xffae0000 0x0 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_PRESETN_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + sai3: sai@ffb70000 { + compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; + reg = <0x0 0xffb70000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 5>; + dma-names = "tx"; + resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai0: sai@ffb80000 { + compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; + reg = <0x0 0xffb80000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 1>, <&dmac 0>; + dma-names = "tx", "rx"; + resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi + &i2s0m0_sdo>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai2: sai@ffb90000 { + compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; + reg = <0x0 0xffb90000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 4>; + dma-names = "tx"; + resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>; + reset-names = "m", "h"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sai1: sai@ffba0000 { + compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; + reg = <0x0 0xffba0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>; + clock-names = "mclk", "hclk"; + dmas = <&dmac 3>, <&dmac 2>; + dma-names = "tx", "rx"; + resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_sclk + &i2s1_lrck + &i2s1_sdi0 + &i2s1_sdi1 + &i2s1_sdi2 + &i2s1_sdi3 + &i2s1_sdo0 + &i2s1_sdo1 + &i2s1_sdo2 + &i2s1_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm: pdm@ffbb0000 { + compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm"; + reg = <0x0 0xffbb0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac 6>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm_clk0 + &pdm_clk1 + &pdm_sdi0 + &pdm_sdi1 + &pdm_sdi2 + &pdm_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_8ch: spdif@ffbc0000 { + compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xffbc0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_pins>; + status = "disabled"; + }; + + gmac0: ethernet@ffbd0000 { + compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffbd0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, + <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, + <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; + clock-names = "stmmaceth", "clk_mac_ref", + "mac_clk_rx", "mac_clk_tx", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_ARESETN_MAC_VO>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + + phy-mode = "rmii"; + clock_in_out = "input"; + phy-handle = <&rmii0_phy>; + + nvmem-cells = <&macphy_bgs>; + nvmem-cell-names = "bgs"; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + rmii0_phy: ethernet-phy@2 { + compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; + reg = <2>; + clocks = <&cru CLK_MACPHY>; + resets = <&cru SRST_RESETN_MACPHY>; + phy-is-integrated; + pinctrl-names = "default"; + pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>; + nvmem-cells = <&macphy_txlevel>; + nvmem-cell-names = "txlevel"; + }; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + gmac1: ethernet@ffbe0000 { + compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffbe0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>, + <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_ARESETN_MAC>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sdhci: mmc@ffbf0000 { + compatible = "rockchip,rk3528-dwcmshc"; + reg = <0x0 0xffbf0000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>, + <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>, + <&cru SRST_TRESETN_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + sfc: spi@ffc00000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xffc00000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdio0: mmc@ffc10000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc10000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>, + <&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + resets = <&cru SRST_HRESETN_SDIO0>; + reset-names = "reset"; + rockchip,use-v2-tuning; + status = "disabled"; + }; + + sdio1: mmc@ffc20000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc20000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>, + <&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + resets = <&cru SRST_HRESETN_SDIO1>; + reset-names = "reset"; + rockchip,use-v2-tuning; + status = "disabled"; + }; + + sdmmc: mmc@ffc30000 { + compatible = "rockchip,rk3528-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xffc30000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>, + <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + resets = <&cru SRST_HRESETN_SDMMC0>; + reset-names = "reset"; + rockchip,use-v2-tuning; + status = "disabled"; + }; + + crypto: crypto@ffc40000 { + compatible = "rockchip,crypto-v4"; + reg = <0x0 0xffc40000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>, + <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; + clock-names = "aclk", "hclk", "sclk", "pka"; + assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; + assigned-clock-rates = <300000000>, <300000000>; + resets = <&cru SRST_RESETN_CORE_CRYPTO>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@ffc50000 { + compatible = "rockchip,rkrng"; + reg = <0x0 0xffc50000 0x0 0x200>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_TRNG>; + clock-names = "hclk_trng"; + resets = <&cru SRST_HRESETN_TRNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + otp: otp@ffce0000 { + compatible = "rockchip,rk3528-otp"; + reg = <0x0 0xffce0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>; + clock-names = "usr", "sbpi", "apb"; + resets = <&cru SRST_RESETN_USER_OTPC_NS>, + <&cru SRST_RESETN_SBPI_OTPC_NS>, + <&cru SRST_PRESETN_OTPC_NS>; + reset-names = "usr", "sbpi", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + cpu_mbist_vmin: cpu-mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <0 3>; + }; + gpu_mbist_vmin: gpu-mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <3 2>; + }; + logic_mbist_vmin: logic-mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <5 2>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + gpu_leakage: gpu-leakage@1c { + reg = <0x1c 0x1>; + }; + test_version: test-version@29 { + reg = <0x29 0x1>; + }; + macphy_bgs: macphy-bgs@2d { + reg = <0x2d 0x1>; + }; + macphy_txlevel: macphy-txlevel@2e { + reg = <0x2e 0x2>; + }; + vdac_out_current: vdac-out-current@30 { + reg = <0x30 0x1>; + }; + cpu_opp_info: cpu-opp-info@32 { + reg = <0x32 0x6>; + }; + gpu_opp_info: gpu-opp-info@38 { + reg = <0x38 0x6>; + }; + dmc_opp_info: dmc-opp-info@3e { + reg = <0x3e 0x6>; + }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@44 { + reg = <0x44 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@45 { + reg = <0x45 0x1>; + }; + }; + + dmac: dma-controller@ffd60000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xffd60000 0x0 0x4000>; + interrupts = , + , + , + , + , + , + , + , + ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + hwlock: hwspinlock@ffd70000 { + compatible = "rockchip,hwspinlock"; + reg = <0x0 0xffd70000 0x0 0x100>; + #hwlock-cells = <1>; + status = "disabled"; + }; + + combphy_pu: phy@ffdc0000 { + compatible = "rockchip,rk3528-naneng-combphy"; + reg = <0x0 0xffdc0000 0x0 0x10000>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&grf>; + rockchip,pipe-phy-grf = <&grf>; + status = "disabled"; + }; + + usb2phy: usb2-phy@ffdf0000 { + compatible = "rockchip,rk3528-usb2phy"; + reg = <0x0 0xffdf0000 0x0 0x10000>; + clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "apb_pclk"; + #clock-cells = <0>; + rockchip,usbgrf = <&grf>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", + "otg-id", + "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + hdmiphy: hdmiphy@ffe00000 { + compatible = "rockchip,rk3528-hdmi-phy"; + reg = <0x0 0xffe00000 0x0 0x10000>; + interrupts = ; + #phy-cells = <0>; + clocks = <&cru PCLK_HDMIPHY>, <&xin24m>; + clock-names = "sysclk", "refclk"; + status = "disabled"; + + inno_hdmiphy_clk: clk-port { + #clock-cells = <0>; + clock-output-names = "clk_hdmiphy_pixel_io"; + status = "okay"; + }; + }; + + acodec: acodec@ffe10000 { + compatible = "rockchip,rk3528-codec"; + reg = <0x0 0xffe10000 0x0 0x1000>; + #sound-dai-cells = <0>; + clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>; + clock-names = "pclk", "mclk"; + resets = <&cru SRST_PRESETN_ACODEC>; + reset-names = "acodec"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3528-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff610000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffaf0000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ffb00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb00000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffb10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb10000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffb20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb20000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3528-pinctrl.dtsi" diff --git a/rk3528/pro-rk3528.dts b/rk3528/pro-rk3528.dts new file mode 100644 index 0000000..b9df924 --- /dev/null +++ b/rk3528/pro-rk3528.dts @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include + +#include "rk3528-evb1-rpdzkj-pwm-pwm.dtsi" +#include "rp-rk3528-ir.dtsi" +#include "rk3528-audio.dtsi" +#include "../rk3528-android.dtsi" + +#include "rp-usb-rk3528.dtsi" +#include "rp-adc-key.dtsi" + +#include "rp-wifi-bt-vs2275s-rk3528.dtsi" + +#include "rp-eth-gmac0-rmii.dtsi" +#include "rp-eth-gmac1-rgmii.dtsi" +#include "rp-eth-pcie2gmac-rk3528.dtsi" + +#include "rp-lcd-hdmi.dtsi" +#include "rp-cvbs-out.dtsi" + +/{ + model = "pro-rk3528"; + compatible = "rockchip,pro-rk3528", "rockchip,rk3528"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + pwr_5v { //5v power en + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + led { //system led + gpio_num = <&nca9555_gpio IO_17 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + usb_pwr { //usb power + gpio_num = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //usb hub + gpio_num = <&gpio1 RK_PC3 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + otg_mode { //OTG SWITCH + gpio_num = <&gpio4 RK_PA5 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + otg_power { //usb otg power + gpio_num = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_en { //spk enable + gpio_num = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + gsm_pwr{ //4g power + gpio_num = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + nca9555_00 { + gpio_num = <&nca9555_gpio IO_00 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_01 { + gpio_num = <&nca9555_gpio IO_01 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_02 { + gpio_num = <&nca9555_gpio IO_02 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_03 { + gpio_num = <&nca9555_gpio IO_03 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_04 { + gpio_num = <&nca9555_gpio IO_04 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_05 { + gpio_num = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_06 { + gpio_num = <&nca9555_gpio IO_06 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_07 { + gpio_num = <&nca9555_gpio IO_07 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_12 { + gpio_num = <&nca9555_gpio IO_12 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_13 { + gpio_num = <&nca9555_gpio IO_13 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_14 { + gpio_num = <&nca9555_gpio IO_14 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_15 { + gpio_num = <&nca9555_gpio IO_15 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555_16 { + gpio_num = <&nca9555_gpio IO_16 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; +}; + +&sdmmc { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + hym8563: rtc-hym8563@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; + nca9555: mfd-gpio@20 { + compatible = "nca9555"; + reg = <0x20>; + status = "okay"; + + nca9555_gpio: gpio-normal@20 { + compatible = "nca9555-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3528/rk3528-audio.dtsi b/rk3528/rk3528-audio.dtsi new file mode 100755 index 0000000..0076bb9 --- /dev/null +++ b/rk3528/rk3528-audio.dtsi @@ -0,0 +1,96 @@ + +/ { + acodec_sound: acodec-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rk3528-acodec"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + simple-audio-card,codec { + sound-dai = <&acodec>; + }; + }; + + + hdmi_sound: hdmi-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&sai3>; + rockchip,codec = <&hdmi>; + rockchip,jack-det; + }; + + pdmics: dummy-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <0>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; +}; + + +&acodec { + pa-ctl-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pdm { + pinctrl-0 = <&pdm_clk1 + &pdm_sdi0>; + status = "okay"; +}; diff --git a/rk3528/rk3528-evb1-rpdzkj-pwm-pwm.dtsi b/rk3528/rk3528-evb1-rpdzkj-pwm-pwm.dtsi new file mode 100755 index 0000000..ef8e064 --- /dev/null +++ b/rk3528/rk3528-evb1-rpdzkj-pwm-pwm.dtsi @@ -0,0 +1,524 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "../rk3528.dtsi" +#include +#include +#include + +/ { + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + /omit-if-no-ref/ + vccio_sd: vccio-sd { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + vdd_logic_gpu: vdd-logic-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_logic_gpu"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1006000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_cpu: vdd-cpu { //vdd_arm + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <746000>; + regulator-max-microvolt = <1201000>; + regulator-init-microvolt = <953000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + /* + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <705000>; + regulator-max-microvolt = <1148000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + */ + vdd_0v9: vdd-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdd_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_1v8: vdd-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + /omit-if-no-ref/ + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&acodec { + pa-ctl-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&combphy_pu { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&crypto { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic_gpu>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_logic_gpu>; + status = "okay"; +}; + +&gpu_bus { + bus-supply = <&vdd_logic_gpu>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + rockchip,pwm-regulator-config = < + (0 + | RKPM_PWM0_M0_REGULATOR_EN + | RKPM_PWM1_M0_REGULATOR_EN + ) + >; +}; + +&sai0 { + pinctrl-0 = <&i2s0m1_lrck &i2s0m1_sclk &i2s0m1_sdi &i2s0m1_sdo>; + status = "disabled"; +}; + +&sai2 { + status = "okay"; +}; + +&sai3 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vdd_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + rockchip,default-sample-phase = <90>; + supports-sd; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + vmmc-supply = <&vcc3v3_sd>; + status = "disabled"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { //Thermal (温度控制) + status = "okay"; +}; + +&vdpp { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + + +&gpu_opp_table { + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>; + opp-microvolt-L6 = <900000 900000 1000000>; + opp-microvolt-L7 = <900000 900000 1000000>; + opp-microvolt-L8 = <900000 900000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>; + opp-microvolt-L6 = <900000 900000 1000000>; + opp-microvolt-L7 = <900000 900000 1000000>; + opp-microvolt-L8 = <900000 900000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>; + opp-microvolt-L6 = <900000 900000 1000000>; + opp-microvolt-L7 = <900000 900000 1000000>; + opp-microvolt-L8 = <900000 900000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L1 = <900000 900000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>; + opp-microvolt-L6 = <900000 900500 1000000>; + opp-microvolt-L7 = <900000 900000 1000000>; + opp-microvolt-L8 = <900000 900000 1000000>; + clock-latency-ns = <40000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L1 = <937500 937500 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <912500 912500 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + opp-microvolt-L5 = <900000 900000 1000000>; + opp-microvolt-L6 = <900000 900000 1000000>; + opp-microvolt-L7 = <900000 900000 1000000>; + opp-microvolt-L8 = <900000 900000 1000000>; + clock-latency-ns = <40000>; + }; +}; + +&gpu_bus_opp_table { + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000 900000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L1 = <900000 900000 1000000>; + }; +}; + + + +&dfi { + status = "disabled"; +}; + + +&dmc { + status = "disabled"; +}; + diff --git a/rk3528/rp-adc-key.dtsi b/rk3528/rp-adc-key.dtsi new file mode 100755 index 0000000..c35e8e7 --- /dev/null +++ b/rk3528/rp-adc-key.dtsi @@ -0,0 +1,35 @@ + +/ { + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <414000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <800000>; + }; + + back-key { + linux,code = ; + label = "back"; + press-threshold-microvolt = <1200000>; + }; + }; +}; \ No newline at end of file diff --git a/rk3528/rp-cvbs-out.dtsi b/rk3528/rp-cvbs-out.dtsi new file mode 100755 index 0000000..49e9fb8 --- /dev/null +++ b/rk3528/rp-cvbs-out.dtsi @@ -0,0 +1,7 @@ +&tve { + status = "okay"; +}; + +&tve_in_vp1 { + status = "okay"; +}; diff --git a/rk3528/rp-eth-gmac0-rmii.dtsi b/rk3528/rp-eth-gmac0-rmii.dtsi new file mode 100755 index 0000000..c3c79bb --- /dev/null +++ b/rk3528/rp-eth-gmac0-rmii.dtsi @@ -0,0 +1,4 @@ +&gmac0 { + status = "okay"; +}; + diff --git a/rk3528/rp-eth-gmac1-rgmii.dtsi b/rk3528/rp-eth-gmac1-rgmii.dtsi new file mode 100755 index 0000000..04f37fe --- /dev/null +++ b/rk3528/rp-eth-gmac1-rgmii.dtsi @@ -0,0 +1,34 @@ +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x33>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_miim + &rgmii_tx_bus2 + &rgmii_rx_bus2 + &rgmii_rgmii_clk + &rgmii_rgmii_bus + &rgmii_clk + ð_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC1_VPU_25M>; + }; +}; + diff --git a/rk3528/rp-eth-pcie2gmac-rk3528.dtsi b/rk3528/rp-eth-pcie2gmac-rk3528.dtsi new file mode 100755 index 0000000..05073dc --- /dev/null +++ b/rk3528/rp-eth-pcie2gmac-rk3528.dtsi @@ -0,0 +1,23 @@ +/{ + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + // gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&pcie2x1 { + pinctrl-0 = <&pciem0_pins>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; diff --git a/rk3528/rp-lcd-hdmi.dtsi b/rk3528/rp-lcd-hdmi.dtsi new file mode 100755 index 0000000..7b84855 --- /dev/null +++ b/rk3528/rp-lcd-hdmi.dtsi @@ -0,0 +1,34 @@ +/** + * enable hdmi dispaly + */ + +&vop { + // assigned-clocks = <&cru DCLK_VOP0>; + //assigned-clock-parents = <&cru PCLK_HDMI>; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&hdmiphy { + status = "okay"; +}; + +&hdmi { + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; diff --git a/rk3528/rp-rk3528-ir.dtsi b/rk3528/rp-rk3528-ir.dtsi new file mode 100755 index 0000000..43b2edb --- /dev/null +++ b/rk3528/rp-rk3528-ir.dtsi @@ -0,0 +1,92 @@ +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x9f00>; + rockchip,key_table = + <0xb0 KEY_BACK>, + <0xbc KEY_UP>, + <0xf5 KEY_DOWN>, + <0xf9 KEY_LEFT>, + <0xf1 KEY_RIGHT>, + <0xb8 KEY_HOME>, + <0x0 KEY_VOLUMEUP>, + <0xa2 KEY_VOLUMEDOWN>, + <0xa8 KEY_POWER>, + <0xe9 KEY_MENU>, + <0xfd KEY_ENTER>; + }; + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; diff --git a/rk3528/rp-usb-rk3528.dtsi b/rk3528/rp-usb-rk3528.dtsi new file mode 100755 index 0000000..3cd6223 --- /dev/null +++ b/rk3528/rp-usb-rk3528.dtsi @@ -0,0 +1,31 @@ +&u2phy_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy>; + status = "okay"; +}; diff --git a/rk3528/rp-wifi-bt-vs2275s-rk3528.dtsi b/rk3528/rp-wifi-bt-vs2275s-rk3528.dtsi new file mode 100755 index 0000000..0c26eaf --- /dev/null +++ b/rk3528/rp-wifi-bt-vs2275s-rk3528.dtsi @@ -0,0 +1,95 @@ + +/{ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <100>; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart2m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart2m1_gpios>; + BT,reset_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + + +&sdio0 { + max-frequency = <200000000>; + no-sd; + no-mmc; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; + /delete-property/ rockchip,use-v2-tuning; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>; +}; + +&pinctrl { + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + bt_gpio: bt-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + uart2m1_gpios: uart2m1-gpios { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3562-amp.dtsi b/rk3562-amp.dtsi new file mode 100644 index 0000000..0cf505c --- /dev/null +++ b/rk3562-amp.dtsi @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + rockchip_amp: rockchip-amp { + compatible = "rockchip,amp"; + clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>, + <&cru PCLK_MAILBOX>, <&cru PCLK_INTC>, + <&cru SCLK_UART7>, <&cru PCLK_UART7>, + <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; + + amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>; + amp-irqs = /bits/ 64 ; + + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* remote amp core address */ + amp_shmem_reserved: amp-shmem@7800000 { + reg = <0x0 0x7800000 0x0 0x400000>; + no-map; + }; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x07c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x08000000 0x0 0x100000>; + no-map; + }; + + /* mcu address */ + mcu_reserved: mcu@8200000 { + reg = <0x0 0x8200000 0x0 0x100000>; + no-map; + }; + + }; + + rpmsg: rpmsg@7c00000 { + compatible = "rockchip,rpmsg"; + mbox-names = "rpmsg-rx", "rpmsg-tx"; + mboxes = <&mailbox 0 &mailbox 3>; + rockchip,vdev-nums = <1>; + /* CPU3: link-id 0x03; MCU: link-id 0x04; */ + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; +}; + +&mailbox { + rockchip,txpoll-period-ms = <1>; + status = "okay"; +}; diff --git a/rk3562-android.dtsi b/rk3562-android.dtsi new file mode 100644 index 0000000..fb1238d --- /dev/null +++ b/rk3562-android.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdhci; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&vop { + support-multi-area; +}; + +&rng { + status = "okay"; +}; diff --git a/rk3562-dictpen-test3-v20.dts b/rk3562-dictpen-test3-v20.dts new file mode 100644 index 0000000..f2198a8 --- /dev/null +++ b/rk3562-dictpen-test3-v20.dts @@ -0,0 +1,1243 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3562.dtsi" +#include "rk3562-linux.dtsi" + +/ { + model = "Rockchip RK3562 DICTPEN TEST3 LP4 V20 Board"; + compatible = "rockchip,rk3562-dictpen-test3-v20", "rockchip,rk3562"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm12 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 50 51 52 53 54 + 55 55 56 57 58 59 60 61 + 62 63 64 64 65 65 66 67 + 68 69 70 71 71 72 73 74 + 75 76 77 78 79 79 80 81 + 82 83 84 85 86 86 87 88 + 89 90 91 92 93 94 94 95 + 96 97 98 99 100 101 101 102 + 103 104 105 106 107 107 108 109 + 110 111 112 113 114 115 115 116 + 117 118 119 120 121 122 123 123 + 124 125 126 127 128 129 130 130 + 131 132 133 134 135 136 136 137 + 138 139 140 141 142 143 143 144 + 145 146 147 147 148 149 150 151 + 152 153 154 155 156 156 157 158 + 159 157 158 159 160 161 162 162 + 163 164 165 166 167 168 169 169 + 170 171 172 173 174 175 175 176 + 177 178 179 180 181 182 182 183 + 184 185 186 187 188 189 190 190 + 191 192 193 194 195 196 197 197 + 198 199 200 201 202 203 204 204 + 205 206 207 208 209 209 210 211 + 212 213 213 214 214 215 215 216 + 216 217 217 218 218 219 219 220 + >; + default-brightness-level = <60>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <2800>; + rockchip,screen-on-voltage = <3000>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + pinctrl-names = "default"; + pinctrl-0 = <&scan_key>; + + button@0 { + label = "home"; + linux,code = ; + gpios = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + debounce-interval = <50>; + }; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk817_codec>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vccsys_lcd: vccsys-lcd { + compatible = "regulator-fixed"; + regulator-name = "vccsys_lcd"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_lcd>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_l>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6203"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,power_gpio = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>; + //BT,wake_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + //BT,wake_host_irq = <&gpio1 RK_PD6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu0_opp_table { + opp-408000000 { + /delete-property/ opp-suspend; + }; + + opp-1200000000 { + opp-suspend; + }; + /delete-node/ opp-1608000000; + /delete-node/ opp-1800000000; + /delete-node/ opp-2016000000; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&sc031gs_out>; + data-lanes = <1>; + }; + + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + power-supply=<&vccsys_lcd>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + + dsi_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gpu_opp_table { + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&otg_switch>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + not-save-power-en = <1>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdda_0v9: vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_npu: vdd_gpu: vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <825000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_ldo1: LDO_REG1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_ldo1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v5_dvp: LDO_REG2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc1v5_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd: LDO_REG5 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_lcd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_ldo7: LDO_REG7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_ldo7"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ntc_table = <42450 40570 38780 37080 35460 33930 + 32460 31070 29750 28490 27280 26140 + 25050 24010 23020 22070 21170 20310 + 19490 18710 17960 17250 16570 15910 + 15290 14700 14130 13590 13070 12570 + 12090 11640 11200 10780 10380 10000 + 9633 9282 8945 8622 8312 8015 7730 + 7456 7194 6942 6700 6468 6245 6031 + 5826 5628 5438 5255 5080 4911 4749 + 4592 4442 4297 4158 4024 3895 3771 + 3651 3536 3425 3318 3215 3115 3019 + 2927 2837 2751 2668 2588>; + ntc_degree_from = <1 10>; + ocv_table = <3400 3653 3679 3704 3731 3750 + 3771 3788 3806 3828 3855 3890 + 3943 3993 4043 4095 4149 4206 + 4264 4321 4377>; + design_capacity = <1000>; + design_qmax = <1010>; + bat_res = <110>; + sleep_enter_current = <30>; + sleep_exit_current = <30>; + sleep_filter_current = <20>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3000>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <26>; + virtual_power = <0>; + chrg_finish_cur = <50>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <2000>; + max_chrg_current = <500>; + max_chrg_voltage = <4400>; + otg5v_suspend_enable = <0>; + chrg_term_mode = <0>; + chrg_finish_cur = <50>; + virtual_power = <0>; + dc_det_adc = <0>; + sample_res = <26>; + extcon = <&u2phy>; + gate_function_disable = <1>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + + power-supply = <&vcc3v3_lcd>; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + + sc031gs: sc031gs@30 { + status = "okay"; + compatible = "smartsens,sc031gs"; + reg = <0x30>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc1v5_dvp>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + + port { + sc031gs_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1>; + }; + }; + }; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&npu_opp_table { + /delete-node/ opp-900000000; + /delete-node/ opp-1000000000; +}; + +&pinctrl { + led_control { + scan_key: scan-key { + rockchip,pins = <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_l: wifi-enable-l { + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm12 { + status = "okay"; + pinctrl-0 = <&pwm12m1_pins>; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ULTRA_MODE + | RKPM_SLP_PMIC_LP + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_OSC_DIS + | RKPM_SLP_32K_PVTM + ) + >; +}; + +&route_dsi { + status = "okay"; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + keep-power-in-suspend; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +/* for inno usb2 phy driver probe and set to phy_sus status */ +&u2phy_host { + /delete-property/ phy-supply; + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&otg_switch>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; + + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&video_phy { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3562-evb.dtsi b/rk3562-evb.dtsi new file mode 100644 index 0000000..c9f16a7 --- /dev/null +++ b/rk3562-evb.dtsi @@ -0,0 +1,596 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <414000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <800000>; + }; + + back-key { + linux,code = ; + label = "back"; + press-threshold-microvolt = <1200000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + pdm_codec: dummy-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdm_codec>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rk-spdif-sound"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&i2c2 { + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm5 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3562-evb1-cam.dtsi b/rk3562-evb1-cam.dtsi new file mode 100644 index 0000000..492863b --- /dev/null +++ b/rk3562-evb1-cam.dtsi @@ -0,0 +1,214 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5695_out0>; + data-lanes = <1 2>; + }; + + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + avdd-supply = <&vcc2v8_dvp>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc1v8_dvp>; + dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out0: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3562-evb1-lp4x-v10-linux-amp.dts b/rk3562-evb1-lp4x-v10-linux-amp.dts new file mode 100644 index 0000000..d39eba9 --- /dev/null +++ b/rk3562-evb1-lp4x-v10-linux-amp.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk817.dtsi" +#include "rk3562-amp.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x02000000 0x0 0x06400000>, + <0x0 0x0a200000 0x0 0xf1e00000>; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; +}; + +/delete-node/ &cpu3; + +&sdmmc0 { + status = "disabled"; +}; diff --git a/rk3562-evb1-lp4x-v10-linux.dts b/rk3562-evb1-lp4x-v10-linux.dts new file mode 100644 index 0000000..a2ac853 --- /dev/null +++ b/rk3562-evb1-lp4x-v10-linux.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk817.dtsi" diff --git a/rk3562-evb1-lp4x-v10-lvds.dts b/rk3562-evb1-lp4x-v10-lvds.dts new file mode 100644 index 0000000..7acba23 --- /dev/null +++ b/rk3562-evb1-lp4x-v10-lvds.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + + +/ { + panel-lvds { + compatible = "simple-panel"; + status = "okay"; + backlight = <&backlight>; + reset-delay-ms = <20>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <164>; + height-mm = <100>; + + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <27000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <15>; + hsync-len = <6>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + }; + +}; + +&backlight { + pwms = <&pwm5 0 25000 0>; + status = "okay"; +}; + +&dsi { + status = "disabled"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp0 { + status = "okay"; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm5 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + status = "okay"; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; diff --git a/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts b/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts new file mode 100644 index 0000000..ed40123 --- /dev/null +++ b/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB MCU PANLE DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-mcu-k350c4516t", "rockchip,rk3562"; +}; + +&backlight { + status = "okay"; + pwms = <&pwm9 0 25000 0>; +}; + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +/* + * The pins of gmac0/pcie2x1 and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&pcie2x1 { + status = "disabled"; +}; + +&pwm9 { + status = "okay"; +}; + +&rgb { + status = "okay"; + rockchip,data-sync-bypass; + pinctrl-names = "default"; + /* + * rgb3x8_pins_m0/rgb3x8_pins_m1 for RGB3x8(8bit) + * rgb565_pins for RGB565(16bit) + */ + pinctrl-0 = <&rgb565_pins>; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + mcu_panel: mcu-panel { + /* + * MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit) + * MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit) + */ + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + init-delay-ms = <10>; + width-mm = <217>; + height-mm = <136>; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + //type delay num val1 val2 val3 + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a + 01 00 01 55 /* + * interface pixel format: + * 66 for RGB3x8(8bit) + * 55 for RGB565(16bit) + */ + + 00 00 01 b0 + 01 00 01 00 + + 00 00 01 b1 + 01 00 01 a0 /* + * frame rate control: + * 70 (45hz) for RGB3x8(8bit) + * a0 (60hz) for RGB565(16bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 02 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 32 01 29 + 00 00 01 2c + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + /* + * 7840125 for frame rate 45Hz + * 10453500 for frame rate 60Hz + */ + clock-frequency = <10453500>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&route_rgb { + status = "okay"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&vcc_mipicsi0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + status = "okay"; + + /* + * Default config is as follows: + * + * mcu-pix-total = <9>; + * mcu-cs-pst = <1>; + * mcu-cs-pend = <8>; + * mcu-rw-pst = <2>; + * mcu-rw-pend = <5>; + * mcu-hold-mode = <0>; // default set to 0 + * + * To increase the frame rate, reduce all parameters because + * the max dclk rate of mcu is 150M in rk3562. + */ + mcu-timing { + mcu-pix-total = <5>; + mcu-cs-pst = <1>; + mcu-cs-pend = <4>; + mcu-rw-pst = <2>; + mcu-rw-pend = <3>; + + mcu-hold-mode = <0>; // default set to 0 + }; +}; diff --git a/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts b/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts new file mode 100644 index 0000000..847e92e --- /dev/null +++ b/rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB VOP3 RGB24BIT DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-FX070-DHM11BOE-A", "rockchip,rk3562"; + + panel: panel { + compatible = "simple-panel"; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + reset-value = <0>; + reset-delay-ms = <10>; + status = "okay"; + + display-timings { + native-mode = <&fx070_dhm11boe_timing>; + + fx070_dhm11boe_timing: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <20>; + hsync-len = <20>; + vsync-len = <2>; //value range <2~22> + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm9 0 25000 0>; + status = "okay"; +}; + +&csi2_dphy0 { + status = "disabled"; +}; + +&dsi { + status = "disabled"; +}; + +/* + * The pins of gmac0/pcie2x1/pdm_codec and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&pcie2x1 { + status = "disabled"; +}; + +&pdm_codec { + status = "disabled"; +}; + +&pwm9 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-0 = <&rgb666_pins>; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&route_rgb { + status = "okay"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&vcc_mipicsi0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; diff --git a/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts b/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts new file mode 100644 index 0000000..ad75ccc --- /dev/null +++ b/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SPI+RGB PANLE DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-rgb-k350c4516t", "rockchip,rk3562"; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_pins>; + spi-delay-us = <10>; + status = "okay"; + + sck-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + miso-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + + /* + * 320x480 RGB/MCU screen K350C4516T + */ + panel: panel { + compatible = "simple-panel-spi"; + reg = <0>; + bus-format = ; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + enable-delay-ms = <20>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + reset-delay-ms = <10>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + init-delay-ms = <10>; + width-mm = <217>; + height-mm = <136>; + rockchip,cmd-type = "spi"; + status = "okay"; + + // type:0 is cmd, 1 is data + panel-init-sequence = [ + /* type delay num val1 val2 val3 */ + 00 00 01 e0 + 01 00 01 00 + 01 00 01 07 + 01 00 01 0f + 01 00 01 0d + 01 00 01 1b + 01 00 01 0a + 01 00 01 3c + 01 00 01 78 + 01 00 01 4a + 01 00 01 07 + 01 00 01 0e + 01 00 01 09 + 01 00 01 1b + 01 00 01 1e + 01 00 01 0f + 00 00 01 e1 + 01 00 01 00 + 01 00 01 22 + 01 00 01 24 + 01 00 01 06 + 01 00 01 12 + 01 00 01 07 + 01 00 01 36 + 01 00 01 47 + 01 00 01 47 + 01 00 01 06 + 01 00 01 0a + 01 00 01 07 + 01 00 01 30 + 01 00 01 37 + 01 00 01 0f + + 00 00 01 c0 + 01 00 01 10 + 01 00 01 10 + + 00 00 01 c1 + 01 00 01 41 + + 00 00 01 c5 + 01 00 01 00 + 01 00 01 22 + 01 00 01 80 + + 00 00 01 36 + 01 00 01 48 + + 00 00 01 3a + 01 00 01 66 /* + * interface pixel format: + * 66 for RGB666(18bit) + */ + + 00 00 01 b0 + 01 00 01 00 + + 00 00 01 b1 + 01 00 01 a0 /* + * frame rate control: + * a0 (60hz) for RGB666(18bit) + */ + 01 00 01 11 + 00 00 01 b4 + 01 00 01 02 + 00 00 01 B6 + 01 00 01 32 /* + * display function control: + * 32 for RGB + * 02 for MCU + */ + 01 00 01 02 + + 00 00 01 b7 + 01 00 01 c6 + + 00 00 01 be + 01 00 01 00 + 01 00 01 04 + + 00 00 01 e9 + 01 00 01 00 + + 00 00 01 f7 + 01 00 01 a9 + 01 00 01 51 + 01 00 01 2c + 01 00 01 82 + + 00 78 01 11 + 00 00 01 29 + ]; + + panel-exit-sequence = [ + //type delay num val1 val2 val3 + 00 0a 01 28 + 00 78 01 10 + ]; + + display-timings { + native-mode = <&kd050fwfba002_timing>; + + kd050fwfba002_timing: timing0 { + /* + * 10453500 for RGB666(18bit) + */ + clock-frequency = <10453500>; + hactive = <320>; + vactive = <480>; + hback-porch = <10>; + hfront-porch = <5>; + vback-porch = <10>; + vfront-porch = <5>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + port { + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; + pwms = <&pwm9 0 25000 0>; +}; + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +/* + * The pins of gmac0/pcie2x1 and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&pcie2x1 { + status = "disabled"; +}; + +&pinctrl { + spi_gpio { + spi_gpio_pins: spi-gpio-pins { + rockchip,pins = + /* spi sdo */ + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + /* spi sdi */ + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + /* spi scl */ + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + /* spi cs */ + <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm9 { + status = "okay"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rgb666_pins>; + + ports { + rgb_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&route_rgb { + status = "okay"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0/vcc_mipicsi0 and rgb are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&vcc_mipicsi0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3562-evb1-lp4x-v10-rgb2lvds.dts b/rk3562-evb1-lp4x-v10-rgb2lvds.dts new file mode 100644 index 0000000..8f05310 --- /dev/null +++ b/rk3562-evb1-lp4x-v10-rgb2lvds.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + + +/ { + panel-rgb { + compatible = "simple-panel"; + status = "okay"; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + reset-delay-ms = <20>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <164>; + height-mm = <100>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <140>; + hfront-porch = <160>; + vback-porch = <20>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm9 0 25000 0>; + status = "okay"; +}; + +&dsi { + status = "disabled"; +}; + +/* + * The pins of gmac0 and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&rgb { + status = "okay"; + pinctrl-0 = <&rgb666_pins>; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&pwm9 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + status = "okay"; +}; + +&route_rgb { + status = "okay"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0 and backlight are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; diff --git a/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts b/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts new file mode 100644 index 0000000..bf76097 --- /dev/null +++ b/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SII9022 RGB2HDMI DISPLAY Ext Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi", "rockchip,rk3562"; +}; + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +/* + * The pins of gmac0 and rgb are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c3m0_xfer>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + bus-format = ; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +/* + * The pins of pcie2x1/pdm_codec and rgb are multiplexed + */ +&pcie2x1 { + status = "disabled"; +}; + +&pdm_codec { + status = "disabled"; +}; + +&pinctrl { + sii902x { + sii902x_hdmi: sii902x-hdmi { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&vo_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&route_rgb { + status = "disabled"; + connect = <&vp0_out_rgb>; +}; + +/* + * The pins of sai0/vcc_mipicsi0/u2phy_host and rgb are multiplexed + */ +&sai0 { + status = "disabled"; +}; + +&u2phy_host { + status = "disabled"; +}; + +&vcc5v0_usb_host { + status = "disabled"; +}; + +&vcc_mipicsi0 { + status = "disabled"; +}; + +&video_phy { + status = "disabled"; +}; diff --git a/rk3562-evb1-lp4x-v10-spdif.dts b/rk3562-evb1-lp4x-v10-spdif.dts new file mode 100644 index 0000000..58ab5ac --- /dev/null +++ b/rk3562-evb1-lp4x-v10-spdif.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dts" + +&spdif_8ch { + /* The pin is conflict with sdmmc0 cmd */ + pinctrl-0 = <&spdifm2_pins>; + status = "okay"; +}; + +&sdmmc0 { + status = "disabled"; +}; diff --git a/rk3562-evb1-lp4x-v10.dts b/rk3562-evb1-lp4x-v10.dts new file mode 100644 index 0000000..296cee0 --- /dev/null +++ b/rk3562-evb1-lp4x-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb1-lp4x-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817.dtsi" diff --git a/rk3562-evb1-lp4x-v10.dtsi b/rk3562-evb1-lp4x-v10.dtsi new file mode 100644 index 0000000..7fdb055 --- /dev/null +++ b/rk3562-evb1-lp4x-v10.dtsi @@ -0,0 +1,569 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "dt-bindings/usb/pd.h" +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include "rk3562-evb1-cam.dtsi" +#include +#include +#include + +/ { + model = "Rockchip RK3562 EVB1 LP4X V10 Board"; + compatible = "rockchip,rk3562-evb1-lp4x-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + rk817_sound: rk817-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&dcdc_boost>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vbat_3v8: vbat-3v8 { + compatible = "regulator-fixed"; + regulator-name = "vbat_3v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + regulator-boot-on; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <0 0x0 + 3300000 0x1>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm7 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_rgmii_clk + &rgmiim0_rgmii_bus + ðm0_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&otg_switch>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + }; + }; +}; + +&i2c5 { + status = "okay"; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + assigned-clocks = <&cru CLK_PMU1_PWM0>; + assigned-clock-rates = <24000000>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + + dr_mode = "otg"; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; diff --git a/rk3562-evb2-cam.dtsi b/rk3562-evb2-cam.dtsi new file mode 100644 index 0000000..3b25402 --- /dev/null +++ b/rk3562-evb2-cam.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + // dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + dw9714_1: dw9714_1@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + // dvdd-supply = <&vcc_mipicsi1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714_1>; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp_vir1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera1 power en */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3562-evb2-ddr4-v10-dual-camera.dts b/rk3562-evb2-ddr4-v10-dual-camera.dts new file mode 100644 index 0000000..f7cb188 --- /dev/null +++ b/rk3562-evb2-ddr4-v10-dual-camera.dts @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + // dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&dw9714>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + ov5695: ov5695@36 { + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM1_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk1_out>; + reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + // dvdd-supply = <&vcc_mipicsi2>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out0: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&rkisp_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3562-evb2-ddr4-v10-image-reverse.dts b/rk3562-evb2-ddr4-v10-image-reverse.dts new file mode 100644 index 0000000..864807b --- /dev/null +++ b/rk3562-evb2-ddr4-v10-image-reverse.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" +#include "rk3562-evb2-nvp6324.dtsi" +#include "rk3562-evb2-image-reverse.dtsi" diff --git a/rk3562-evb2-ddr4-v10-linux-amp.dts b/rk3562-evb2-ddr4-v10-linux-amp.dts new file mode 100644 index 0000000..9938576 --- /dev/null +++ b/rk3562-evb2-ddr4-v10-linux-amp.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk809.dtsi" +#include "rk3562-evb2-cam.dtsi" +#include "rk3562-amp.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x02000000 0x0 0x04b80000>, + <0x0 0x0a200000 0x0 0x75e00000>; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; +}; + +/delete-node/ &cpu3; + +&sdmmc0 { + status = "disabled"; +}; diff --git a/rk3562-evb2-ddr4-v10-linux.dts b/rk3562-evb2-ddr4-v10-linux.dts new file mode 100644 index 0000000..f95406b --- /dev/null +++ b/rk3562-evb2-ddr4-v10-linux.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-linux.dtsi" +#include "rk3562-rk809.dtsi" +#include "rk3562-evb2-cam.dtsi" diff --git a/rk3562-evb2-ddr4-v10-pdm-mic-array.dts b/rk3562-evb2-ddr4-v10-pdm-mic-array.dts new file mode 100644 index 0000000..b10f50b --- /dev/null +++ b/rk3562-evb2-ddr4-v10-pdm-mic-array.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dts" + +&pdm { + /* The pin pdmm0_clk1 is conflict with i2s0_mclk which used by rk809_codec */ + pinctrl-0 = <&pdmm0_clk0 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + status = "okay"; +}; + +&pdm_mic_array { + status = "okay"; +}; + diff --git a/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts b/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts new file mode 100644 index 0000000..c701178 --- /dev/null +++ b/rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi.dts @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" + +/ { + model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB BT1120 TO HDMI V10 Ext Board"; + compatible = "rockchip,rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3562"; +}; + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +/* + * The pins of gamc0 and bt1120 are multiplexed + */ +&gmac0 { + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c1m1_xfer>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + /* + * MEDIA_BUS_FMT_YUYV8_1X16 for bt1120 + * MEDIA_BUS_FMT_UYVY8_2X8 for bt656 + */ + bus-format = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&pinctrl { + sii902x { + sii902x_hdmi_int: sii902x-hdmi-int { + rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + /* + * <&bt1120_pins> for bt1120 + * <&bt656_pins> for bt656 + */ + pinctrl-0 = <&bt1120_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "disabled"; +}; diff --git a/rk3562-evb2-ddr4-v10.dts b/rk3562-evb2-ddr4-v10.dts new file mode 100644 index 0000000..2288139 --- /dev/null +++ b/rk3562-evb2-ddr4-v10.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-evb2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" +#include "rk3562-evb2-cam.dtsi" diff --git a/rk3562-evb2-ddr4-v10.dtsi b/rk3562-evb2-ddr4-v10.dtsi new file mode 100644 index 0000000..5478c8a --- /dev/null +++ b/rk3562-evb2-ddr4-v10.dtsi @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include +#include + +/ { + model = "Rockchip RK3562 EVB2 DDR4 V10 Board"; + compatible = "rockchip,rk3562-evb2-ddr4-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + vcc3v3_clk: vcc3v3-clk { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc25_ddr: vcc25-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc25_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x42>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_rgmii_clk + &rgmiim0_rgmii_bus + ðm0_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c5 { + status = "okay"; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio1 RK_PC7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <3>; + }; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + assigned-clocks = <&cru CLK_PMU1_PWM0>; + assigned-clock-rates = <24000000>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <1>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&pwm6 { + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&sdmmc0 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif_8ch { + pinctrl-0 = <&spdifm0_pins>; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc5v0_usb_otg>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy { + status = "okay"; +}; diff --git a/rk3562-evb2-image-reverse.dtsi b/rk3562-evb2-image-reverse.dtsi new file mode 100644 index 0000000..561128b --- /dev/null +++ b/rk3562-evb2-image-reverse.dtsi @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/{ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_vehicle: drm-vehicle@0{ + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M + linux,cma-default; + }; + }; + + gpio_det: gpio-det { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&vehicle_gpios>; + + /*if use the reverse, please config this*/ + car-reverse { + car-reverse-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + linux,debounce-ms = <5>; + label = "car-reverse"; + gpio,wakeup; + }; + }; + + vehicle: vehicle { + compatible = "rockchip,vehicle"; + status = "okay"; + + // pinctrl-names = "default"; + // pinctrl-0 = <&camm0_clk0_out>; + + clocks = <&cru ACLK_VICAP>, + <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, + <&cru CSIRX0_CLK_DATA>, + <&cru CSIRX1_CLK_DATA>, + <&cru CSIRX2_CLK_DATA>, + <&cru CSIRX3_CLK_DATA>; + clock-names = "aclk_cif", + "hclk_cif", + "dclk_cif", + "csirx0_data", + "csirx1_data", + "csirx2_data", + "csirx3_data"; + resets = <&cru SRST_A_VICAP>, + <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, + <&cru SRST_I0_VICAP>, + <&cru SRST_I1_VICAP>, + <&cru SRST_I2_VICAP>, + <&cru SRST_I3_VICAP>; + reset-names = "rst_cif_a", + "rst_cif_h", + "rst_cif_d", + "rst_cif_i0", + "rst_cif_i1", + "rst_cif_i2", + "rst_cif_i3"; + power-domains = <&power RK3562_PD_VI>; + cif,drop-frames = <4>; //frames to drop + cif,chip-id = <2>; /*0:rk3568 1:rk3588 2:rk3562*/ + rockchip,grf = <&sys_grf>; + rockchip,cru = <&cru>; + rockchip,cif = <&rkcif>; + rockchip,gpio-det = <&gpio_det>; + rockchip,cif-sensor = <&cif_sensor>; + rockchip,cif-phy = <&cif_phy>; + ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25 + /*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/ + vehicle,rotate-mirror = <0x00>; + vehicle,crtc_name = "video_port0"; + vehicle,plane_name = "Esmart0-win0"; + }; + + cif_phy: cif_phy { + status = "okay"; + + csi2_dphy0 { + status = "okay"; + clocks = <&cru CLK_CAM0_OUT2IO>, + <&cru PCLK_CSIPHY0>, + <&cru PCLK_CSIHOST0>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host"; + resets = <&cru SRST_P_CSIPHY0>, + <&cru SRST_P_CSIHOST0>; + reset-names = "srst_p_csiphy", + "srst_csihost_p"; + csihost-idx = <0>; + rockchip,csi2-dphy = <&csi2_dphy0_hw>; + rockchip,csi2 = <&mipi0_csi2>; + }; + csi2_dphy3 { + status = "disabled"; + clocks = <&cru CLK_CAM2_OUT2IO>, + <&cru PCLK_CSIPHY1>, + <&cru PCLK_CSIHOST2>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host"; + resets = <&cru SRST_P_CSIPHY1>, + <&cru SRST_P_CSIHOST2>; + reset-names = "srst_p_csiphy", + "srst_csihost_p"; + csihost-idx = <2>; + rockchip,csi2-dphy = <&csi2_dphy1_hw>; + rockchip,csi2 = <&mipi2_csi2>; + }; + }; + + cif_sensor: cif_sensor { + compatible = "rockchip,sensor"; + status = "okay"; + + nvp6324 { + status = "okay"; + // dphy0 + powerdown-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + pwdn_active = <1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + rst_active = <1>; + // dphy3 + // powerdown-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + // pwdn_active = <1>; + // reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + // rst_active = <1>; + + orientation = <90>; + i2c_add = <0x60>; + i2c_chl = <4>; + cif_chl = <0>; + ad_chl = <0>; + mclk_rate = <24>; + rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_vehicle>; + memory-region-names = "drm-logo", "drm-vehicle"; +}; + +&i2c4 { + status = "okay"; +}; + +&pinctrl { + vehicle { + vehicle_gpios: vehicle-pins { + /* gpios */ + rockchip,pins = + /* car-reverse */ + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3562-evb2-nvp6324.dtsi b/rk3562-evb2-nvp6324.dtsi new file mode 100644 index 0000000..07b53bf --- /dev/null +++ b/rk3562-evb2-nvp6324.dtsi @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&n4_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + jaguar1: jaguar1@30 { + compatible = "jaguar1-v4l2"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pd-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "jaguar1"; + rockchip,camera-module-lens-name = "jaguar1"; + rockchip,default_rect= <1920 1080>; // default resolution + port { + n4_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3562-iotest-lp3-v10-dsm.dts b/rk3562-iotest-lp3-v10-dsm.dts new file mode 100644 index 0000000..403924d --- /dev/null +++ b/rk3562-iotest-lp3-v10-dsm.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + + #include "rk3562-iotest-lp3-v10.dts" + +&dsm { + status = "okay"; +}; + +&dsm_sound { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sdmmc0 { + status = "disabled"; +}; diff --git a/rk3562-iotest-lp3-v10-linux.dts b/rk3562-iotest-lp3-v10-linux.dts new file mode 100644 index 0000000..44ef84c --- /dev/null +++ b/rk3562-iotest-lp3-v10-linux.dts @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-linux.dtsi" + +/ { + model = "Rockchip RK3562 IOTEST LP3 V10 Board"; + compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + dsm_sound: dsm-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&dsm>; + }; + }; +}; + +#include "rk3562-rk809.dtsi" + +&combphy_pu { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; diff --git a/rk3562-iotest-lp3-v10.dts b/rk3562-iotest-lp3-v10.dts new file mode 100644 index 0000000..3b5681c --- /dev/null +++ b/rk3562-iotest-lp3-v10.dts @@ -0,0 +1,576 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" +#include + +/ { + model = "Rockchip RK3562 IOTEST LP3 V10 Board"; + compatible = "rockchip,rk3562-iotest-lp3-v10", "rockchip,rk3562"; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + test-power { + status = "okay"; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + dsm_sound: dsm-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&dsm>; + }; + }; +}; + +&combphy_pu { + status = "okay"; +}; + + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + status = "okay"; + //rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gpu { + status = "okay"; + mali-supply = <&vdd_gpu>; +}; + +&i2c2 { + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA7 GPIO_ACTIVE_LOW>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm5 { + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&video_phy { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3562-linux.dtsi b/rk3562-linux.dtsi new file mode 100644 index 0000000..4f32ff5 --- /dev/null +++ b/rk3562-linux.dtsi @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/rk3562-pinctrl.dtsi b/rk3562-pinctrl.dtsi new file mode 100644 index 0000000..b311448 --- /dev/null +++ b/rk3562-pinctrl.dtsi @@ -0,0 +1,2352 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + cam { + /omit-if-no-ref/ + camm0_clk0_out: camm0-clk0-out { + rockchip,pins = + /* camm0_clk0_out */ + <3 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm0_clk1_out: camm0-clk1-out { + rockchip,pins = + /* camm0_clk1_out */ + <3 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk0_out: camm1-clk0-out { + rockchip,pins = + /* camm1_clk0_out */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + camm1_clk1_out: camm1-clk1-out { + rockchip,pins = + /* camm1_clk1_out */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk2_out: cam-clk2-out { + rockchip,pins = + /* cam_clk2_out */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clk3_out: cam-clk3-out { + rockchip,pins = + /* cam_clk3_out */ + <3 RK_PB5 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* can0_tx_m0 */ + <3 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <3 RK_PB7 6 &pcfg_pull_none>, + /* can0_tx_m1 */ + <3 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m2_pins: can0m2-pins { + rockchip,pins = + /* can0_rx_m2 */ + <0 RK_PC7 2 &pcfg_pull_none>, + /* can0_tx_m2 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* can1_tx_m0 */ + <1 RK_PC0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* can1_tx_m1 */ + <0 RK_PC0 4 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clk_32k_in: clk-32k-in { + rockchip,pins = + /* clk_32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + clk0 { + /omit-if-no-ref/ + clk0_32k_out: clk0-32k-out { + rockchip,pins = + /* clk0_32k_out */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + }; + + clk1 { + /omit-if-no-ref/ + clk1_32k_out: clk1-32k-out { + rockchip,pins = + /* clk1_32k_out */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + }; + + dsm { + /omit-if-no-ref/ + dsm_pins: dsm-pins { + rockchip,pins = + /* dsm_aud_ln */ + <1 RK_PB4 5 &pcfg_pull_none>, + /* dsm_aud_lp */ + <1 RK_PB3 5 &pcfg_pull_none>, + /* dsm_aud_rn */ + <1 RK_PB6 6 &pcfg_pull_none>, + /* dsm_aud_rp */ + <1 RK_PB5 6 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + ethm0_pins: ethm0-pins { + rockchip,pins = + /* eth_clk_25m_out_m0 */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ethm1_pins: ethm1-pins { + rockchip,pins = + /* eth_clk_25m_out_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PB1 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PA0 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PA1 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PA2 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PB4 5 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PB5 5 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <3 RK_PD3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <3 RK_PA0 1 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <3 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <4 RK_PA5 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <4 RK_PA6 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PB6 5 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PB7 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC2 1 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PC7 4 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD0 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PA2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PA3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi0: i2s0m0-sdi0 { + rockchip,pins = + /* i2s0_sdi0_m0 */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi1: i2s0m0-sdi1 { + rockchip,pins = + /* i2s0_sdi1_m0 */ + <3 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi2: i2s0m0-sdi2 { + rockchip,pins = + /* i2s0_sdi2_m0 */ + <3 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi3: i2s0m0-sdi3 { + rockchip,pins = + /* i2s0_sdi3_m0 */ + <3 RK_PA6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo0: i2s0m0-sdo0 { + rockchip,pins = + /* i2s0_sdo0_m0 */ + <3 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo1: i2s0m0-sdo1 { + rockchip,pins = + /* i2s0_sdo1_m0 */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo2: i2s0m0-sdo2 { + rockchip,pins = + /* i2s0_sdo2_m0 */ + <3 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m0_sdo3: i2s0m0-sdo3 { + rockchip,pins = + /* i2s0_sdo3_m0 */ + <3 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PC4 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PC6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PC5 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi0: i2s0m1-sdi0 { + rockchip,pins = + /* i2s0_sdi0_m1 */ + <1 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi1: i2s0m1-sdi1 { + rockchip,pins = + /* i2s0_sdi1_m1 */ + <1 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi2: i2s0m1-sdi2 { + rockchip,pins = + /* i2s0_sdi2_m1 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi3: i2s0m1-sdi3 { + rockchip,pins = + /* i2s0_sdi3_m1 */ + <1 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo0: i2s0m1-sdo0 { + rockchip,pins = + /* i2s0_sdo0_m1 */ + <1 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo1: i2s0m1-sdo1 { + rockchip,pins = + /* i2s0_sdo1_m1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo2: i2s0m1-sdo2 { + rockchip,pins = + /* i2s0_sdo2_m1 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_sdo3: i2s0m1-sdo3 { + rockchip,pins = + /* i2s0_sdo3_m1 */ + <2 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1_lrck_m0 */ + <3 RK_PC6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1_mclk_m0 */ + <3 RK_PC4 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1_sclk_m0 */ + <3 RK_PC5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1_sdi0_m0 */ + <3 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1_sdi1_m0 */ + <3 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1_sdi2_m0 */ + <3 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1_sdi3_m0 */ + <3 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1_sdo0_m0 */ + <3 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1_sdo1_m0 */ + <4 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1_sdo2_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1_sdo3_m0 */ + <4 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1_lrck_m1 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1_mclk_m1 */ + <3 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1_sclk_m1 */ + <3 RK_PB3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1_sdi0_m1 */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1_sdi1_m1 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1_sdi2_m1 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1_sdi3_m1 */ + <3 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1_sdo0_m1 */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1_sdo1_m1 */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1_sdo2_m1 */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1_sdo3_m1 */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2_lrck_m0 */ + <1 RK_PD6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2_mclk_m0 */ + <2 RK_PA1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2_sclk_m0 */ + <1 RK_PD5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2_sdi_m0 */ + <2 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2_sdo_m0 */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2_lrck_m1 */ + <4 RK_PA1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2_mclk_m1 */ + <3 RK_PD6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2_sclk_m1 */ + <4 RK_PB1 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2_sdi_m1 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2_sdo_m1 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flash_trigin */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* isp_flash_trigout */ + <3 RK_PC3 2 &pcfg_pull_none>, + /* isp_prelight_trigout */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_mcu_tck_m0 */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m0 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_mcu_tck_m1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* jtag_cpu_mcu_tms_m1 */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqn_m0 */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* pcie20_perstn_m0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* pcie20_waken_m0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqn_m1 */ + <3 RK_PA6 4 &pcfg_pull_none>, + /* pcie20_perstn_m1 */ + <3 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_waken_m1 */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk0: pdmm0-clk0 { + rockchip,pins = + /* pdm_clk0_m0 */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdm_clk1_m0 */ + <3 RK_PA2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdm_sdi0_m0 */ + <3 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdm_sdi1_m0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdm_sdi2_m0 */ + <3 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdm_sdi3_m0 */ + <3 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk0: pdmm1-clk0 { + rockchip,pins = + /* pdm_clk0_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdm_clk1_m1 */ + <4 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdm_sdi0_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdm_sdi1_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdm_sdi2_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdm_sdi3_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_int: pmic-int { + rockchip,pins = + <0 RK_PA3 0 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + soc_slppin_gpio: soc-slppin-gpio { + rockchip,pins = + <0 RK_PA2 0 &pcfg_output_low>; + }; + + /omit-if-no-ref/ + soc_slppin_slp: soc-slppin-slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PC3 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PC7 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <0 RK_PA7 1 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <1 RK_PD0 3 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PB7 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PD1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PC2 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <1 RK_PD2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC1 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PD3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <0 RK_PC0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PD4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PC1 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PA5 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PC2 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <1 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <1 RK_PC3 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_m0 */ + <1 RK_PB6 5 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_m1 */ + <1 RK_PC4 4 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <4 RK_PA1 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <3 RK_PB4 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <3 RK_PB5 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC5 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <1 RK_PD7 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_m0 */ + <3 RK_PC6 4 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_m1 */ + <2 RK_PA0 5 &pcfg_pull_none_drv_level_1>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + ref_pins: ref-pins { + rockchip,pins = + /* ref_clk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmiim0_miim: rgmiim0-miim { + rockchip,pins = + /* rgmii_mdc_m0 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* rgmii_mdio_m0 */ + <4 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_er: rgmiim0-rx_er { + rockchip,pins = + /* rgmii_rxer_m0 */ + <4 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rx_bus2: rgmiim0-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0_m0 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_rxdv_m0 */ + <4 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_tx_bus2: rgmiim0-tx_bus2 { + rockchip,pins = + /* rgmii_txd0_m0 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_txd1_m0 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_txen_m0 */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_clk: rgmiim0-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk_m0 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* rgmii_txclk_m0 */ + <3 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_rgmii_bus: rgmiim0-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2_m0 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* rgmii_txd2_m0 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_txd3_m0 */ + <3 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim0_clk: rgmiim0-clk { + rockchip,pins = + /* rgmiim0_clk */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_miim: rgmiim1-miim { + rockchip,pins = + /* rgmii_mdc_m1 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_er: rgmiim1-rx_er { + rockchip,pins = + /* rgmii_rxer_m1 */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rx_bus2: rgmiim1-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0_m1 */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_tx_bus2: rgmiim1-tx_bus2 { + rockchip,pins = + /* rgmii_txd0_m1 */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* rgmii_txd1_m1 */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* rgmii_txen_m1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_clk: rgmiim1-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk_m1 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_rgmii_bus: rgmiim1-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2_m1 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* rgmii_txd2_m1 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_txd3_m1 */ + <1 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmiim1_clk: rgmiim1-clk { + rockchip,pins = + /* rgmiim1_clk */ + <1 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + rmii { + /omit-if-no-ref/ + rmii_pins: rmii-pins { + rockchip,pins = + /* rmii_clk */ + <1 RK_PD5 5 &pcfg_pull_none>, + /* rmii_mdc */ + <1 RK_PC7 5 &pcfg_pull_none>, + /* rmii_mdio */ + <1 RK_PD0 5 &pcfg_pull_none>, + /* rmii_rxd0 */ + <1 RK_PD4 5 &pcfg_pull_none>, + /* rmii_rxd1 */ + <1 RK_PD7 6 &pcfg_pull_none>, + /* rmii_rxdv_crs */ + <1 RK_PD6 5 &pcfg_pull_none>, + /* rmii_rxer */ + <2 RK_PA0 6 &pcfg_pull_none>, + /* rmii_txd0 */ + <1 RK_PD1 5 &pcfg_pull_none>, + /* rmii_txd1 */ + <1 RK_PD2 5 &pcfg_pull_none>, + /* rmii_txen */ + <1 RK_PD3 5 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_detn */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_detn */ + <1 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <0 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC3 3 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m0 */ + <0 RK_PC5 3 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m0 */ + <0 RK_PC4 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m0_csn0: spi0m0-csn0 { + rockchip,pins = + /* spi0m0_csn0 */ + <0 RK_PC2 3 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m0_csn1: spi0m0-csn1 { + rockchip,pins = + /* spi0m0_csn1 */ + <0 RK_PB7 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <3 RK_PB5 4 &pcfg_pull_none_drv_level_3>, + /* spi0_miso_m1 */ + <3 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi0_mosi_m1 */ + <3 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi0m1_csn0: spi0m1-csn0 { + rockchip,pins = + /* spi0m1_csn0 */ + <3 RK_PB7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi0m1_csn1: spi0m1-csn1 { + rockchip,pins = + /* spi0m1_csn1 */ + <3 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <3 RK_PD6 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m0 */ + <4 RK_PA3 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m0 */ + <4 RK_PA2 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m0_csn0: spi1m0-csn0 { + rockchip,pins = + /* spi1m0_csn0 */ + <3 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m0_csn1: spi1m0-csn1 { + rockchip,pins = + /* spi1m0_csn1 */ + <4 RK_PA0 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <1 RK_PC0 4 &pcfg_pull_none_drv_level_3>, + /* spi1_miso_m1 */ + <1 RK_PB4 4 &pcfg_pull_none_drv_level_3>, + /* spi1_mosi_m1 */ + <1 RK_PB3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi1m1_csn0: spi1m1-csn0 { + rockchip,pins = + /* spi1m1_csn0 */ + <1 RK_PB6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi1m1_csn1: spi1m1-csn1 { + rockchip,pins = + /* spi1m1_csn1 */ + <1 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <4 RK_PB6 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m0 */ + <3 RK_PD2 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m0 */ + <3 RK_PD3 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m0_csn0: spi2m0-csn0 { + rockchip,pins = + /* spi2m0_csn0 */ + <4 RK_PB5 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m0_csn1: spi2m0-csn1 { + rockchip,pins = + /* spi2m0_csn1 */ + <4 RK_PB4 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <2 RK_PA1 4 &pcfg_pull_none_drv_level_3>, + /* spi2_miso_m1 */ + <2 RK_PA0 4 &pcfg_pull_none_drv_level_3>, + /* spi2_mosi_m1 */ + <1 RK_PD7 4 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + spi2m1_csn0: spi2m1-csn0 { + rockchip,pins = + /* spi2m1_csn0 */ + <1 RK_PD6 4 &pcfg_pull_none_drv_level_3>; + }; + /omit-if-no-ref/ + spi2m1_csn1: spi2m1-csn1 { + rockchip,pins = + /* spi2m1_csn1 */ + <1 RK_PD5 4 &pcfg_pull_none_drv_level_3>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_pins: tsadcm0-pins { + rockchip,pins = + /* tsadc_shut_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_pins: tsadcm1-pins { + rockchip,pins = + /* tsadc_shut_m1 */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <1 RK_PB3 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <1 RK_PB4 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <1 RK_PD1 1 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <1 RK_PD2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <1 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PA6 3 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PA5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PC1 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PC0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA1 2 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA0 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <3 RK_PA2 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <3 RK_PA3 2 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB5 6 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB4 6 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <4 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PC0 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB7 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_ctsn: uart3m1-ctsn { + rockchip,pins = + /* uart3m1_ctsn */ + <3 RK_PB6 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3m1_rtsn: uart3m1-rtsn { + rockchip,pins = + /* uart3m1_rtsn */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PD1 3 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PD0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <3 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <1 RK_PD5 3 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <1 RK_PD6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_ctsn: uart4m1-ctsn { + rockchip,pins = + /* uart4m1_ctsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4m1_rtsn: uart4m1-rtsn { + rockchip,pins = + /* uart4m1_rtsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PB7 3 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PB5 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PA7 5 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PA6 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <3 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <0 RK_PC7 1 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <0 RK_PC6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <4 RK_PB0 5 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <4 RK_PA7 5 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PC7 3 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PC4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PD2 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PD3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 3 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB4 3 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <3 RK_PB3 3 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <3 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <3 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PD5 3 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PD7 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <4 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <4 RK_PB3 3 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <4 RK_PB2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <3 RK_PC3 3 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <3 RK_PC2 3 &pcfg_pull_up>; + }; + }; + + vo { + /omit-if-no-ref/ + vo_pins: vo-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d0 */ + <4 RK_PA4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d1 */ + <4 RK_PA5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d8 */ + <4 RK_PA6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d9 */ + <4 RK_PA7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d16 */ + <4 RK_PB0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d17 */ + <4 RK_PB1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + vo { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m0: rgb3x8-pins-m0 { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb3x8_pins_m1: rgb3x8-pins-m1 { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb565_pins: rgb565-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + rgb666_pins: rgb666-pins { + rockchip,pins = + /* vo_lcdc_clk */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_4>, + /* vo_lcdc_d2 */ + <4 RK_PB2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d3 */ + <3 RK_PC4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d4 */ + <3 RK_PC5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d5 */ + <3 RK_PC6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d6 */ + <3 RK_PC7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d7 */ + <3 RK_PD0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d10 */ + <3 RK_PD1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d11 */ + <3 RK_PD2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d12 */ + <3 RK_PD3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d13 */ + <3 RK_PD4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d14 */ + <3 RK_PD5 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d15 */ + <3 RK_PD6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d18 */ + <4 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d19 */ + <3 RK_PD7 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d20 */ + <4 RK_PA0 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d21 */ + <4 RK_PA1 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d22 */ + <4 RK_PA2 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_d23 */ + <4 RK_PA3 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_den */ + <4 RK_PB6 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_hsync */ + <4 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* vo_lcdc_vsync */ + <4 RK_PB5 1 &pcfg_pull_none_drv_level_3>; + }; + }; +}; diff --git a/rk3562-rk809.dtsi b/rk3562-rk809.dtsi new file mode 100644 index 0000000..02f9191 --- /dev/null +++ b/rk3562-rk809.dtsi @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&i2c0 { + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG1 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc1v8_dvp: LDO_REG9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; diff --git a/rk3562-rk817-tablet-camera.dtsi b/rk3562-rk817-tablet-camera.dtsi new file mode 100644 index 0000000..f2d5399 --- /dev/null +++ b/rk3562-rk817-tablet-camera.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ +/ { + vcc_mipipwr: vcc-mipipwr-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicam_pwr>; + regulator-name = "vcc_mipipwr"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + + dw9763: dw9763@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + avdd-supply = <&vcc2v8_dvp>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <25>; + rockchip,vcm-rated-current = <100>; + rockchip,vcm-step-mode = <4>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13855: ov13855@36 { + status = "okay"; + compatible = "ovti,ov13855"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc_mipipwr>; + dvdd-supply = <&vcc1v2_dvp>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763>; + + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + avdd-supply = <&vcc2v8_dvp>; + dovdd-supply = <&vcc_mipipwr>; + dvdd-supply = <&vcc1v2_dvp>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0_in0>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir0_in1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp_vir0_in1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipicam_pwr: mipicam-pwr { + rockchip,pins = + /* camera power en */ + <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3562-rk817-tablet-v10.dts b/rk3562-rk817-tablet-v10.dts new file mode 100644 index 0000000..4f9edc0 --- /dev/null +++ b/rk3562-rk817-tablet-v10.dts @@ -0,0 +1,1060 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "rk3562.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk817-tablet-camera.dtsi" + +/ { + model = "Rockchip RK3562 RK817 TABLET LP4 Board"; + compatible = "rockchip,rk3562-rk817-tablet", "rockchip,rk3562"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 50 51 52 53 54 + 55 55 56 57 58 59 60 61 + 62 63 64 64 65 65 66 67 + 68 69 70 71 71 72 73 74 + 75 76 77 78 79 79 80 81 + 82 83 84 85 86 86 87 88 + 89 90 91 92 93 94 94 95 + 96 97 98 99 100 101 101 102 + 103 104 105 106 107 107 108 109 + 110 111 112 113 114 115 115 116 + 117 118 119 120 121 122 123 123 + 124 125 126 127 128 129 130 130 + 131 132 133 134 135 136 136 137 + 138 139 140 141 142 143 143 144 + 145 146 147 147 148 149 150 151 + 152 153 154 155 156 156 157 158 + 159 157 158 159 160 161 162 162 + 163 164 165 166 167 168 169 169 + 170 171 172 173 174 175 175 176 + 177 178 179 180 181 182 182 183 + 184 185 186 187 188 189 190 190 + 191 192 193 194 195 196 197 197 + 198 199 200 201 202 203 204 204 + 205 206 207 208 209 209 210 211 + 212 213 213 214 214 215 215 216 + 216 217 217 218 218 219 219 220 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc0 4>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm7 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi { + status = "okay"; + + panel@0 { + compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; + reg = <0>; + + backlight = <&backlight>; + //power-supply=<&vcc_3v3>; + enable-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>; + + prepare-delay-ms = <20>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + width-mm = <135>; + height-mm = <216>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 15 00 02 E0 00 + //--- PASSWORD ----// + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 80 03 + //--- Page1 ----// + 15 00 02 E0 01 + //Set VCOM + 15 00 02 00 00 + 15 00 02 01 3B + //Set VCOM_Reverse + //15 00 02 03 00 + //15 00 02 04 A0 + 15 00 02 0C 74 + //Set Gamma Power, VGMP,VGMN,VGSP,VGSN + 15 00 02 17 00 + 15 00 02 18 AF //VGMP=4.8V + 15 00 02 19 00 //VGSP=0.3V + 15 00 02 1A 00 + 15 00 02 1B AF + 15 00 02 1C 00 + //SETPANEL + 15 00 02 35 26 //ASP=0110 + //SETPANEL + 15 00 02 37 09 //SS=1,BGR=1 + //SET RGBCYC + 15 00 02 38 04 //JDT=100 column inversion + 15 00 02 39 00 //RGB_N_EQ1, 0x12 + 15 00 02 3A 01 //RGB_N_EQ2, 0x18 + 15 00 02 3C 78 //SET EQ3 for TE_H + 15 00 02 3D FF //SET CHGEN_ON, + 15 00 02 3E FF //SET CHGEN_OFF, + 15 00 02 3F 7F //SET CHGEN_OFF2, + //Set TCON + 15 00 02 40 06 //RSO=800 RGB + 15 00 02 41 A0 //LN=640->1280 line + 15 00 02 42 81 //SLT + 15 00 02 43 14 //VFP=20 + 15 00 02 44 23 //VBP=24 + 15 00 02 45 28 //HBP=40 + //--- power voltage ----// + 15 00 02 55 02 //DCDCM=0001, JD PWR_IC + 15 00 02 57 69 + 15 00 02 59 0A //VCL = -2.9V + 15 00 02 5A 2A //VGH = 15V + 15 00 02 5B 17 //VGL = -11V + //--- Gamma ----// + 15 00 02 5D 7F + 15 00 02 5E 6B + 15 00 02 5F 5C + 15 00 02 60 4F + 15 00 02 61 4D + 15 00 02 62 3F + 15 00 02 63 42 + 15 00 02 64 2B + 15 00 02 65 44 + 15 00 02 66 43 + 15 00 02 67 43 + 15 00 02 68 63 + 15 00 02 69 52 + 15 00 02 6A 5A + 15 00 02 6B 4F + 15 00 02 6C 4E + 15 00 02 6D 20 + 15 00 02 6E 0F + 15 00 02 6F 00 + 15 00 02 70 7F + 15 00 02 71 6B + 15 00 02 72 5C + 15 00 02 73 4F + 15 00 02 74 4D + 15 00 02 75 3F + 15 00 02 76 42 + 15 00 02 77 2B + 15 00 02 78 44 + 15 00 02 79 43 + 15 00 02 7A 43 + 15 00 02 7B 63 + 15 00 02 7C 52 + 15 00 02 7D 5A + 15 00 02 7E 4F + 15 00 02 7F 4E + 15 00 02 80 20 + 15 00 02 81 0F + 15 00 02 82 00 + //Page2, for GIP + 15 00 02 E0 02 + //GIP_L Pin mapping + 15 00 02 00 02 //STV3 -> STV2 + 15 00 02 01 02 //Stv3 -> STV2 + 15 00 02 02 00 //STV4 -> STV0 + 15 00 02 03 00 //STV4 -> STV0 + 15 00 02 04 1E //VDS -> VGH + 15 00 02 05 1E //VDS -> VGH + 15 00 02 06 1F //VSD -> VGL + 15 00 02 07 1F //VSD -> VGL + 15 00 02 08 1F + 15 00 02 09 17 //VDD2 -> FLM + 15 00 02 0A 17 //VDD2 -> FLM + 15 00 02 0B 37 //VDD1 -> INV_FLM + 15 00 02 0C 37 //VDD1 -> INV_FLM + 15 00 02 0D 47 //CLK8 -> CLK3 + 15 00 02 0E 47 //CLK8 -> CLK3 + 15 00 02 0F 45 //CLK6 -> CLK1 + 15 00 02 10 45 //CLK6 -> CLK1 + 15 00 02 11 4B //CLK4 -> CLK7 + 15 00 02 12 4B //CLK4 -> CLK7 + 15 00 02 13 49 //CLK2 -> CLK5 + 15 00 02 14 49 //CLK2 -> CLK5 + 15 00 02 15 1F //VGL + //GIP_R Pin mapping + 15 00 02 16 01 //STV1 -> STV1 + 15 00 02 17 01 //STV1 -> STV1 + 15 00 02 18 00 //STV2 -> STV0 + 15 00 02 19 00 //STV2 -> STV0 + 15 00 02 1A 1E //VDS -> VGH + 15 00 02 1B 1E //VDS -> VGH + 15 00 02 1C 1F //VSD -> VGL + 15 00 02 1D 1F //VSD -> VGL + 15 00 02 1E 1F + 15 00 02 1F 17 //VDD2 -> FLM + 15 00 02 20 17 //VDD2 -> FLM + 15 00 02 21 37 //VDD1 -> INV_FLM + 15 00 02 22 37 //VDD1 -> INV_FLM + 15 00 02 23 46 //CLK7 -> CLK2 + 15 00 02 24 46 //CLK7 -> CLK2 + 15 00 02 25 44 //CLK5 -> CLK0 + 15 00 02 26 44 //CLK5 -> CLK0 + 15 00 02 27 4A //CLK3 -> CLK6 + 15 00 02 28 4A //CLK3 -> CLK6 + 15 00 02 29 48 //CLK1 -> CLK4 + 15 00 02 2A 48 //CLK1 -> CLK4 + 15 00 02 2B 1F //VGL + //GIP_L_GS Pin mapping + 15 00 02 2C 01 //STV3 -> STV1 + 15 00 02 2D 01 + 15 00 02 2E 00 //STV4 -> STV0 + 15 00 02 2F 00 + 15 00 02 30 1F //VDS -> VGL + 15 00 02 31 1F + 15 00 02 32 1E //VSD -> VGH + 15 00 02 33 1E + 15 00 02 34 1F // + 15 00 02 35 17 //VDD2 -> FLM + 15 00 02 36 17 + 15 00 02 37 37 //VDD1 -> INV_FLM + 15 00 02 38 37 + 15 00 02 39 08 //CLK8 -> CLK4 + 15 00 02 3A 08 + 15 00 02 3B 0A //CLK6 -> CLK6 + 15 00 02 3C 0A + 15 00 02 3D 04 //CLK4 -> CLK0 + 15 00 02 3E 04 + 15 00 02 3F 06 //CLK2 -> CLK2 + 15 00 02 40 06 + 15 00 02 41 1F //VGL + //GIP_R_GS Pin mapping + 15 00 02 42 02 //STV1 -> STV2 + 15 00 02 43 02 + 15 00 02 44 00 //STV2 -> STV0 + 15 00 02 45 00 + 15 00 02 46 1F //VDS -> VGL + 15 00 02 47 1F + 15 00 02 48 1E //VSD -> VGH + 15 00 02 49 1E + 15 00 02 4A 1F // + 15 00 02 4B 17 //VDD2 -> FLM + 15 00 02 4C 17 + 15 00 02 4D 37 //VDD1 -> INV_FLM + 15 00 02 4E 37 + 15 00 02 4F 09 //CLK7 -> CLK5 + 15 00 02 50 09 + 15 00 02 51 0B //CLK5 -> CLK7 + 15 00 02 52 0B + 15 00 02 53 05 //CLK3 -> CLK1 + 15 00 02 54 05 + 15 00 02 55 07 //CLK1 -> CLK3 + 15 00 02 56 07 + 15 00 02 57 1F //VGL + //GIP Timing + 15 00 02 58 40 + 15 00 02 5B 30 //STV_NUM,STV_S0 + 15 00 02 5C 16 //STV_S0 + 15 00 02 5D 34 //STV_W / S1 + 15 00 02 5E 05 //STV_S2 + 15 00 02 5F 02 //STV_S3 + 15 00 02 63 00 //SETV_ON + 15 00 02 64 6A //SETV_OFF + 15 00 02 67 73 + 15 00 02 68 1D //CKV_S0 + 15 00 02 69 08 + 15 00 02 6A 6A + 15 00 02 6B 08 //Dummy clk + 15 00 02 6C 00 + 15 00 02 6D 00 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 75 FF + 15 00 02 77 DD //VEN_EN=1 + 15 00 02 78 3F + 15 00 02 79 15 //0x0C + 15 00 02 7A 17 //VEN_S0 + 15 00 02 7D 14 //VEN_ON + 15 00 02 7E 82 //VEN_OFF + //Page4 + 15 00 02 E0 04 + 15 00 02 00 0E + 15 00 02 02 B3 + 15 00 02 09 61 + 15 00 02 0E 48 + //Page0 + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 0C + 05 78 01 11 + 05 64 01 29 + ]; + + panel-exit-sequence = [ + 05 01 01 28 + 05 03 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <70000000>; + hactive = <800>; + vactive = <1280>; + + hfront-porch = <40>; + hsync-len = <20>; + hback-porch = <20>; + + vfront-porch = <20>; + vsync-len = <4>; + vback-porch = <20>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v2_dvp: LDO_REG8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc1v2_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3671 3686 3712 3738 3756 3773 + 3787 3802 3819 3840 3868 3916 3959 + 3998 4041 4087 4138 4191 4247 4313>; + design_capacity = <5780>; + design_qmax = <6358>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3950>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4350>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + gate_function_disable = <1>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <25>; + use-ext-amplifier; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + + ts@40 { + compatible = "GSL,GSL3673_800X1280"; + reg = <0x40>; + irq_gpio_number = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + rst_gpio_number = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio0 RK_PA7 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + tp { + tp_gpio: tp-gpio { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>, + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_enable_gpio: lcd-enable-gpio { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&route_dsi { + status = "okay"; +}; + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <200000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&otg_switch>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&video_phy { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3562-rk817.dtsi b/rk3562-rk817.dtsi new file mode 100644 index 0000000..8bfd246 --- /dev/null +++ b/rk3562-rk817.dtsi @@ -0,0 +1,254 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; diff --git a/rk3562-test1-ddr3-v10.dts b/rk3562-test1-ddr3-v10.dts new file mode 100644 index 0000000..31e4a7c --- /dev/null +++ b/rk3562-test1-ddr3-v10.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-test1-ddr3-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" + +&rk809_codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&mclkout_sai2>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai2>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_mclk>; + hp-volume = <20>; + spk-volume = <3>; + /delete-property/ mic-in-differential; + status = "okay"; +}; diff --git a/rk3562-test1-ddr3-v10.dtsi b/rk3562-test1-ddr3-v10.dtsi new file mode 100644 index 0000000..5bd49a1 --- /dev/null +++ b/rk3562-test1-ddr3-v10.dtsi @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include + +/ { + model = "Rockchip RK3562 TEST1 DDR3 V10 Board"; + compatible = "rockchip,rk3562-test1-ddr3-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai2>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg_pwren>; + }; + + vcc3v3_clk: vcc3v3-clk { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_clk"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc25_ddr: vcc25-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc25_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + tx_delay = <0x3f>; + /* rx_delay = <0x3f>; */ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_miim + &rgmiim1_tx_bus2 + &rgmiim1_rx_bus2 + &rgmiim1_rgmii_clk + &rgmiim1_rgmii_bus + ðm1_pins>; + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +>1x { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + /* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ + power-supply = <&vcc3v3_lcd_n>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&route_dsi { + status = "okay"; +}; + +&sai2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; +}; + +&sdmmc0 { + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc1 { + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd &sdmmc1_det>; + /* Should disable gmac0 and fix hardware if enabling sdmmc1 */ + status = "disabled"; +}; + +&pwm6 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + status = "okay"; + phy-supply = <&vcc5v0_usb_host>; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&vcc5v0_usb_otg>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy { + status = "okay"; +}; diff --git a/rk3562-test2-ddr4-v10.dts b/rk3562-test2-ddr4-v10.dts new file mode 100644 index 0000000..8116283 --- /dev/null +++ b/rk3562-test2-ddr4-v10.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562-test2-ddr4-v10.dtsi" +#include "rk3562-android.dtsi" +#include "rk3562-rk809.dtsi" diff --git a/rk3562-test2-ddr4-v10.dtsi b/rk3562-test2-ddr4-v10.dtsi new file mode 100644 index 0000000..37d8eb5 --- /dev/null +++ b/rk3562-test2-ddr4-v10.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3562.dtsi" +#include "rk3562-evb.dtsi" +#include +#include + +/ { + model = "Rockchip RK3562 TEST2 DDR4 V10 Board"; + compatible = "rockchip,rk3562-test2-ddr4-v10", "rockchip,rk3562"; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&dsi { + status = "okay"; +}; + +&dsi_in_vp0 { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_clk>; + + phy-handle = <&rmii_phy>; + status = "okay"; +}; + +&mdio0 { + rmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pwm6 { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +&video_phy { + status = "okay"; +}; diff --git a/rk3562.dtsi b/rk3562.dtsi new file mode 100644 index 0000000..7c15aba --- /dev/null +++ b/rk3562.dtsi @@ -0,0 +1,3072 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3562"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; + csi2dphy3 = &csi2_dphy3; + csi2dphy4 = &csi2_dphy4; + csi2dphy5 = &csi2_dphy5; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + rkcif_mipi_lvds0= &rkcif_mipi_lvds; + rkcif_mipi_lvds1= &rkcif_mipi_lvds1; + rkcif_mipi_lvds2= &rkcif_mipi_lvds2; + rkcif_mipi_lvds3= &rkcif_mipi_lvds3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &sfc; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + hclk_vepu: hclk_vepu@ff100324 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100324 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VI>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vdpu: aclk_vdpu@ff100328 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100328 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_TOP_VIO>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vi_isp: aclk_vi_isp@ff10032c { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff10032c 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_TOP_VIO>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vo: aclk_vo@ff100334 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100334 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_TOP_VIO>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vepu: aclk_vepu@ff100324 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100324 0 0x10>; + clock-names = "link"; + clocks = <&aclk_vi_isp>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rga_jdec: aclk_rga_jdec@ff100338 { + compatible = "rockchip,rk3562-clock-gate-link"; + reg = <0 0xff100338 0 0x10>; + clock-names = "link"; + clocks = <&aclk_vo>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + mclkin_sai0: mclkin-sai0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mclk_sai0_from_io"; + }; + + mclkin_sai1: mclkin-sai1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mclk_sai1_from_io"; + }; + + mclkin_sai2: mclkin-sai2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "mclk_sai2_from_io"; + }; + + mclkout_sai0: mclkout-sai0@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI0_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai0_to_io"; + rockchip,bit-shift = <4>; + }; + + mclkout_sai1: mclkout-sai1@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI1_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai1_to_io"; + rockchip,bit-shift = <9>; + }; + + mclkout_sai2: mclkout-sai2@ff040070 { + compatible = "rockchip,clk-out"; + reg = <0 0xff040070 0 0x4>; + clocks = <&cru MCLK_SAI2_OUT2IO>; + #clock-cells = <0>; + clock-output-names = "mclk_sai2_to_io"; + rockchip,bit-shift = <11>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&scmi_clk ARMCLK>; + cpu-idle-states = <&CPU_SLEEP>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <138>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <120>; + exit-latency-us = <250>; + min-residency-us = <900>; + }; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + mbist-vmin = <825000 900000 975000>; + nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&mbist_vmin>, <&cpu_pvtpll>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm"; + + rockchip,pvtm-voltage-sel = < + 0 1280 0 + 1281 1350 1 + 1351 1420 2 + 1421 1490 3 + 1491 9999 4 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x634>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&sys_grf>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <925000>; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1150000>; + opp-microvolt-L0 = <850000 850000 1150000>; + opp-microvolt-L1 = <825000 825000 1150000>; + opp-microvolt-L2 = <825000 825000 1150000>; + opp-microvolt-L3 = <825000 825000 1150000>; + opp-microvolt-L4 = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <925000 925000 1150000>; + opp-microvolt-L0 = <925000 925000 1150000>; + opp-microvolt-L1 = <900000 900000 1150000>; + opp-microvolt-L2 = <875000 875000 1150000>; + opp-microvolt-L3 = <850000 850000 1150000>; + opp-microvolt-L4 = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1000000 1000000 1150000>; + opp-microvolt-L0 = <1000000 1000000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <950000 950000 1150000>; + opp-microvolt-L3 = <925000 925000 1150000>; + opp-microvolt-L4 = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1037500 1037500 1150000>; + opp-microvolt-L0 = <1037500 1037500 1150000>; + opp-microvolt-L1 = <1012500 1012500 1150000>; + opp-microvolt-L2 = <987500 987500 1150000>; + opp-microvolt-L3 = <962500 962500 1150000>; + opp-microvolt-L4 = <937500 937500 1150000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1125000 1125000 1150000>; + opp-microvolt-L0 = <1125000 1125000 1150000>; + opp-microvolt-L1 = <1100000 1100000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + opp-microvolt-L3 = <1050000 1050000 1150000>; + opp-microvolt-L4 = <1025000 1025000 1150000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <1150000 1150000 1150000>; + opp-microvolt-L0 = <1150000 1150000 1150000>; + opp-microvolt-L1 = <1150000 1150000 1150000>; + opp-microvolt-L2 = <1125000 1125000 1150000>; + opp-microvolt-L3 = <1100000 1100000 1150000>; + opp-microvolt-L4 = <1075000 1075000 1150000>; + clock-latency-ns = <40000>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + /* dphy0 full mode */ + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy0 split mode 01 */ + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy0 split mode 23 */ + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 full mode */ + csi2_dphy3: csi2-dphy3 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 split mode 01 */ + csi2_dphy4: csi2-dphy4 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + /* dphy1 split mode 23 */ + csi2_dphy5: csi2-dphy5 { + compatible = "rockchip,rk3562-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + status = "disabled"; + }; + + csu: csu { + compatible = "rockchip,rk3562-csu"; + rockchip,clock = , + , + , + ; + rockchip,bus = <0 0x00a000a8 0x7001>, + <1 0x00a000a8 0x7c39>, + <2 0x00a000a8 0x7c39>, + <3 0x00a000a8 0x7c39>, + <4 0x00a000a4 0xb007>, + <5 0x00a000a8 0x7034>, + <6 0x00a000a8 0x7034>, + <7 0x00a000a8 0x7034>, + <8 0x00a000a8 0x7001>; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + status = "disabled"; + + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + /* devfreq = <&dmc>; */ + + route { + route_dsi: route-dsi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dsi>; + }; + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_lvds>; + }; + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_rgb>; + }; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3562-dmc"; + interrupts = ; + interrupt-names = "complete"; + devfreq-events = <&dfi>; + clocks = <&scmi_clk CLK_DDR>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + upthreshold = <40>; + downdifferential = <20>; + system-status-level = < + /*system status freq level*/ + SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH + SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW + SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH + SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH + SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH + SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH + >; + auto-min-freq = <324000>; + auto-freq-en = <1>; + #cooling-cells = <2>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <850000 900000 925000>; + nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&log_mbist_vmin>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <900000>; + + rockchip,leakage-voltage-sel = < + 1 15 0 + 16 20 1 + 21 254 2 + >; + + opp-1560000000 { + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <900000 900000 950000>; + opp-microvolt-L0 = <900000 900000 950000>; + opp-microvolt-L1 = <875000 875000 950000>; + opp-microvolt-L2 = <850000 850000 950000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <3>; + rockchip,resetgroup-count = <3>; + status = "disabled"; + }; + + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2 { + compatible = "rockchip,rk3562-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + vendor_storage_rm: vendor-storage-rm@00000000 { + compatible = "rockchip,vendor-storage-rm"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + }; + + rkcif_mipi_lvds: rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds1: rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds2: rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds3: rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkisp_vir0: rkisp-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir1: rkisp-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir2: rkisp-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir3: rkisp-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <685>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + trips { + threshold: trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + vendor_storage: vendor-storage { + compatible = "rockchip,ram-vendor-storage"; + memory-region = <&vendor_storage_rm>; + status = "okay"; + }; + + scmi_shmem: scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + }; + + usbdrd30: usbdrd { + compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>, + <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>; + clock-names = "ref", "suspend", "bus", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: usb@fe500000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3562_PD_PHP>; + resets = <&cru SRST_USB3OTG>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "disabled"; + }; + }; + + gic: interrupt-controller@fe901000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xfe901000 0 0x1000>, + <0x0 0xfe902000 0 0x2000>, + <0x0 0xfe904000 0 0x2000>, + <0x0 0xfe906000 0 0x2000>; + interrupts = ; + }; + + usb_host0_ehci: usb@fed00000 { + compatible = "generic-ehci"; + reg = <0x0 0xfed00000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fed40000 { + compatible = "generic-ohci"; + reg = <0x0 0xfed40000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>, + <&u2phy>; + clock-names = "usbhost", "arbiter", "utmi"; + phys = <&u2phy_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + debug: debug@fed90000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfed90000 0x0 0x2000>, + <0x0 0xfed92000 0x0 0x2000>, + <0x0 0xfed94000 0x0 0x2000>, + <0x0 0xfed96000 0x0 0x2000>; + }; + + qos_dma2ddr: qos@fee03800 { + compatible = "syscon"; + reg = <0x0 0xfee03800 0x0 0x20>; + }; + + shaping_dam2ddr: shaping@fee03888 { + compatible = "syscon"; + reg = <0x0 0xfee03888 0x0 0x4>; + }; + + qos_mcu: qos@fee10000 { + compatible = "syscon"; + reg = <0x0 0xfee10000 0x0 0x20>; + }; + + shaping_mcu: shaping@fee10088 { + compatible = "syscon"; + reg = <0x0 0xfee10088 0x0 0x4>; + }; + + qos_dft_apb: qos@fee10100 { + compatible = "syscon"; + reg = <0x0 0xfee10100 0x0 0x20>; + }; + + shaping_dft_apb: shaping@fee10188 { + compatible = "syscon"; + reg = <0x0 0xfee10188 0x0 0x4>; + }; + + qos_gmac: qos@fee10200 { + compatible = "syscon"; + reg = <0x0 0xfee10200 0x0 0x20>; + }; + + shaping_gmac: shaping@fee10288 { + compatible = "syscon"; + reg = <0x0 0xfee10288 0x0 0x4>; + }; + + qos_mac100: qos@fee10300 { + compatible = "syscon"; + reg = <0x0 0xfee10300 0x0 0x20>; + }; + + shaping_mac100: shaping@fee10388 { + compatible = "syscon"; + reg = <0x0 0xfee10388 0x0 0x4>; + }; + + qos_dcf: qos@fee10400 { + compatible = "syscon"; + reg = <0x0 0xfee10400 0x0 0x20>; + }; + + qos_cpu: qos@fee20000 { + compatible = "syscon"; + reg = <0x0 0xfee20000 0x0 0x20>; + }; + + shaping_cpu: shaping@fee20088 { + compatible = "syscon"; + reg = <0x0 0xfee20088 0x0 0x4>; + }; + + qos_daplite_apb: qos@fee20100 { + compatible = "syscon"; + reg = <0x0 0xfee20100 0x0 0x20>; + }; + + shaping_daplite_apb: shaping@fee20188 { + compatible = "syscon"; + reg = <0x0 0xfee20188 0x0 0x4>; + }; + + qos_gpu: qos@fee30000 { + compatible = "syscon"; + reg = <0x0 0xfee30000 0x0 0x20>; + priority-init = <0x202>; + }; + + shaping_gpu: shaping@fee30088 { + compatible = "syscon"; + reg = <0x0 0xfee30088 0x0 0x4>; + }; + + qos_npu: qos@fee40000 { + compatible = "syscon"; + reg = <0x0 0xfee40000 0x0 0x20>; + }; + + shaping_npu: shaping@fee40088 { + compatible = "syscon"; + reg = <0x0 0xfee40088 0x0 0x4>; + }; + + qos_rkvdec: qos@fee50000 { + compatible = "syscon"; + reg = <0x0 0xfee50000 0x0 0x20>; + }; + + shaping_rkvdec: shaping@fee50088 { + compatible = "syscon"; + reg = <0x0 0xfee50088 0x0 0x4>; + }; + + qos_vepu: qos@fee60000 { + compatible = "syscon"; + reg = <0x0 0xfee60000 0x0 0x20>; + }; + + shaping_vepu: shaping@fee60088 { + compatible = "syscon"; + reg = <0x0 0xfee60088 0x0 0x4>; + }; + + qos_isp: qos@fee70000 { + compatible = "syscon"; + reg = <0x0 0xfee70000 0x0 0x20>; + }; + + shaping_isp: shaping@fee70088 { + compatible = "syscon"; + reg = <0x0 0xfee70088 0x0 0x4>; + }; + + qos_vicap: qos@fee70100 { + compatible = "syscon"; + reg = <0x0 0xfee70100 0x0 0x20>; + }; + + shaping_vicap: shaping@fee70188 { + compatible = "syscon"; + reg = <0x0 0xfee70188 0x0 0x4>; + }; + + qos_vop: qos@fee80000 { + compatible = "syscon"; + reg = <0x0 0xfee80000 0x0 0x20>; + }; + + shaping_vop: shaping@fee80088 { + compatible = "syscon"; + reg = <0x0 0xfee80088 0x0 0x4>; + }; + + qos_jpeg: qos@fee90000 { + compatible = "syscon"; + reg = <0x0 0xfee90000 0x0 0x20>; + }; + + shaping_jpeg: shaping@fee90088 { + compatible = "syscon"; + reg = <0x0 0xfee90088 0x0 0x4>; + }; + + qos_rga_rd: qos@fee90100 { + compatible = "syscon"; + reg = <0x0 0xfee90100 0x0 0x20>; + }; + + shaping_rga_rd: shaping@fee90188 { + compatible = "syscon"; + reg = <0x0 0xfee90188 0x0 0x4>; + }; + + qos_rga_wr: qos@fee90200 { + compatible = "syscon"; + reg = <0x0 0xfee90200 0x0 0x20>; + }; + + shaping_rga_wr: shaping@fee90288 { + compatible = "syscon"; + reg = <0x0 0xfee90288 0x0 0x4>; + }; + + qos_pcie: qos@feea0000 { + compatible = "syscon"; + reg = <0x0 0xfeea0000 0x0 0x20>; + }; + + shaping_pcie: shaping@feea0088 { + compatible = "syscon"; + reg = <0x0 0xfeea0088 0x0 0x4>; + shaping-init = <0x5>; + }; + + qos_usb3: qos@feea0100 { + compatible = "syscon"; + reg = <0x0 0xfeea0100 0x0 0x20>; + }; + + shaping_usb3: shaping@feea0188 { + compatible = "syscon"; + reg = <0x0 0xfeea0188 0x0 0x4>; + }; + + qos_crypto_apb: qos@feeb0000 { + compatible = "syscon"; + reg = <0x0 0xfeeb0000 0x0 0x20>; + }; + + shaping_crypto_apb: shaping@feeb0088 { + compatible = "syscon"; + reg = <0x0 0xfeeb0088 0x0 0x4>; + }; + + qos_crypto: qos@feeb0100 { + compatible = "syscon"; + reg = <0x0 0xfeeb0100 0x0 0x20>; + }; + + shaping_crypto: shaping@feeb0188 { + compatible = "syscon"; + reg = <0x0 0xfeeb0188 0x0 0x4>; + }; + + qos_dmac: qos@feeb0200 { + compatible = "syscon"; + reg = <0x0 0xfeeb0200 0x0 0x20>; + }; + + shaping_dmac: shaping@feeb0288 { + compatible = "syscon"; + reg = <0x0 0xfeeb0288 0x0 0x4>; + }; + + qos_emmc: qos@feeb0300 { + compatible = "syscon"; + reg = <0x0 0xfeeb0300 0x0 0x20>; + }; + + shaping_emmc: shaping@feeb0388 { + compatible = "syscon"; + reg = <0x0 0xfeeb0388 0x0 0x4>; + }; + + qos_fspi: qos@feeb0400 { + compatible = "syscon"; + reg = <0x0 0xfeeb0400 0x0 0x20>; + }; + + shaping_fspi: shaping@feeb0488 { + compatible = "syscon"; + reg = <0x0 0xfeeb0488 0x0 0x4>; + }; + + qos_rkdma: qos@feeb0500 { + compatible = "syscon"; + reg = <0x0 0xfeeb0500 0x0 0x20>; + }; + + shaping_rkdma: shaping@feeb0588 { + compatible = "syscon"; + reg = <0x0 0xfeeb0588 0x0 0x4>; + }; + + qos_sdmmc0: qos@feeb0600 { + compatible = "syscon"; + reg = <0x0 0xfeeb0600 0x0 0x20>; + }; + + shaping_sdmmc0: shaping@feeb0688 { + compatible = "syscon"; + reg = <0x0 0xfeeb0688 0x0 0x4>; + }; + + qos_sdmmc1: qos@feeb0700 { + compatible = "syscon"; + reg = <0x0 0xfeeb0700 0x0 0x20>; + }; + + shaping_sdmmc1: shaping@feeb0788 { + compatible = "syscon"; + reg = <0x0 0xfeeb0788 0x0 0x4>; + }; + + qos_usb2: qos@feeb0800 { + compatible = "syscon"; + reg = <0x0 0xfeeb0800 0x0 0x20>; + }; + + shaping_usb2: shaping@feeb0888 { + compatible = "syscon"; + reg = <0x0 0xfeeb0888 0x0 0x4>; + }; + + pmu_grf: syscon@ff010000 { + compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff010000 0x0 0x10000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x220>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + sys_grf: syscon@ff030000 { + compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff030000 0x0 0x10000>; + + lvds: lvds { + compatible = "rockchip,rk3562-lvds"; + phys = <&video_phy>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_lvds>; + status = "disabled"; + }; + }; + }; + }; + }; + + peri_grf: syscon@ff040000 { + compatible = "rockchip,rk3562-peri-grf", "syscon"; + reg = <0x0 0xff040000 0x0 0x10000>; + }; + + ioc_grf: syscon@ff060000 { + compatible = "rockchip,rk3562-ioc-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff060000 0x0 0x30000>; + + rgb: rgb { + compatible = "rockchip,rk3562-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&vo_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_rgb>; + status = "disabled"; + }; + }; + }; + }; + }; + + usbphy_grf: syscon@ff090000 { + compatible = "rockchip,rk3562-usbphy-grf", "syscon"; + reg = <0x0 0xff090000 0x0 0x8000>; + }; + + pipephy_grf: syscon@ff098000 { + compatible = "rockchip,rk3562-pipephy-grf", "syscon"; + reg = <0x0 0xff098000 0x0 0x8000>; + }; + + cru: clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0x0 0xff100000 0x0 0x40000>; + rockchip,grf = <&sys_grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_HPLL>; + assigned-clock-rates = + <1188000000>, <1000000000>, <983040000>; + }; + + i2c0: i2c@ff200000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xff200000 0x0 0x1000>; + clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@ff210000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff210000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 0>; + status = "disabled"; + }; + + spi0: spi@ff220000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff220000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru SCLK_IN_PMU1_SPI0>; + clock-names = "spiclk", "apb_pclk", "sclk_in"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + pwm0: pwm@ff230000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@ff230010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@ff230020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@ff230030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff230030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@ff258000 { + compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xff258000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3562-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3562_PD_GPU { + reg = ; + pm_qos = <&qos_gpu>; + pm_shaping = <&shaping_gpu>; + }; + /* These power domains are grouped by VD_NPU */ + pd_npu@RK3562_PD_NPU { + reg = ; + pm_qos = <&qos_npu>; + pm_shaping = <&shaping_npu>; + }; + /* These power domains are grouped by VD_LOGIC */ + pd_vdpu@RK3562_PD_VDPU { + reg = ; + pm_qos = <&qos_rkvdec>; + pm_shaping = <&shaping_rkvdec>; + }; + pd_vi@RK3562_PD_VI { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + pm_qos = <&qos_isp>, + <&qos_vicap>; + pm_shaping = <&shaping_isp>, + <&shaping_vicap>; + + pd_vepu@RK3562_PD_VEPU { + reg = ; + pm_qos = <&qos_vepu>; + pm_shaping = <&shaping_vepu>; + }; + }; + pd_vo@RK3562_PD_VO { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + pm_qos = <&qos_vop>; + pm_shaping= <&shaping_vop>; + + pd_rga@RK3562_PD_RGA { + reg = ; + pm_qos = <&qos_rga_rd>, + <&qos_rga_wr>, + <&qos_jpeg>; + pm_shaping = <&shaping_rga_rd>, + <&shaping_rga_wr>, + <&shaping_jpeg>; + }; + }; + pd_php@RK3562_PD_PHP { + reg = ; + pm_qos = <&qos_pcie>, + <&qos_usb3>; + pm_shaping = <&shaping_pcie>, + <&shaping_usb3>; + }; + }; + }; + + pmu_mailbox: mailbox@ff290000 { + compatible = "rockchip,rk3562-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xff290000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_PMU1_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + rknpu: npu@ff300000 { + compatible = "rockchip,rk3562-rknpu"; + reg = <0x0 0xff300000 0x0 0x10000>; + interrupts = ; + clocks = <&scmi_clk ACLK_RKNN>, <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; + clock-names = "scmi_clk", "aclk", "hclk"; + assigned-clocks = <&cru ACLK_RKNN>; + assigned-clock-rates = <600000000>; + resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3562_PD_NPU>; + operating-points-v2 = <&npu_opp_table>; + iommus = <&rknpu_mmu>; + status = "disabled"; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 975000>; + nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&mbist_vmin>, <&npu_pvtpll>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm"; + + rockchip,pvtm-voltage-sel = < + 0 760 0 + 761 800 1 + 801 840 2 + 841 880 3 + 881 9999 4 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x674>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <900000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&sys_grf>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <925000>; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <875000 875000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + opp-microvolt-L1 = <850000 850000 1000000>; + opp-microvolt-L2 = <825000 825000 1000000>; + opp-microvolt-L3 = <825000 825000 1000000>; + opp-microvolt-L4 = <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <925000 925000 1000000>; + opp-microvolt-L0 = <925000 925000 1000000>; + opp-microvolt-L1 = <900000 900000 1000000>; + opp-microvolt-L2 = <875000 875000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; + opp-microvolt-L4 = <825000 825000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <975000 975000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + opp-microvolt-L4 = <875000 875000 1000000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <1000000 1000000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + opp-microvolt-L3 = <950000 950000 1000000>; + opp-microvolt-L4 = <925000 925000 1000000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <1000000 1000000 1000000>; + opp-microvolt-L2 = <1000000 1000000 1000000>; + opp-microvolt-L3 = <975000 975000 1000000>; + opp-microvolt-L4 = <950000 950000 1000000>; + }; + }; + + rknpu_mmu: iommu@ff30a000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff30a000 0x0 0x40>; + interrupts = ; + interrupt-names = "rknpu_mmu"; + clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3562_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@ff320000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xff320000 0x0 0x4000>; + + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + + upthreshold = <40>; + downdifferential = <10>; + + clocks = <&scmi_clk CLK_GPU>, <&cru CLK_GPU>, + <&cru CLK_GPU_BRG>, <&cru ACLK_GPU_PRE>; + clock-names = "clk_mali", "clk_gpu", "clk_gpu_brg", "aclk_gpu"; + power-domains = <&power RK3562_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <820>; + + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 975000>; + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&mbist_vmin>, <&gpu_pvtpll>; + nvmem-cell-names = "leakage", "opp-info", "mbist-vmin", "pvtm"; + + rockchip,pvtm-voltage-sel = < + 0 780 0 + 781 820 1 + 821 860 2 + 861 900 3 + 901 9999 4 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x654>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <900000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <0 0>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,grf = <&sys_grf>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <925000>; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <825000 825000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>; + opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <825000 825000 1000000>; + opp-microvolt-L4 = <825000 825000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L0 = <950000 950000 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; + opp-microvolt-L4 = <900000 900000 1000000>; + }; + }; + + rkvdec: rkvdec@ff340100 { + compatible = "rockchip,rkv-decoder-rk3562", "rockchip,rkv-decoder-v2"; + reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; + rockchip,normal-rates = <198000000>, <0>, <396000000>; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <198000000>, <396000000>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_HEVC_CA>; + reset-names = "video_a", "video_h", "video_hevc_cabac"; + power-domains = <&power RK3562_PD_VDPU>; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + rockchip,task-capacity = <16>; + status = "disabled"; + }; + + rkvdec_mmu: iommu@ff340800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "aclk", "iface", "clk_hevc_cabac"; + power-domains = <&power RK3562_PD_VDPU>; + rockchip,shootdown-entire; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkvenc: rkvenc@ff360000 { + compatible = "rockchip,rkv-encoder-rk3562", "rockchip,rkv-encoder-v2"; + reg = <0x0 0xff360000 0x0 0x6000>; + interrupts = ; + interrupt-names = "irq_rkvenc"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <297000000>, <0>, <297000000>; + resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, + <&cru SRST_RKVENC_CORE>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; + assigned-clock-rates = <297000000>, <297000000>; + power-domains = <&power RK3562_PD_VEPU>; + iommus = <&rkvenc_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + status = "disabled"; + }; + + rkvenc_mmu: iommu@ff36f000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff36f000 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvenc_mmu"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3562_PD_VEPU>; + rockchip,shootdown-entire; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi0_csi2_hw: mipi0-csi2-hw@ff380000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; + reg = <0x0 0xff380000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST0>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST0>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi1_csi2_hw: mipi1-csi2-hw@ff390000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; + reg = <0x0 0xff390000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST1>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST1>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi2_csi2_hw: mipi2-csi2-hw@ff3a0000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; + reg = <0x0 0xff3a0000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST2>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST2>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi3_csi2_hw: mipi3-csi2-hw@ff3b0000 { + compatible = "rockchip,rk3562-mipi-csi2-hw"; + reg = <0x0 0xff3b0000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSIHOST3>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSIHOST3>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 { + compatible = "rockchip,rk3562-csi2-dphy-hw"; + reg = <0x0 0xff3c0000 0x0 0x10000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + resets = <&cru SRST_P_CSIPHY0>; + reset-names = "srst_p_csiphy0"; + rockchip,grf = <&sys_grf>; + status = "okay"; + }; + + csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 { + compatible = "rockchip,rk3562-csi2-dphy-hw"; + reg = <0x0 0xff3d0000 0x0 0x10000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + resets = <&cru SRST_P_CSIPHY1>; + reset-names = "srst_p_csiphy1"; + rockchip,grf = <&sys_grf>; + status = "okay"; + }; + + rkcif: rkcif@ff3e0000 { + compatible = "rockchip,rk3562-cif"; + reg = <0x0 0xff3e0000 0x0 0x800>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, + <&cru CSIRX0_CLK_DATA>, <&cru CSIRX1_CLK_DATA>, + <&cru CSIRX2_CLK_DATA>, <&cru CSIRX3_CLK_DATA>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif", + "csirx0_data", "csirx1_data", "csirx2_data", + "csirx3_data"; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, + <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>, + <&cru SRST_I3_VICAP>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", + "rst_cif_i0", "rst_cif_i1", "rst_cif_i2", + "rst_cif_i3"; + power-domains = <&power RK3562_PD_VI>; + rockchip,grf = <&sys_grf>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mmu: iommu@ff3e0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff3e0800 0x0 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3562_PD_VI>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkisp: isp@ff3f0000 { + compatible = "rockchip,rk3562-rkisp"; + reg = <0x0 0xff3f0000 0x0 0x7f00>; + interrupts = , + , + ; + interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp_core"; + power-domains = <&power RK3562_PD_VI>; + iommus = <&rkisp_mmu>; + status = "disabled"; + }; + + rkisp_mmu: iommu@ff3f7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff3f7f00 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + power-domains = <&power RK3562_PD_VI>; + status = "disabled"; + }; + + vop: vop@ff400000 { + compatible = "rockchip,rk3562-vop"; + reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP>; + clock-names = "aclk_vop", + "hclk_vop", + "dclk_vp0"; + resets = <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP>; + reset-names = "axi", + "ahb", + "dclk_vp0"; + rockchip,csu = <&csu CSU_VOP_ACLK>; + rockchip,csu-names = "aclk"; + iommus = <&vop_mmu>; + power-domains = <&power RK3562_PD_VO>; + rockchip,grf = <&ioc_grf>; + assigned-clocks = <&cru DCLK_VOP>; + assigned-clock-parents = <&cru PLL_VPLL>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&rgb_in_vp0>; + }; + + vp0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vp0>; + }; + + vp0_out_lvds: endpoint@2 { + reg = <2>; + remote-endpoint = <&lvds_in_vp0>; + }; + }; + }; + }; + + vop_mmu: iommu@ff407e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff407e00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "disabled"; + }; + + rga2: rga@ff440000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xff440000 0x0 0x1000>; + interrupts = ; + interrupt-names = "rga2_irq"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; + iommus = <&rga2_mmu>; + power-domains = <&power RK3562_PD_RGA>; + status = "disabled"; + }; + + rga2_mmu: iommu@ff440f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff440f00 0x0 0x100>; + interrupts = ; + interrupt-names = "rga2_mmu"; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3562_PD_RGA>; + status = "disabled"; + }; + + jpegd: jpegd@ff450000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xff450000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,disable-auto-freq; + resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; + reset-names = "video_a", "video_h"; + power-domains = <&power RK3562_PD_RGA>; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + status = "disabled"; + }; + + jpegd_mmu: iommu@ff450480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xff450480 0x0 0x40>; + interrupts = ; + interrupt-names = "jpegd_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + power-domains = <&power RK3562_PD_RGA>; + rockchip,shootdown-entire; + #iommu-cells = <0>; + status = "disabled"; + }; + + dfi: dfi@ff4c0000 { + reg = <0x00 0xff4c0000 0x00 0x400>; + compatible = "rockchip,rk3562-dfi"; + rockchip,pmugrf = <&pmu_grf>; + status = "disabled"; + }; + + pcie2x1: pcie@ff500000 { + compatible = "rockchip,rk3562-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xff>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + , + ; + interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <8>; + num-viewport = <8>; + num-ob-windows = <2>; + max-link-speed = <2>; + num-lanes = <1>; + phys = <&combphy_pu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3562_PD_PHP>; + ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 + 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 + 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 + 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe000000 0x0 0x400000>, + <0x0 0xff500000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + }; + }; + + spi1: spi@ff640000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff640000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>; + clock-names = "spiclk", "apb_pclk", "sclk_in"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi2: spi@ff650000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xff650000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>, <&cru SCLK_IN_SPI2>; + clock-names = "spiclk", "apb_pclk", "sclk_in"; + dmas = <&dmac 17>, <&dmac 16>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + uart1: serial@ff670000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 10>, <&dmac 1>; /* tx:10 rx:1 */ + status = "disabled"; + }; + + uart2: serial@ff680000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 2>; /* rx:2 */ + status = "disabled"; + }; + + uart3: serial@ff690000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 3>; /* rx:3 */ + status = "disabled"; + }; + + uart4: serial@ff6a0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 4>; /* rx:4 */ + status = "disabled"; + }; + + uart5: serial@ff6b0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 11>, <&dmac 5>; /* tx:11 rx:5 */ + status = "disabled"; + }; + + uart6: serial@ff6c0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 6>; /* rx:6 */ + status = "disabled"; + }; + + uart7: serial@ff6d0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 7>; /* rx:7 */ + status = "disabled"; + }; + + uart8: serial@ff6e0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6e0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 8>; /* rx:8 */ + status = "disabled"; + }; + + uart9: serial@ff6f0000 { + compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff6f0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac 9>; /* rx:9 */ + status = "disabled"; + }; + + pwm4: pwm@ff700000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@ff700010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@ff700020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@ff700030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff700030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@ff710000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@ff710010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@ff710020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@ff710030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff710030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@ff720000 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@ff720010 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@ff720020 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@ff720030 { + compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xff720030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + saradc0: saradc@ff730000 { + compatible = "rockchip,rk3562-saradc"; + reg = <0x0 0xff730000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + u2phy: usb2-phy@ff740000 { + compatible = "rockchip,rk3562-usb2phy"; + reg = <0x0 0xff740000 0x0 0x10000>; + clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>; + clock-names = "phyclk", "pclk"; + #clock-cells = <0>; + clock-output-names = "usb480m_phy"; + rockchip,usbgrf = <&usbphy_grf>; + status = "disabled"; + + u2phy_otg: otg-port { + #phy-cells = <0>; + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", "linestate"; + status = "disabled"; + }; + + u2phy_host: host-port { + #phy-cells = <0>; + interrupts = ; + interrupt-names = "linestate"; + status = "disabled"; + }; + }; + + combphy_pu: phy@ff750000 { + compatible = "rockchip,rk3562-naneng-combphy"; + reg = <0x0 0xff750000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>, + <&cru PCLK_PHP>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&cru CLK_PIPEPHY_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&peri_grf>; + rockchip,pipe-phy-grf = <&pipephy_grf>; + status = "disabled"; + }; + + sai0: sai@ff800000 { + compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; + reg = <0x0 0xff800000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru CLK_SAI0_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; + dmas = <&dmac 19>, <&dmac 18>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0 + &i2s0m0_sdo1 + &i2s0m0_sdo2 + &i2s0m0_sdo3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI0"; + status = "disabled"; + }; + + sai1: sai@ff810000 { + compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; + reg = <0x0 0xff810000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru CLK_SAI1_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; + dmas = <&dmac 21>, <&dmac 20>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI1"; + status = "disabled"; + }; + + sai2: sai@ff820000 { + compatible = "rockchip,rk3562-sai", "rockchip,sai-v1"; + reg = <0x0 0xff820000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru CLK_SAI2_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; + dmas = <&dmac 23>, <&dmac 22>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>; + reset-names = "m", "h"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_lrck + &i2s2m0_sclk + &i2s2m0_sdi + &i2s2m0_sdo>; + #sound-dai-cells = <0>; + sound-name-prefix = "SAI2"; + status = "disabled"; + }; + + pdm: pdm@ff830000 { + compatible = "rockchip,rk3562-pdm", "rockchip,rv1126-pdm"; + reg = <0x0 0xff830000 0x0 0x1000>; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + assigned-clocks = <&cru MCLK_PDM>; + assigned-clock-parents = <&cru PLL_HPLL>; + dmas = <&dmac 31>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm0_clk0 + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_8ch: spdif@ff840000 { + compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xff840000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac 30>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; + assigned-clocks = <&cru CLK_SPDIF_SRC>; + assigned-clock-parents = <&cru PLL_HPLL>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_pins>; + status = "disabled"; + }; + + dsm: dsm@ff850000 { + compatible = "rockchip,rk3562-dsm"; + reg = <0x0 0xff850000 0x0 0x1000>; + clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>; + clock-names = "dac", "pclk"; + resets = <&cru SRST_DSM>; + reset-names = "reset" ; + rockchip,grf = <&peri_grf>; + pinctrl-names = "default"; + pinctrl-0 = <&dsm_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sfc: spi@ff860000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xff860000 0x0 0x10000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhci: mmc@ff870000 { + compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc"; + reg = <0x0 0xff870000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdmmc0: mmc@ff880000 { + compatible = "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff880000 0x0 0x10000>; + interrupts = ; + max-frequency = <200000000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + resets = <&cru SRST_H_SDMMC0>; + reset-names = "reset"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + sdmmc1: mmc@ff890000 { + compatible = "rockchip,rk3562-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff890000 0x0 0x10000>; + interrupts = ; + max-frequency = <200000000>; + clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + resets = <&cru SRST_H_SDMMC1>; + reset-names = "reset"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + crypto: crypto@ff8a0000 { + compatible = "rockchip,crypto-v4"; + reg = <0x0 0xff8a0000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk ACLK_CRYPTO>, <&scmi_clk HCLK_CRYPTO>, + <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>, + <&scmi_clk PCLK_CRYPTO>; + clock-names = "aclk", "hclk", "sclk", "pka", "pclk"; + assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>; + assigned-clock-rates = <200000000>, <300000000>; + resets = <&cru SRST_CORE_CRYPTO>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@ff8e0000 { + compatible = "rockchip,rkrng"; + reg = <0x0 0xff8e0000 0x0 0x200>; + interrupts = ; + clocks = <&scmi_clk HCLK_RK_RNG_NS>; + clock-names = "hclk_trng"; + resets = <&cru SRST_H_RK_RNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + otp: otp@ff930000 { + compatible = "rockchip,rk3562-otp"; + reg = <0x0 0xff930000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, + <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>, + <&cru PCLK_OTPPHY>; + clock-names = "usr", "sbpi", "apb", "arb", "phy"; + resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>, + <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>, + <&cru SRST_P_OTPPHY>; + reset-names = "usr", "sbpi", "apb", "arb", "phy"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + mbist_vmin: mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <0 2>; + }; + log_mbist_vmin: log-mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <4 2>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@2a { + reg = <0x2a 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@2b { + reg = <0x2b 0x1>; + }; + tsadc_trim_base_frac: tsadc-trim-base-frac@2c { + reg = <0x2c 0x1>; + bits = <4 4>; + }; + tsadc_trim_base: tsadc-trim-base@2d { + reg = <0x2d 0x1>; + }; + cpu_opp_info: cpu-opp-info@2e { + reg = <0x2e 0x6>; + }; + gpu_opp_info: gpu-opp-info@34 { + reg = <0x34 0x6>; + }; + npu_opp_info: npu-opp-info@3a { + reg = <0x3a 0x6>; + }; + dmc_opp_info: dmc-opp-info@40 { + reg = <0x40 0x6>; + }; + cpu_pvtpll: cpu-pvtpll@46 { + reg = <0x46 0x2>; + }; + gpu_pvtpll: gpu-pvtpll@48 { + reg = <0x48 0x2>; + }; + npu_pvtpll: npu-pvtpll@4a { + reg = <0x4a 0x2>; + }; + }; + + dmac: dma-controller@ff990000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff990000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + rkdmac: dma-controller@ff9a0000 { + compatible = "rockchip,rk3562-dma", "rockchip,dma-v1"; + reg = <0x0 0xff9a0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_RKDMAC>; + clock-names = "aclk"; + #dma-cells = <1>; + dma-channels = <42>; + dma-requests = <42>; + rockchip,grf = <&peri_grf>; + }; + + hwlock: hwspinlock@ff9e0000 { + compatible = "rockchip,hwspinlock"; + reg = <0x0 0xff9e0000 0x0 0x100>; + #hwlock-cells = <1>; + status = "disabled"; + }; + + i2c1: i2c@ffa00000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa00000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@ffa10000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa10000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@ffa20000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa20000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@ffa30000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa30000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@ffa40000 { + compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xffa40000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rktimer: timer@ffa50000 { + compatible = "rockchip,rk3562-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xffa50000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@ffa60000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xffa60000 0x0 0x100>; + clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + tsadc: tsadc@ffa70000 { + compatible = "rockchip,rk3562-tsadc"; + reg = <0x0 0xffa70000 0x0 0x400>; + rockchip,grf = <&sys_grf>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; + assigned-clock-rates = <1200000>, <12000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>, <&tsadc_trim_base>, <&tsadc_trim_base_frac>; + nvmem-cell-names = "trim_l", "trim_h", "trim_base", "trim_base_frac"; + status = "disabled"; + }; + + gmac0: ethernet@ffa80000 { + compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xffa80000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&ioc_grf>; + clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>, + <&cru PCLK_GMAC>, <&cru ACLK_GMAC>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_A_GMAC>; + reset-names = "stmmaceth"; + rockchip,csu = <&csu CSU_GMAC_ACLK>, <&csu CSU_GMAC_PCLK>; + rockchip,csu-names = "aclk", "pclk"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + saradc1: saradc@ffaa0000 { + compatible = "rockchip,rk3562-saradc"; + reg = <0x0 0xffaa0000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC_VCCIO156>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + mailbox: mailbox@ffae0000 { + compatible = "rockchip,rk3562-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xffae0000 0x0 0x200>; + interrupts = ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + dsi: dsi@ffb10000 { + compatible = "rockchip,rk3562-mipi-dsi"; + reg = <0x0 0xffb10000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSITX>; + clock-names = "pclk"; + resets = <&cru SRST_P_DSITX>; + reset-names = "apb"; + phys = <&video_phy>; + phy-names = "dphy"; + rockchip,grf = <&sys_grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi>; + status = "disabled"; + }; + }; + }; + }; + + video_phy: phy@ffb20000 { + compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy", + "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; + reg = <0x0 0xffb20000 0x0 0x10000>, + <0x0 0xffb10000 0x0 0x10000>; + reg-names = "phy", "host"; + clocks = <&cru CLK_MIPIDSIPHY_REF>, + <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>; + clock-names = "ref", "pclk", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_DSIPHY>; + reset-names = "apb"; + #phy-cells = <0>; + status = "disabled"; + }; + + gmac1: ethernet@ffb30000 { + compatible = "rockchip,rk3562-gmac"; + reg = <0x0 0xffb30000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&ioc_grf>; + clocks = <&cru CLK_MAC100_50M_MATRIX>, <&cru CLK_MAC100_50M_MATRIX>, + <&cru PCLK_MAC100>, <&cru ACLK_MAC100>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac"; + resets = <&cru SRST_A_MAC100>; + reset-names = "stmmaceth"; + rockchip,csu = <&csu CSU_GMAC_ACLK>, <&csu CSU_GMAC_PCLK>; + rockchip,csu-names = "aclk", "pclk"; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3562-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff260000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff260000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff620000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff630000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffac0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffac0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffad0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffad0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3562"; + status = "disabled"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_DEEP1_MODE + | RKPM_SLP_PMIC_LP + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_OSC_DIS + | RKPM_SLP_32K_PVTM + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO0_WKUP_EN + ) + >; + }; +}; + +#include "rk3562-pinctrl.dtsi" diff --git a/rk3562/lga-rk3562.dts b/rk3562/lga-rk3562.dts new file mode 100755 index 0000000..4d83558 --- /dev/null +++ b/rk3562/lga-rk3562.dts @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +//#include "../rk3562-evb1-lp4x-v10.dtsi" +//#include "../rk3562-android.dtsi" +//#include "../rk3562-rk817.dtsi" +#include + +#include "rk3562-evb-rpdzkj-rk817-pwm.dtsi" +#include "../rk3562-linux.dtsi" + +/*** usb ***/ +#include "rp-usb-rk3562.dtsi" + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" + +/* camera */ +//#include "rp-mipi-camera0-rk3562.dtsi" +//#include "rp-mipi-camera1-rk3562.dtsi" +#include "rp-mipi-camera-3562-dual-gc8034-ov13855.dtsi" +/* ethernet */ +#include "rp-eth-gmac.dtsi" +#include "rp-eth-pcie2gmac-rk3562.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-vs2275s-rk3562.dtsi" + +/***************** SINGLE LCD ****************/ +#include "pro-rk3562-single-lcd-gpio.dtsi" // gpio config of lcd + +/* MIPI to HDMI */ +//#include "rp-lcd-mipi2hdmi-lt8912.dtsi" + +/* MIPI DSI */ +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-7-720-1280.dtsi" +#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-8-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-10-1200-1920.dtsi" + +/* LVDS DSI */ +//#include "rp-lcd-lvds-7-1024-600.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/{ + + model = "lga-rk3562"; + compatible = "rpdzkj,lga-rk3562-v10", "rockchip,rk3562"; + /* + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + temperature-device = "soc-thermal"; + temp-on = <60000>; + time = <10000>; + status = "okay"; + }; + */ + + vdd_3v3_5v_control: vdd-3v3-5v-control { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_5v_control"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; //In the uboot phase fixed.c resolves gpio + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_control>; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + // pinctrl-names = "default"; + // pinctrl-0 = <&vcc5v0_host_en>; + // pinctrl-1 = <&vcc5v0_otg_en>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + led { //system led + gpio_num = <&nca9555_gpio IO_00 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + vdd_4g { + gpio_num = <&nca9555_gpio IO_15 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_pwr { + gpio_num = <&nca9555_gpio IO_03 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { //usb hub + gpio_num = <&nca9555_gpio IO_02 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&nca9555_gpio IO_14 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //spk mute + gpio_num = <&nca9555_gpio IO_17 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + wifi_pwr { + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + +// WIFI,poweren_gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + // fan { //fan + // gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // }; + + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + nca9555_01 { + gpio_num = <&nca9555_gpio IO_01 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_15 { + gpio_num = <&nca9555_gpio IO_15 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_16 { + gpio_num = <&nca9555_gpio IO_16 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_17 { + gpio_num = <&nca9555_gpio IO_17 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555b_00 { + gpio_num = <&nca9555b_gpio IO_00 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_01 { + gpio_num = <&nca9555b_gpio IO_01 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_02 { + gpio_num = <&nca9555b_gpio IO_02 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_03 { + gpio_num = <&nca9555b_gpio IO_03 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_04 { + gpio_num = <&nca9555b_gpio IO_04 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_05 { + gpio_num = <&nca9555b_gpio IO_05 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_06 { + gpio_num = <&nca9555b_gpio IO_06 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_07 { + gpio_num = <&nca9555b_gpio IO_07 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_10 { + gpio_num = <&nca9555b_gpio IO_10 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_11 { + gpio_num = <&nca9555b_gpio IO_11 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_12 { + gpio_num = <&nca9555b_gpio IO_12 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_13 { + gpio_num = <&nca9555b_gpio IO_13 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_14 { + gpio_num = <&nca9555b_gpio IO_14 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_15 { + gpio_num = <&nca9555b_gpio IO_15 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_16 { + gpio_num = <&nca9555b_gpio IO_16 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + nca9555b_17 { + gpio_num = <&nca9555b_gpio IO_17 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + /** 24M osc clock to mcp2515 */ + osc_24m: osc24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; +}; + + +&i2c1 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; + + nca9555: mfd-gpio@20 { + compatible = "nca9555"; + reg = <0x20>; + status = "okay"; + + nca9555_gpio: gpio-normal@20 { + compatible = "nca9555-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + nca9555b: mfd-gpio@21 { + compatible = "nca9555"; + reg = <0x21>; + status = "okay"; + + nca9555b_gpio: gpio-normal@21 { + compatible = "nca9555-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + + + + +/*** RS232 ***/ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +/*** TTL ***/ +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +/* RS485 */ +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +//&rk_headset { +// status = "okay"; +// pinctrl-names = "default"; +// pinctrl-0 = <&hp_det>; +// headset_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +//}; + +//&spi0 { +// status = "okay"; +// +// spi_dev@0 { +// compatible = "rockchip,spidev"; +// reg = <0>; +// spi-max-frequency = <12000000>; +// spi-lsb-first; +// }; +//}; + +&spi0 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi0m0_csn0 &spi0m0_pins>; + + spi2can: mcp2515@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&osc_24m>; + interrupt-parent = <&gpio0>; + interrupts = ; + // vdd-supply = <®5v0>; + // xceiver-supply = <®5v0>; + gpio-controller; + spi-max-frequency = <10000000>; + }; +}; + + +/******** must be close,if not system no run ******/ +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +&rk817 { + battery { + compatible = "rk817,battery"; + status = "okay"; + ocv_table = <3300 3337 3374 3411 3447 3485 3524 + 3561 3598 3635 3672 3709 3746 3785 + 3822 3859 3896 3933 3970 4007 4050>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <3300>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; //test mode, 1 to force report 66% + + //rpdzkj add Mandatory configuration under the condition of no battery, the power connected to external DC is 0, and 50% is reported + dc_rpdzkj_psy = <1>; //强制é…置无电池情况下接外部DC电é‡ä¸º0上报50% 1:enable 0:not + + + }; + + charger { + compatible = "rk817,charger"; + status = "okay"; + min_input_voltage = <4500>; + max_input_current = <3000>;//1500 + max_chrg_current = <1000>;//2000 + max_chrg_voltage = <4350>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + // extcon = <&u2phy>; //otg charging + gate_function_disable = <1>; + + //power_dc2otg = <1>; + //dc_det_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; //å¯é…ç½®pins 读å–dc转3.3V以下电压åšdc充电检测脚 + //rpdzkj add Configure external DC to detect and report charging status + rpdzkj_dc_vbus = <1>; //é…置外部DCæ£€æµ‹ä¸ŠæŠ¥å……ç”µçŠ¶æ€ 1:enable 0:not + }; +}; + +&pinctrl { + power_control{ + vdd_control: vdd-control { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +// headphone { +// hp_det: hp-det { +// rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; +// }; +// }; +}; diff --git a/rk3562/pro-rk3562-single-lcd-gpio.dtsi b/rk3562/pro-rk3562-single-lcd-gpio.dtsi new file mode 100755 index 0000000..1682051 --- /dev/null +++ b/rk3562/pro-rk3562-single-lcd-gpio.dtsi @@ -0,0 +1,107 @@ + + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm3 { + status = "okay"; +}; + + +//MIPI DSI +&dsi_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight>; +}; + + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight>; +}; + +// POWER GPIO +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +// TP +&i2c2 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PC6 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk3562/pro-rk3562.dts b/rk3562/pro-rk3562.dts new file mode 100755 index 0000000..300a85e --- /dev/null +++ b/rk3562/pro-rk3562.dts @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +//#include "../rk3562-evb1-lp4x-v10.dtsi" +//#include "../rk3562-android.dtsi" +//#include "../rk3562-rk817.dtsi" +#include + +#include "rk3562-evb-rpdzkj-rk817-pwm.dtsi" +#include "../rk3562-linux.dtsi" + +/*** usb ***/ +#include "rp-usb-rk3562.dtsi" + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" + +/* camera */ +//#include "rp-mipi-camera0-rk3562.dtsi" +//#include "rp-mipi-camera1-rk3562.dtsi" +#include "rp-mipi-camera-3562-dual-gc8034-ov13855.dtsi" + +/* ethernet */ +#include "rp-eth-gmac.dtsi" +#include "rp-eth-pcie2gmac-rk3562.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-vs2275s-rk3562.dtsi" + +/***************** SINGLE LCD ****************/ +#include "pro-rk3562-single-lcd-gpio.dtsi" // gpio config of lcd + +/* MIPI to HDMI */ +//#include "rp-lcd-mipi2hdmi-lt8912.dtsi" + +/* MIPI DSI */ +//#include "rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi-7-720-1280.dtsi" +#include "rp-lcd-mipi-7-1024-600.dtsi" +//#include "rp-lcd-mipi-7-1200-1920.dtsi" +//#include "rp-lcd-mipi-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-8-1200-1920.dtsi" +//#include "rp-lcd-mipi-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi-10-1200-1920.dtsi" + +/* LVDS DSI */ +//#include "rp-lcd-lvds-7-1024-600.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/{ + + model = "pro-rk3562"; + compatible = "rpdzkj,pro-rk3562-v10", "rockchip,rk3562"; + /* + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + temperature-device = "soc-thermal"; + temp-on = <60000>; + time = <10000>; + status = "okay"; + }; + */ + + vdd_3v3_5v_control: vdd-3v3-5v-control { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_5v_control"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; //In the uboot phase fixed.c resolves gpio + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_control>; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + // pinctrl-names = "default"; + // pinctrl-0 = <&vcc5v0_host_en>; + // pinctrl-1 = <&vcc5v0_otg_en>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + led { //system led + gpio_num = <&nca9555_gpio IO_00 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + vdd_4g { + gpio_num = <&nca9555_gpio IO_01 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_pwr { + gpio_num = <&nca9555_gpio IO_03 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { //usb hub + gpio_num = <&nca9555_gpio IO_02 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&nca9555_gpio IO_14 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + wifi_pwr { + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + +// WIFI,poweren_gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + // fan { //fan + // gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // }; + + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + nca9555_15 { + gpio_num = <&nca9555_gpio IO_15 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_16 { + gpio_num = <&nca9555_gpio IO_16 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + nca9555_17 { + gpio_num = <&nca9555_gpio IO_17 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; + + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; +}; + + +&i2c1 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; + + nca9555: mfd-gpio@20 { + compatible = "nca9555"; + reg = <0x20>; + status = "okay"; + + nca9555_gpio: gpio-normal@20 { + compatible = "nca9555-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +/*** RS232 ***/ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +/*** TTL ***/ +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; +}; + +&spi0 { + status = "okay"; + + pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +/******** must be close,if not system no run ******/ +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +&rk817 { + battery { + compatible = "rk817,battery"; + status = "okay"; + ocv_table = <3300 3337 3374 3411 3447 3485 3524 + 3561 3598 3635 3672 3709 3746 3785 + 3822 3859 3896 3933 3970 4007 4050>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <3300>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; //test mode, 1 to force report 66% + + //rpdzkj add Mandatory configuration under the condition of no battery, the power connected to external DC is 0, and 50% is reported + dc_rpdzkj_psy = <1>; //强制é…置无电池情况下接外部DC电é‡ä¸º0上报50% 1:enable 0:not + + + }; + + charger { + compatible = "rk817,charger"; + status = "okay"; + min_input_voltage = <4500>; + max_input_current = <3000>;//1500 + max_chrg_current = <1000>;//2000 + max_chrg_voltage = <4350>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + // extcon = <&u2phy>; //otg charging + gate_function_disable = <1>; + + //power_dc2otg = <1>; + //dc_det_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; //å¯é…ç½®pins 读å–dc转3.3V以下电压åšdc充电检测脚 + //rpdzkj add Configure external DC to detect and report charging status + rpdzkj_dc_vbus = <1>; //é…置外部DCæ£€æµ‹ä¸ŠæŠ¥å……ç”µçŠ¶æ€ 1:enable 0:not + }; +}; + +&pinctrl { + power_control{ + vdd_control: vdd-control { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3562/rk3562-evb-rpdzkj-rk817-pwm.dtsi b/rk3562/rk3562-evb-rpdzkj-rk817-pwm.dtsi new file mode 100755 index 0000000..06d0d42 --- /dev/null +++ b/rk3562/rk3562-evb-rpdzkj-rk817-pwm.dtsi @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "dt-bindings/usb/pd.h" +#include "../rk3562.dtsi" + +/ { + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3250>; + rockchip,screen-on-voltage = <3300>; + status = "okay"; + }; + + rk817_sound: rk817-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + // hp-det-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&sai0>; + rockchip,codec = <&rk817_codec>; + // pinctrl-names = "default"; + // pinctrl-0 = <&hp_det>; + }; + rk_headset: rk-headset { + compatible = "rockchip_headset"; + }; + +// sdio_pwrseq: sdio-pwrseq { +// compatible = "mmc-pwrseq-simple"; +// clocks = <&rk817 1>; +// clock-names = "ext_clock"; +// pinctrl-names = "default"; +// pinctrl-0 = <&wifi_enable_h>; +// +// /* +// * On the module itself this is one of these (depending +// * on the actual card populated): +// * - SDIO_RESET_L_WL_REG_ON +// * - PDN (power down when low) +// */ +// post-power-on-delay-ms = <200>; +// reset-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_LOW>; +// }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + regulator-boot-on; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <0 0x0 + 3300000 0x1>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm7 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm6 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc_sys>; + status = "okay"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v_midu: vcc5v-midu { + compatible = "regulator-fixed"; + regulator-name = "vcc5v_midu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + /* + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + */ +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +//&bus_soc { +// rockchip,soc-bus-table = <0 0x00a000a8 0x7001>, +// <1 0x00a000a8 0x7c39>, +// <2 0x00a000a8 0x7c39>, +// <3 0x00a000a8 0x7c39>, +// <4 0x00a000a5 0xb007>, +// <5 0x00a000a8 0x7034>, +// <6 0x00a000a8 0x7034>, +// <7 0x00a000a8 0x7034>, +// <8 0x00a000a8 0x7001>; +//}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + dsi_panel: panel@0 { + status = "disabled"; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&dcdc_boost>; + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + /* + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3671 3686 3712 3738 3756 3773 + 3787 3802 3819 3840 3868 3916 3959 + 3998 4041 4087 4138 4191 4247 4313>; + design_capacity = <5780>; + design_qmax = <6358>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3400>; + zero_algorithm_vol = <3950>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4350>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&u2phy>; + gate_function_disable = <1>; + }; + */ + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&mclkout_sai0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_sai0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_mclk>; + hp-volume = <20>; + spk-volume = <55>; + status = "okay"; + }; + }; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pinctrl { + /* + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + */ + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + /* + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + */ +}; + +&pwm6 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga2_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + + +&sai0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0m0_lrck + &i2s0m0_sclk + &i2s0m0_sdi0 + &i2s0m0_sdo0>; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&saradc1 { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + supports-emmc; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; +/* +&sdmmc1 { + max-frequency = <200000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; +*/ +&tsadc { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3562/rp-adc-key.dtsi b/rk3562/rp-adc-key.dtsi new file mode 100755 index 0000000..e2acf1b --- /dev/null +++ b/rk3562/rp-adc-key.dtsi @@ -0,0 +1,34 @@ + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc0 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <414000>; + }; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <800000>; + }; + + back-key { + linux,code = ; + label = "back"; + press-threshold-microvolt = <1200000>; + }; + }; +}; diff --git a/rk3562/rp-audio-rk817.dtsi b/rk3562/rp-audio-rk817.dtsi new file mode 100755 index 0000000..d1ae86c --- /dev/null +++ b/rk3562/rp-audio-rk817.dtsi @@ -0,0 +1,43 @@ + +/ { + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + // hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; + // io-channels = <&saradc 1>; + // io-channel-names = "adc-detect"; + // keyup-threshold-microvolt = <1800000>; + // poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_2ch>; + rockchip,codec = <&rk817_codec>; + // pinctrl-names = "default"; + // pinctrl-0 = <&hp_det>; + // play-pause-key { + // label = "playpause"; + // linux,code = ; + // press-threshold-microvolt = <2000>; + // }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2s1_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk3562/rp-eth-gmac.dtsi b/rk3562/rp-eth-gmac.dtsi new file mode 100755 index 0000000..e32fb0a --- /dev/null +++ b/rk3562/rp-eth-gmac.dtsi @@ -0,0 +1,34 @@ +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 10000 100000>; + + tx_delay = <0x1c>; + /*rx_delay = <0x3f>;*/ + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_rgmii_clk + &rgmiim0_rgmii_bus + &rgmiim0_clk + ðm0_pins>; + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; diff --git a/rk3562/rp-eth-pcie2gmac-rk3562.dtsi b/rk3562/rp-eth-pcie2gmac-rk3562.dtsi new file mode 100755 index 0000000..fc684a5 --- /dev/null +++ b/rk3562/rp-eth-pcie2gmac-rk3562.dtsi @@ -0,0 +1,23 @@ +/{ + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + // gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&combphy_pu { + status = "okay"; +}; + +&pcie2x1 { + pinctrl-0 = <&pcie20m0_pins>; + reset-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; diff --git a/rk3562/rp-lcd-lvds-10-1280-800.dtsi b/rk3562/rp-lcd-lvds-10-1280-800.dtsi new file mode 100755 index 0000000..b7bebe7 --- /dev/null +++ b/rk3562/rp-lcd-lvds-10-1280-800.dtsi @@ -0,0 +1,187 @@ +#include +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <138>; + hfront-porch = <136>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +&video_phy { + status = "okay"; +}; + +&lvds_in_vp0 { + status = "okay"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp0_out_lvds>; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1280>; + gtp_resolution_y = <800>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + goodix,cfg-group2 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; + goodix,cfg-group3 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; +}; + diff --git a/rk3562/rp-lcd-lvds-7-1024-600.dtsi b/rk3562/rp-lcd-lvds-7-1024-600.dtsi new file mode 100755 index 0000000..ade6dbf --- /dev/null +++ b/rk3562/rp-lcd-lvds-7-1024-600.dtsi @@ -0,0 +1,172 @@ +#include +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&dsi { + status = "disabled"; +}; + +&dsi_in_vp0 { + status = "disabled"; +}; + +&video_phy { + status = "okay"; +}; + +&lvds_in_vp0 { + status = "okay"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp0_out_lvds>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 5A 00 04 58 02 05 3D 00 01 + 08 32 0F 5A 32 03 05 00 00 + 00 00 02 00 00 18 1A 1E 14 + 87 29 0A 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 + 2B FF 7F 19 46 32 3C 78 94 + D5 02 08 00 00 04 98 40 00 + 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 + 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 02 04 06 08 0A + 0C 0E 10 12 14 FF FF FF FF + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 1D 1E 1F 20 + 21 22 24 26 28 29 2A FF FF + FF FF FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6F 01 + ]; + }; + diff --git a/rk3562/rp-lcd-mipi-10-1200-1920.dtsi b/rk3562/rp-lcd-mipi-10-1200-1920.dtsi new file mode 100755 index 0000000..158d286 --- /dev/null +++ b/rk3562/rp-lcd-mipi-10-1200-1920.dtsi @@ -0,0 +1,182 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "270"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + // reset-delay-ms = <60>; + // init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + // unprepare-delay-ms = <60>; + // disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; +}; diff --git a/rk3562/rp-lcd-mipi-10-800-1280-v3.dtsi b/rk3562/rp-lcd-mipi-10-800-1280-v3.dtsi new file mode 100755 index 0000000..d59a7e4 --- /dev/null +++ b/rk3562/rp-lcd-mipi-10-800-1280-v3.dtsi @@ -0,0 +1,173 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "90"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; +}; diff --git a/rk3562/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi b/rk3562/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi new file mode 100755 index 0000000..ea6ae19 --- /dev/null +++ b/rk3562/rp-lcd-mipi-5-720-1280-v2-boxTP.dtsi @@ -0,0 +1,213 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "270"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; +// rockchip,lane-rate = <480>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + //MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <45>; + hfront-porch = <45>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 4D D0 02 00 05 05 35 00 01 08 32 + 08 5A 3C 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 29 0A 55 57 B5 + 06 00 00 00 41 22 10 00 01 00 0F + 00 2A 00 00 19 50 32 3C 78 94 D5 + 02 08 00 00 04 A2 40 00 8F 4A 00 + 80 55 00 73 61 00 67 70 00 67 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 + 06 08 0A 0F 10 12 FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF 8D 01 + ]; +}; diff --git a/rk3562/rp-lcd-mipi-5.5-720-1280-v2.dtsi b/rk3562/rp-lcd-mipi-5.5-720-1280-v2.dtsi new file mode 100755 index 0000000..2d2b9fa --- /dev/null +++ b/rk3562/rp-lcd-mipi-5.5-720-1280-v2.dtsi @@ -0,0 +1,162 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + 39 00 05 B8 26 22 20 03 + 39 00 04 BF 02 11 00 + 39 00 0B B3 0C 10 0A 50 03 FF 00 00 00 00 + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + 39 00 02 BC 46 + 39 00 02 CC 0B + 39 00 02 B4 80 + 39 00 04 B2 C8 12 30 + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 00 C0 10 + 39 00 0D C1 53 00 1E 1E 77 C1 FF FF AF AF 7F 7F + 39 00 03 B5 07 07 + 39 00 03 B6 70 70 + 39 00 07 C6 00 00 FF FF 01 FF + 39 00 40 E9 C2 10 05 04 FE 02 81 12 31 45 3F 83 12 91 3B 2A 08 05 00 00 00 00 08 05 00 00 00 00 FF 02 46 02 48 68 88 88 88 80 88 FF 13 57 13 58 78 88 88 88 81 88 00 00 00 00 00 12 B1 3B 00 00 00 00 00 + 39 00 3E EA 00 1A 00 00 00 00 00 00 00 00 00 00 FF 31 75 31 18 78 88 88 88 85 88 FF 20 64 20 08 68 88 88 88 84 88 20 10 00 00 54 00 00 00 00 00 00 00 C0 00 00 0C 00 00 00 00 30 02 A1 00 00 00 00 + 39 00 23 E0 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A + 05 ff 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <42>; + hfront-porch = <44>; + vback-porch = <10>; + vfront-porch = <14>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>1x { + status = "okay"; + compatible = "goodix,gt1x"; + reg = <0x5d>; + + /** + * goodix,rst-gpio = <>; + * goodix,irq-gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ +}; diff --git a/rk3562/rp-lcd-mipi-7-1024-600.dtsi b/rk3562/rp-lcd-mipi-7-1024-600.dtsi new file mode 100755 index 0000000..259e8ec --- /dev/null +++ b/rk3562/rp-lcd-mipi-7-1024-600.dtsi @@ -0,0 +1,196 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ //old touch + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + goodix,cfg-group5 = [ //new touch + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; +}; diff --git a/rk3562/rp-lcd-mipi-7-1200-1920.dtsi b/rk3562/rp-lcd-mipi-7-1200-1920.dtsi new file mode 100755 index 0000000..070cc4b --- /dev/null +++ b/rk3562/rp-lcd-mipi-7-1200-1920.dtsi @@ -0,0 +1,250 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <900>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 14 42 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 de 03 00 + 39 60 03 c9 02 23 + + 39 00 02 b0 00 + 39 00 06 14 08 b0 00 22 00 + 39 30 02 b4 0c + 39 40 03 b6 3a d3 + 39 50 02 51 e6 + 39 30 02 53 2c + + 05 78 01 29 + 05 78 01 11 + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 8c 83 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 c9 02 23 + 39 60 03 ca 01 23 + 39 10 03 cb 10 05 + 39 10 03 cc 05 10 + 39 10 03 d0 00 00 + + + 39 10 03 b6 03 00 + 39 10 03 de 03 00 + 39 10 03 d6 05 00 + 39 60 03 b7 4b 02 + + 05 00 01 2c + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1200>; + vactive = <1900>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + goodix,cfg-group0 = [ //sensor id 0 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + + + goodix,cfg-group2 = [ //sensor id 2 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + goodix,cfg-group5 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01 + ]; +}; diff --git a/rk3562/rp-lcd-mipi-7-720-1280.dtsi b/rk3562/rp-lcd-mipi-7-720-1280.dtsi new file mode 100755 index 0000000..cadeb1f --- /dev/null +++ b/rk3562/rp-lcd-mipi-7-720-1280.dtsi @@ -0,0 +1,430 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 75 03 + + 39 00 02 E0 01 + // 39 00 02 4A 30 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 0A 07 + 39 00 02 0C 74 + 39 00 02 17 00 + 39 00 02 18 D7 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B D7 + 39 00 02 1C 01 + 39 00 02 1F 74 + 39 00 02 20 19 + 39 00 02 21 19 + 39 00 02 22 0E + 39 00 02 27 43 + + 39 00 02 37 09 + 39 00 02 38 04 + 39 00 02 39 08 + 39 00 02 3A 18 + 39 00 02 3B 18 + 39 00 02 3C 72 + 39 00 02 3E FF + 39 00 02 3E FF + 39 00 02 3F FF + 39 00 02 40 04 + 39 00 02 41 A0 + 39 00 02 43 08 + 39 00 02 44 07 + 39 00 02 45 30 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 65 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 0F + + 39 00 02 5D 7C + 39 00 02 5E 5F + 39 00 02 5F 4D + 39 00 02 60 3F + 39 00 02 61 39 + 39 00 02 62 29 + 39 00 02 63 2B + 39 00 02 64 12 + 39 00 02 65 28 + 39 00 02 66 24 + 39 00 02 67 22 + 39 00 02 68 3E + 39 00 02 69 2C + 39 00 02 6A 33 + 39 00 02 6B 26 + 39 00 02 6C 23 + 39 00 02 6D 18 + 39 00 02 6E 09 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 5F + 39 00 02 72 4D + 39 00 02 73 3F + 39 00 02 74 39 + 39 00 02 75 29 + 39 00 02 76 2B + 39 00 02 77 12 + 39 00 02 78 28 + 39 00 02 79 24 + 39 00 02 7A 22 + 39 00 02 7B 3E + 39 00 02 7C 2C + 39 00 02 7D 33 + 39 00 02 7E 26 + 39 00 02 7F 23 + 39 00 02 80 18 + 39 00 02 81 09 + 39 00 02 82 00 + + 39 00 02 E0 02 + 39 00 02 00 37 + 39 00 02 01 17 + 39 00 02 02 0A + 39 00 02 03 06 + 39 00 02 04 08 + 39 00 02 05 04 + 39 00 02 06 00 + 39 00 02 07 1F + 39 00 02 08 1F + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 1F + 39 00 02 10 3F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1E + 39 00 02 14 10 + 39 00 02 15 1F + + 39 00 02 16 37 + 39 00 02 17 17 + 39 00 02 18 0B + 39 00 02 19 07 + 39 00 02 1A 09 + 39 00 02 1B 05 + 39 00 02 1C 01 + 39 00 02 1D 1F + 39 00 02 1E 1F + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 1F + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1E + 39 00 02 2A 11 + 39 00 02 2B 1F + 39 00 02 2C 37 + 39 00 02 2D 17 + 39 00 02 2E 05 + 39 00 02 2F 09 + 39 00 02 30 07 + 39 00 02 31 0B + 39 00 02 32 11 + 39 00 02 33 1F + 39 00 02 34 1F + 39 00 02 35 1F + 39 00 02 36 1F + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 3F + 39 00 02 3D 1F + 39 00 02 3E 1E + 39 00 02 3F 1F + 39 00 02 40 01 + + 39 00 02 41 1F + 39 00 02 42 38 + 39 00 02 43 18 + 39 00 02 44 04 + 39 00 02 45 08 + 39 00 02 46 06 + 39 00 02 47 0A + 39 00 02 48 10 + 39 00 02 49 1F + 39 00 02 4A 1F + 39 00 02 4B 1F + 39 00 02 4C 1F + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1E + 39 00 02 55 1F + 39 00 02 56 00 + 39 00 02 57 1F + 39 00 02 58 10 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 10 + 39 00 02 5C 01 + 39 00 02 5D 50 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 30 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 06 + 39 00 02 64 6A + 39 00 02 65 55 + 39 00 02 66 08 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 08 + 39 00 02 6A 6E + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 80 + 39 00 02 76 00 + 39 00 02 77 0D + 39 00 02 78 18 + 39 00 02 79 00 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 04 + 39 00 02 04 01 + 39 00 02 0E 38 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E6 02 + // 39 00 02 36 00 + 39 C8 02 11 00 + 39 C8 02 29 00 + + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <65000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <34>; + hfront-porch = <34>; + vback-porch = <6>; + vfront-porch = <20>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 57 58 02 00 04 05 35 00 01 08 32 0F + 5A 32 03 05 00 00 00 00 02 00 00 18 + 1A 1E 14 8A 2A 0C 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 2B FF 7F + 19 46 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 40 30 FF + FF 27 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 24 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0F 10 12 13 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 81 01 + ]; + goodix,cfg-group2 = [ + 5A 58 02 00 04 05 35 00 01 08 + 32 0F 5A 32 03 05 00 00 00 00 + 02 00 00 18 1A 1E 14 8A 2A 0C + 55 57 B5 06 00 00 00 20 33 1C + 14 01 00 0F 00 2B FF 7F 19 46 + 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 + 61 00 6F 70 00 6F 00 00 00 00 + F0 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 08 0A 0F 10 + 12 13 24 22 21 20 1F 1E 1D 1C + 18 16 FF FF FF FF FF FF 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 5E 01 + ]; +}; diff --git a/rk3562/rp-lcd-mipi-8-1200-1920.dtsi b/rk3562/rp-lcd-mipi-8-1200-1920.dtsi new file mode 100755 index 0000000..dbc9e7b --- /dev/null +++ b/rk3562/rp-lcd-mipi-8-1200-1920.dtsi @@ -0,0 +1,193 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "90"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "320"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <940>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 5E B0 04 80 07 05 05 00 01 0F 28 05 + 50 32 03 05 00 00 00 00 00 00 00 00 + 00 00 00 8C 2C 0E 52 54 31 0D 00 00 + 01 80 04 1C 00 00 00 00 00 03 64 32 + 00 00 00 52 66 94 C5 02 07 00 00 04 + 83 53 00 82 57 00 80 5B 00 7F 5F 00 + 7E 63 00 7E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 08 0A 0C 0F 10 12 13 14 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 22 01 + ]; + + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + + ]; +}; diff --git a/rk3562/rp-lcd-mipi-8-800-1280-v3.dtsi b/rk3562/rp-lcd-mipi-8-800-1280-v3.dtsi new file mode 100755 index 0000000..2cf8d86 --- /dev/null +++ b/rk3562/rp-lcd-mipi-8-800-1280-v3.dtsi @@ -0,0 +1,418 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "90"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + rockchip,lane-rate = <480>; + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + + 39 00 04 FF 98 81 03 + + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 57 //54 + 39 00 02 04 D3 //D4 + 39 00 02 05 00 + 39 00 02 06 11 + 39 00 02 07 08 //09 + 39 00 02 08 00 + 39 00 02 09 00 + 39 00 02 0a 3F //00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F //00 + 39 00 02 10 3F //00 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 78 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 //GCH/L + 39 00 02 44 00 + + + 39 00 02 50 00 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + 39 00 02 5e 00 + 39 00 02 5f 0D //FW_CGOUT_L[1] + 39 00 02 60 0D //FW_CGOUT_L[2] + 39 00 02 61 0C //FW_CGOUT_L[3] + 39 00 02 62 0C //FW_CGOUT_L[4] + 39 00 02 63 0F //FW_CGOUT_L[5] + 39 00 02 64 0F //FW_CGOUT_L[6] + 39 00 02 65 0E //FW_CGOUT_L[7] + 39 00 02 66 0E //FW_CGOUT_L[8] + 39 00 02 67 08 //FW_CGOUT_L[9] + 39 00 02 68 02 //FW_CGOUT_L[10] + 39 00 02 69 02 //FW_CGOUT_L[11] + 39 00 02 6a 02 //FW_CGOUT_L[12] + 39 00 02 6b 02 //FW_CGOUT_L[13] + 39 00 02 6c 02 //FW_CGOUT_L[14] + 39 00 02 6d 02 //FW_CGOUT_L[15] + 39 00 02 6e 02 //FW_CGOUT_L[16] + 39 00 02 6f 02 //FW_CGOUT_L[17] + 39 00 02 70 14 //FW_CGOUT_L[18] + 39 00 02 71 15 //FW_CGOUT_L[19] + 39 00 02 72 06 //FW_CGOUT_L[20] + 39 00 02 73 02 //FW_CGOUT_L[21] + 39 00 02 74 02 //FW_CGOUT_L[22] + + 39 00 02 75 0D //BW_CGOUT_L[1] + 39 00 02 76 0D //BW_CGOUT_L[2] + 39 00 02 77 0C //BW_CGOUT_L[3] + 39 00 02 78 0C //BW_CGOUT_L[4] + 39 00 02 79 0F //BW_CGOUT_L[5] + 39 00 02 7a 0F //BW_CGOUT_L[6] + 39 00 02 7b 0E //BW_CGOUT_L[7] + 39 00 02 7c 0E //BW_CGOUT_L[8] + 39 00 02 7d 08 //BW_CGOUT_L[9] + 39 00 02 7e 02 //BW_CGOUT_L[10] + 39 00 02 7f 02 //BW_CGOUT_L[11] + 39 00 02 80 02 //BW_CGOUT_L[12] + 39 00 02 81 02 //BW_CGOUT_L[13] + 39 00 02 82 02 //BW_CGOUT_L[14] + 39 00 02 83 02 //BW_CGOUT_L[15] + 39 00 02 84 02 //BW_CGOUT_L[16] + 39 00 02 85 02 //BW_CGOUT_L[17] + 39 00 02 86 14 //BW_CGOUT_L[18] + 39 00 02 87 15 //BW_CGOUT_L[19] + 39 00 02 88 06 //BW_CGOUT_L[20] + 39 00 02 89 02 //BW_CGOUT_L[21] + 39 00 02 8A 02 //BW_CGOUT_L[22] + + + + 39 00 04 FF 98 81 04 + + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 87 + 39 00 02 55 84 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 10 + 39 00 02 62 00 + + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 1F + 39 00 02 A3 12 + 39 00 02 A4 16 + 39 00 02 A5 29 + 39 00 02 A6 1E + 39 00 02 A7 1F + 39 00 02 A8 7E + 39 00 02 A9 1B + 39 00 02 AA 28 + 39 00 02 AB 6D + 39 00 02 AC 19 + 39 00 02 AD 18 + 39 00 02 AE 4C + 39 00 02 AF 1E + 39 00 02 B0 23 + 39 00 02 B1 52 + 39 00 02 B2 6D + 39 00 02 B3 3F + + 39 00 02 C0 00 + 39 00 02 C1 12 + 39 00 02 C2 20 + 39 00 02 C3 10 + 39 00 02 C4 13 + 39 00 02 C5 27 + 39 00 02 C6 1B + 39 00 02 C7 1D + 39 00 02 C8 75 + 39 00 02 C9 1F + 39 00 02 CA 28 + 39 00 02 CB 68 + 39 00 02 CC 1A + 39 00 02 CD 18 + 39 00 02 CE 4D + 39 00 02 CF 25 + 39 00 02 D0 2E + 39 00 02 D1 53 + 39 00 02 D2 60 + 39 00 02 D3 3F + + 39 00 04 FF 98 81 00 + 39 00 02 35 00 + 05 80 01 11 + 05 20 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <70>; + hfront-porch = <70>; + vback-porch = <22>; + vfront-porch = <16>; + hsync-len = <20>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + /** jc */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01 + ]; + +}; diff --git a/rk3562/rp-lcd-mipi2hdmi-lt8912.dtsi b/rk3562/rp-lcd-mipi2hdmi-lt8912.dtsi new file mode 100755 index 0000000..9c781b9 --- /dev/null +++ b/rk3562/rp-lcd-mipi2hdmi-lt8912.dtsi @@ -0,0 +1,158 @@ +#define RP_SINGLE_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi { + status = "okay"; + //rockchip,lane-rate = <480>; + + dsi_panel: panel@0 { + status = "okay"; + compatible = "aoly,sl008pa21y1285-b00","simple-panel-dsi"; + reg = <0>; + + init-delay-ms = <120>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; +// dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | +// MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + +// dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | +// MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HBP | MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET)>; + + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi_timing0>; + dsi_timing0: timing0 { + clock-frequency = <148500000>;//140000000 + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>;//60 + hfront-porch = <88>; + vback-porch = <36>;//23 + vfront-porch = <4>;//12 + hsync-len = <44>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi_in_vp0 { + status = "okay"; +}; + +&video_phy { + status = "okay"; +}; + +&route_dsi { + status = "okay"; + connect = <&vp0_out_dsi>; +}; + + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + + /delete-node/ gt1x@14; + lt89121: lt89121@48 { + status = "okay"; + compatible = "lt8912_i2c"; + reg = <0x48>; + // reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + }; + + +}; + + diff --git a/rk3562/rp-lcd-rgb-7-1024-600.dtsi b/rk3562/rp-lcd-rgb-7-1024-600.dtsi new file mode 100755 index 0000000..244f79c --- /dev/null +++ b/rk3562/rp-lcd-rgb-7-1024-600.dtsi @@ -0,0 +1,306 @@ + +/{ + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <200>; + }; + + + + panel { + status = "okay"; + compatible = "simple-panel"; + backlight = <&backlight>; + + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + //bus-format = ; + bus-format = ; + + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + power-supply = <&vcc18_lcd_n>; + //enable-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <51200000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <12>; + vfront-porch = <23>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_rgb: endpoint { + remote-endpoint = <&rgb_out_panel>; + }; + }; + }; + }; +}; + +&pwm0 { + status = "okay"; +}; + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "RGB"; + extend_device = "HDMI-A"; + extend_rotate = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; +}; + + +&display_subsystem { + status = "okay"; +}; + +&rgb { + status = "okay"; + phys = <&video_phy>; + phy-names = "phy"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&lcdc_m0_rgb_pins>; + pinctrl-1 = <&lcdc_m0_sleep_pins>; + + + + +}; + + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_panel: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vopb { + status = "okay"; + + +}; + +&video_phy { + status = "okay"; +}; + +&route_rgb { + connect = <&vopb_out_rgb>; + status = "okay"; +}; + +&dsi_in_vopb { + status = "disabled"; +}; + +&route_dsi { + status = "disabled"; +}; + +// TP +//&i2c1 { +// status = "okay"; +// clock-frequency = <200000>; +// +// gt9xx: goodix_ts@5d { +// /***** tp pin ******/ +// pinctrl-names = "default"; +// pinctrl-0 = <&goodix_irq>; +// goodix_rst_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; +// goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; +// +// status = "okay"; +// compatible = "goodix,gt9xx"; +// reg = <0x5d>; +// gtp_resolution_x = <1024>; +// gtp_resolution_y = <600>; +// gtp_int_tarigger = <1>; +// gtp_change_x2y = <0>; +// gtp_overturn_x = <0>; +// gtp_overturn_y = <0>; +// gtp_send_cfg = <1>; +// gtp_touch_wakeup = <1>; +// +// /** +// * goodix_rst_gpio = <>; +// * goodix_irq_gpio = <>; +// * +// * touch panel interrupt and reset pin +// * please refer to ***-lcd-gpio.dtsi +// * that included in main dts. +// */ +// +// goodix,cfg-group0 = [ +// 46 00 04 58 02 0A 3D 00 01 08 +// 28 05 50 32 03 05 00 00 00 00 +// 00 00 00 18 1A 1E 14 8D 2D 88 +// 17 15 31 0D 00 00 01 9B 03 1D +// 00 00 00 00 00 00 00 00 00 00 +// 00 1E 5A 94 C5 02 08 00 00 00 +// 61 21 00 57 29 00 4E 34 00 48 +// 41 00 43 51 00 43 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 01 04 05 06 07 08 09 +// 0C 0D 0E 0F 10 11 14 15 FF FF +// FF FF 00 00 00 00 00 00 00 00 +// 00 00 00 02 04 06 07 08 0A 0C +// 0F 10 11 12 13 19 1B 1C 1E 1F +// 20 21 22 23 24 25 26 27 FF FF +// FF FF FF FF 00 00 00 00 00 00 +// 00 00 00 00 FD 01 +// ]; +// +// +// goodix,cfg-group1 = [ +// 46 00 04 58 02 0A 3D 00 01 08 +// 28 05 50 32 03 05 00 00 00 00 +// 00 00 00 18 1A 1E 14 8D 2D 88 +// 17 15 31 0D 00 00 01 9B 03 1D +// 00 00 00 00 00 00 00 00 00 00 +// 00 1E 5A 94 C5 02 08 00 00 00 +// 61 21 00 57 29 00 4E 34 00 48 +// 41 00 43 51 00 43 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 01 04 05 06 07 08 09 +// 0C 0D 0E 0F 10 11 14 15 FF FF +// FF FF 00 00 00 00 00 00 00 00 +// 00 00 00 02 04 06 07 08 0A 0C +// 0F 10 11 12 13 19 1B 1C 1E 1F +// 20 21 22 23 24 25 26 27 FF FF +// FF FF FF FF 00 00 00 00 00 00 +// 00 00 00 00 FD 01 +// ]; +// +// goodix,cfg-group3 = [ +// 46 00 04 58 02 0A 3D 00 01 08 +// 28 05 50 32 03 05 00 00 00 00 +// 00 00 00 18 1A 1E 14 8D 2D 88 +// 17 15 31 0D 00 00 01 9B 03 1D +// 00 00 00 00 00 00 00 00 00 00 +// 00 1E 5A 94 C5 02 08 00 00 00 +// 61 21 00 57 29 00 4E 34 00 48 +// 41 00 43 51 00 43 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 00 00 00 00 00 00 00 +// 00 00 00 01 04 05 06 07 08 09 +// 0C 0D 0E 0F 10 11 14 15 FF FF +// FF FF 00 00 00 00 00 00 00 00 +// 00 00 00 02 04 06 07 08 0A 0C +// 0F 10 11 12 13 19 1B 1C 1E 1F +// 20 21 22 23 24 25 26 27 FF FF +// FF FF FF FF 00 00 00 00 00 00 +// 00 00 00 00 FD 01 +// ]; +// }; +//}; +// +// +//&pinctrl { +// goodix { +// goodix_irq: goodix-irq { +// rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; +// }; +// }; +//}; + diff --git a/rk3562/rp-mipi-camera-3562-dual-gc8034-ov13855.dtsi b/rk3562/rp-mipi-camera-3562-dual-gc8034-ov13855.dtsi new file mode 100644 index 0000000..86ad193 --- /dev/null +++ b/rk3562/rp-mipi-camera-3562-dual-gc8034-ov13855.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/// { +// vcc_mipicsi0: vcc-mipicsi0-regulator { +// compatible = "regulator-fixed"; +// gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; +// pinctrl-names = "default"; +// pinctrl-0 = <&mipicsi0_pwr>; +// regulator-name = "vcc_mipicsi0"; +// enable-active-high; +// regulator-always-on; +// regulator-boot-on; +// }; +// +// vcc_mipicsi1: vcc-mipicsi1-regulator { +// compatible = "regulator-fixed"; +// gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; +// pinctrl-names = "default"; +// pinctrl-0 = <&mipicsi1_pwr>; +// regulator-name = "vcc_mipicsi1"; +// enable-active-high; +// regulator-always-on; +// regulator-boot-on; +// }; +//}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov13855_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ov13855_1: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + + + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + +// dw9763_0: dw9763_0@c { +// compatible = "dongwoon,dw9763"; +// status = "okay"; +// reg = <0x0c>; +// rockchip,vcm-max-current = <120>; +// rockchip,vcm-start-current = <20>; +// rockchip,vcm-rated-current = <90>; +// rockchip,vcm-step-mode = <3>; +// rockchip,vcm-t-src = <0x20>; +// rockchip,vcm-t-div = <1>; +// rockchip,camera-module-index = <0>; +// rockchip,camera-module-facing = "back"; +// }; + + vm149c_0: vm149c_0@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <20>; // 马达的å¯åŠ¨ç”µæµ + rockchip,vcm-rated-current = <100>; // 马达的é¢å®šç”µæµ + rockchip,vcm-step-mode = <13>; // 马达驱动 ic 的电æµè¾“å‡ºæ¨¡å¼ + rockchip,camera-module-index = <0>; // æ¨¡ç»„ç¼–å· + rockchip,camera-module-facing = "back"; // 模组æœå‘，有"back"å’Œ"front" +}; + + + ov13855_0: ov13855_0@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; +// lens-focus = <&dw9763_0>; + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipi_in_ov13855_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_LOW>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_LOW>; + // dvdd-supply = <&vcc_mipicsi0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&vm149c_0>; + // lens-focus = <&dw9714>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_gc8034_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + vm149c_1: vm149c_1@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <20>; // 马达的å¯åŠ¨ç”µæµ + rockchip,vcm-rated-current = <100>; // 马达的é¢å®šç”µæµ + rockchip,vcm-step-mode = <13>; // 马达驱动 ic 的电æµè¾“å‡ºæ¨¡å¼ + rockchip,camera-module-index = <1>; // æ¨¡ç»„ç¼–å· + rockchip,camera-module-facing = "front"; // 模组æœå‘，有"back"å’Œ"front" +}; + +// dw9763_1: dw9763_1@c { +// compatible = "dongwoon,dw9763"; +// status = "okay"; +// reg = <0x0c>; +// rockchip,vcm-max-current = <120>; +// rockchip,vcm-start-current = <20>; +// rockchip,vcm-rated-current = <90>; +// rockchip,vcm-step-mode = <3>; +// rockchip,vcm-t-src = <0x20>; +// rockchip,vcm-t-div = <1>; +// rockchip,camera-module-index = <1>; +// rockchip,camera-module-facing = "front"; +// }; + + + ov13855_1: ov13855_1@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + //lens-focus = <&dw9763_1>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_ov13855_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_LOW>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_LOW>; +// dvdd-supply = <&vcc_mipicsi1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + lens-focus = <&vm149c_1>; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_gc8034_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp_vir1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + +//&pinctrl { +// cam { +// mipicsi0_pwr: mipicsi0-pwr { +// rockchip,pins = +// /* camera power en */ +// <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; +// }; +// mipicsi1_pwr: mipicsi1-pwr { +// rockchip,pins = +// /* camera1 power en */ +// <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; +// }; +// }; +//}; +// diff --git a/rk3562/rp-mipi-camera0-gc2093-imx334-imx415-rk3562.dtsi b/rk3562/rp-mipi-camera0-gc2093-imx334-imx415-rk3562.dtsi new file mode 100755 index 0000000..f19e8e7 --- /dev/null +++ b/rk3562/rp-mipi-camera0-gc2093-imx334-imx415-rk3562.dtsi @@ -0,0 +1,215 @@ + +/ { + + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc1v8_dvp>; + }; +}; + +&i2c4 { + status = "okay"; + gc2093_0: gc2093_0@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A1"; + port { + ucam_0_out0: endpoint { + remote-endpoint = <&mipi_in_0_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx334_0: imx334_0@1a { + compatible = "sony,imx334"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + // conflict with csi-ctl-gpios// + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1522-FG3"; + rockchip,camera-module-lens-name = "CS-P1150-IRC-8M-FAU"; + + port { + ucam_0_out1: endpoint { + remote-endpoint = <&mipi_in_0_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + imx415_0: imx415_0@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_0_out2: endpoint { + remote-endpoint = <&mipi_in_0_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_0_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ucam_0_out0>; + data-lanes = <1 2>; + }; + + mipi_in_0_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_0_out1>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_0_ucam2: endpoint@2 { + reg = <2>; + remote-endpoint = <&ucam_0_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + diff --git a/rk3562/rp-mipi-camera0-rk3562.dtsi b/rk3562/rp-mipi-camera0-rk3562.dtsi new file mode 100755 index 0000000..16c8912 --- /dev/null +++ b/rk3562/rp-mipi-camera0-rk3562.dtsi @@ -0,0 +1,200 @@ + +/ { + + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc1v8_dvp>; + }; +}; + +&i2c4 { + status = "okay"; + + dw9763_0: dw9763_0@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_0: ov13855_0@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_0>; + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipi_in_ov13855_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + gc8034_0: gc8034_0@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&camm0_clk0_out>; + pwdn-gpios = <&nca9555_gpio IO_05 GPIO_ACTIVE_LOW>; + reset-gpios = <&nca9555_gpio IO_04 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_gc8034_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_gc8034_0: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ov13855_0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + diff --git a/rk3562/rp-mipi-camera1-gc2093-imx334-imx415-rk3562.dtsi b/rk3562/rp-mipi-camera1-gc2093-imx334-imx415-rk3562.dtsi new file mode 100755 index 0000000..2cd6683 --- /dev/null +++ b/rk3562/rp-mipi-camera1-gc2093-imx334-imx415-rk3562.dtsi @@ -0,0 +1,200 @@ +&i2c5 { + status = "okay"; + gc2093_2: gc2093_2@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A1"; + port { + ucam_2_out0: endpoint { + remote-endpoint = <&mipi_in_2_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx334_1: imx334_1@1a { + compatible = "sony,imx334"; + status = "0kay"; + reg = <0x1a>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + // conflict with csi-ctl-gpios// + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1522-FG3"; + rockchip,camera-module-lens-name = "CS-P1150-IRC-8M-FAU"; + + port { + ucam_1_out1: endpoint { + remote-endpoint = <&mipi_in_1_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + imx415_1: imx415_1@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_1_out2: endpoint { + remote-endpoint = <&mipi_in_1_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_2_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ucam_2_out0>; + data-lanes = <1 2>; + }; + + mipi_in_1_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_1_out1>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_1_ucam2: endpoint@2 { + reg = <2>; + remote-endpoint = <&ucam_1_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/rk3562/rp-mipi-camera1-rk3562.dtsi b/rk3562/rp-mipi-camera1-rk3562.dtsi new file mode 100755 index 0000000..ff7fe8d --- /dev/null +++ b/rk3562/rp-mipi-camera1-rk3562.dtsi @@ -0,0 +1,186 @@ +&i2c5 { + status = "okay"; + + dw9763_1: dw9763_1@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_1: ov13855_1@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_HIGH>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "KYT-10203-v1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_1>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_ov13855_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM2_OUT2IO>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clk2_out>; + pwdn-gpios = <&nca9555_gpio IO_11 GPIO_ACTIVE_LOW>; + reset-gpios = <&nca9555_gpio IO_10 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_gc8034_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_gc8034_1: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ov13855_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2 3 4>; + }; + + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp_vir2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/rk3562/rp-usb-rk3562.dtsi b/rk3562/rp-usb-rk3562.dtsi new file mode 100755 index 0000000..490f364 --- /dev/null +++ b/rk3562/rp-usb-rk3562.dtsi @@ -0,0 +1,32 @@ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_otg { + status = "okay"; + vbus-supply = <&otg_switch>; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; diff --git a/rk3562/rp-wifi-bt-vs2275s-rk3562.dtsi b/rk3562/rp-wifi-bt-vs2275s-rk3562.dtsi new file mode 100755 index 0000000..abc76b3 --- /dev/null +++ b/rk3562/rp-wifi-bt-vs2275s-rk3562.dtsi @@ -0,0 +1,124 @@ + +/{ + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <100>; + reset-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&sys_grf>; + wifi_chip_type = "ap6275s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +// WIFI,poweren_gpio = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + supports-sdio; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +// post_power_on_delay_ms = <100>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&sai2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_lrck + &i2s2m0_sclk + &i2s2m0_sdi + &i2s2m0_sdo>; +}; + +&pinctrl { + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_gpio: bt-gpio { + rockchip,pins = + <2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + uart1_gpios: uart1-gpios { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3562j-core-ddr4-v10.dts b/rk3562j-core-ddr4-v10.dts new file mode 100644 index 0000000..bdd68af --- /dev/null +++ b/rk3562j-core-ddr4-v10.dts @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3562j-electric.dtsi" + +/ { + model = "Rockchip RK3562J CORE DDR4 V10 Board"; + compatible = "rockchip,rk3562j-core-ddr4-v10", "rockchip,rk3562"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <0>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&expander0 11 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy_pu { + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac0 { + phy-mode = "rmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim0_miim + &rgmiim0_tx_bus2 + &rgmiim0_rx_bus2 + &rgmiim0_clk>; + + phy-handle = <&rmii_phy>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + expander0: pca953x@26 { + vcc-supply = <&vcc_3v3>; + compatible = "nxp,pca9555"; + reg = <0x26>; + gpio-controller; + #gpio-cells = <2>; + status = "okay"; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_cpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_buck4: DCDC_REG4 { + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_buck4"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo3: LDO_REG3 { + regulator-name = "vcc_ldo3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo5: LDO_REG5 { + regulator-name = "vcc_ldo5"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo6: LDO_REG6 { + regulator-name = "vcc_ldo6"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo7: LDO_REG7 { + regulator-name = "vcc_ldo7"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo8: LDO_REG8 { + regulator-name = "vcc_ldo8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ldo9: LDO_REG9 { + regulator-name = "vcc_ldo9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_sys"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_sw1: SWITCH_REG1 { + regulator-name = "vcc_sw1"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1m0_xfer>; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m0_xfer>; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m1_xfer>; +}; + +&mdio0 { + rmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clocks = <&cru CLK_GMAC_ETH_OUT2IO>; + assigned-clock-rates = <25000000>; + }; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3m0_pins>; +}; + +&pwm4 { + status = "okay"; + pinctrl-0 = <&pwm4m0_pins>; +}; + +&pwm7 { + status = "okay"; + pinctrl-0 = <&pwm7m0_pins>; +}; + +&pwm8 { + status = "okay"; + pinctrl-0 = <&pwm8m0_pins>; +}; + +&pwm9 { + status = "okay"; + pinctrl-0 = <&pwm9m0_pins>; +}; + +&rng { + status = "okay"; +}; + +&saradc0 { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + status = "okay"; +}; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1m1_csn0 &spi1m1_pins>; +}; + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi2m1_csn0 &spi2m1_pins>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy { + status = "okay"; +}; + +&u2phy_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn &uart2m1_rtsn>; +}; + +&uart4 { + status = "okay"; + pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; +}; + +&uart5 { + status = "okay"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-0 = <&uart9m1_xfer>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; + dr_mode = "otg"; + extcon = <&u2phy>; + maximum-speed = "high-speed"; + phys = <&u2phy_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; diff --git a/rk3562j-electric.dtsi b/rk3562j-electric.dtsi new file mode 100644 index 0000000..1f36d72 --- /dev/null +++ b/rk3562j-electric.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3562j.dtsi" + +&cpu0_opp_table { + /* + * Max CPU frequency is 1.8GHz for the overdrive mode, + * but it will reduce chip lifetime. + */ + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; diff --git a/rk3562j.dtsi b/rk3562j.dtsi new file mode 100644 index 0000000..b2ec94f --- /dev/null +++ b/rk3562j.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include "rk3562.dtsi" + +/ { + can0: can@ff600000 { + compatible = "rockchip,rk3562-can"; + reg = <0x0 0xff600000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; + reset-names = "can", "can-apb"; + status = "disabled"; + }; + + can1: can@ff610000 { + compatible = "rockchip,rk3562-can"; + reg = <0x0 0xff610000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; + reset-names = "can", "can-apb"; + status = "disabled"; + }; +}; + +&cpu0_opp_table { + /delete-node/ mbist-vmin; + /* + * Max CPU frequency is 1.8GHz for the overdrive mode, + * but it will reduce chip lifetime. + */ + /delete-node/ opp-1416000000; + /delete-node/ opp-1608000000; + /delete-node/ opp-1800000000; + /delete-node/ opp-2016000000; + opp-408000000 { + opp-microvolt = <850000 850000 1150000>; + }; + opp-600000000 { + opp-microvolt = <850000 850000 1150000>; + }; + opp-816000000 { + opp-microvolt = <850000 850000 1150000>; + }; + opp-1008000000 { + opp-microvolt = <850000 850000 1150000>; + }; + opp-1200000000 { + opp-microvolt-L4 = <850000 850000 1150000>; + }; +}; + +&gpu_opp_table { + /delete-node/ mbist-vmin; + /* + * Max GPU frequency is 900MHz for the overdrive mode, + * but it will reduce chip lifetime. + */ + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + opp-300000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-400000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-500000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-600000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-700000000 { + opp-microvolt-L3 = <850000 850000 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + }; +}; + +&npu_opp_table { + /delete-node/ mbist-vmin; + /* + * Max NPU frequency is 900MHz for the overdrive mode, + * but it will reduce chip lifetime. + */ + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + /delete-node/ opp-1000000000; + opp-300000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-400000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-500000000 { + opp-microvolt = <850000 850000 1000000>; + }; + opp-600000000 { + opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; + opp-microvolt-L4 = <850000 850000 1000000>; + }; + opp-700000000 { + opp-microvolt-L4 = <850000 850000 1000000>; + status = "disabled"; + }; +}; diff --git a/rk3566-box-demo-v10.dts b/rk3566-box-demo-v10.dts new file mode 100644 index 0000000..1bd285b --- /dev/null +++ b/rk3566-box-demo-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3566-box-demo-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 BOX DEMO V10 ANDROID Board"; + compatible = "rockchip,rk3566-box-demo-v10", "rockchip,rk3566"; +}; diff --git a/rk3566-box-demo-v10.dtsi b/rk3566-box-demo-v10.dtsi new file mode 100644 index 0000000..41ac0af --- /dev/null +++ b/rk3566-box-demo-v10.dtsi @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3566-box.dtsi" + +/ { + model = "Rockchip RK3566 BOX DEMO V10 Board"; + compatible = "rockchip,rk3568-box-demo-v10", "rockchip,rk3566"; + + gpio-leds { + compatible = "gpio-leds"; + + ir-led { + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + work-led { + gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h &wifi_32k>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_sd: vcc3v3-sd-regulator { + compatible = "regulator-gpio"; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x1 + 3300000 0x0>; + }; + + vccio_sd: vccio-sd-regulator { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy1_usq { + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc4c33_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout>; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c2{ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + + gc8034: gc8034@37 { + status = "okay"; + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + /*pwren-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;*/ + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + gc4c33: gc4c33@29 { + status = "okay"; + compatible = "galaxycore,gc4c33"; + reg = <0x29>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + /*pwren-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;*/ + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "PCORW0009A"; + rockchip,camera-module-lens-name = "40IRC-4M"; + port { + gc4c33_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pwm15 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m1_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +/* Need to be modified according to the actual hardware */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <50000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + //sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + non-removable; + mmc-pwrseq = <&sdio_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3566-box.dtsi b/rk3566-box.dtsi new file mode 100644 index 0000000..77189ab --- /dev/null +++ b/rk3566-box.dtsi @@ -0,0 +1,472 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566.dtsi" +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "hdmi-sound"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + status = "disabled"; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc_1v8: vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: vcc_3v3{ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_fixed: vdd-fixed { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-init-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + auto-freq-en = <0>; + center-supply = <&vdd_fixed>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_fixed>; + status = "okay"; +}; + +&gpu_opp_table { + /delete-node/ opp-800000000; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; +}; + +&rk_rga { + status = "okay"; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_fixed>; + status = "okay"; +}; + +&rknpu_mmu { + status = "disabled"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_CENTER_OFF + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_PMIC_LP + | RKPM_SLP_32K_PVTM + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_PWM0_WKUP_EN + | RKPM_CPU0_WKUP_EN + ) + >; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&u2phy1_otg { + status = "disabled"; +}; + +&usb2phy1 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + maximum-speed = "high-speed"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + + diff --git a/rk3566-eink.dtsi b/rk3566-eink.dtsi new file mode 100644 index 0000000..40f2478 --- /dev/null +++ b/rk3566-eink.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/ { + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + waveform_reserved: waveform@10800000 { + reg = <0x0 0x10800000 0x0 0x100000>; + }; + + display_reserved: framebuffer@10900000 { + reg = <0x0 0x10900000 0x0 0x2000000>; + }; + }; + + ebc_dev: ebc-dev { + compatible = "rockchip,ebc-dev"; + ebc_tcon = <&ebc>; + eink_tcon = <&eink>; + memory-region = <&display_reserved>; + waveform-region = <&waveform_reserved>; + status = "okay"; + }; +}; + +&cpu0_opp_table { + opp-216000000 { + opp-hz = /bits/ 64 <216000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-312000000 { + opp-hz = /bits/ 64 <312000000>; + opp-microvolt = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + auto-freq-en = <0>; + status = "okay"; +}; + +&dmc_opp_table { + opp-324000000 { + opp-hz = /bits/ 64 <324000000>; + opp-microvolt = <875000>; + }; + opp-528000000 { + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <875000>; + }; +}; + +&ebc { + status = "okay"; +}; + +&eink { + status = "okay"; +}; + +&gpu_opp_table { + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <825000>; + }; + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <825000>; + }; +}; + +&lpddr4_params { + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <528>; + freq_1 = <324>; + freq_2 = <324>; + freq_3 = <324>; +}; + +&lpddr4x_params { + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <528>; + freq_1 = <324>; + freq_2 = <324>; + freq_3 = <324>; +}; + +&rockchip_suspend { + status = "okay"; + + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_LOGOFF + | RKPM_SLP_CENTER_OFF + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_OSC_DIS + | RKPM_SLP_PMIC_LP + | RKPM_SLP_32K_PVTM + ) + >; +}; + diff --git a/rk3566-evb-mipitest-v10.dts b/rk3566-evb-mipitest-v10.dts new file mode 100644 index 0000000..3f21588 --- /dev/null +++ b/rk3566-evb-mipitest-v10.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3566-evb-mipitest-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3566-evb-mipitest-v10.dtsi b/rk3566-evb-mipitest-v10.dtsi new file mode 100644 index 0000000..a68269f --- /dev/null +++ b/rk3566-evb-mipitest-v10.dtsi @@ -0,0 +1,507 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" +#include "rk3566-evb.dtsi" + +/ { + model = "Rockchip RK3566 EVB MIPITEST V10 Board"; + compatible = "rockchip,rk3566-evb-mipitest-v10", "rockchip,rk3566"; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&audiopwmout_diff { + status = "disabled"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy1 { + status = "okay"; + + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov02k10_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&edp { + hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + status = "disabled"; + power-supply = <&vcc3v3_lcd0_n>; +}; + +&hdmi { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + + /* split mode: lane0/1 */ + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&dphy1_in>; + data-lanes = <1 2>; + }; + }; + }; + + ov02k10: ov02k10@36 { + status = "okay"; + compatible = "ovti,ov02k10"; + reg = <0x36>; + clocks = <&cru CLK_CAM1_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout1>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov02k10_out: endpoint { + remote-endpoint = <&dphy2_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s3_2ch { + status = "disabled"; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy2_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "disabled"; +}; + +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + +&u2phy1_host { + status = "disabled"; +}; + +&u2phy1_otg { + status = "disabled"; +}; + +&usb2phy1 { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3566-evb.dtsi b/rk3566-evb.dtsi new file mode 100644 index 0000000..d1aa123 --- /dev/null +++ b/rk3566-evb.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb.dtsi" diff --git a/rk3566-evb1-ddr4-v10-linux.dts b/rk3566-evb1-ddr4-v10-linux.dts new file mode 100644 index 0000000..a22cc8c --- /dev/null +++ b/rk3566-evb1-ddr4-v10-linux.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb1-ddr4-v10.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Rockchip RK3566 EVB1 DDR4 V10 Linux Board"; + compatible = "rockchip,rk3566-evb1-ddr4-v10-linux", "rockchip,rk3566"; +}; diff --git a/rk3566-evb1-ddr4-v10-lvds.dts b/rk3566-evb1-ddr4-v10-lvds.dts new file mode 100644 index 0000000..98a3840 --- /dev/null +++ b/rk3566-evb1-ddr4-v10-lvds.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3566-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd1_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <30>; + hfront-porch = <30>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; + }; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; diff --git a/rk3566-evb1-ddr4-v10.dts b/rk3566-evb1-ddr4-v10.dts new file mode 100644 index 0000000..55e31aa --- /dev/null +++ b/rk3566-evb1-ddr4-v10.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3566-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" + +&bt_sco { + status = "okay"; +}; + +&bt_sound { + status = "okay"; +}; + +&i2s3_2ch { + status = "okay"; +}; diff --git a/rk3566-evb1-ddr4-v10.dtsi b/rk3566-evb1-ddr4-v10.dtsi new file mode 100644 index 0000000..8963446 --- /dev/null +++ b/rk3566-evb1-ddr4-v10.dtsi @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" +#include "rk3566-evb.dtsi" + +/ { + model = "Rockchip RK3566 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3566-evb1-ddr4-v10", "rockchip,rk3566"; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&audiopwmout_diff { + status = "disabled"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy1 { + status = "okay"; + + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov02k10_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&edp { + hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + + /* split mode: lane0/1 */ + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&dphy1_in>; + data-lanes = <1 2>; + }; + }; + }; + + ov02k10: ov02k10@36 { + status = "okay"; + compatible = "ovti,ov02k10"; + reg = <0x36>; + clocks = <&cru CLK_CAM1_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout1>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov02k10_out: endpoint { + remote-endpoint = <&dphy2_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_sclktx &i2s2m1_lrcktx &i2s2m1_sdi &i2s2m1_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&i2s3_2ch { + status = "disabled"; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy2_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&work_led { + gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3566-evb2-lp4x-v10-edp.dts b/rk3566-evb2-lp4x-v10-edp.dts new file mode 100644 index 0000000..d441e55 --- /dev/null +++ b/rk3566-evb2-lp4x-v10-edp.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include "rk3566-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + panel-edp { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <120>; + height-mm = <160>; + + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; +}; + +&dsi0 { + status = "disabled"; +}; + +&edp { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "okay"; +}; + +&route_edp { + connect = <&vp1_out_edp>; + status = "okay"; +}; diff --git a/rk3566-evb2-lp4x-v10-eink.dts b/rk3566-evb2-lp4x-v10-eink.dts new file mode 100644 index 0000000..83546ee --- /dev/null +++ b/rk3566-evb2-lp4x-v10-eink.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" +#include "rk3566-eink.dtsi" + +/ { + model = "Rockchip RK3566 EVB2 LP4X V10 Eink Board"; + compatible = "rockchip,rk3566-evb2-lp4x-v10-eink", "rockchip,rk3566"; +}; + +&backlight { + status = "disabled"; +}; + +&backlight1 { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_panel { + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; +}; + +&ebc { + /* clock rate 1000M/n, (n=1~32) */ + assigned-clocks = <&cru CPLL_333M>, <&cru DCLK_EBC>; + //assigned-clock-rates = <340000000>, <340000000>; + assigned-clock-rates = <250000000>, <250000000>; + //assigned-clock-rates = <100000000>, <100000000>; + status = "okay"; +}; + +&ebc_dev { + pmic = <&tps65185>; + status = "okay"; +#if 0 + /* ED097TC2U1 */ + panel,width = <1200>; + panel,height = <825>; + panel,vir_width = <1200>; + panel,vir_height = <825>; + panel,sdck = <25000000>; + panel,lsl = <4>; + panel,lbl = <4>; + panel,ldl = <300>; + panel,lel = <36>; + panel,gdck-sta = <18>; + panel,lgonl = <265>; + panel,fsl = <2>; + panel,fbl = <4>; + panel,fdl = <825>; + panel,fel = <24>; + panel,mirror = <0>; + panel,panel_16bit = <0>; + panel,panel_color = <0>; + panel,width-mm = <203>; + panel,height-mm = <140>; +#endif +#if 1 + /* ES103TC1 */ + panel,width = <1872>; + panel,height = <1404>; + panel,vir_width = <1872>; + panel,vir_height = <1404>; + panel,sdck = <33300000>; + panel,lsl = <18>; + panel,lbl = <17>; + panel,ldl = <234>; + panel,lel = <7>; + panel,gdck-sta = <34>; + panel,lgonl = <192>; + panel,fsl = <1>; + panel,fbl = <4>; + panel,fdl = <1404>; + panel,fel = <12>; + panel,mirror = <0>; + panel,panel_16bit = <1>; + panel,panel_color = <0>; + panel,width-mm = <157>; + panel,height-mm = <210>; +#endif +#if 0 + /* ES133TC1 */ + panel,width = <2200>; + panel,height = <1650>; + panel,vir_width = <2208>; + panel,vir_height = <1650>; + panel,sdck = <37500000>; + panel,lsl = <4>; + panel,lbl = <8>; + panel,ldl = <275>; + panel,lel = <14>; + panel,gdck-sta = <34>; + panel,lgonl = <217>; + panel,fsl = <1>; + panel,fbl = <4>; + panel,fdl = <1650>; + panel,fel = <6>; + panel,mirror = <0>; + panel,panel_16bit = <1>; + panel,panel_color = <0>; + panel,width-mm = <157>; + panel,height-mm = <210>; +#endif +#if 0 + panel,width = <2232>; + panel,height = <1680>; + panel,vir_width = <2240>; + panel,vir_height = <1680>; + panel,sdck = <33300000>; + panel,lsl = <4>; + panel,lbl = <8>; + panel,ldl = <279>; + panel,lel = <14>; + panel,gdck-sta = <34>; + panel,lgonl = <217>; + panel,fsl = <1>; + panel,fbl = <4>; + panel,fdl = <1680>; + panel,fel = <6>; + panel,mirror = <0>; + panel,panel_16bit = <1>; + panel,panel_color = <0>; + panel,width-mm = <157>; + panel,height-mm = <210>; +#endif +}; + +&gmac1 { + status = "disabled"; +}; + +>1x { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; + +&hdmi_sound{ + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + tsc@24 { + status = "okay"; + compatible = "cy,cyttsp5_i2c_adapter"; + reg = <0x24>; + cy,adapter_id = "cyttsp5_i2c_adapter"; + //cytp-supply = <&vcc_sd>; + cy,core { + cy,name = "cyttsp5_core"; + pinctrl-names = "default"; + pinctrl-0 = <&tsc_gpio>; + cy,irq_gpio = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + cy,rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + cy,hid_desc_register = <1>; + /* CY_CORE_FLAG_RESTORE_PARAMETERS */ + cy,flags = <6>; + /* CY_CORE_EWG_NONE */ + cy,easy_wakeup_gesture = <0>; + cy,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + cy,btn_keys-tag = <0>; + cy,mt { + cy,name = "cyttsp5_mt"; + cy,inp_dev_name = "cyttsp5_mt"; + cy,flags = <0>; + cy,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + <0x35 0 1872 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1404 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0>; + + cy,vkeys_x = <1872>; + cy,vkeys_y = <1404>; + + cy,revert_x = <0>; + cy,revert_y = <0>; + cy,xy_exchange = <0>; + + cy,virtual_keys = /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 1360 90 160 180 + /* KEY_MENU */ + 139 1360 270 160 180 + /* KEY_HOMEPAGE */ + 172 1360 450 160 180 + /* KEY SEARCH */ + 217 1360 630 160 180>; + }; + + cy,btn { + cy,name = "cyttsp5_btn"; + cy,inp_dev_name = "cyttsp5_btn"; + }; + + cy,proximity { + cy,name = "cyttsp5_proximity"; + cy,inp_dev_name = "cyttsp5_proximity"; + cy,abs = + /* ABS_DISTANCE, CY_PROXIMITY_MIN_VAL, CY_PROXIMITY_MAX_VAL, 0, 0 */ + <0x19 0 1 0 0>; + }; + }; + }; + + tps65185: tps65185@68 { + status = "okay"; + compatible = "ti,tps65185"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65185_gpio>; + int-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + vcomctl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + powerup-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + status = "okay"; + + wacom: wacom@9 { + compatible = "wacom,w9013"; + reg = <0x09>; + pinctrl-names = "default"; + pinctrl-0 = <&wacom_gpio>; + gpio_detect = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_intr = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_rst = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + revert_x = <0>; + revert_y = <0>; + xy_exchange = <0>; + }; +}; + +&video_phy0 { + status = "disabled"; +}; + +&mxc6655xa { + status = "disabled"; +}; + +&pinctrl { + tps_pmic { + tps65185_gpio: tps65185-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + tsc { + tsc_gpio: tsc-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + wacom { + wacom_gpio: wacom-gpio { + rockchip,pins = + <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&vcc_camera { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; +}; diff --git a/rk3566-evb2-lp4x-v10-i2s-mic-array.dts b/rk3566-evb2-lp4x-v10-i2s-mic-array.dts new file mode 100644 index 0000000..5ba1318 --- /dev/null +++ b/rk3566-evb2-lp4x-v10-i2s-mic-array.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 EVB2 LP4X V10 Board I2S Mic Array"; + compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3566"; + + rk809_sound_micarray: rk809-sound-micarray { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&es7243e>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es7243e: es7243e@10 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7243E_MicArray_0"; + reg = <0x10>; + }; + + es7243e_11: es7243e@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7243E_MicArray_1"; + reg = <0x11>; + }; + + es7243e_12: es7243e@12 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7243E_MicArray_2"; + reg = <0x12>; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sclkrx + &i2s1m0_lrckrx + &i2s1m0_sdo0 + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3>; +}; + +&rk809_codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + pdmdata-out-enable; + adc-for-loopback; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; +}; + +&rk809_sound { + status = "disabled"; +}; diff --git a/rk3566-evb2-lp4x-v10-linux.dts b/rk3566-evb2-lp4x-v10-linux.dts new file mode 100644 index 0000000..04e2155 --- /dev/null +++ b/rk3566-evb2-lp4x-v10-linux.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb2-lp4x-v10.dtsi" +#include "rk3568-linux.dtsi" +#include + +&vp0 { + cursor-win-id = ; +}; diff --git a/rk3566-evb2-lp4x-v10-pdm-mic-array.dts b/rk3566-evb2-lp4x-v10-pdm-mic-array.dts new file mode 100644 index 0000000..55e9679 --- /dev/null +++ b/rk3566-evb2-lp4x-v10-pdm-mic-array.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 EVB2 LP4X V10 Board PDM Mic Array"; + compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3566"; + + rk809_sound_micarray: rk809-sound-micarray { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "pdm"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&rk809_codec 1>; + }; + }; + simple-audio-card,dai-link@2 { + format = "pdm"; + cpu { + sound-dai = <&pdm>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es7202: es7202@30 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + reg = <0x30>; + }; + + es7202_31: es7202@31 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_2"; + reg = <0x31>; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdo0>; +}; + +&pdm { + status = "okay"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; +}; + +&rk809_codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + pdmdata-out-enable; + adc-for-loopback; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; +}; + +&rk809_sound { + status = "disabled"; +}; + diff --git a/rk3566-evb2-lp4x-v10.dts b/rk3566-evb2-lp4x-v10.dts new file mode 100644 index 0000000..3b36bdb --- /dev/null +++ b/rk3566-evb2-lp4x-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3566-evb2-lp4x-v10.dtsi b/rk3566-evb2-lp4x-v10.dtsi new file mode 100644 index 0000000..7b434c5 --- /dev/null +++ b/rk3566-evb2-lp4x-v10.dtsi @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3566-evb.dtsi" + +/ { + model = "Rockchip RK3566 EVB2 LP4X V10 Board"; + compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3566"; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + /* + * dphy0 only used for full mode, + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&gc5025_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in_dphy0>; + }; + }; + }; +}; + +&csi2_dphy1 { + status = "disabled"; + + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + //remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "disabled"; + + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_in: endpoint@1 { + reg = <1>; + //remote-endpoint = <&gc5025_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x25>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + + /* split mode: lane0/1 */ + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + /* split mode: lane:2/3 */ + gc5025: gc5025@37 { + status = "okay"; + compatible = "galaxycore,gc5025"; + reg = <0x37>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + power-domains = <&power RK3568_PD_VI>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + gc5025_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + + /* full mode: lane0-3 */ + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&dphy0_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c4 { + /* i2c4 sda conflict with camera pwdn */ + status = "disabled"; + + /* + * gc2145 needs to be disabled, + * when gmac1 is enabled; + * pinctrl conflicts; + */ + gc2145: gc2145@3c { + status = "disabled"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + /* conflict with gmac1m1_rgmii_pins & cif_clk*/ + pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; + + /*avdd-supply = <&vcc2v8_dvp>;*/ + /*dovdd-supply = <&vcc1v8_dvp>;*/ + /*dvdd-supply = <&vcc1v8_dvp>;*/ + + /*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/ + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + + + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy2_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_dvp { + status = "disabled"; + + port { + /* Parallel bus endpoint */ + dvp_in_bcam: endpoint { + remote-endpoint = <&gc2145_out>; + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + isp0_in_dphy0: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy0_out>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&spdif_8ch { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&work_led { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk3566-evb3-ddr3-v10-linux.dts b/rk3566-evb3-ddr3-v10-linux.dts new file mode 100644 index 0000000..e292b0d --- /dev/null +++ b/rk3566-evb3-ddr3-v10-linux.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb3-ddr3-v10.dtsi" +#include "rk3568-linux.dtsi" diff --git a/rk3566-evb3-ddr3-v10.dts b/rk3566-evb3-ddr3-v10.dts new file mode 100644 index 0000000..09f5260 --- /dev/null +++ b/rk3566-evb3-ddr3-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3566-evb3-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3566-evb3-ddr3-v10.dtsi b/rk3566-evb3-ddr3-v10.dtsi new file mode 100644 index 0000000..6d3768c --- /dev/null +++ b/rk3566-evb3-ddr3-v10.dtsi @@ -0,0 +1,513 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" +#include "rk3566-evb.dtsi" + +/ { + model = "Rockchip RK3566 EVB3 DDR3 V10 Board"; + compatible = "rockchip,rk3566-evb3-DDR3-v10", "rockchip,rk3566"; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&combphy1_usq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&edp { + hpd-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2_level3 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; + + tx_delay = <0x41>; + rx_delay = <0x2e>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + + gc2145: gc2145@3c { + status = "okay"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; + + /*avdd-supply = <&vcc2v8_dvp>;*/ + /*dovdd-supply = <&vcc1v8_dvp>;*/ + /*dvdd-supply = <&vcc1v8_dvp>;*/ + + power-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + /*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/ + pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; + + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + +&i2s1_8ch { + status = "disabled"; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&i2s3_2ch { + status = "okay"; + pinctrl-names = "default"; + rockchip,clk-trcm = <1>; + pinctrl-0 = <&i2s3m1_sclk + &i2s3m1_lrck + &i2s3m1_sdi + &i2s3m1_sdo>; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_dvp { + status = "okay"; + + port { + /* Parallel bus endpoint */ + dvp_in_bcam: endpoint { + remote-endpoint = <&gc2145_out>; + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&rk809_codec { + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S3_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3m1_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; +}; + +&rk809_sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec 0>; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sata1 { + status = "okay"; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&work_led { + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; +}; diff --git a/rk3566-evb5-lp4x-v10.dts b/rk3566-evb5-lp4x-v10.dts new file mode 100644 index 0000000..600fc3c --- /dev/null +++ b/rk3566-evb5-lp4x-v10.dts @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3566-evb5-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3566-evb5-lp4x-v10.dtsi b/rk3566-evb5-lp4x-v10.dtsi new file mode 100644 index 0000000..55bfa76 --- /dev/null +++ b/rk3566-evb5-lp4x-v10.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" +#include "rk3566-evb.dtsi" + +/ { + model = "Rockchip RK3566 EVB5 LP4X V10 Board"; + compatible = "rockchip,rk3566-evb5-lp4x-v10", "rockchip,rk3566"; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&audiopwmout_diff { + status = "disabled"; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "disabled"; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&edp { + hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&edp_phy { + status = "disabled"; +}; + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2_level3 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; + + tx_delay = <0x41>; + rx_delay = <0x2e>; + + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c5 { + status = "disabled"; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&i2s3_2ch { + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "disabled"; +}; + +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + +&route_dsi0 { + status = "okay"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + +&uart3 { + status = "disabled"; +}; + +&uart4 { + status = "disabled"; +}; + +&uart7 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + status = "disabled"; +}; + +&work_led { + status = "disabled"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3566-rk817-eink-w103.dts b/rk3566-rk817-eink-w103.dts new file mode 100644 index 0000000..f1eb6ad --- /dev/null +++ b/rk3566-rk817-eink-w103.dts @@ -0,0 +1,1115 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" +#include "rk3566-eink.dtsi" + +/ { + model = "Rockchip RK3566 RK817 EINK LP4X Board"; + compatible = "rockchip,rk3566-rk817-eink", "rockchip,rk3566"; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + rockchip,auto-wakeup-interval = <60>; + status = "okay"; + }; + + adc_keys: adc-keys { + status = "okay"; + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <9000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + gpio_keys: gpio-keys { + status = "disabled"; + compatible = "gpio-keys"; + autorepeat; + + BACK { + label = "GPIO Key Home"; + debounce-interval = <10>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + linux,input-type = ; + linux,code = ; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + + led@2 { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "battery-charging"; + label = "battery_charging"; + retain-state-suspended; + }; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + irq-gpio = <&gpio0 RK_PC7 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_tp: vcc-tp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_tp_en>; + regulator-name = "vcc_tp"; + regulator-boot-on; + startup-delay-us = <10000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk817-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_vbat &wifi_host_wake_irq>; + WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>, + <&bt_reset_gpio>, + <&bt_wake_gpio>, + <&bt_irq_gpio>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&ebc { + /* clock rate 1000M/n, (n=1~32) */ + assigned-clocks = <&cru CPLL_333M>, <&cru DCLK_EBC>; + //assigned-clock-rates = <340000000>, <340000000>; + assigned-clock-rates = <250000000>, <250000000>; + status = "okay"; +}; + +&ebc_dev { + pmic = <&tps65185>; + status = "okay"; +#if 0 + /* ED097TC2U1 */ + panel,width = <1200>; + panel,height = <825>; + panel,vir_width = <1200>; + panel,vir_height = <825>; + panel,sdck = <25000000>; + panel,lsl = <4>; + panel,lbl = <4>; + panel,ldl = <300>; + panel,lel = <36>; + panel,gdck-sta = <18>; + panel,lgonl = <265>; + panel,fsl = <2>; + panel,fbl = <4>; + panel,fdl = <825>; + panel,fel = <24>; + panel,mirror = <0>; + panel,panel_16bit = <0>; + panel,panel_color = <0>; + panel,width-mm = <203>; + panel,height-mm = <140>; +#endif +#if 1 + /* ES103TC1 */ + panel,width = <1872>; + panel,height = <1404>; + panel,vir_width = <1872>; + panel,vir_height = <1404>; + panel,sdck = <33300000>; + panel,lsl = <18>; + panel,lbl = <17>; + panel,ldl = <234>; + panel,lel = <7>; + panel,gdck-sta = <34>; + panel,lgonl = <192>; + panel,fsl = <1>; + panel,fbl = <4>; + panel,fdl = <1404>; + panel,fel = <12>; + panel,mirror = <0>; + panel,panel_16bit = <1>; + panel,panel_color = <0>; + panel,width-mm = <157>; + panel,height-mm = <210>; +#endif +#if 0 + /* ES133TC1 */ + panel,width = <2200>; + panel,height = <1650>; + panel,vir_width = <2208>; + panel,vir_height = <1650>; + panel,sdck = <37500000>; + panel,lsl = <4>; + panel,lbl = <8>; + panel,ldl = <275>; + panel,lel = <14>; + panel,gdck-sta = <34>; + panel,lgonl = <217>; + panel,fsl = <1>; + panel,fbl = <4>; + panel,fdl = <1650>; + panel,fel = <6>; + panel,mirror = <0>; + panel,panel_16bit = <1>; + panel,panel_color = <0>; + panel,width-mm = <157>; + panel,height-mm = <210>; +#endif +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + /*remote-endpoint = <&ov5648_out>;*/ + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <0>; + regulator-initial-mode = <0x2>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + regulator-changeable-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; +// pinctrl-names = "default", "pmic-sleep", +// "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; +// pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; +// pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; +// pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + regulator-changeable-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + regulator-changeable-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + regulator-changeable-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + regulator-changeable-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + sleep_sta_ctl: LDO_REG9 { + regulator-name = "sleep_sta_ctl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-changeable-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3513 3578 3687 3734 3752 3763 + 3766 3771 3784 3804 3836 3885 3925 + 3962 4005 4063 4114 4169 4227 4303>; + design_capacity = <4150>; + design_qmax = <4565>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3450>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + low_power_sleep = <1>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + gate_function_disable = <1>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + out-l2spk-r2hp; + spk-ctl-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + wacom: wacom@9 { + compatible = "wacom,w9013"; + reg = <0x09>; + pwr-supply = <&vcc_tp>; + pinctrl-names = "default"; + pinctrl-0 = <&wacom_gpio>; + gpio_detect = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + gpio_intr = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + gpio_rst = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + revert_x = <0>; + revert_y = <0>; + xy_exchange = <0>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + tps65185: tps65185@68 { + status = "okay"; + compatible = "ti,tps65185"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65185_gpio>; + wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + vcomctl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + int-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + powerup-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + poweren-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c4 { + //camera +}; + +&i2c5 { + status = "okay"; + + sensor@4c { + status = "okay"; + compatible = "gs_mma7660"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + reprobe_en = <1>; + }; + + tsc@24 { + status = "okay"; + compatible = "cy,cyttsp5_i2c_adapter"; + reg = <0x24>; + cy,adapter_id = "cyttsp5_i2c_adapter"; + pinctrl-names = "default"; + pinctrl-0 = <&tsc_gpio>; + cytp-supply = <&vcc_tp>; + cy,core { + cy,name = "cyttsp5_core"; + cy,irq_gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + cy,rst_gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + cy,hid_desc_register = <1>; + /* CY_CORE_FLAG_RESTORE_PARAMETERS */ + cy,flags = <6>; + /* CY_CORE_EWG_NONE */ + cy,easy_wakeup_gesture = <0>; + cy,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + cy,btn_keys-tag = <0>; + cy,mt { + cy,name = "cyttsp5_mt"; + cy,inp_dev_name = "cyttsp5_mt"; + cy,flags = <0xA8>; + cy,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + <0x35 0 1404 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1872 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0>; + + cy,vkeys_x = <1404>; + cy,vkeys_y = <1872>; + cy,revert_x = <0>; + cy,revert_y = <0>; + cy,xy_exchange = <0>; + + cy,virtual_keys = + /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 1360 90 160 180 + /* KEY_MENU */ + 139 1360 270 160 180 + /* KEY_HOMEPAGE */ + 172 1360 450 160 180 + /* KEY SEARCH */ + 217 1360 630 160 180>; + }; + + cy,btn { + cy,name = "cyttsp5_btn"; + cy,inp_dev_name = "cyttsp5_btn"; + }; + + cy,proximity { + cy,name = "cyttsp5_proximity"; + cy,inp_dev_name = "cyttsp5_proximity"; + cy,abs = + /* ABS_DISTANCE, CY_PROXIMITY_MIN_VAL, CY_PROXIMITY_MAX_VAL, 0, 0 */ + <0x19 0 1 0 0>; + }; + }; + }; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "disabled"; +}; + +&pinctrl { + wacom { + wacom_gpio: wacom-gpio { + rockchip,pins = + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tsc { + tsc_gpio: tsc-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>, //touch q gpio + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tps_pmic { + tps65185_gpio: tps65185-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_vbat: wifi-vbat { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + vcc-tp { + vcc_tp_en: vcc-tp-en { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_1v8>; +}; + +&pwm0 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + + rockchip,regulator-off-in-mem-lite = + <&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>, + <&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>, + <&sleep_sta_ctl>; + rockchip,regulator-on-in-mem-lite = + <&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>; + + rockchip,regulator-off-in-mem = + <&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>, + <&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>, + <&sleep_sta_ctl>; + rockchip,regulator-on-in-mem = + <&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>; + + rockchip,regulator-off-in-mem-ultra = + <&vdd_logic>, <&vdd_gpu>, <&vcc_ddr>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>, + <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>, <&vccio_acodec>, <&vccio_sd>, + <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>; + rockchip,regulator-on-in-mem-ultra = <&vdd_cpu>, <&sleep_sta_ctl>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566-rk817-eink-w6.dts b/rk3566-rk817-eink-w6.dts new file mode 100644 index 0000000..ab8e87e --- /dev/null +++ b/rk3566-rk817-eink-w6.dts @@ -0,0 +1,968 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" +#include "rk3566-eink.dtsi" + +/ { + model = "Rockchip RK3566 RK817 EINK W6 LP4X Board"; + compatible = "rockchip,rk3566-rk817-eink-W6", "rockchip,rk3566"; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + rockchip,auto-wakeup-interval = <60>; + status = "okay"; + }; + + adc_keys: adc-keys { + status = "disabled"; + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 =<&leds_gpio>; + + led@1 { + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "battery-full"; + label = "battery_full"; + retain-state-suspended; + }; + + led@2 { + gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "battery-charging"; + label = "battery_charging"; + retain-state-suspended; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rst>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc_tp: vcc-tp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_tp_en>; + regulator-name = "vcc_tp"; + }; + + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + mic_sound: mic-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,rk-mic-sound"; + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_vbat &wifi_host_wake_irq>; + WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&ebc { + /* clock rate 1000M/n, (n=1~32) */ + assigned-clocks = <&cru CPLL_333M>, <&cru DCLK_EBC>; + assigned-clock-rates = <85000000>, <85000000>; + status = "okay"; +}; + +&ebc_dev { + pmic = <&tps65185>; + status = "okay"; + + /* ED060XCD */ + panel,width = <1024>; + panel,height = <758>; + panel,vir_width = <1024>; + panel,vir_height = <758>; + panel,sdck = <20000000>; + panel,lsl = <6>; + panel,lbl = <6>; + panel,ldl = <256>; + panel,lel = <38>; + panel,gdck-sta = <4>; + panel,lgonl = <262>; + panel,fsl = <2>; + panel,fbl = <4>; + panel,fdl = <758>; + panel,fel = <5>; + panel,mirror = <0>; + panel,panel_16bit = <0>; + panel,panel_color = <0>; + panel,width-mm = <90>; + panel,height-mm = <122>; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ov5648_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <0>; + regulator-boot-on; + regulator-always-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + regulator-changeable-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; +// pinctrl-names = "default", "pmic-sleep", +// "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; +// pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; +// pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; +// pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + regulator-changeable-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + regulator-changeable-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + regulator-changeable-in-suspend; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + regulator-changeable-in-suspend; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + sleep_sta_ctl: LDO_REG9 { + regulator-name = "sleep_sta_ctl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + regulator-changeable-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-changeable-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3513 3578 3687 3734 3752 3763 + 3766 3771 3784 3804 3836 3885 3925 + 3962 4005 4063 4114 4169 4227 4303>; + design_capacity = <2250>; + design_qmax = <2750>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3450>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + low_power_sleep = <1>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + gate_function_disable = <1>; + }; + }; +}; + +&i2c1 { + status = "okay"; + + ov5648: ov5648@36 { + status = "okay"; + compatible = "ovti,ov5648"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + /* avdd-supply = <&vcc2v8_dvp>; */ + dovdd-supply = <&vcc1v8_dvp>; + /* dvdd-supply = <&vcc1v8_dvp>; */ + + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + //reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + port { + ov5648_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + tps65185: tps65185@68 { + compatible = "ti,tps65185"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65185_gpio>; + int-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + vcomctl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + powerup-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + poweren-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + }; + +}; + +&i2c5 { + status = "okay"; + + sensor@4c { + status = "okay"; + compatible = "gs_mma7660"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <6>; + reprobe_en = <1>; + }; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + touch-gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <758>; + max-x = <1024>; + max-y = <758>; + tp-size = <9111>; + tp-supply = <&vcc_tp>; + wakeup-source; + touchscreen-key-map = <158>; //KEY_HOMEPAGE=172,KEY_BACK=158,KEY_MENU=139 + goodix,driver-send-cfg = <0>; + goodix,cfg-group0 =[ + 42 00 03 00 04 0A 45 03 22 1F 28 0F 64 3C 03 0F 00 00 00 00 11 00 + 08 00 00 00 00 8B 29 0E 71 6F B2 04 00 00 00 39 02 10 00 21 00 00 + 00 03 64 32 00 00 00 3C 78 94 D5 02 07 00 00 04 C8 40 00 B1 4A 00 + 9E 55 00 8E 61 00 7F 70 00 7F 70 00 00 00 F0 90 3C FF FF 07 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 02 04 06 08 0A 0C 0F 10 12 13 16 + 18 1C 1D 1E 1F 20 21 22 FF FF FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF F6 01 + ]; + }; + + ft5436: focaltech@38 { + status = "okay"; + compatible = "focaltech,ft5436"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + vdd-supply = <&vcc_tp>; + focaltech,reset-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + focaltech,irq-gpio = <&gpio0 RK_PA6 IRQ_TYPE_EDGE_FALLING>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1024 758>; + focaltech,have-key = <1>; + focaltech,key-number = <1>; + + focaltech,key-x-coords = <300>; + focaltech,key-y-coords = <1200>; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "disabled"; +}; + +&pinctrl { + cam { + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + camera_rst: camera-rst { + rockchip,pins = + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + leds_gpio: leds-gpio { + rockchip,pins = + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tps_pmic { + tps65185_gpio: tps65185-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + tp { + tp_gpio: tp-gpio { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc-tp { + vcc_tp_en: vcc-tp-en { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_vbat: wifi-vbat { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc1v8_dvp>; +}; + +&pwm4 { + status = "disabled"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + + rockchip,regulator-off-in-mem-lite = + <&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>, + <&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>, + <&sleep_sta_ctl>; + rockchip,regulator-on-in-mem-lite = + <&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>; + + rockchip,regulator-off-in-mem = + <&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>, + <&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>, + <&sleep_sta_ctl>; + rockchip,regulator-on-in-mem = + <&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>; + + rockchip,regulator-off-in-mem-ultra = + <&vdd_logic>, <&vdd_gpu>, <&vcc_ddr>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>, + <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>, <&vccio_acodec>, <&vccio_sd>, + <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>; + rockchip,regulator-on-in-mem-ultra = <&vdd_cpu>, <&sleep_sta_ctl>; +}; + +&saradc { + status = "disabled"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566-rk817-eink.dts b/rk3566-rk817-eink.dts new file mode 100644 index 0000000..39543fd --- /dev/null +++ b/rk3566-rk817-eink.dts @@ -0,0 +1,955 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" +#include "rk3566-eink.dtsi" + +/ { + model = "Rockchip RK3566 RK817 EINK LP4X Board"; + compatible = "rockchip,rk3566-rk817-eink", "rockchip,rk3566"; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + rockchip,auto-wakeup-interval = <60>; + status = "okay"; + }; + + adc_keys: adc-keys { + status = "disabled"; + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "disabled"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&ebc { + /* clock rate 1000M/n, (n=1~32) */ + assigned-clocks = <&cru CPLL_333M>, <&cru DCLK_EBC>; + assigned-clock-rates = <250000000>, <250000000>; + status = "okay"; +}; + +&ebc_dev { + pmic = <&tps65185>; + status = "okay"; +#if 0 + /* ED097TC2U1 */ + panel,width = <1200>; + panel,height = <825>; + panel,vir_width = <1200>; + panel,vir_height = <825>; + panel,sdck = <25000000>; + panel,lsl = <4>; + panel,lbl = <4>; + panel,ldl = <300>; + panel,lel = <36>; + panel,gdck-sta = <18>; + panel,lgonl = <265>; + panel,fsl = <2>; + panel,fbl = <4>; + panel,fdl = <825>; + panel,fel = <24>; + panel,mirror = <0>; + panel,panel_16bit = <0>; + panel,panel_color = <0>; + panel,width-mm = <203>; + panel,height-mm = <140>; +#else + /* ES103TC1 */ + panel,width = <1872>; + panel,height = <1404>; + panel,vir_width = <1872>; + panel,vir_height = <1404>; + panel,sdck = <33300000>; + panel,lsl = <18>; + panel,lbl = <17>; + panel,ldl = <234>; + panel,lel = <7>; + panel,gdck-sta = <34>; + panel,lgonl = <192>; + panel,fsl = <1>; + panel,fbl = <4>; + panel,fdl = <1404>; + panel,fel = <12>; + panel,mirror = <0>; + panel,panel_16bit = <1>; + panel,panel_color = <0>; + panel,width-mm = <157>; + panel,height-mm = <210>; +#endif +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3513 3578 3687 3734 3752 3763 + 3766 3771 3784 3804 3836 3885 3925 + 3962 4005 4063 4114 4169 4227 4303>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3450>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + gate_function_disable = <1>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + out-l2spk-r2hp; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + tps65185: tps65185@68 { + status = "okay"; + compatible = "ti,tps65185"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&tps65185_gpio>; + int-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + vcomctl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + powerup-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c2 { + status = "okay"; + wacom: wacom@9 { + compatible = "wacom,w9013"; + reg = <0x09>; + pinctrl-names = "default"; + pinctrl-0 = <&wacom_gpio>; + gpio_detect = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_intr = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_rst = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + revert_x = <0>; + revert_y = <0>; + xy_exchange = <0>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + ts@40 { + compatible = "gslX680-pad"; + reg = <0x40>; + touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PB1 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + screen_max_x = <1200>; + screen_max_y = <1920>; + revert_x = <0>; + revert_y = <1>; + revert_xy = <0>; + chip_id = <1>; + status = "disabled"; + }; + + tsc@24 { + status = "okay"; + compatible = "cy,cyttsp5_i2c_adapter"; + reg = <0x24>; + cy,adapter_id = "cyttsp5_i2c_adapter"; + //cytp-supply = <&vcc_sd>; + cy,core { + cy,name = "cyttsp5_core"; + pinctrl-names = "default"; + pinctrl-0 = <&tsc_gpio>; + cy,irq_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + cy,rst_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + cy,1v8_gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + cy,2v8_gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + cy,hid_desc_register = <1>; + /* CY_CORE_FLAG_RESTORE_PARAMETERS */ + cy,flags = <6>; + /* CY_CORE_EWG_NONE */ + cy,easy_wakeup_gesture = <0>; + cy,btn_keys = <172 /* KEY_HOMEPAGE */ + /* previously was KEY_HOME, new Android versions use KEY_HOMEPAGE */ + 139 /* KEY_MENU */ + 158 /* KEY_BACK */ + 217 /* KEY_SEARCH */ + 114 /* KEY_VOLUMEDOWN */ + 115 /* KEY_VOLUMEUP */ + 212 /* KEY_CAMERA */ + 116>; /* KEY_POWER */ + cy,btn_keys-tag = <0>; + cy,mt { + cy,name = "cyttsp5_mt"; + cy,inp_dev_name = "cyttsp5_mt"; + cy,flags = <0>; + cy,abs = + /* ABS_MT_POSITION_X, CY_ABS_MIN_X, CY_ABS_MAX_X, 0, 0 */ + <0x35 0 1872 0 0 + /* ABS_MT_POSITION_Y, CY_ABS_MIN_Y, CY_ABS_MAX_Y, 0, 0 */ + 0x36 0 1404 0 0 + /* ABS_MT_PRESSURE, CY_ABS_MIN_P, CY_ABS_MAX_P, 0, 0 */ + 0x3a 0 255 0 0 + /* CY_IGNORE_VALUE, CY_ABS_MIN_W, CY_ABS_MAX_W, 0, 0 */ + 0xffff 0 255 0 0 + /* ABS_MT_TRACKING_ID, CY_ABS_MIN_T, CY_ABS_MAX_T, 0, 0 */ + 0x39 0 15 0 0 + /* ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0 */ + 0x30 0 255 0 0 + /* ABS_MT_TOUCH_MINOR, 0, 255, 0, 0 */ + 0x31 0 255 0 0 + /* ABS_MT_ORIENTATION, -127, 127, 0, 0 */ + 0x34 0xffffff81 127 0 0 + /* ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0 */ + 0x37 0 1 0 0 + /* ABS_DISTANCE, 0, 255, 0, 0 */ + 0x19 0 255 0 0>; + + cy,vkeys_x = <1872>; + cy,vkeys_y = <1404>; + cy,revert_x = <0>; + cy,revert_y = <1>; + cy,xy_exchange = <0>; + + cy,virtual_keys = + /* KeyCode CenterX CenterY Width Height */ + /* KEY_BACK */ + <158 1360 90 160 180 + /* KEY_MENU */ + 139 1360 270 160 180 + /* KEY_HOMEPAGE */ + 172 1360 450 160 180 + /* KEY SEARCH */ + 217 1360 630 160 180>; + }; + + cy,btn { + cy,name = "cyttsp5_btn"; + cy,inp_dev_name = "cyttsp5_btn"; + }; + + cy,proximity { + cy,name = "cyttsp5_proximity"; + cy,inp_dev_name = "cyttsp5_proximity"; + cy,abs = + /* ABS_DISTANCE, CY_PROXIMITY_MIN_VAL, CY_PROXIMITY_MAX_VAL, 0, 0 */ + <0x19 0 1 0 0>; + }; + }; + }; +}; + +&i2c5 { + status = "disabled"; + + kxtj: kxtj3@e { + status = "disabled"; + compatible = "gs_kxtj9"; + pinctrl-names = "default"; + pinctrl-0 = <&kxtj3_irq_gpio>; + reg = <0x0e>; + irq-gpio = <&gpio4 RK_PC6 IRQ_TYPE_EDGE_RISING>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + power-off-in-suspend = <1>; + layout = <5>; + }; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "disabled"; +}; + +&pinctrl { + wacom { + wacom_gpio: wacom-gpio { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + tsc { + tsc_gpio: tsc-gpio { + rockchip,pins = + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tps_pmic { + tps65185_gpio: tps65185-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + tp { + tp_gpio: tp-gpio { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sensor { + kxtj3_irq_gpio: kxtj3-irq-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm4 { + status = "disabled"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&saradc { + status = "disabled"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + keep-power-in-suspend; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <50000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566-rk817-tablet-k108.dts b/rk3566-rk817-tablet-k108.dts new file mode 100644 index 0000000..179641a --- /dev/null +++ b/rk3566-rk817-tablet-k108.dts @@ -0,0 +1,1308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 RK817 TABLET K108 LP4X Board"; + compatible = "rockchip,rk3566-rk817-tablet-k108", "rockchip,rk3566"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + flash_rgb13h: flash-rgb13h { + status = "okay"; + compatible = "led,rgb13h"; + label = "gpio-flash"; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_gpios>; + led-max-microamp = <20000>; + flash-max-microamp = <20000>; + flash-max-timeout-us = <1000000>; + enable-gpio = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + irq-gpio = <&gpio3 RK_PA6 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rst>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk817-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8723cs"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,vbat_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy1_usq { + rockchip,dis-u3otg1-port; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc2385_out>; + data-lanes = <1>; + }; + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1000>; + panel@0 { + compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; + reg = <0>; + + backlight = <&backlight>; + power-supply=<&vcc_3v3>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + stbyb-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>, <&lcd_stanby_gpio>; + + prepare-delay-ms = <120>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + stbyb-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + + width-mm = <229>; + height-mm = <143>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 29 00 04 FF 98 81 03 + 23 00 02 01 00 + 23 00 02 02 00 + 23 00 02 03 73 + 23 00 02 04 00 + 23 00 02 05 00 + 23 00 02 06 08 + 23 00 02 07 00 + 23 00 02 08 00 + 23 00 02 09 00 + 23 00 02 0A 01 + 23 00 02 0B 01 + 23 00 02 0C 00 + 23 00 02 0D 01 + 23 00 02 0E 01 + 23 00 02 0F 00 + 23 00 02 10 00 + 23 00 02 11 00 + 23 00 02 12 00 + 23 00 02 13 1F + 23 00 02 14 1F + 23 00 02 15 00 + 23 00 02 16 00 + 23 00 02 17 00 + 23 00 02 18 00 + 23 00 02 19 00 + 23 00 02 1A 00 + 23 00 02 1B 00 + 23 00 02 1C 00 + 23 00 02 1D 00 + 23 00 02 1E 40 + 23 00 02 1F C0 + 23 00 02 20 06 + 23 00 02 21 01 + 23 00 02 22 06 + 23 00 02 23 01 + 23 00 02 24 88 + 23 00 02 25 88 + 23 00 02 26 00 + 23 00 02 27 00 + 23 00 02 28 3B + 23 00 02 29 03 + 23 00 02 2A 00 + 23 00 02 2B 00 + 23 00 02 2C 00 + 23 00 02 2D 00 + 23 00 02 2E 00 + 23 00 02 2F 00 + 23 00 02 30 00 + 23 00 02 31 00 + 23 00 02 32 00 + 23 00 02 33 00 + 23 00 02 34 00 + 23 00 02 35 00 + 23 00 02 36 00 + 23 00 02 37 00 + 23 00 02 38 00 + 23 00 02 39 00 + 23 00 02 3A 00 + 23 00 02 3B 00 + 23 00 02 3C 00 + 23 00 02 3D 00 + 23 00 02 3E 00 + 23 00 02 3F 00 + 23 00 02 40 00 + 23 00 02 41 00 + 23 00 02 42 00 + 23 00 02 43 00 + 23 00 02 44 00 + 23 00 02 50 01 + 23 00 02 51 23 + 23 00 02 52 45 + 23 00 02 53 67 + 23 00 02 54 89 + 23 00 02 55 AB + 23 00 02 56 01 + 23 00 02 57 23 + 23 00 02 58 45 + 23 00 02 59 67 + 23 00 02 5A 89 + 23 00 02 5B AB + 23 00 02 5C CD + 23 00 02 5D EF + 23 00 02 5E 00 + 23 00 02 5F 01 + 23 00 02 60 01 + 23 00 02 61 06 + 23 00 02 62 06 + 23 00 02 63 07 + 23 00 02 64 07 + 23 00 02 65 00 + 23 00 02 66 00 + 23 00 02 67 02 + 23 00 02 68 02 + 23 00 02 69 05 + 23 00 02 6A 05 + 23 00 02 6B 02 + 23 00 02 6C 0D + 23 00 02 6D 0D + 23 00 02 6E 0C + 23 00 02 6F 0C + 23 00 02 70 0F + 23 00 02 71 0F + 23 00 02 72 0E + 23 00 02 73 0E + 23 00 02 74 02 + 23 00 02 75 01 + 23 00 02 76 01 + 23 00 02 77 06 + 23 00 02 78 06 + 23 00 02 79 07 + 23 00 02 7A 07 + 23 00 02 7B 00 + 23 00 02 7C 00 + 23 00 02 7D 02 + 23 00 02 7E 02 + 23 00 02 7F 05 + 23 00 02 80 05 + 23 00 02 81 02 + 23 00 02 82 0D + 23 00 02 83 0D + 23 00 02 84 0C + 23 00 02 85 0C + 23 00 02 86 0F + 23 00 02 87 0F + 23 00 02 88 0E + 23 00 02 89 0E + 23 00 02 8A 02 + 29 00 04 FF 98 81 04 + 23 00 02 6C 15 + 23 00 02 6E 2A + 23 00 02 6F 33 + 23 00 02 8D 1B + 23 00 02 87 BA + 23 00 02 3A 24 + 23 00 02 26 76 + 23 00 02 B2 D1 + 29 00 04 FF 98 81 01 + 23 00 02 22 0A + 23 00 02 31 00 + 23 00 02 43 66 + 23 00 02 53 40 + 23 00 02 50 87 + 23 00 02 51 82 + 23 00 02 60 15 + 23 00 02 61 01 + 23 00 02 62 0C + 23 00 02 63 00 + 29 00 04 FF 98 81 00 + 23 00 02 35 00 + + 05 78 01 11 + 05 dc 01 29 + //05 00 01 35 + ]; + + panel-exit-sequence = [ + 05 dc 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + + hsync-len = <1>;//19 + hback-porch = <60>;//40 + hfront-porch = <80>;//123 + + vsync-len = <1>; + vback-porch = <25>; + vfront-porch = <35>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3513 3578 3687 3734 3752 3763 + 3766 3771 3784 3804 3836 3885 3925 + 3962 4005 4063 4114 4169 4227 4303>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3450>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + out-l2spk-r2hp; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + gc2385: gc2385@37 { + compatible = "galaxycore,gc2385"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clk>; + + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + port { + gc2385_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "okay"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + pinctrl-0 = <&cam_clkout0>; + pinctrl-1 = <&cam_sleep>; + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + flash-leds = <&flash_rgb13h>; + lens-focus = <&dw9714>; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <138>; + i2c-scl-falling-time-ns = <4>; + + gt9xx: gt9xx@14 { + compatible = "goodix,gt9xx"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <>9xx_gpio>; + touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + max-x = <1200>; + max-y = <1920>; + tp-size = <9110>; + tp-supply = <&vcc_3v3>; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <144>; + i2c-scl-falling-time-ns = <4>; + + sensor@4c { + compatible = "gs_mc3230"; + reg = <0x4c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <9>; + reprobe_en = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_gpio>; + irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + cam { + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + cam_sleep: cam-sleep { + rockchip,pins = + /* cam_sleep */ + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camera_rst: camera-rst { + rockchip,pins = + /* front camera reset */ + <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + /* back camra reset */ + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + flash_led_gpios: flash-led { + rockchip,pins = + /* flash led enable */ + <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + gt9xx { + gt9xx_gpio: gt9xx-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_enable_gpio: lcd-enable-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_stanby_gpio: lcd-stanby-gpio { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sensor { + sensor_gpio: sensor-gpio { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_det_gpio: sdmmc0-det-gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc3v3_pmu>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm4 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det_gpio>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&usbhost_dwc3 { + phys = <&u2phy0_host>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566-rk817-tablet-rkg11.dts b/rk3566-rk817-tablet-rkg11.dts new file mode 100644 index 0000000..c414eec --- /dev/null +++ b/rk3566-rk817-tablet-rkg11.dts @@ -0,0 +1,1181 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 RK817 TABLET RKG11 LP4 Board"; + compatible = "rockchip,rk3566-rk817-tablet-rkg11", "rockchip,rk3566"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + es7210_sound: es7210-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es7210"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&es7210>; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk817-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk817_codec>; + }; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>, + <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "rtl8821cs"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,vbat_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + vibrator { + compatible = "rk-vibrator-gpio"; + vibrator-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc5035_out>; + data-lanes = <1 2>; + }; + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi0 { + status = "okay"; + rockchip,dual-channel = <&dsi1>; + panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + //vsp-supply = <&outp>; + //vsn-supply = <&outn>; + //enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>, <&lcd_panel_vsp>, <&lcd_panel_vsn>; + + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + enable-delay-ms = <60>; + disable-delay-ms = <60>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <8>; + panel-init-sequence = [ + 05 20 01 11 + 05 96 01 29 + ]; + + panel-exit-sequence = [ + 05 05 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <255000000>; + hactive = <1600>; + vactive = <2176>; + hsync-len = <14>; //20, 50 + hback-porch = <25>; //50, 56 + hfront-porch = <25>;//50, 30 + vsync-len = <8>; + vback-porch = <73>; + vfront-porch = <250>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3510 3679 3691 3714 3738 3759 3776 + 3795 3811 3834 3852 3881 3942 3976 + 4012 4075 4114 4177 4232 4277 4351>; + design_capacity = <7916>; + design_qmax = <8708>; + bat_res = <110>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3450>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S3_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3m1_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + use-ext-amplifier; + //out-l2spk-r2hp; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + dio5632@3e { + compatible = "DIO5632"; + reg = <0x3e>; + status = "disabled"; + + outp: outp@3e { + regulator-name = "LCD_VSP"; + vin-supply = <&vccsys>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + }; + + outn: outn@3e { + regulator-name = "LCD_VSN"; + vin-supply = <&vccsys>; + enable-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + }; + }; + + es7210: es7210@43 { + #sound-dai-cells = <0>; + compatible = "ES7210_MicArray_0"; + reg = <0x43>; + clocks = <&cru I2S1_MCLKOUT_RX>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT_RX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_RX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + + gc5035: gc5035@37 { + compatible = "galaxycore,gc5035"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + + //reset pin control by hardware,used this pin switch to mipi input + //0->FRONT camera, 1->REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "XHG-RKX11F-V5"; + rockchip,camera-module-lens-name = "HR232H65"; + port { + gc5035_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "okay"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + pinctrl-0 = <&cam_clkout0>; + pinctrl-1 = <&cam_sleep>; + //reset pin control by hardware,used this pin switch to mipi input + //0->FRONT camera, 1->REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "XHG-RKX11B-V10"; + rockchip,camera-module-lens-name = "default"; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + power-supply = <&vcc3v3_lcd0_n>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + focaltech,irq-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + focaltech,have-key = <0>; + focaltech,key-number = <3>; + focaltech,keys = <256 1068 64 64 128 1068 64 64 192 1068 64 64>; + focaltech,key-x-coord = <1600>; + focaltech,key-y-coord = <2176>; + focaltech,max-touch-number = <5>; + }; +}; + +&i2c5 { + status = "okay"; + + sensor@18 { + compatible = "gs_sc7a20"; + reg = <0x18>; + type = ; + irq_enable = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_gpio>; + irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_LEVEL_LOW>; + poll_delay_ms = <10>; + layout = <7>; + status = "disabled"; + }; + + ls_em3071x@24 { + compatible = "ls_em3071x"; + reg = <0x24>; + type = ; + irq_enable = <0>; + poll_delay_ms = <100>; + status = "okay"; + }; + + ps_em3071x@24 { + compatible = "ps_em3071x"; + reg = <0x24>; + type = ; + pinctrl-names = "default"; + pinctrl-0 = <&em3071x_irq_gpio>; + irq-gpio = <&gpio3 RK_PA6 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <1>; + ps_threshold_high = <25>; + ps_threshold_low = <15>; + poll_delay_ms = <100>; + status = "okay"; + }; + + icm20607_acc@68 { + compatible = "icm2060x_acc"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <1>; + status = "okay"; + }; + + icm20607_gyro@68 { + compatible = "icm2060x_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <1>; + status = "okay"; + }; + + ak09918_compass: ak09918_compass@c { + compatible = "ak09918"; + reg = <0x0c>; + type = ; + irq_enable = <0>; + poll_delay_ms = <30>; + layout = <1>; + status = "okay"; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclkrx + &i2s1m0_lrckrx + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3>; +}; + +&i2s3_2ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3m1_sclk + &i2s3m1_lrck + &i2s3m1_sdi + &i2s3m1_sdo>; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + cam { + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + cam_sleep: cam-sleep { + rockchip,pins = + /* cam_sleep */ + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camera_rst: camera-rst { + rockchip,pins = + /* front camera reset */ + <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + /* back camra reset */ + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + flash_led_gpios: flash-led { + rockchip,pins = + /* flash led enable */ + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_gpio: tp-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_enable_gpio: lcd-enable-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_panel_vsp: lcd-panel-vsp { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + lcd_panel_vsn: lcd-panel-vsn { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sensor { + sensor_gpio:sensor-gpio { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + em3071x_irq_gpio: em3071x-irq-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mh248_irq_gpio: mh248-irq-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vccio_acodec>; +}; + +&pwm4 { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_gpu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "disabled"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566-rk817-tablet-v10.dts b/rk3566-rk817-tablet-v10.dts new file mode 100644 index 0000000..9cdae50 --- /dev/null +++ b/rk3566-rk817-tablet-v10.dts @@ -0,0 +1,1208 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 RK817 TABLET LP4X Board"; + compatible = "rockchip,rk3566-rk817-tablet", "rockchip,rk3566"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 50 51 52 53 54 + 55 55 56 57 58 59 60 61 + 62 63 64 64 65 65 66 67 + 68 69 70 71 71 72 73 74 + 75 76 77 78 79 79 80 81 + 82 83 84 85 86 86 87 88 + 89 90 91 92 93 94 94 95 + 96 97 98 99 100 101 101 102 + 103 104 105 106 107 107 108 109 + 110 111 112 113 114 115 115 116 + 117 118 119 120 121 122 123 123 + 124 125 126 127 128 129 130 130 + 131 132 133 134 135 136 136 137 + 138 139 140 141 142 143 143 144 + 145 146 147 147 148 149 150 151 + 152 153 154 155 156 156 157 158 + 159 157 158 159 160 161 162 162 + 163 164 165 166 167 168 169 169 + 170 171 172 173 174 175 175 176 + 177 178 179 180 181 182 182 183 + 184 185 186 187 188 189 190 190 + 191 192 193 194 195 196 197 197 + 198 199 200 201 202 203 204 204 + 205 206 207 208 209 209 210 211 + 212 213 213 214 214 215 215 216 + 216 217 217 218 218 219 219 220 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + flash_rgb13h: flash-rgb13h { + status = "okay"; + compatible = "led,rgb13h"; + label = "gpio-flash"; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_gpios>; + led-max-microamp = <20000>; + flash-max-microamp = <20000>; + flash-max-timeout-us = <1000000>; + enable-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rst>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 2>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc2385_out>; + data-lanes = <1>; + }; + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1000>; + panel@0 { + compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; + reg = <0>; + + backlight = <&backlight>; + //power-supply=<&vcc_3v3>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + stbyb-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>, <&lcd_stanby_gpio>; + + prepare-delay-ms = <120>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + stbyb-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + + width-mm = <229>; + height-mm = <143>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 23 00 02 B0 01 + 23 00 02 C3 0F + 23 00 02 C4 00 + 23 00 02 C5 00 + 23 00 02 C6 00 + 23 00 02 C7 00 + 23 00 02 C8 0D + 23 00 02 C9 12 + 23 00 02 CA 11 + 23 00 02 CD 1D + 23 00 02 CE 1B + 23 00 02 CF 0B + 23 00 02 D0 09 + 23 00 02 D1 07 + 23 00 02 D2 05 + 23 00 02 D3 01 + 23 00 02 D7 10 + 23 00 02 D8 00 + 23 00 02 D9 00 + 23 00 02 DA 00 + 23 00 02 DB 00 + 23 00 02 DC 0E + 23 00 02 DD 12 + 23 00 02 DE 11 + 23 00 02 E1 1E + 23 00 02 E2 1C + 23 00 02 E3 0C + 23 00 02 E4 0A + 23 00 02 E5 08 + 23 00 02 E6 06 + 23 00 02 E7 02 + 23 00 02 B0 03 + 23 00 02 BE 03 + 23 00 02 CC 44 + 23 00 02 C8 07 + 23 00 02 C9 05 + 23 00 02 CA 42 + 23 00 02 CD 3E + 23 00 02 CF 60 + 23 00 02 D2 04 + 23 00 02 D3 04 + 23 00 02 D4 01 + 23 00 02 D5 00 + 23 00 02 D6 03 + 23 00 02 D7 04 + 23 00 02 D9 01 + 23 00 02 DB 01 + 23 00 02 E4 F0 + 23 00 02 E5 0A + 23 00 02 B0 00 + 23 00 02 BA 8F// NEW ADD + 23 00 02 BD 63 + 23 00 02 C2 08 + 23 00 02 C4 10 + 23 00 02 B0 02 + 23 00 02 C0 00 + 23 00 02 C1 0A + 23 00 02 C2 20 + 23 00 02 C3 24 + 23 00 02 C4 23 + 23 00 02 C5 29 + 23 00 02 C6 23 + 23 00 02 C7 1C + 23 00 02 C8 19 + 23 00 02 C9 17 + 23 00 02 CA 17 + 23 00 02 CB 18 + 23 00 02 CC 1A + 23 00 02 CD 1E + 23 00 02 CE 20 + 23 00 02 CF 23 + 23 00 02 D0 07 + 23 00 02 D1 00 + 23 00 02 D2 00 + 23 00 02 D3 0A + 23 00 02 D4 13 + 23 00 02 D5 1C + 23 00 02 D6 1A + 23 00 02 D7 13 + 23 00 02 D8 17 + 23 00 02 D9 1C + 23 00 02 DA 19 + 23 00 02 DB 17 + 23 00 02 DC 17 + 23 00 02 DD 18 + 23 00 02 DE 1A + 23 00 02 DF 1E + 23 00 02 E0 20 + 23 00 02 E1 23 + 23 00 02 E2 07 + + 05 78 01 11 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 dc 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + + hsync-len = <1>;//19 + hback-porch = <60>;//40 + hfront-porch = <80>;//123 + + vsync-len = <1>; + vback-porch = <25>; + vfront-porch = <35>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <4700000>; + regulator-max-microvolt = <5400000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3513 3578 3687 3734 3752 3763 + 3766 3771 3784 3804 3836 3885 3925 + 3962 4005 4063 4114 4169 4227 4303>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3350>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + gate_function_disable = <1>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + out-l2spk-r2hp; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + gc2385: gc2385@37 { + compatible = "galaxycore,gc2385"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clk>; + + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + port { + gc2385_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "okay"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + pinctrl-0 = <&cam_clkout0>; + pinctrl-1 = <&cam_sleep>; + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + flash-leds = <&flash_rgb13h>; + lens-focus = <&dw9714>; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <138>; + i2c-scl-falling-time-ns = <4>; + + ts@40 { + compatible = "gslX680-pad"; + reg = <0x40>; + touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PB1 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + screen_max_x = <1200>; + screen_max_y = <1920>; + revert_x = <0>; + revert_y = <1>; + revert_xy = <0>; + chip_id = <1>; + status = "okay"; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <144>; + i2c-scl-falling-time-ns = <4>; + + sensor@18 { + compatible = "gs_sc7a20"; + reg = <0x18>; + type = ; + irq_enable = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_gpio>; + irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_RISING>; + poll_delay_ms = <10>; + layout = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + cam { + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + cam_sleep: cam-sleep { + rockchip,pins = + /* cam_sleep */ + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camera_rst: camera-rst { + rockchip,pins = + /* front camera reset */ + <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + /* back camra reset */ + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + flash_led_gpios: flash-led { + rockchip,pins = + /* flash led enable */ + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_gpio: tp-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_enable_gpio: lcd-enable-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_stanby_gpio: lcd-stanby-gpio { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sensor { + sensor_gpio: sensor-gpio { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc1v8_dvp>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm4 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566-rk817-tablet.dts b/rk3566-rk817-tablet.dts new file mode 100644 index 0000000..58bf46b --- /dev/null +++ b/rk3566-rk817-tablet.dts @@ -0,0 +1,1221 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3566.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3566 RK817 TABLET LP4X Board"; + compatible = "rockchip,rk3566-rk817-tablet", "rockchip,rk3566"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 50 51 52 53 54 + 55 55 56 57 58 59 60 61 + 62 63 64 64 65 65 66 67 + 68 69 70 71 71 72 73 74 + 75 76 77 78 79 79 80 81 + 82 83 84 85 86 86 87 88 + 89 90 91 92 93 94 94 95 + 96 97 98 99 100 101 101 102 + 103 104 105 106 107 107 108 109 + 110 111 112 113 114 115 115 116 + 117 118 119 120 121 122 123 123 + 124 125 126 127 128 129 130 130 + 131 132 133 134 135 136 136 137 + 138 139 140 141 142 143 143 144 + 145 146 147 147 148 149 150 151 + 152 153 154 155 156 156 157 158 + 159 157 158 159 160 161 162 162 + 163 164 165 166 167 168 169 169 + 170 171 172 173 174 175 175 176 + 177 178 179 180 181 182 182 183 + 184 185 186 187 188 189 190 190 + 191 192 193 194 195 196 197 197 + 198 199 200 201 202 203 204 204 + 205 206 207 208 209 209 210 211 + 212 213 213 214 214 215 215 216 + 216 217 217 218 218 219 219 220 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + flash_rgb13h: flash-rgb13h { + status = "okay"; + compatible = "led,rgb13h"; + label = "gpio-flash"; + pinctrl-names = "default"; + pinctrl-0 = <&flash_led_gpios>; + led-max-microamp = <20000>; + flash-max-microamp = <20000>; + flash-max-timeout-us = <1000000>; + enable-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + vccsys: vccsys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v8_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_rst>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + rk817-sound { + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk817"; + hp-det-gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 2>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk817_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + }; + + vcc_sd: vcc-sd { + compatible = "regulator-gpio"; + enable-active-low; + enable-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_sd_h>; + regulator-name = "vcc_sd"; + states = <3300000 0x0 + 3300000 0x1>; + }; + + wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk817 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&gc2385_out>; + data-lanes = <1>; + }; + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov8858_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1000>; + panel@0 { + compatible = "aoly,sl008pa21y1285-b00", "simple-panel-dsi"; + reg = <0>; + + backlight = <&backlight>; + //power-supply=<&vcc_3v3>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_gpio>, <&lcd_rst_gpio>; + + prepare-delay-ms = <120>; + reset-delay-ms = <120>; + init-delay-ms = <120>; + stbyb-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + + width-mm = <229>; + height-mm = <143>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 23 00 02 B0 01 + 23 00 02 C3 0F + 23 00 02 C4 00 + 23 00 02 C5 00 + 23 00 02 C6 00 + 23 00 02 C7 00 + 23 00 02 C8 0D + 23 00 02 C9 12 + 23 00 02 CA 11 + 23 00 02 CD 1D + 23 00 02 CE 1B + 23 00 02 CF 0B + 23 00 02 D0 09 + 23 00 02 D1 07 + 23 00 02 D2 05 + 23 00 02 D3 01 + 23 00 02 D7 10 + 23 00 02 D8 00 + 23 00 02 D9 00 + 23 00 02 DA 00 + 23 00 02 DB 00 + 23 00 02 DC 0E + 23 00 02 DD 12 + 23 00 02 DE 11 + 23 00 02 E1 1E + 23 00 02 E2 1C + 23 00 02 E3 0C + 23 00 02 E4 0A + 23 00 02 E5 08 + 23 00 02 E6 06 + 23 00 02 E7 02 + 23 00 02 B0 03 + 23 00 02 BE 03 + 23 00 02 CC 44 + 23 00 02 C8 07 + 23 00 02 C9 05 + 23 00 02 CA 42 + 23 00 02 CD 3E + 23 00 02 CF 60 + 23 00 02 D2 04 + 23 00 02 D3 04 + 23 00 02 D4 01 + 23 00 02 D5 00 + 23 00 02 D6 03 + 23 00 02 D7 04 + 23 00 02 D9 01 + 23 00 02 DB 01 + 23 00 02 E4 F0 + 23 00 02 E5 0A + 23 00 02 B0 00 + 23 00 02 BA 8F// NEW ADD + 23 00 02 BD 63 + 23 00 02 C2 08 + 23 00 02 C4 10 + 23 00 02 B0 02 + 23 00 02 C0 00 + 23 00 02 C1 0A + 23 00 02 C2 20 + 23 00 02 C3 24 + 23 00 02 C4 23 + 23 00 02 C5 29 + 23 00 02 C6 23 + 23 00 02 C7 1C + 23 00 02 C8 19 + 23 00 02 C9 17 + 23 00 02 CA 17 + 23 00 02 CB 18 + 23 00 02 CC 1A + 23 00 02 CD 1E + 23 00 02 CE 20 + 23 00 02 CF 23 + 23 00 02 D0 07 + 23 00 02 D1 00 + 23 00 02 D2 00 + 23 00 02 D3 0A + 23 00 02 D4 13 + 23 00 02 D5 1C + 23 00 02 D6 1A + 23 00 02 D7 13 + 23 00 02 D8 17 + 23 00 02 D9 1C + 23 00 02 DA 19 + 23 00 02 DB 17 + 23 00 02 DC 17 + 23 00 02 DD 18 + 23 00 02 DE 1A + 23 00 02 DF 1E + 23 00 02 E0 20 + 23 00 02 E1 23 + 23 00 02 E2 07 + + 05 78 01 11 + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 dc 01 28 + 05 78 01 10 + ]; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <160000000>; + hactive = <1200>; + vactive = <1920>; + + hsync-len = <1>;//19 + hback-porch = <60>;//40 + hfront-porch = <80>;//123 + + vsync-len = <1>; + vback-porch = <25>; + vfront-porch = <35>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vccsys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk817: pmic@20 { + compatible = "rockchip,rk817"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vccsys>; + vcc2-supply = <&vccsys>; + vcc3-supply = <&vccsys>; + vcc4-supply = <&vccsys>; + vcc5-supply = <&vccsys>; + vcc6-supply = <&vccsys>; + vcc7-supply = <&vccsys>; + vcc8-supply = <&vccsys>; + vcc9-supply = <&dcdc_boost>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca1v8_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3000000>; + }; + }; + + vcc_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_dvp: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc1v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc2v8_dvp: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "vcc2v8_dvp"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + dcdc_boost: BOOST { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "boost"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + otg_switch: OTG_SWITCH { + regulator-name = "otg_switch"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + battery { + compatible = "rk817,battery"; + ocv_table = <3400 3513 3578 3687 3734 3752 3763 + 3766 3771 3784 3804 3836 3885 3925 + 3962 4005 4063 4114 4169 4227 4303>; + design_capacity = <5000>; + design_qmax = <5500>; + bat_res = <100>; + sleep_enter_current = <150>; + sleep_exit_current = <180>; + sleep_filter_current = <100>; + power_off_thresd = <3350>; + zero_algorithm_vol = <3850>; + max_soc_offset = <60>; + monitor_sec = <5>; + sample_res = <10>; + virtual_power = <0>; + }; + + charger { + compatible = "rk817,charger"; + min_input_voltage = <4500>; + max_input_current = <1500>; + max_chrg_current = <2000>; + max_chrg_voltage = <4300>; + chrg_term_mode = <0>; + chrg_finish_cur = <300>; + virtual_power = <0>; + dc_det_adc = <0>; + extcon = <&usb2phy0>; + }; + + rk817_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + out-l2spk-r2hp; + spk-ctl-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + + dw9714: dw9714@c { + compatible = "dongwoon,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,vcm-start-current = <10>; + rockchip,vcm-rated-current = <85>; + rockchip,vcm-step-mode = <5>; + rockchip,camera-module-facing = "back"; + }; + + gc2385: gc2385@37 { + compatible = "galaxycore,gc2385"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default"; + pinctrl-0 = <&cif_clk>; + + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + port { + gc2385_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1>; + }; + }; + }; + + ov8858: ov8858@36 { + status = "okay"; + compatible = "ovti,ov8858"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; + pinctrl-0 = <&cam_clkout0>; + pinctrl-1 = <&cam_sleep>; + //reset pin control by hardware,used this pin switch to mipi input + //1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HS5885-BNSM1018-V01"; + rockchip,camera-module-lens-name = "default"; + flash-leds = <&flash_rgb13h>; + lens-focus = <&dw9714>; + port { + ov8858_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <138>; + i2c-scl-falling-time-ns = <4>; + + ts@40 { + compatible = "gslX680-pad"; + reg = <0x40>; + touch-gpio = <&gpio3 RK_PB0 IRQ_TYPE_LEVEL_HIGH>; + reset-gpio = <&gpio3 RK_PB1 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_gpio>; + screen_max_x = <1200>; + screen_max_y = <1920>; + revert_x = <0>; + revert_y = <1>; + revert_xy = <0>; + chip_id = <1>; + status = "okay"; + }; +}; + +&i2c5 { + status = "okay"; + clock-frequency = <400000>; + i2c-scl-rising-time-ns = <144>; + i2c-scl-falling-time-ns = <4>; + + sensor@18 { + compatible = "gs_sc7a20"; + reg = <0x18>; + type = ; + irq_enable = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&sensor_gpio>; + irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_RISING>; + poll_delay_ms = <10>; + layout = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + status = "okay"; +}; + +&pinctrl { + cam { + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + cam_sleep: cam-sleep { + rockchip,pins = + /* cam_sleep */ + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + camera_rst: camera-rst { + rockchip,pins = + /* front camera reset */ + <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, + /* back camra reset */ + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + flash_led_gpios: flash-led { + rockchip,pins = + /* flash led enable */ + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + tp { + tp_gpio: tp-gpio { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lcd_enable_gpio: lcd-enable-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sensor { + sensor_gpio: sensor-gpio { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc_sd { + vcc_sd_h: vcc-sd-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm4 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + rockchip,default-sample-phase = <90>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3566.dtsi b/rk3566.dtsi new file mode 100644 index 0000000..266b5cb --- /dev/null +++ b/rk3566.dtsi @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3568.dtsi" + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ lvds1; + }; +}; + +&cpu0_opp_table { + /delete-node/ opp-1992000000; +}; + +&lpddr4_params { + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; +}; + +&lpddr4x_params { + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; +}; + +&power { + pd_pipe@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_sata1>, + <&qos_sata2>, + <&qos_usb3_0>, + <&qos_usb3_1>; + }; +}; + +&rkisp { + rockchip,iq-feature = /bits/ 64 <0x1BFBF7FE67FF>; +}; + +&usbdrd_dwc3 { + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + snps,usb2-lpm-disable; +}; + +/delete-node/ &combphy0_us; +/delete-node/ &gmac0_clkin; +/delete-node/ &gmac0_xpcsclk; +/delete-node/ &gmac0; +/delete-node/ &gmac_uio0; +/delete-node/ &lvds1; +/delete-node/ &pcie30_phy_grf; +/delete-node/ &pcie30phy; +/delete-node/ &pcie3x1; +/delete-node/ &pcie3x2; +/delete-node/ &qos_pcie3x1; +/delete-node/ &qos_pcie3x2; +/delete-node/ &qos_sata0; +/delete-node/ &sata0; +/delete-node/ &vp1_out_lvds1; +/delete-node/ &vp2_out_lvds1; diff --git a/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts b/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts new file mode 100644 index 0000000..e6972db --- /dev/null +++ b/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include + +#include "rk3567-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3567 EVB2 LP4X V10 Board"; + compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567"; + + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <96>; + hfront-porch = <120>; + vback-porch = <16>; + vfront-porch = <64>; + hsync-len = <64>; + vsync-len = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-even-pixels; + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + dual-channel; + + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + lvds1_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&lvds1_in_vp1 { + status = "okay"; +}; + +&lvds1_in_vp2 { + status = "disabled"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dts b/rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dts new file mode 100644 index 0000000..30f9109 --- /dev/null +++ b/rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds.dts @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include + +#include "rk3567-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3567 EVB2 LP4X V10 Board with one vp two single channel lvds"; + compatible = "rockchip,rk3567-evb2-lp4x-v10-one-vp-two-single-channel-lvds", "rockchip,rk3567"; + + /* panel: claa070wp03xg */ + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <134000000>; + hactive = <1600>; /* each panel show 1600 / 2 = 800 pxiel */ + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /** + * Panel <----> LVDS0 + * Panel <----> LVDS1 + */ + port@0 { + reg = <0>; + dual-lvds-left-pixels; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-right-pixels; + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + dual-channel; + + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + lvds1_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1_in_vp1 { + status = "okay"; +}; + +&lvds1_in_vp2 { + status = "disabled"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3567-evb2-lp4x-v10-single-channel-lvds.dts b/rk3567-evb2-lp4x-v10-single-channel-lvds.dts new file mode 100644 index 0000000..85621d5 --- /dev/null +++ b/rk3567-evb2-lp4x-v10-single-channel-lvds.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include + +#include "rk3567-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3567 EVB2 LP4X V10 Board with single channel lvds"; + compatible = "rockchip,rk3567-evb2-lp4x-v10-single-channel-lvds", "rockchip,rk3567"; + + /* panel: claa070wp03xg */ + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <67000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "disabled"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dts b/rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dts new file mode 100644 index 0000000..9f3e37e --- /dev/null +++ b/rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds.dts @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include + +#include "rk3567-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3567 EVB2 LP4X V10 Board with two vp two separate single channel lvds"; + compatible = "rockchip,rk3567-evb2-lp4x-v10-two-vp-two-separate-single-channel-lvds", "rockchip,rk3567"; + + /** + * VP1 -> LVDS0 -> Panel0 + * VP2 -> LVDS1 -> Panel1 + */ + + /* panel: claa070wp03xg */ + panel-lvds0 { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <67000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + }; + }; + + /* panel: claa070wp03xg */ + panel-lvds1 { + compatible = "simple-panel"; + backlight = <&backlight1>; + power-supply = <&vcc3v3_lcd1_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing1>; + timing1: timing1 { + clock-frequency = <67000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds1_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&lvds1_in_vp1 { + status = "disabled"; +}; + +&lvds1_in_vp2 { + status = "okay"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3567-evb2-lp4x-v10.dts b/rk3567-evb2-lp4x-v10.dts new file mode 100644 index 0000000..96e3397 --- /dev/null +++ b/rk3567-evb2-lp4x-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3567-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3567-evb2-lp4x-v10.dtsi b/rk3567-evb2-lp4x-v10.dtsi new file mode 100644 index 0000000..1dadc17 --- /dev/null +++ b/rk3567-evb2-lp4x-v10.dtsi @@ -0,0 +1,648 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3567.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3567 EVB2 LP4X V10 Board"; + compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567"; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu_rk860>; +}; + +&bus_npu { + pvtm-supply = <&vdd_cpu_rk860>; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + /* + * dphy0 only used for full mode, + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&gc5025_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in_dphy0>; + }; + }; + }; +}; + +&csi2_dphy1 { + status = "disabled"; + + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_in: endpoint@1 { + reg = <1>; + //remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "disabled"; + + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_in: endpoint@1 { + reg = <1>; + //remote-endpoint = <&gc5025_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd0_rst_gpio>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd1_rst_gpio>; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x25>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&i2c0 { + vdd_cpu_rk860: rk8600@40{ + compatible = "rockchip,rk8600"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m1_xfer>; + + /* split mode: lane0/1 */ + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; + + /* split mode: lane:2/3 */ + gc5025: gc5025@37 { + status = "okay"; + compatible = "galaxycore,gc5025"; + reg = <0x37>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + power-domains = <&power RK3568_PD_VI>; + /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + gc5025_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + + /* full mode: lane0-3 */ + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&dphy0_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c4 { + /* i2c4 sda conflict with camera pwdn */ + status = "disabled"; + + /* + * gc2145 needs to be disabled, + * when gmac1 is enabled; + * pinctrl conflicts; + */ + gc2145: gc2145@3c { + status = "disabled"; + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + /* conflict with gmac1m1_rgmii_pins & cif_clk*/ + pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; + + /*avdd-supply = <&vcc2v8_dvp>;*/ + /*dovdd-supply = <&vcc1v8_dvp>;*/ + /*dvdd-supply = <&vcc1v8_dvp>;*/ + + /*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/ + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CameraKing"; + rockchip,camera-module-lens-name = "Largan"; + port { + gc2145_out: endpoint { + remote-endpoint = <&dvp_in_bcam>; + }; + }; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&mdio1 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + + + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy2_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd0 { + lcd0_rst_gpio: lcd0-rst-gpio { + rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd1 { + lcd1_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_dvp { + status = "disabled"; + + port { + /* Parallel bus endpoint */ + dvp_in_bcam: endpoint { + remote-endpoint = <&gc2145_out>; + bus-width = <8>; + vsync-active = <0>; + hsync-active = <1>; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy1_out>; + }; + isp0_in_dphy0: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy0_out>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdio_pwrseq { + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&spdif_8ch { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&work_led { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk3567.dtsi b/rk3567.dtsi new file mode 100644 index 0000000..60ef55b --- /dev/null +++ b/rk3567.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include "rk3568.dtsi" + +&power { + pd_pipe@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_usb3_0>, + <&qos_usb3_1>; + }; +}; + +/delete-node/ &can0; +/delete-node/ &can1; +/delete-node/ &can2; +/delete-node/ &pcie30_phy_grf; +/delete-node/ &pcie30phy; +/delete-node/ &pcie3x1; +/delete-node/ &pcie3x2; +/delete-node/ &qos_pcie3x1; +/delete-node/ &qos_pcie3x2; +/delete-node/ &qos_sata0; +/delete-node/ &qos_sata1; +/delete-node/ &qos_sata2; +/delete-node/ &sata0; +/delete-node/ &sata1; +/delete-node/ &sata2; diff --git a/rk3568-amp.dtsi b/rk3568-amp.dtsi new file mode 100644 index 0000000..8de181d --- /dev/null +++ b/rk3568-amp.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/ { + rockchip_amp: rockchip-amp { + compatible = "rockchip,rk3568-amp"; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>, + <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>, + <&cru ACLK_MCU>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; + status = "okay"; + + amp_cpus: amp-cpus { + amp-cpu3 { + id = <0x0 0x300>; + entry = <0x0 0x2800000>; + boot-on = <0>; + mode = <0>; + }; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* remote amp core address */ + amp_shmem_reserved: amp-shmem@7800000 { + reg = <0x0 0x7800000 0x0 0x400000>; + no-map; + }; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x7c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x8000000 0x0 0x100000>; + no-map; + }; + + /* mcu address */ + mcu_reserved: mcu@8200000 { + reg = <0x0 0x8200000 0x0 0x100000>; + no-map; + }; + }; + + rpmsg: rpmsg@7c00000 { + compatible = "rockchip,rpmsg"; + mbox-names = "rpmsg-rx", "rpmsg-tx"; + mboxes = <&mailbox 0 &mailbox 3>; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; +}; + +&mailbox { + rockchip,txpoll-period-ms = <1>; + status = "okay"; +}; + diff --git a/rk3568-android.dtsi b/rk3568-android.dtsi new file mode 100644 index 0000000..87c4ba3 --- /dev/null +++ b/rk3568-android.dtsi @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0"; + }; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdmmc1; + mmc2 = &sdhci; + mmc3 = &sdmmc2; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; + + vendor_storage: vendor-storage { + compatible = "rockchip,ram-vendor-storage"; + memory-region = <&vendor_storage_rm>; + status = "okay"; + }; +}; + +&reserved_memory { + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 0x10000000 0x0 0x00800000>; + linux,cma-default; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; + + vendor_storage_rm: vendor-storage-rm@00000000 { + compatible = "rockchip,vendor-storage-rm"; + reg = <0x0 0x0 0x0 0x0>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&vop { + support-multi-area; +}; diff --git a/rk3568-dram-default-timing.dtsi b/rk3568-dram-default-timing.dtsi new file mode 100644 index 0000000..99247fb --- /dev/null +++ b/rk3568-dram-default-timing.dtsi @@ -0,0 +1,400 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/ { + ddr3_params: ddr3-params { + /* version information */ + version = <0x100>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; + freq_1 = <324>; + freq_2 = <528>; + freq_3 = <780>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = <300>; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <33>; + phy_ca_drv_odten = <33>; + phy_clk_drv_odten = <33>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <33>; + phy_ca_drv_odtoff = <33>; + phy_clk_drv_odtoff = <33>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <120>; + phy_odt = <167>; + phy_odt_puup_en = <1>; + phy_odt_pudn_en = <1>; + /* odt enable freq */ + dram_dq_odt_en_freq = <333>; + phy_odt_en_freq = <333>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0xf>; + phy_ca_sr_odten = <0x3>; + phy_clk_sr_odten = <0x0>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0xf>; + phy_ca_sr_odtoff = <0x3>; + phy_clk_sr_odtoff = <0x0>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + }; + + ddr4_params: ddr4-params { + /* version information */ + version = <0x100>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; + freq_1 = <324>; + freq_2 = <528>; + freq_3 = <780>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = <625>; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <37>; + phy_ca_drv_odten = <37>; + phy_clk_drv_odten = <37>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <37>; + phy_ca_drv_odtoff = <37>; + phy_clk_drv_odtoff = <37>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <120>; + phy_odt = <139>; + phy_odt_puup_en = <1>; + phy_odt_pudn_en = <1>; + /* odt enable freq */ + dram_dq_odt_en_freq = <500>; + phy_odt_en_freq = <500>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0xe>; + phy_ca_sr_odten = <0x1>; + phy_clk_sr_odten = <0x1>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0xe>; + phy_ca_sr_odtoff = <0x1>; + phy_clk_sr_odtoff = <0x1>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <(((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 0) | \ + ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 8) | \ + ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 16) | \ + ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 24))>; + dq_map_cs0_dq_h = <(((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 0) | \ + ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 8) | \ + ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 16) | \ + ((3 << 0 | 1 << 2 | 1 << 4 | 3 << 6) << 24))>; + dq_map_cs1_dq_l = <(((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 0) | \ + ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 8) | \ + ((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 16) | \ + ((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 24))>; + dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 0) | \ + ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 8) | \ + ((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 16) | \ + ((3 << 0 | 1 << 2 | 1 << 4 | 3 << 6) << 24))>; + }; + + lpddr3_params: lpddr3-params { + /* version information */ + version = <0x100>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1056>; + freq_1 = <324>; + freq_2 = <528>; + freq_3 = <780>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = ; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <37>; + phy_ca_drv_odten = <37>; + phy_clk_drv_odten = <39>; + dram_dq_drv_odten = <34>; + /* drv when odt off */ + phy_dq_drv_odtoff = <37>; + phy_ca_drv_odtoff = <37>; + phy_clk_drv_odtoff = <39>; + dram_dq_drv_odtoff = <34>; + /* odt info */ + dram_odt = <120>; + phy_odt = <148>; + phy_odt_puup_en = <1>; + phy_odt_pudn_en = <1>; + /* odt enable freq */ + dram_dq_odt_en_freq = <333>; + phy_odt_en_freq = <333>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0xf>; + phy_ca_sr_odten = <0x1>; + phy_clk_sr_odten = <0xf>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0xf>; + phy_ca_sr_odtoff = <0x1>; + phy_clk_sr_odtoff = <0xf>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x2 << 6) | (0x0 << 4) | (0x3 << 2) | (0x1 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + }; + + lpddr4_params: lpddr4-params { + /* version information */ + version = <0x100>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1560>; + freq_1 = <324>; + freq_2 = <528>; + freq_3 = <780>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = ; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <30>; + phy_ca_drv_odten = <38>; + phy_clk_drv_odten = <38>; + dram_dq_drv_odten = <40>; + /* drv when odt off */ + phy_dq_drv_odtoff = <30>; + phy_ca_drv_odtoff = <38>; + phy_clk_drv_odtoff = <38>; + dram_dq_drv_odtoff = <40>; + /* odt info */ + dram_odt = <80>; + phy_odt = <60>; + phy_odt_puup_en = ; + phy_odt_pudn_en = ; + /* odt enable freq */ + dram_dq_odt_en_freq = <800>; + phy_odt_en_freq = <800>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0x0>; + phy_ca_sr_odten = <0xf>; + phy_clk_sr_odten = <0xf>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0x0>; + phy_ca_sr_odtoff = <0xf>; + phy_clk_sr_odtoff = <0xf>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + /* lp4 odt info */ + lp4_ca_odt = <120>; + lp4_drv_pu_cal_odten = ; + lp4_drv_pu_cal_odtoff = ; + phy_lp4_drv_pulldown_en_odten = <0>; + phy_lp4_drv_pulldown_en_odtoff = <0>; + /* lp4 odt enable freq */ + lp4_ca_odt_en_freq = <800>; + /* lp4 cs drv info and ca odt info */ + phy_lp4_cs_drv_odten = <0>; + phy_lp4_cs_drv_odtoff = <0>; + lp4_odte_ck_en = <1>; + lp4_odte_cs_en = <1>; + lp4_odtd_ca_en = <0>; + /* lp4 vref info when odt enable */ + phy_lp4_dq_vref_odten = <166>; + lp4_dq_vref_odten = <300>; + lp4_ca_vref_odten = <380>; + /* lp4 vref info when odt disable */ + phy_lp4_dq_vref_odtoff = <420>; + lp4_dq_vref_odtoff = <420>; + lp4_ca_vref_odtoff = <420>; + }; + + lpddr4x_params: lpddr4x-params { + /* version information */ + version = <0x100>; + expanded_version = ; + reserved = ; + /* freq info, freq_0 is final frequency, unit: MHz */ + freq_0 = <1560>; + freq_1 = <324>; + freq_2 = <528>; + freq_3 = <780>; + freq_4 = ; + freq_5 = ; + /* power save setting */ + pd_idle = <13>; + sr_idle = <93>; + sr_mc_gate_idle = <0>; + srpd_lite_idle = <0>; + standby_idle = <0>; + pd_dis_freq = <1066>; + sr_dis_freq = <800>; + dram_dll_dis_freq = ; + phy_dll_dis_freq = ; + /* drv when odt on */ + phy_dq_drv_odten = <29>; + phy_ca_drv_odten = <36>; + phy_clk_drv_odten = <36>; + dram_dq_drv_odten = <40>; + /* drv when odt off */ + phy_dq_drv_odtoff = <29>; + phy_ca_drv_odtoff = <36>; + phy_clk_drv_odtoff = <36>; + dram_dq_drv_odtoff = <40>; + /* odt info */ + dram_odt = <80>; + phy_odt = <60>; + phy_odt_puup_en = ; + phy_odt_pudn_en = ; + /* odt enable freq */ + dram_dq_odt_en_freq = <800>; + phy_odt_en_freq = <800>; + /* slew rate when odt enable */ + phy_dq_sr_odten = <0x0>; + phy_ca_sr_odten = <0x0>; + phy_clk_sr_odten = <0x0>; + /* slew rate when odt disable */ + phy_dq_sr_odtoff = <0x0>; + phy_ca_sr_odtoff = <0x0>; + phy_clk_sr_odtoff = <0x0>; + /* ssmod setting*/ + ssmod_downspread = <0>; + ssmod_div = <0>; + ssmod_spread = <0>; + /* 2T mode */ + mode_2t = ; + /* speed bin */ + speed_bin = ; + /* dram extended temperature support */ + dram_ext_temp = <0>; + /* byte map */ + byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>; + /* dq map */ + dq_map_cs0_dq_l = <0>; + dq_map_cs0_dq_h = <0>; + dq_map_cs1_dq_l = <0>; + dq_map_cs1_dq_h = <0>; + /* lp4 odt info */ + lp4_ca_odt = <120>; + lp4_drv_pu_cal_odten = ; + lp4_drv_pu_cal_odtoff = ; + phy_lp4_drv_pulldown_en_odten = <0>; + phy_lp4_drv_pulldown_en_odtoff = <0>; + /* odt enable freq */ + lp4_ca_odt_en_freq = <800>; + /* lp4 cs drv info and ca odt info */ + phy_lp4_cs_drv_odten = <0>; + phy_lp4_cs_drv_odtoff = <0>; + lp4_odte_ck_en = <0>; + lp4_odte_cs_en = <0>; + lp4_odtd_ca_en = <0>; + /* lp4 vref info when odt enable */ + phy_lp4_dq_vref_odten = <166>; + lp4_dq_vref_odten = <228>; + lp4_ca_vref_odten = <343>; + /* lp4 vref info when odt disable */ + phy_lp4_dq_vref_odtoff = <420>; + lp4_dq_vref_odtoff = <420>; + lp4_ca_vref_odtoff = <343>; + }; +}; diff --git a/rk3568-evb.dtsi b/rk3568-evb.dtsi new file mode 100644 index 0000000..f13c238 --- /dev/null +++ b/rk3568-evb.dtsi @@ -0,0 +1,1846 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + hp-det-gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + WIFI,poweren_gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight1>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <1>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c1 { + status = "okay"; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c5 { + status = "okay"; + + mxc6655xa: mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&i2s3_2ch { + pinctrl-0 = <&i2s3m0_sclk &i2s3m0_lrck &i2s3m0_sdi &i2s3m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>, <&cru PLL_GPLL>; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3568-evb1-ddr4-v10-dual-camera.dts b/rk3568-evb1-ddr4-v10-dual-camera.dts new file mode 100644 index 0000000..c4106a3 --- /dev/null +++ b/rk3568-evb1-ddr4-v10-dual-camera.dts @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" +#include "rk3568-evb1-dual-camera.dtsi" diff --git a/rk3568-evb1-ddr4-v10-linux-amp.dts b/rk3568-evb1-ddr4-v10-linux-amp.dts new file mode 100644 index 0000000..0c1b215 --- /dev/null +++ b/rk3568-evb1-ddr4-v10-linux-amp.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10-linux.dts" +#include "rk3568-amp.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x03880000 0x0 0x04b80000>, + <0x0 0x0a200000 0x0 0x75e00000>; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>; +}; + +/delete-node/ &cpu3; diff --git a/rk3568-evb1-ddr4-v10-linux-spi-nor.dts b/rk3568-evb1-ddr4-v10-linux-spi-nor.dts new file mode 100644 index 0000000..2598fdd --- /dev/null +++ b/rk3568-evb1-ddr4-v10-linux-spi-nor.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Linux SPI NOR Board"; + compatible = "rockchip,rk3568-evb1-ddr4-v10-linux-spi-nor", "rockchip,rk3568"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=/dev/mtdblock3 rootfstype=squashfs rootwait"; + }; + +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/rk3568-evb1-ddr4-v10-linux.dts b/rk3568-evb1-ddr4-v10-linux.dts new file mode 100644 index 0000000..b6b618b --- /dev/null +++ b/rk3568-evb1-ddr4-v10-linux.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-linux.dtsi" +#include + +&vp0 { + cursor-win-id = ; +}; + +&vp1 { + cursor-win-id = ; +}; diff --git a/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds-linux.dts b/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds-linux.dts new file mode 100644 index 0000000..fb33ac5 --- /dev/null +++ b/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds-linux.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include +#include "rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi" +#include "rk3568-linux.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 V10 Board with one vp two single channel lvds"; + compatible = "rockchip,rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds", "rockchip,rk3568"; +}; + +&vp0 { + cursor-win-id = ; +}; + +&vp1 { + cursor-win-id = ; +}; diff --git a/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dts b/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dts new file mode 100644 index 0000000..43b0df3 --- /dev/null +++ b/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 V10 Board with one vp two single channel lvds"; + compatible = "rockchip,rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds", "rockchip,rk3568"; +}; diff --git a/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi b/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi new file mode 100644 index 0000000..51e1d19 --- /dev/null +++ b/rk3568-evb1-ddr4-v10-one-vp-two-single-channel-lvds.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include "rk3568-evb1-ddr4-v10.dtsi" + +/ { + /* panel: claa070wp03xg */ + panel { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <134000000>; + hactive = <1600>; /* each panel show 1600 / 2 = 800 pxiel */ + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /** + * Panel <----> LVDS0 + * Panel <----> LVDS1 + */ + port@0 { + reg = <0>; + dual-lvds-left-pixels; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + port@1 { + reg = <1>; + dual-lvds-right-pixels; + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + dual-channel; + + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + lvds1_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&lvds1_in_vp1 { + status = "okay"; +}; + +&lvds1_in_vp2 { + status = "disabled"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3568-evb1-ddr4-v10-single-channel-lvds.dts b/rk3568-evb1-ddr4-v10-single-channel-lvds.dts new file mode 100644 index 0000000..e0f543a --- /dev/null +++ b/rk3568-evb1-ddr4-v10-single-channel-lvds.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 V10 Board with single channel lvds"; + compatible = "rockchip,rk3568-evb1-ddr4-v10-single-channel-lvds", "rockchip,rk3568"; + + /* panel: claa070wp03xg */ + panel-lvds0 { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <67000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "disabled"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds.dts b/rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds.dts new file mode 100644 index 0000000..13d0f91 --- /dev/null +++ b/rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds.dts @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 V10 Board with two vp two separate single channel lvds"; + compatible = "rockchip,rk3568-evb1-ddr4-v10-two-vp-two-separate-single-channel-lvds", "rockchip,rk3568"; + + /** + * VP1 -> LVDS0 -> Panel0 + * VP2 -> LVDS1 -> Panel1 + */ + + /* panel: claa070wp03xg */ + panel-lvds0 { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd0_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <67000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds0: endpoint { + remote-endpoint = <&lvds0_out_panel>; + }; + }; + }; + }; + + /* panel: claa070wp03xg */ + panel-lvds1 { + compatible = "simple-panel"; + backlight = <&backlight1>; + power-supply = <&vcc3v3_lcd1_n>; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + display-timings { + native-mode = <&timing1>; + timing1: timing1 { + clock-frequency = <67000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <4>; + vfront-porch = <2>; + hsync-len = <8>; + vsync-len = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_lvds1: endpoint { + remote-endpoint = <&lvds1_out_panel>; + }; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&backlight1 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp1 { + status = "okay"; +}; + +&lvds0 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds0_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + }; +}; + +&lvds0_in_vp1 { + status = "okay"; +}; + +&lvds1 { + status = "okay"; + ports { + port@1 { + reg = <1>; + lvds1_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&lvds1_in_vp1 { + status = "disabled"; +}; + +&lvds1_in_vp2 { + status = "okay"; +}; + +&rgb_in_vp2 { + status = "disabled"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; diff --git a/rk3568-evb1-ddr4-v10.dts b/rk3568-evb1-ddr4-v10.dts new file mode 100644 index 0000000..c505c37 --- /dev/null +++ b/rk3568-evb1-ddr4-v10.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" + +&bt_sco { + status = "okay"; +}; + +&bt_sound { + status = "okay"; +}; + +&i2s3_2ch { + status = "okay"; +}; diff --git a/rk3568-evb1-ddr4-v10.dtsi b/rk3568-evb1-ddr4-v10.dtsi new file mode 100644 index 0000000..dc9ad42 --- /dev/null +++ b/rk3568-evb1-ddr4-v10.dtsi @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568 EVB1 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb1-ddr4-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_vga: vcc3v3-vga { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_vga"; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; +}; + +&edp { + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c4 { + status = "okay"; + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + power-domains = <&power RK3568_PD_VI>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + os04a10: os04a10@36 { + compatible = "ovti,os04a10"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk809_sound { + hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&route_edp { + status = "okay"; + connect = <&vp0_out_edp>; +}; + +&sata2 { + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk3568-evb1-dual-camera.dtsi b/rk3568-evb1-dual-camera.dtsi new file mode 100644 index 0000000..334651d --- /dev/null +++ b/rk3568-evb1-dual-camera.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy_hw { + status = "okay"; +}; + +/* + * csi2_dphy1 & csi2_dphy2 used for split mode, + * csi2_dphy0 used for full mode, + * full mode and split mode are mutually exclusive + */ +&csi2_dphy0 { + status = "disabled"; + /delete-node/ ports; +}; + +&csi2_dphy1 { + status = "okay"; + /* + * dphy1 only used for split mode, + * can be used concurrently with dphy2 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_gc2093_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc2093_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + /* + * dphy2 only used for split mode, + * can be used concurrently with dphy1 + * full mode and split mode are mutually exclusive + */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_gc2053_ir: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc2053_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + dphy2_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&isp_in1>; + }; + }; + }; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&dphy1_out>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + /delete-node/ gc8034@37; + /delete-node/ os04a10@36; + /delete-node/ ov5695@36; + + gc2053: gc2053@37 { + status = "okay"; + compatible = "galaxycore,gc2053"; + reg = <0x37>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A3"; + port { + gc2053_out: endpoint { + remote-endpoint = <&mipi_in_gc2053_ir>; + data-lanes = <1 2>; + }; + }; + }; + + gc2093: gc2093@7e { + status = "okay"; + compatible = "galaxycore,gc2093"; + reg = <0x7e>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A1"; + port { + gc2093_out: endpoint { + remote-endpoint = <&mipi_in_gc2093_rgb>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp_in2>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + + +&rkisp { + status = "okay"; + max-input = <3840 2160 30>; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + /* gc2053-ir->dphy2->isp_vir0 */ + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&dphy2_out>; + }; + }; +}; + +&rkisp_vir1 { + status = "okay"; + /* gc2093-rgb->dphy1->csi2->vicap */ + /* vicap sditf->isp_vir1 */ + port { + #address-cells = <1>; + #size-cells = <0>; + + isp_in2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; diff --git a/rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dts b/rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dts new file mode 100644 index 0000000..4d06c0b --- /dev/null +++ b/rk3568-evb2-lp4x-v10-bt1120-to-hdmi.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&dsi0 { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi_int>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + bus-format = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&video_phy0 { + status = "disabled"; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bt1120_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&vcc3v3_lcd1_n { + status = "disabled"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/rk3568-evb2-lp4x-v10.dts b/rk3568-evb2-lp4x-v10.dts new file mode 100644 index 0000000..23f5f03 --- /dev/null +++ b/rk3568-evb2-lp4x-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb2-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3568-evb2-lp4x-v10.dtsi b/rk3568-evb2-lp4x-v10.dtsi new file mode 100644 index 0000000..34b7f28 --- /dev/null +++ b/rk3568-evb2-lp4x-v10.dtsi @@ -0,0 +1,476 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568 EVB2 LP4X V10 Board"; + compatible = "rockchip,rk3568-evb2-lp4x-v10", "rockchip,rk3568"; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + qsgmii_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "qsgmii_3v3"; + regulator-min-microvolt = <0100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <0100000 0x0 + 3300000 0x1>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; +}; + +&gmac0 { + phy-supply = <&qsgmii_3v3>; + phy-mode = "qsgmii"; + rockchip,xpcs = <&xpcs>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>; + assigned-clock-parents = <&gmac0_xpcsclk>; + + power-domains = <&power RK3568_PD_PIPE>; + phys = <&combphy1_usq PHY_TYPE_QSGMII>; + phy-handle = <&qsgmii_phy0>; + + status = "okay"; +}; + +&gmac1 { + phy-supply = <&qsgmii_3v3>; + phy-mode = "qsgmii"; + + snps,reset-gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>; + assigned-clock-parents = <&gmac1_xpcsclk>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim>; + + power-domains = <&power RK3568_PD_PIPE>; + phy-handle = <&qsgmii_phy1>; + + status = "okay"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c4 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PD7 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&mdio1 { + qsgmii_phy0: phy@0 { + compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + qsgmii_phy1: phy@1 { + compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; + qsgmii_phy2: phy@2 { + compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22"; + reg = <0x2>; + }; + qsgmii_phy3: phy@3 { + compatible = "ethernet-phy-id001c.c942", "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sii902x { + sii902x_hdmi_int: sii902x-hdmi-int { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm3 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&pwm7 { + status = "disabled"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sdio_pwrseq { + clocks = <&pmucru CLK_RTC_32K>; + pinctrl-0 = <&wifi_enable_h &wifi_32k>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&xpcs { + status = "okay"; +}; diff --git a/rk3568-evb4-lp3-v10.dts b/rk3568-evb4-lp3-v10.dts new file mode 100644 index 0000000..5884da4 --- /dev/null +++ b/rk3568-evb4-lp3-v10.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" +/{ + model = "Rockchip RK3568 EVB4 LP3 V10 Board"; + compatible = "rockchip,rk3568-evb4-lp3-v10", "rockchip,rk3568"; +}; diff --git a/rk3568-evb5-ddr4-v10.dts b/rk3568-evb5-ddr4-v10.dts new file mode 100644 index 0000000..e9eb333 --- /dev/null +++ b/rk3568-evb5-ddr4-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb5-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3568-evb5-ddr4-v10.dtsi b/rk3568-evb5-ddr4-v10.dtsi new file mode 100644 index 0000000..beba4ab --- /dev/null +++ b/rk3568-evb5-ddr4-v10.dtsi @@ -0,0 +1,552 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568 EVB5 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb5-ddr4-v10", "rockchip,rk3568"; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + rockchip,sgmii-mac-sel = <0>; + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; +}; + +&edp { + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&gmac0 { + phy-mode = "sgmii"; + + rockchip,pipegrf = <&pipegrf>; + rockchip,xpcs = <&xpcs>; + + snps,reset-gpio = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>; + assigned-clock-parents = <&gmac0_xpcsclk>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim>; + + power-domains = <&power RK3568_PD_PIPE>; + phys = <&combphy1_usq PHY_TYPE_SGMII>; + phy-handle = <&sgmii_phy>; + + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2_level3 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk_level2 + &gmac1m1_rgmii_bus_level3>; + + tx_delay = <0x46>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi_int>; + interrupt-parent = <&gpio4>; + interrupts = ; + reset-gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + bus-format = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + power-domains = <&power RK3568_PD_VI>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + os04a10: os04a10@36 { + compatible = "ovti,os04a10"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&mdio0 { + sgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sii902x { + sii902x_hdmi_int: sii902x-hdmi-int { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sata2 { + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk3568-evb6-ddr3-v10-linux.dts b/rk3568-evb6-ddr3-v10-linux.dts new file mode 100644 index 0000000..a11975f --- /dev/null +++ b/rk3568-evb6-ddr3-v10-linux.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-linux.dtsi" diff --git a/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts b/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts new file mode 100644 index 0000000..106e85c --- /dev/null +++ b/rk3568-evb6-ddr3-v10-rk628-bt1120-to-hdmi.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" + +&dsi0 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + rk628: rk628@50 { + reg = <0x50>; + interrupt-parent = <&gpio0>; + interrupts = ; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&video_phy0 { + status = "disabled"; +}; + +#include + +&rk628_hdmi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_post_process: endpoint { + remote-endpoint = <&post_process_out_hdmi>; + }; + }; + }; +}; + +&rk628_post_process { + pinctrl-names = "default"; + pinctrl-0 = <&rk628_vop_pins>; + status = "okay"; + + mode-sync-pol = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + post_process_in_bt1120: endpoint { + remote-endpoint = <&bt1120_out_post_process>; + }; + }; + + port@1 { + reg = <1>; + + post_process_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_post_process>; + }; + }; + }; +}; + +&rk628_bt1120_rx { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bt1120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_bt1120>; + }; + }; + + port@1 { + reg = <1>; + + bt1120_out_post_process: endpoint { + remote-endpoint = <&post_process_in_bt1120>; + }; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&bt1120_pins>; + + ports { + port@1 { + reg = <1>; + + rgb_out_bt1120: endpoint { + remote-endpoint = <&bt1120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&vcc3v3_lcd1_n { + status = "disabled"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts b/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts new file mode 100644 index 0000000..1cefbfa --- /dev/null +++ b/rk3568-evb6-ddr3-v10-rk628-rgb2dsi.dts @@ -0,0 +1,419 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" + +&dsi0 { + status = "disabled"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + rk628: rk628@50 { + reg = <0x50>; + interrupt-parent = <&gpio0>; + interrupts = ; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +#include + +&backlight { + pwms = <&pwm14 0 25000 0>; +}; + +&pwm14 { + status = "okay"; +}; + +&rk628_dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi0_in_post_process: endpoint { + remote-endpoint = <&post_process_out_dsi0>; + }; + }; + }; + + panel@0 { + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + enable-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + disable-delay-ms = <120>; + unprepare-delay-ms = <120>; + init-delay-ms = <120>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings3: display-timings { + native-mode = <&dsi0_timing3>; + dsi0_timing3: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; +}; + +&rk628_combtxphy { + status = "okay"; +}; + +&rk628_post_process { + pinctrl-names = "default"; + pinctrl-0 = <&rk628_vop_pins>; + status = "okay"; + + mode-sync-pol = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + post_process_in_rgb: endpoint { + remote-endpoint = <&rgb_out_post_process>; + }; + }; + + port@1 { + reg = <1>; + + post_process_out_dsi0: endpoint { + remote-endpoint = <&dsi0_in_post_process>; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_post_process: endpoint { + remote-endpoint = <&post_process_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&vcc3v3_lcd1_n { + status = "disabled"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts b/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts new file mode 100644 index 0000000..a4759f1 --- /dev/null +++ b/rk3568-evb6-ddr3-v10-rk628-rgb2hdmi.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" + +&dsi0 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + rk628: rk628@50 { + reg = <0x50>; + interrupt-parent = <&gpio0>; + interrupts = ; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +#include + +&rk628_hdmi { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_post_process: endpoint { + remote-endpoint = <&post_process_out_hdmi>; + }; + }; + }; +}; + +&rk628_post_process { + pinctrl-names = "default"; + pinctrl-0 = <&rk628_vop_pins>; + status = "okay"; + + mode-sync-pol = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + post_process_in_rgb: endpoint { + remote-endpoint = <&rgb_out_post_process>; + }; + }; + + port@1 { + reg = <1>; + + post_process_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_post_process>; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_post_process: endpoint { + remote-endpoint = <&post_process_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&vcc3v3_lcd1_n { + status = "disabled"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts b/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts new file mode 100644 index 0000000..ec43b24 --- /dev/null +++ b/rk3568-evb6-ddr3-v10-rk628-rgb2lvds.dts @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + vcc33_lcd: vcc33-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc33_lcd"; + regulator-boot-on; + regulator-always-on; + gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel { + compatible = "simple-panel"; + power-supply = <&vcc33_lcd>; + backlight = <&backlight>; + enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + bus-format = ; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <66600000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <30>; + hfront-porch = <30>; + vback-porch = <3>; + vfront-porch = <3>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&dsi0 { + status = "disabled"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <400000>; + status = "okay"; + + rk628: rk628@50 { + reg = <0x50>; + interrupt-parent = <&gpio0>; + interrupts = ; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +#include + +&backlight { + pwms = <&pwm14 0 25000 0>; +}; + +&pwm14 { + status = "okay"; +}; + +&rk628_lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_in_post_process: endpoint { + remote-endpoint = <&post_process_out_lvds>; + }; + }; + + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; +&rk628_combtxphy { + status = "okay"; +}; + +&rk628_post_process { + pinctrl-names = "default"; + pinctrl-0 = <&rk628_vop_pins>; + status = "okay"; + + mode-sync-pol = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + post_process_in_rgb: endpoint { + remote-endpoint = <&rgb_out_post_process>; + }; + }; + + port@1 { + reg = <1>; + + post_process_out_lvds: endpoint { + remote-endpoint = <&lvds_in_post_process>; + }; + }; + }; +}; + +&rgb { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + rgb_out_post_process: endpoint { + remote-endpoint = <&post_process_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&vcc3v3_lcd1_n { + status = "disabled"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&gmac1 { + status = "disabled"; +}; diff --git a/rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dts b/rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dts new file mode 100644 index 0000000..24c4deb --- /dev/null +++ b/rk3568-evb6-ddr3-v10-rk630-bt656-to-cvbs.dts @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" + +&dsi0 { + status = "disabled"; +}; + +&hdmi { + status = "disabled"; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <100000>; + + rk630: rk630@50 { + compatible = "rockchip,rk630"; + reg = <0x50>; + reset-gpios = <&gpio2 RK_PC7 GPIO_ACTIVE_LOW>; + status = "okay"; + + rk630_tve: rk630-tve { + compatible = "rockchip,rk630-tve"; + status = "okay"; + + ports { + port { + rk630_tve_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rk630_tve>; + }; + }; + }; + }; + }; +}; + +&rgb { + pinctrl-names = "default"; + pinctrl-0 = <&bt656m0_pins>; /* bt656m0_pins or bt656m1_pins */ + status = "okay"; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_rk630_tve: endpoint@0 { + reg = <0>; + remote-endpoint = <&rk630_tve_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&vcc3v3_lcd1_n { + status = "disabled"; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/rk3568-evb6-ddr3-v10.dts b/rk3568-evb6-ddr3-v10.dts new file mode 100644 index 0000000..6e34fa4 --- /dev/null +++ b/rk3568-evb6-ddr3-v10.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb6-ddr3-v10.dtsi" +#include "rk3568-android.dtsi" diff --git a/rk3568-evb6-ddr3-v10.dtsi b/rk3568-evb6-ddr3-v10.dtsi new file mode 100644 index 0000000..c93e473 --- /dev/null +++ b/rk3568-evb6-ddr3-v10.dtsi @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568 EVB6 DDR3 V10 Board"; + compatible = "rockchip,rk3568-evb6-ddr3-v10", "rockchip,rk3568"; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&bt_sound { + status = "disabled"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + rockchip,dis-u3otg1-port; + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +/* + * video_phy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +/* + * video_phy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd1_n>; +}; + +/* + * power-supply should switche to vcc3v3_lcd1_n + * when mipi panel is connected to dsi1. + */ +>1x { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + + mxc6655xa: mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <4>; + }; +}; + +&i2c4 { + status = "okay"; + os04a10: os04a10@36 { + compatible = "ovti,os04a10"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + /* power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */ + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + /* rockchip,camera-module-lens-name = "M12-4IR-4MP-F16"; */ + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c5 { + status = "disabled"; + + /delete-node/ mxc6655xa@15; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x1 { + rockchip,bifurcation; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + rockchip,bifurcation; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wifi_32k: wifi-32k { + rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&sdmmc1 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&sdio_pwrseq { + clocks = <&pmucru CLK_RTC_32K>; + pinctrl-0 = <&wifi_enable_h &wifi_32k>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&usbhost_dwc3 { + phys = <&u2phy0_host>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2_level3 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; + + tx_delay = <0x46>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; diff --git a/rk3568-evb7-ddr4-v10.dts b/rk3568-evb7-ddr4-v10.dts new file mode 100644 index 0000000..ecb9683 --- /dev/null +++ b/rk3568-evb7-ddr4-v10.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb1-ddr4-v10.dtsi" +#include "rk3568-android.dtsi" +/{ + model = "Rockchip RK3568 EVB7 DDR4 V10 Board"; + compatible = "rockchip,rk3568-evb7-ddr4-v10", "rockchip,rk3568"; +}; diff --git a/rk3568-evb8-lp4-v10-linux.dts b/rk3568-evb8-lp4-v10-linux.dts new file mode 100644 index 0000000..e3abd49 --- /dev/null +++ b/rk3568-evb8-lp4-v10-linux.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb8-lp4-v10.dtsi" +#include "rk3568-linux.dtsi" +#include + +&vp0 { + cursor-win-id = ; +}; + +&vp1 { + cursor-win-id = ; +}; diff --git a/rk3568-evb8-lp4-v10.dts b/rk3568-evb8-lp4-v10.dts new file mode 100644 index 0000000..b382cb4 --- /dev/null +++ b/rk3568-evb8-lp4-v10.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568-evb8-lp4-v10.dtsi" +#include "rk3568-android.dtsi" + +&bt_sco { + status = "okay"; +}; + +&bt_sound { + status = "okay"; +}; + +&i2s3_2ch { + status = "okay"; +}; diff --git a/rk3568-evb8-lp4-v10.dtsi b/rk3568-evb8-lp4-v10.dtsi new file mode 100644 index 0000000..f6269ac --- /dev/null +++ b/rk3568-evb8-lp4-v10.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-evb1-ddr4-v10.dtsi" + +/ { + model = "Rockchip RK3568 EVB8 LP4 V10 Board"; + compatible = "rockchip,rk3568-evb8-lp4-v10", "rockchip,rk3568"; +}; + +&i2c0 { + status = "okay"; + /delete-node/ tcs4525@1c; + + vdd_cpu: rk8600@40 { + compatible = "rockchip,rk8600"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; diff --git a/rk3568-iotest-ddr3-v10-linux.dts b/rk3568-iotest-ddr3-v10-linux.dts new file mode 100644 index 0000000..6af87ca --- /dev/null +++ b/rk3568-iotest-ddr3-v10-linux.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include + +/ { + model = "Rockchip RK3568 IOTEST DDR3 V10 Board"; + compatible = "rockchip,rk3568-iotest-ddr3-v10", "rockchip,rk3568"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&rkvdec { + /delete-property/ vdec-supply; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/delete-node/ &display_subsystem; diff --git a/rk3568-iotest-ddr3-v10.dts b/rk3568-iotest-ddr3-v10.dts new file mode 100644 index 0000000..489967f --- /dev/null +++ b/rk3568-iotest-ddr3-v10.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3568 IOTEST DDR3 V10 Board"; + compatible = "rockchip,rk3568-iotest-ddr3-v10", "rockchip,rk3568"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&usbdrd_dwc3 { + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbhost_dwc3 { + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; diff --git a/rk3568-linux.dtsi b/rk3568-linux.dtsi new file mode 100644 index 0000000..c7e3096 --- /dev/null +++ b/rk3568-linux.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; +}; + +&vop { + disable-win-move; +}; diff --git a/rk3568-nvr-demo-v10-linux-spi-nand.dts b/rk3568-nvr-demo-v10-linux-spi-nand.dts new file mode 100644 index 0000000..50bd024 --- /dev/null +++ b/rk3568-nvr-demo-v10-linux-spi-nand.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568-nvr-demo-v10.dtsi" +#include "rk3568-nvr-linux.dtsi" + +/ { + model = "Rockchip RK3568 NVR DEMO DDR4 V10 Linux SPI NAND Board"; + compatible = "rockchip,rk3568-nvr-demo-ddr4-v10-linux-spi-nand", "rockchip,rk3568"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs"; + }; + +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x1 { + status = "disabled"; +}; + +&pcie3x2 { + status = "disabled"; +}; diff --git a/rk3568-nvr-demo-v10-linux.dts b/rk3568-nvr-demo-v10-linux.dts new file mode 100644 index 0000000..3317db6 --- /dev/null +++ b/rk3568-nvr-demo-v10-linux.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-nvr-demo-v10.dtsi" +#include "rk3568-nvr-linux.dtsi" + +/ { + model = "Rockchip RK3568 NVR DEMO DDR4 V10 Linux Board"; + compatible = "rockchip,rk3568-nvr-demo-ddr4-v10-linux", "rockchip,rk3568"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x1 { + status = "disabled"; +}; + +&pcie3x2 { + status = "disabled"; +}; diff --git a/rk3568-nvr-demo-v10.dts b/rk3568-nvr-demo-v10.dts new file mode 100644 index 0000000..053d202 --- /dev/null +++ b/rk3568-nvr-demo-v10.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-nvr-demo-v10.dtsi" +#include "rk3568-android.dtsi" + +/ { + model = "Rockchip RK3568 NVR DEMO DDR4 V10 ANDROID Board"; + compatible = "rockchip,rk3568-nvr-demo-ddr4-v10", "rockchip,rk3568"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x1 { + status = "disabled"; +}; + +&pcie3x2 { + status = "disabled"; +}; diff --git a/rk3568-nvr-demo-v10.dtsi b/rk3568-nvr-demo-v10.dtsi new file mode 100644 index 0000000..3f59acc --- /dev/null +++ b/rk3568-nvr-demo-v10.dtsi @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-nvr.dtsi" +#include + +/ { + model = "Rockchip RK3568 NVR DEMO V10 Board"; + compatible = "rockchip,rk3568-nvr-demo-v10", "rockchip,rk3568"; + + gpio-leds { + compatible = "gpio-leds"; + + hdd-led { + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + net-led { + gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work-led { + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "timer"; + }; + }; + + i2s1_sound: i2s1-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,i2s1-sound"; + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&es8311>; + }; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1_usq { + pinctrl-names = "default"; + pinctrl-0 = <&sata_pm_reset>; + rockchip,dis-u3otg1-port; + status = "okay"; +}; + +&combphy2_psq{ + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x43>; + rx_delay = <0x33>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x2d>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + es8311: es8311@18 { + compatible = "everest,es8311"; + reg = <0x18>; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + adc-pga-gain = <6>; /* 18dB */ + adc-volume = <0xbf>; /* 0dB */ + dac-volume = <0xbf>; /* 0dB */ + aec-mode = "dac left, adc right"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + spk-ctl-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; + + rk618@50 { + compatible = "rockchip,rk618"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3m1_mclk &rk618_int>; + clocks = <&cru I2S3_MCLKOUT>; + clock-names = "clkin"; + assigned-clocks =<&cru I2S3_MCLKOUT>, <&cru I2S3_MCLK_IOE>; + assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, <&cru I2S3_MCLKOUT>; + assigned-clock-rates = <11289600>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + status = "okay"; + + clock: cru { + compatible = "rockchip,rk618-cru"; + clocks = <&cru I2S3_MCLKOUT>, <&cru DCLK_VOP2>; + clock-names = "clkin", "lcdc0_dclkp"; + assigned-clocks = <&clock SCALER_PLLIN_CLK>, + <&clock VIF_PLLIN_CLK>, + <&clock SCALER_CLK>, + <&clock VIF0_PRE_CLK>, + <&clock CODEC_CLK>, + <&clock DITHER_CLK>; + assigned-clock-parents = <&cru I2S3_MCLKOUT_TX>, + <&clock LCDC0_CLK>, + <&clock SCALER_PLL_CLK>, + <&clock VIF_PLL_CLK>, + <&cru I2S3_MCLKOUT>, + <&clock VIF0_CLK>; + #clock-cells = <1>; + status = "okay"; + }; + + hdmi { + compatible = "rockchip,rk618-hdmi"; + clocks = <&clock HDMI_CLK>; + clock-names = "hdmi"; + assigned-clocks = <&clock HDMI_CLK>; + assigned-clock-parents = <&clock VIF0_CLK>; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + hdmi_in_rgb: endpoint { + remote-endpoint = <&rgb_out_hdmi>; + }; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x1 { + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pwm15 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m1_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + ports { + port@1 { + reg = <1>; + + rgb_out_hdmi: endpoint { + remote-endpoint = <&hdmi_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&pinctrl { + rk618 { + rk618_reset: rk618-reeset { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_high>; + }; + rk618_int: rk618-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sata { + sata_pm_reset: sata-pm-reset { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; diff --git a/rk3568-nvr-demo-v12-linux-spi-nand.dts b/rk3568-nvr-demo-v12-linux-spi-nand.dts new file mode 100644 index 0000000..de8c1a1 --- /dev/null +++ b/rk3568-nvr-demo-v12-linux-spi-nand.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +/dts-v1/; + +#include "rk3568-nvr-demo-v12.dtsi" +#include "rk3568-nvr-linux.dtsi" + +/ { + model = "Rockchip RK3568 NVR DEMO DDR4 V12 Linux SPI NAND Board"; + compatible = "rockchip,rk3568-nvr-demo-ddr4-v12-linux-spi-nand", "rockchip,rk3568"; + + chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs"; + }; + +}; + diff --git a/rk3568-nvr-demo-v12-linux.dts b/rk3568-nvr-demo-v12-linux.dts new file mode 100644 index 0000000..b605c3d --- /dev/null +++ b/rk3568-nvr-demo-v12-linux.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-nvr-demo-v12.dtsi" +#include "rk3568-nvr-linux.dtsi" + +/ { + model = "Rockchip RK3568 NVR DEMO DDR4 V12 Linux Board"; + compatible = "rockchip,rk3568-nvr-demo-ddr4-v12-linux", "rockchip,rk3568"; +}; + diff --git a/rk3568-nvr-demo-v12.dtsi b/rk3568-nvr-demo-v12.dtsi new file mode 100644 index 0000000..6bb5036 --- /dev/null +++ b/rk3568-nvr-demo-v12.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3568-nvr-demo-v10.dtsi" + +/ { + model = "Rockchip RK3568 NVR DEMO V12 Board"; + compatible = "rockchip,rk3568-nvr-demo-v12", "rockchip,rk3568"; +}; + +&gmac0 { + tx_delay = <0x35>; + rx_delay = <0x2d>; +}; + +&gmac1 { + tx_delay = <0x43>; + rx_delay = <0x27>; +}; + +&gpu { + mali-supply = <&vdd_npu>; + status = "okay"; +}; + +&vdd_logic { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1000000>; +}; + +&vdd_npu { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; +}; diff --git a/rk3568-nvr-linux.dtsi b/rk3568-nvr-linux.dtsi new file mode 100644 index 0000000..f9908b6 --- /dev/null +++ b/rk3568-nvr-linux.dtsi @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + debug: debug@fd904000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd904000 0x0 0x1000>, + <0x0 0xfd905000 0x0 0x1000>, + <0x0 0xfd906000 0x0 0x1000>, + <0x0 0xfd907000 0x0 0x1000>; + }; + + cspmu: cspmu@fd90c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd90c000 0x0 0x1000>, + <0x0 0xfd90d000 0x0 0x1000>, + <0x0 0xfd90e000 0x0 0x1000>, + <0x0 0xfd90f000 0x0 0x1000>; + }; +}; + +&reserved_memory { + ramoops: ramoops@110000 { + compatible = "ramoops"; + reg = <0x0 0x110000 0x0 0xf0000>; + record-size = <0x20000>; + console-size = <0x80000>; + ftrace-size = <0x00000>; + pmsg-size = <0x50000>; + }; +}; + +&rng { + status = "okay"; +}; diff --git a/rk3568-nvr.dtsi b/rk3568-nvr.dtsi new file mode 100644 index 0000000..d030582 --- /dev/null +++ b/rk3568-nvr.dtsi @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568.dtsi" +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi-sound"; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rknpu_reserved: rknpu { + compatible = "shared-dma-pool"; + inactive; + reusable; + size = <0x0 0x20000000>; + alignment = <0x0 0x1000>; + }; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc_1v8: vcc_1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3: vcc_3v3{ + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_fixed: vdd-fixed { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-init-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + regulator-init-microvolt = <950000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu0_opp_table { + /delete-node/ opp-1992000000; +}; + +&CPU_SLEEP { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&edp { + hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "okay"; +}; + +&edp_phy { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_fixed>; + status = "okay"; +}; + +&gpu_opp_table { + /delete-node/ opp-800000000; +}; + +&hdmi { + skip-check-420-mode; + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +/* Need to be modified according to the actual hardware */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; +}; + +&rk_rga { + status = "okay"; +}; + +&rknpu { + memory-region = <&rknpu_reserved>; + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "disabled"; +}; + +&rkvdec { + rockchip,disable-auto-freq; + assigned-clock-rates = <396000000>, <396000000>, <396000000>, <600000000>; + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvdec_sram { + reg = <0x0 0x10000>; +}; + +&rkvenc { + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spdif_8ch { + status = "okay"; +}; + +&sram { + reg = <0x0 0xfdcc0000 0x0 0x10000>; + ranges = <0x0 0x0 0xfdcc0000 0x10000>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + phys = <&u2phy0_host>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP1>; + assigned-clock-parents = <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3568-pcie-ep-lp4x-v10-linux.dts b/rk3568-pcie-ep-lp4x-v10-linux.dts new file mode 100644 index 0000000..4f255e1 --- /dev/null +++ b/rk3568-pcie-ep-lp4x-v10-linux.dts @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Rockchip RK3568 PCIe EP LP4X V10 Board"; + compatible = "rockchip,rk3568-pcie-ep-lp4x-v10", "rockchip,rk3568"; + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait default_hugepagesz=32M hugepagesz=32M hugepages=1"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + work_led: work { + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + bar0_region: bar0-region@0x3c000000 { + reg = <0x0 0x3c000000 0x0 0x00400000>; + }; + bar2_region: bar2-region@0x40000000 { + reg = <0x0 0x40000000 0x0 0x04000000>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vccio_1v8: vccio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vccio_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vccio_3v3: vccio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vccio_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_gpu: vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <920000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc3v3_sys>; + status = "okay"; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1000000>; + regulator-init-microvolt = <920000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc3v3_sys>; + status = "okay"; + }; + + vdd_npu: vdd-npu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + regulator-name = "vdd_npu"; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <920000>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc3v3_sys>; + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m0_pins>; + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&display_subsystem { + status = "okay"; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x3c>; + rx_delay = <0x2f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x4f>; + rx_delay = <0x26>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + vdd_cpu: rk8600@40 { + compatible = "rockchip,rk8600"; + reg = <0x40>; + vin-supply = <&vcc3v3_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1500000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + compatible = "rockchip,rk3568-pcie-std-ep"; + memory-region = <&bar0_region>, <&bar2_region>; + memory-region-names = "bar0", "bar2"; + status = "okay"; +}; + +&pinctrl { + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vccio_3v3>; + vccio1-supply = <&vccio_3v3>; + vccio3-supply = <&vccio_3v3>; + vccio4-supply = <&vccio_3v3>; + vccio5-supply = <&vccio_3v3>; + vccio6-supply = <&vccio_3v3>; + vccio7-supply = <&vccio_3v3>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vccio_1v8>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vccio_3v3>; + vqmmc-supply = <&vccio_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + //mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&spi0 { + status = "okay"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0m1_cs0 &spi0m1_pins>; + pinctrl-1 = <&spi0m1_cs0 &spi0m1_pins_hs>; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins>; + pinctrl-1 = <&spi2m1_cs0 &spi2m1_cs1 &spi2m1_pins_hs>; +}; + +&tsadc { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +/* RS485 */ +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer &uart4m0_ctsn &uart4m0_rtsn>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; + vbus-supply = <&vcc5v0_otg>; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3568-pinctrl.dtsi b/rk3568-pinctrl.dtsi new file mode 100644 index 0000000..a78bdf9 --- /dev/null +++ b/rk3568-pinctrl.dtsi @@ -0,0 +1,3119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_volsel */ + <0 RK_PA7 1 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3568-toybrick-sd0-android.dts b/rk3568-toybrick-sd0-android.dts new file mode 100644 index 0000000..1f2f044 --- /dev/null +++ b/rk3568-toybrick-sd0-android.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-sd0.dtsi" +#include "rk3568-android.dtsi" +//#include "rk3568-toybrick-sd0-mipi-tx0.dtsi" +/delete-node/ &board_id; +/ { + model = "Rockchip RK3568 Toybrick SD0 Board"; + compatible = "rockchip,rk3568-toybrick-sd0-linux","rockchip,rk3568"; +}; diff --git a/rk3568-toybrick-sd0-linux.dts b/rk3568-toybrick-sd0-linux.dts new file mode 100644 index 0000000..f126bab --- /dev/null +++ b/rk3568-toybrick-sd0-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-sd0.dtsi" +#include "rk3568-linux.dtsi" +//#include "rk3568-toybrick-sd0-mipi-tx0.dtsi" +/delete-node/ &board_id; +/ { + model = "Rockchip RK3568 Toybrick SD0 Board"; + compatible = "rockchip,rk3568-toybrick-sd0-linux","rockchip,rk3568"; +}; diff --git a/rk3568-toybrick-sd0-mipi-tx0.dtsi b/rk3568-toybrick-sd0-mipi-tx0.dtsi new file mode 100644 index 0000000..7dbcf64 --- /dev/null +++ b/rk3568-toybrick-sd0-mipi-tx0.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + compatible = "rockchip,rk3568-toybrick-sd0-mipi-tx0", "rockchip,rk3568"; +}; + +/* + * mipi_dphy0 needs to be enabled + * when dsi0 is enabled + */ +&backlight { + status = "okay"; + pwms = <&pwm14 0 25000 0>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; +}; + +&i2c1 { + status = "okay"; + power-supply = <&vcc3v3_lcd0_n>; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + status = "okay"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + goodix,rst-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pwm14{ + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&pinctrl { + touch { + touch_pin: touch-pin { + rockchip,pins = + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3568-toybrick-sd0.dtsi b/rk3568-toybrick-sd0.dtsi new file mode 100644 index 0000000..7526f29 --- /dev/null +++ b/rk3568-toybrick-sd0.dtsi @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-toybrick.dtsi" + +/delete-node/ &adc_keys; + +/ { + compatible = "rockchip,rk3568-toybrick-sd0", "rockchip,rk3568"; + + bt-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <512>; + simple-audio-card,name = "rockchip,bt"; + #simple-audio-card,bitclock-master = <&sound2_master>; + #simple-audio-card,frame-master = <&sound2_master>; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + sound2_master:simple-audio-card,codec { + #sound-dai-cells = <0>; + sound-dai = <&bt_sco>; + }; + }; + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 2>; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; +}; + +&bus_npu { + status = "okay"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov50c40_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + ð1m1_pins>; + + tx_delay = <0x30>; + rx_delay = <0x28>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2s2_2ch { + status = "okay"; + #sound-dai-cells = <0>; +}; + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + regulators { + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdo0 + &i2s1m0_sdi0>; +}; + +&i2c5 { + status = "okay"; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + // must be high at last + power-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + // must be high at last do at vcc_camera + //reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20-RK3568"; + //lens-focus = <&cam_ircut0>; + port { + imx415_out: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + aw8601: aw8601@c { + compatible = "awinic,aw8601"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <56>; + rockchip,vcm-rated-current = <96>; + rockchip,vcm-step-mode = <4>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + otp_eeprom: otp_eeprom@50 { + compatible = "rk,otp_eeprom"; + status = "okay"; + reg = <0x50>; + }; + + ov50c40: ov50c40@36 { + compatible = "ovti,ov50c40"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;// must be high at last + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;// must be high at last + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HZGA06"; + rockchip,camera-module-lens-name = "ZE0082C1-RK3568"; + eeprom-ctrl = <&otp_eeprom>; + lens-focus = <&aw8601>; + port { + ov50c40_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&leds { + status = "okay"; + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC1_OUT>; + }; +}; + +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "okay"; +}; + +&reserved_memory { + linux,cma { + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 0x10000000 0x0 0x08000000>; + linux,cma-default; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&rockchip_suspend { + status = "disabled"; +}; + +&rknpu { + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <200>; + status = "okay"; +}; + +&sdmmc1 { + status = "disabled"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_pin>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_4>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_pin: uart1-pin { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3568-toybrick-x0-android.dts b/rk3568-toybrick-x0-android.dts new file mode 100644 index 0000000..795506d --- /dev/null +++ b/rk3568-toybrick-x0-android.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-x0.dtsi" +#include "rk3568-android.dtsi" +/ { + compatible = "rockchip,rk3568-toybrick-x0-android","rockchip,rk3568"; +}; + diff --git a/rk3568-toybrick-x0-linux.dts b/rk3568-toybrick-x0-linux.dts new file mode 100644 index 0000000..9abc800 --- /dev/null +++ b/rk3568-toybrick-x0-linux.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +#include "rk3568-toybrick-x0.dtsi" +#include "rk3568-linux.dtsi" +/delete-node/ &board_id; +/ { + compatible = "rockchip,rk3568-toybrick-x0-linux","rockchip,rk3568"; +}; diff --git a/rk3568-toybrick-x0.dtsi b/rk3568-toybrick-x0.dtsi new file mode 100644 index 0000000..c71eeda --- /dev/null +++ b/rk3568-toybrick-x0.dtsi @@ -0,0 +1,725 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include "rk3568.dtsi" +#include "rk3568-toybrick.dtsi" + +/delete-node/ &adc_keys; + +/ { + compatible = "rockchip,rk3568-toybrick", "rockchip,rk3568"; + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + poll-interval = <100>; + keyup-threshold-microvolt = <1800000>; + + menu-key { + linux,code = ; + label = "menu"; + press-threshold-microvolt = <1250000>; + }; + + mute-key { + linux,code = ; + label = "mute"; + press-threshold-microvolt = <850000>; + }; + + vol-down-key { + linux,code = ; + label = "volume down"; + press-threshold-microvolt = <400000>; + }; + + vol-up-key { + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <20000>; + }; + }; + + gpio_leds: gpio-leds { + compatible = "gpio-leds"; + led@1 { + gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + label = "blue"; // Blue LED + retain-state-suspended; + }; + + led@2 { + gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + label = "red"; // Red LED + retain-state-suspended; + }; + + led@3 { + gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; + label = "green"; // Green LED + retain-state-suspended; + }; + }; + + pcie20_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie20_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + pcie30_avdd0v9: pcie30-avdd0v9 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + pcie30_3v3: gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "pcie30_3v3"; + regulator-min-microvolt = <100000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <100000 0x0 + 3300000 0x1>; + }; + + rk_headset: rk-headset { + compatible = "rockchip_headset"; + headset_gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 1>; + }; + + rk809_sound_micarray: rk809-sound-micarray { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&rk809_codec 0>; + }; + }; + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&i2s1_8ch>; + }; + codec { + sound-dai = <&es7210>; + }; + }; + }; + + rt5672-sound { + compatible = "rockchip-rt5670"; + status = "disabled"; + dais { + dai0 { + audio-codec = <&rt5670>; + audio-controller = <&i2s1_8ch>; + format = "i2s"; + }; + dai1 { + audio-codec = <&rt5670>; + audio-controller = <&i2s1_8ch>; + format = "i2s"; + }; + dai2 { + audio-codec = <&es7210>; + audio-controller = <&i2s1_8ch>; + format = "i2s"; + }; + }; + }; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + mipi_in_ucam1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_ucam2: endpoint@3 { + reg = <3>; + remote-endpoint = <&ov5695_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x37>; + rx_delay = <0x2e>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + + tx_delay = <0x47>; + rx_delay = <0x28>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + rt5670: rt5670@1c { + status = "okay"; + #sound-dai-cell = <0>; + compatible = "realtek,rt5670"; + reg = <0x1c>; + }; + + es7210: es7210@40 { + #sound-dai-cells = <0>; + compatible = "MicArray_0"; + reg = <0x40>; + clocks = <&cru I2S1_MCLKOUT_RX>;//csqerr + clock-names = "mclk"; + }; + + es7210_1: es7210@42 { + compatible = "MicArray_1"; + reg = <0x42>; + }; +}; + +&i2c4 { + status = "okay"; + + gc8034: gc8034@37 { + compatible = "galaxycore,gc8034"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>;//CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,grf = <&grf>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401"; + port { + gc8034_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + ov9750_1: ov9750_1@36 { + compatible = "ovti,ov9750"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + power-domains = <&power RK3568_PD_VI>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT0854-FV1"; + rockchip,camera-module-lens-name = "CHT-842B-MD"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + ov5695: ov5695@36 { + status = "okay"; + compatible = "ovti,ov5695"; + reg = <0x36>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + port { + ov5695_out: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_pin>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; + + mxc6655xa: mxc6655xa@15 { + status = "disabled"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_pin>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + }; +}; + +&i2s1_8ch { + status = "okay"; + #sound-dai-cells = <0>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_sclkrx + &i2s1m0_lrcktx + &i2s1m0_sclkrx + &i2s1m0_lrckrx + &i2s1m0_sdo0 + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3>; +}; + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&pcie30_3v3>; + status = "okay"; +}; + +&pwm7 { + status = "okay"; +}; + +&rk809_sound { + status = "okay"; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&sata2 { + status = "okay"; +}; + +&sdio_pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <20>; + status = "okay"; +}; + +&sdmmc1 { + status = "disabled"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&vcc3v3_lcd1_n { + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_pin>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_up_drv_level_4>; + }; + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_4>; + }; + }; + + leds_pin: leds-pin { + rockchip,pins = + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + mxc6655xa { + mxc6655xa_irq_pin: mxc6655xa_irq_pin { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_pin: uart8-pin { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3568-toybrick.dtsi b/rk3568-toybrick.dtsi new file mode 100644 index 0000000..39a5072 --- /dev/null +++ b/rk3568-toybrick.dtsi @@ -0,0 +1,1862 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + /* + * extliux conf: extlinux.conf.${FLAG}.${BOARD_ID} + * dtb file: toybrick.dtb.${FLAG}.${BOARD_ID} + */ + board_id: board-id { + compatible = "board-id"; + io-channels = <&saradc 4>; + /* + * ID: adc-value/adc-io + * ------------------------- + * 0: adc-io is low level + * 1: 0 ~ 100 + * 2: 100 ~ 199 + * 3: 200 ~ 299 + * 4: 300 ~ 399 + * 5: 400 ~ 499 + * 6: 500 ~ 599 + * 7: 600 ~ 699 + * 8: 700 ~ 799 + * 9: 800 ~ 899 + * 10: 900 ~ 1024 + */ + adc-io = <29>;// GPIO0_D5 + thresholds = <100 200 300 400 500 600 700 800 900>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight1: backlight1 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + #simple-audio-card,bitclock-master = <&sound2_master>; + #simple-audio-card,frame-master = <&sound2_master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + sound2_master:simple-audio-card,codec { + #sound-dai-cells = <0>; + sound-dai = <&bt_sco>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + spdif-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "okay"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + test-power { + status = "okay"; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + regulator-name = "vcc5v0_otg"; + }; + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_pin>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can0m1_pins>; + status = "disabled"; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "disabled"; +}; + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; + status = "disabled"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight1>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_pin>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_pin>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <20>; + spk-volume = <3>; + mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "okay"; + + mxc6655xa: mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_pin>; + reg = <0x15>; + irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&i2s3_2ch { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +/** + * Model: TB-RK3568X + * ----------------------------------------------------------- + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + * | supply | domain | net | source | voltage | + * ----------------------------------------------------------- + * | pmuio1-supply | PMUIO1 | vcc3v3_pmu | LDO6 | 3.3V | + * | pmuio2-supply | PMUIO2 | vcc3v3_pmu | LDO6 | 3.3V | + * | vccio1-supply | VCCIO1 | vccio_acodec | LDO4 | 1.8V | + * | vccio2-supply | VCCIO2 | vccio_flash | vcc_1v8 | 1.8V | + * | vccio3-supply | VCCIO3 | vccio_sd | LDO5 | 3.3V | + * | vccio4-supply | VCCIO4 | vcc_1v8 | DCDC5 | 1.8V | + * | vccio5-supply | VCCIO5 | vcc_3v3 | SWITCH1 | 3.3V | + * | vccio6-supply | VCCIO6 | vcc_1v8 | DCDC5 | 1.8V | + * | vccio7-supply | VCCIO7 | vcc_3v3 | SWITCH1 | 3.3V | + * ----------------------------------------------------------- + */ +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + // vccio2-supply = <&vccio_flash>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm7 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&pinctrl { + + mxc6655xa { + mxc6655xa_irq_pin: mxc6655xa_irq_pin { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_pin: soc_slppin_pin { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_pin: touch-pin { + rockchip,pins = + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_pin: uart8-pin { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3568.dtsi b/rk3568.dtsi new file mode 100644 index 0000000..d2a2e76 --- /dev/null +++ b/rk3568.dtsi @@ -0,0 +1,3872 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3568-dram-default-timing.dtsi" + +/ { + compatible = "rockchip,rk3568"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; + dsi0 = &dsi0; + dsi1 = &dsi1; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + mmc3 = &sdmmc2; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + lvds0 = &lvds; + lvds1 = &lvds1; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x0>; + enable-method = "psci"; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + #cooling-cells = <2>; + dynamic-power-coefficient = <187>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x100>; + enable-method = "psci"; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x200>; + enable-method = "psci"; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0 0x300>; + enable-method = "psci"; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>, + <&specification_serial_number>, <&remark_spec_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number", "remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <1200000>; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 87000 1 + 87001 91000 2 + 91001 100000 3 + >; + rockchip,pvtm-freq = <408000>; + rockchip,pvtm-volt = <900000>; + rockchip,pvtm-ch = <0 5>; + rockchip,pvtm-sample-time = <1000>; + rockchip,pvtm-number = <10>; + rockchip,pvtm-error = <1000>; + rockchip,pvtm-ref-temp = <40>; + rockchip,pvtm-temp-prop = <26 26>; + rockchip,thermal-zone = "soc-thermal"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1992 75000 + >; + + /* RK3568 && RK3568M cpu OPPs */ + opp-408000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1104000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <900000 900000 1150000>; + opp-microvolt-L0 = <900000 900000 1150000>; + opp-microvolt-L1 = <850000 850000 1150000>; + opp-microvolt-L2 = <850000 850000 1150000>; + opp-microvolt-L3 = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1025000 1025000 1150000>; + opp-microvolt-L0 = <1025000 1025000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <950000 950000 1150000>; + opp-microvolt-L3 = <925000 925000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1100000 1100000 1150000>; + opp-microvolt-L0 = <1100000 1100000 1150000>; + opp-microvolt-L1 = <1050000 1050000 1150000>; + opp-microvolt-L2 = <1025000 1025000 1150000>; + opp-microvolt-L3 = <1000000 1000000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1150000 1150000 1150000>; + opp-microvolt-L0 = <1150000 1150000 1150000>; + opp-microvolt-L1 = <1100000 1100000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + opp-microvolt-L3 = <1050000 1050000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1992000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1992000000>; + opp-microvolt = <1150000 1150000 1150000>; + opp-microvolt-L0 = <1150000 1150000 1150000>; + opp-microvolt-L1 = <1150000 1150000 1150000>; + opp-microvolt-L2 = <1125000 1125000 1150000>; + opp-microvolt-L3 = <1100000 1100000 1150000>; + clock-latency-ns = <40000>; + }; + + /* RK3568J cpu OPPs */ + opp-j-1008000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <850000 850000 1150000>; + clock-latency-ns = <40000>; + }; + opp-j-1416000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + + /* RK3568M cpu OPPs */ + opp-m-1608000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1000000 1000000 1150000>; + clock-latency-ns = <40000>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,cortex-a55-pmu", "arm,armv8-pmuv3"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + memory-region = <&drm_logo>, <&drm_cubic_lut>; + memory-region-names = "drm-logo", "drm-cubic-lut"; + ports = <&vop_out>; + devfreq = <&dmc>; + + route { + route_dsi0: route-dsi0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dsi0>; + }; + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_dsi1>; + }; + route_edp: route-edp { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_edp>; + }; + route_hdmi: route-hdmi { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi>; + }; + route_lvds: route-lvds { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_lvds>; + }; + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp2_out_rgb>; + }; + }; + }; + + edac: edac { + compatible = "rockchip,rk3568-edac"; + interrupts = , + ; + interrupt-names = "ce", "ue"; + status = "disabled"; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + + rockchip,clk-init = <1104000000>; + }; + }; + + sdei: sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + mipi_csi2: mipi-csi2 { + compatible = "rockchip,rk3568-mipi-csi2"; + rockchip,hw = <&mipi_csi2_hw>; + status = "disabled"; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <6>; + rockchip,resetgroup-count = <6>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3568"; + status = "disabled"; + rockchip,sleep-debug-en = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_LOGOFF + | RKPM_SLP_CENTER_OFF + | RKPM_SLP_HW_PLLS_OFF + | RKPM_SLP_PMUALIVE_32K + | RKPM_SLP_OSC_DIS + | RKPM_SLP_PMIC_LP + | RKPM_SLP_32K_PVTM + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <905>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + trips { + threshold: trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + #clock-cells = <0>; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + gmac0_xpcsclk: xpcs-gmac0-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clk_gmac0_xpcs_mii"; + #clock-cells = <0>; + }; + + gmac1_xpcsclk: xpcs-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clk_gmac1_xpcs_mii"; + #clock-cells = <0>; + }; + + i2s1_mclkin_rx: i2s1-mclkin-rx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s1_mclkin_rx"; + }; + + i2s1_mclkin_tx: i2s1-mclkin-tx { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s1_mclkin_tx"; + }; + + i2s2_mclkin: i2s2-mclkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s2_mclkin"; + }; + + i2s3_mclkin: i2s3-mclkin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + clock-output-names = "i2s3_mclkin"; + }; + + mpll: mpll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <800000000>; + clock-output-names = "mpll"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_out0>; + }; + + scmi_shmem: scmi-shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + }; + + sata0: sata@fc000000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc000000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, + <&cru CLK_SATA0_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy0_us PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata1: sata@fc400000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy1_usq PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy2_psq PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + usbdrd30: usbdrd { + compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>, <&cru PCLK_PIPE>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3: dwc3@fcc00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&combphy0_us PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + reset-names = "usb3-otg"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "disabled"; + }; + }; + + usbhost30: usbhost { + compatible = "rockchip,rk3568-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>, <&cru PCLK_PIPE>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk", "pipe_clk"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbhost_dwc3: dwc3@fd000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = ; + dr_mode = "host"; + phys = <&u2phy0_host>, <&combphy1_usq PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG1>; + reset-names = "usb3-host"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + gic: interrupt-controller@fd400000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ + <0x0 0xfd460000 0 0xc0000>; /* GICR */ + interrupts = ; + its: interrupt-controller@fd440000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfd440000 0x0 0x20000>; + }; + }; + + usb_host0_ehci: usb@fd800000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fd840000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fd880000 { + compatible = "generic-ehci"; + reg = <0x0 0xfd880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fd8c0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfd8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>, + <&cru PCLK_USB>, <&usb2phy1>; + clock-names = "usbhost", "arbiter", "pclk", "utmi"; + phys = <&u2phy1_host>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + xpcs: syscon@fda00000 { + compatible = "rockchip,rk3568-xpcs", "syscon"; + reg = <0x0 0xfda00000 0x0 0x200000>; + status = "disabled"; + }; + + pmugrf: syscon@fdc20000 { + compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc20000 0x0 0x10000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3568-pmu-io-voltage-domain"; + status = "disabled"; + }; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x200>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + }; + }; + + pipegrf: syscon@fdc50000 { + compatible = "rockchip,rk3568-pipegrf", "syscon"; + reg = <0x0 0xfdc50000 0x0 0x1000>; + }; + + grf: syscon@fdc60000 { + compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdc60000 0x0 0x10000>; + + io_domains: io-domains { + compatible = "rockchip,rk3568-io-voltage-domain"; + status = "disabled"; + }; + + lvds0: lvds: lvds { + compatible = "rockchip,rk3568-lvds"; + phys = <&video_phy0>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds0_in_vp1: lvds_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_lvds>; + status = "disabled"; + }; + + lvds0_in_vp2: lvds_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_lvds>; + status = "disabled"; + }; + }; + }; + }; + + lvds1: lvds1 { + compatible = "rockchip,rk3568-lvds"; + phys = <&video_phy1>; + phy-names = "phy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + lvds1_in_vp1: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp1_out_lvds1>; + }; + + lvds1_in_vp2: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp2_out_lvds1>; + }; + }; + }; + }; + + rgb: rgb { + compatible = "rockchip,rk3568-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&lcdc_ctl>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_rgb>; + status = "disabled"; + }; + }; + }; + }; + + }; + + pipe_phy_grf0: syscon@fdc70000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc70000 0x0 0x1000>; + }; + + pipe_phy_grf1: syscon@fdc80000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc80000 0x0 0x1000>; + }; + + pipe_phy_grf2: syscon@fdc90000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfdc90000 0x0 0x1000>; + }; + + usb2phy0_grf: syscon@fdca0000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca0000 0x0 0x8000>; + }; + + usb2phy1_grf: syscon@fdca8000 { + compatible = "rockchip,rk3568-usb2phy-grf", "syscon"; + reg = <0x0 0xfdca8000 0x0 0x8000>; + }; + + edp_phy_grf: syscon@fdcb0000 { + compatible = "rockchip,rk3568-edp-phy-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfdcb0000 0x0 0x100>; + clocks = <&cru PCLK_EDPPHY_GRF>; + + edp_phy: edp-phy { + compatible = "rockchip,rk3568-edp-phy"; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>; + clock-names = "refclk"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + pcie30_phy_grf: syscon@fdcb8000 { + compatible = "rockchip,pcie30-phy-grf", "syscon"; + reg = <0x0 0xfdcb8000 0x0 0x10000>; + }; + + sram: sram@fdcc0000 { + compatible = "mmio-sram"; + reg = <0x0 0xfdcc0000 0x0 0xb000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xfdcc0000 0xb000>; + + /* start address and size should be 4k algin */ + rkvdec_sram: rkvdec-sram@0 { + reg = <0x0 0xb000>; + }; + }; + + pmucru: clock-controller@fdd00000 { + compatible = "rockchip,rk3568-pmucru"; + reg = <0x0 0xfdd00000 0x0 0x1000>; + rockchip,grf = <&grf>; + rockchip,pmugrf = <&pmugrf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = <&pmucru SCLK_32K_IOE>; + assigned-clock-parents = <&pmucru CLK_RTC_32K>; + }; + + cru: clock-controller@fdd20000 { + compatible = "rockchip,rk3568-cru"; + reg = <0x0 0xfdd20000 0x0 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&pmucru CLK_RTC_32K>, <&cru ACLK_RKVDEC_PRE>, + <&cru CLK_RKVDEC_CORE>, <&pmucru PLL_PPLL>, + <&pmucru PCLK_PMU>, <&cru PLL_CPLL>, + <&cru CPLL_500M>, <&cru CPLL_333M>, + <&cru CPLL_250M>, <&cru CPLL_125M>, + <&cru CPLL_100M>, <&cru CPLL_62P5M>, + <&cru CPLL_50M>, <&cru CPLL_25M>, + <&cru PLL_GPLL>, + <&cru ACLK_BUS>, <&cru PCLK_BUS>, + <&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>, + <&cru HCLK_TOP>, <&cru PCLK_TOP>, + <&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>, + <&cru PLL_NPLL>, <&cru ACLK_PIPE>, + <&cru PCLK_PIPE>, <&cru CLK_I2S0_8CH_TX_SRC>, + <&cru CLK_I2S0_8CH_RX_SRC>, <&cru CLK_I2S1_8CH_TX_SRC>, + <&cru CLK_I2S1_8CH_RX_SRC>, <&cru CLK_I2S2_2CH_SRC>, + <&cru CLK_I2S2_2CH_SRC>, <&cru CLK_I2S3_2CH_RX_SRC>, + <&cru CLK_I2S3_2CH_TX_SRC>, <&cru MCLK_SPDIF_8CH_SRC>, + <&cru ACLK_VOP>; + assigned-clock-rates = + <32768>, <300000000>, + <300000000>, <200000000>, + <100000000>, <1000000000>, + <500000000>, <333000000>, + <250000000>, <125000000>, + <100000000>, <62500000>, + <50000000>, <25000000>, + <1188000000>, + <150000000>, <100000000>, + <500000000>, <400000000>, + <150000000>, <100000000>, + <300000000>, <150000000>, + <1200000000>, <400000000>, + <100000000>, <1188000000>, + <1188000000>, <1188000000>, + <1188000000>, <1188000000>, + <1188000000>, <1188000000>, + <1188000000>, <1188000000>, + <500000000>; + assigned-clock-parents = + <&pmucru CLK_RTC32K_FRAC>, <&cru PLL_GPLL>, + <&cru PLL_GPLL>; + }; + + i2c0: i2c@fdd40000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfdd40000 0x0 0x1000>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fdd50000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfdd50000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 0>, <&dmac0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + pwm0: pwm@fdd70000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@fdd70010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@fdd70020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@fdd70030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfdd70030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3_pins>; + clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@fdd90000 { + compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfdd90000 0x0 0x1000>; + + power: power-controller { + compatible = "rockchip,rk3568-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + pd_npu@RK3568_PD_NPU { + reg = ; + clocks = <&cru ACLK_NPU_PRE>, + <&cru HCLK_NPU_PRE>, + <&cru PCLK_NPU_PRE>; + pm_qos = <&qos_npu>; + }; + /* These power domains are grouped by VD_GPU */ + pd_gpu@RK3568_PD_GPU { + reg = ; + clocks = <&cru ACLK_GPU_PRE>, + <&cru PCLK_GPU_PRE>; + pm_qos = <&qos_gpu>; + }; + /* These power domains are grouped by VD_LOGIC */ + pd_vi@RK3568_PD_VI { + reg = ; + clocks = <&cru HCLK_VI>, + <&cru PCLK_VI>; + pm_qos = <&qos_isp>, + <&qos_vicap0>, + <&qos_vicap1>; + }; + pd_vo@RK3568_PD_VO { + reg = ; + clocks = <&cru HCLK_VO>, + <&cru PCLK_VO>, + <&cru ACLK_VOP_PRE>; + pm_qos = <&qos_hdcp>, + <&qos_vop_m0>, + <&qos_vop_m1>; + }; + pd_rga@RK3568_PD_RGA { + reg = ; + clocks = <&cru HCLK_RGA_PRE>, + <&cru PCLK_RGA_PRE>; + pm_qos = <&qos_ebc>, + <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc>, + <&qos_rga_rd>, + <&qos_rga_wr>; + }; + pd_vpu@RK3568_PD_VPU { + reg = ; + clocks = <&cru HCLK_VPU_PRE>; + pm_qos = <&qos_vpu>; + }; + pd_rkvdec@RK3568_PD_RKVDEC { + clocks = <&cru HCLK_RKVDEC_PRE>; + reg = ; + pm_qos = <&qos_rkvdec>; + }; + pd_rkvenc@RK3568_PD_RKVENC { + reg = ; + clocks = <&cru HCLK_RKVENC_PRE>; + pm_qos = <&qos_rkvenc_rd_m0>, + <&qos_rkvenc_rd_m1>, + <&qos_rkvenc_wr_m0>; + }; + pd_pipe@RK3568_PD_PIPE { + reg = ; + clocks = <&cru PCLK_PIPE>; + pm_qos = <&qos_pcie2x1>, + <&qos_pcie3x1>, + <&qos_pcie3x2>, + <&qos_sata0>, + <&qos_sata1>, + <&qos_sata2>, + <&qos_usb3_0>, + <&qos_usb3_1>; + }; + }; + }; + + pvtm@fde00000 { + compatible = "rockchip,rk3568-core-pvtm"; + reg = <0x0 0xfde00000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@0 { + reg = <0>; + clocks = <&cru CLK_CORE_PVTM>, <&cru PCLK_CORE_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_CORE_PVTM>, <&cru SRST_P_CORE_PVTM>; + reset-names = "rts", "rst-p"; + thermal-zone = "soc-thermal"; + }; + }; + + rknpu: npu@fde40000 { + compatible = "rockchip,rk3568-rknpu", "rockchip,rknpu"; + reg = <0x0 0xfde40000 0x0 0x10000>; + interrupts = ; + clocks = <&scmi_clk 2>, <&cru CLK_NPU>, <&cru ACLK_NPU>, <&cru HCLK_NPU>; + clock-names = "scmi_clk", "clk", "aclk", "hclk"; + assigned-clocks = <&cru CLK_NPU>; + assigned-clock-rates = <600000000>; + resets = <&cru SRST_A_NPU>, <&cru SRST_H_NPU>; + reset-names = "srst_a", "srst_h"; + power-domains = <&power RK3568_PD_NPU>; + operating-points-v2 = <&npu_opp_table>; + iommus = <&rknpu_mmu>; + status = "disabled"; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>, + <&specification_serial_number>, <&remark_spec_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number", "remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <1000000>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1000 50000 + >; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 87000 1 + 87001 91000 2 + 91001 100000 3 + >; + rockchip,pvtm-ch = <0 5>; + + /* RK3568 && RK3568M npu OPPs */ + opp-200000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-300000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-400000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-700000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <875000 875000 1000000>; + opp-microvolt-L0 = <875000 875000 1000000>; + opp-microvolt-L1 = <850000 850000 1000000>; + opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; + }; + opp-800000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <925000 925000 1000000>; + opp-microvolt-L0 = <925000 925000 1000000>; + opp-microvolt-L1 = <900000 900000 1000000>; + opp-microvolt-L2 = <875000 875000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + }; + opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <975000 975000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <950000 950000 1000000>; + opp-microvolt-L2 = <925000 925000 1000000>; + opp-microvolt-L3 = <900000 900000 1000000>; + }; + opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; + status = "disabled"; + }; + + /* RK3568J npu OPPs */ + opp-j-600000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + }; + + /* RK3568M npu OPPs */ + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <925000 925000 1000000>; + }; + }; + + bus_npu: bus-npu { + compatible = "rockchip,rk3568-bus"; + rockchip,busfreq-policy = "clkfreq"; + clocks = <&scmi_clk 2>; + clock-names = "bus"; + operating-points-v2 = <&bus_npu_opp_table>; + status = "disabled"; + }; + + bus_npu_opp_table: bus-npu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&core_pvtm>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 91000 1 + 91001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <875000>; + opp-microvolt-L2 = <875000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <900000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <925000>; + opp-microvolt-L2 = <900000>; + }; + }; + + rknpu_mmu: iommu@fde4b000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfde4b000 0x0 0x40>; + interrupts = ; + interrupt-names = "rknpu_mmu"; + clocks = <&cru ACLK_NPU>, <&cru HCLK_NPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_NPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + gpu: gpu@fde60000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xfde60000 0x0 0x4000>; + + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + + upthreshold = <40>; + downdifferential = <10>; + + clocks = <&scmi_clk 1>, <&cru CLK_GPU>; + clock-names = "clk_mali", "clk_gpu"; + power-domains = <&power RK3568_PD_GPU>; + #cooling-cells = <2>; + operating-points-v2 = <&gpu_opp_table>; + + status = "disabled"; + gpu_power_model: power-model { + compatible = "simple-power-model"; + leakage-range= <5 15>; + ls = <(-24002) 22823 0>; + static-coefficient = <100000>; + dynamic-coefficient = <953>; + ts = <(-108890) 63610 (-1355) 20>; + thermal-zone = "gpu-thermal"; + }; + }; + + gpu_opp_table: opp-table2 { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>, + <&specification_serial_number>, <&remark_spec_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number", "remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <1000000>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 800 50000 + >; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 87000 1 + 87001 91000 2 + 91001 100000 3 + >; + rockchip,pvtm-ch = <0 5>; + + /* RK3568 && RK3568M gpu OPPs */ + opp-200000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-300000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-400000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <850000 850000 1000000>; + }; + opp-600000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>; + opp-microvolt-L2 = <850000 850000 1000000>; + opp-microvolt-L3 = <850000 850000 1000000>; + }; + opp-700000000 { + opp-supported-hw = <0xfb 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <950000 950000 1000000>; + opp-microvolt-L0 = <950000 950000 1000000>; + opp-microvolt-L1 = <925000 925000 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>; + opp-microvolt-L3 = <875000 875000 1000000>; + }; + opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <1000000 1000000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <950000 950000 1000000>; + opp-microvolt-L3 = <925000 925000 1000000>; + }; + + /* RK3568J gpu OPPs */ + opp-j-600000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 1000000>; + }; + + /* RK3568M gpu OPPs */ + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <950000 950000 1000000>; + }; + + }; + + pvtm@fde80000 { + compatible = "rockchip,rk3568-gpu-pvtm"; + reg = <0x0 0xfde80000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@1 { + reg = <1>; + clocks = <&cru CLK_GPU_PVTM>, <&cru PCLK_GPU_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; + reset-names = "rts", "rst-p"; + thermal-zone = "gpu-thermal"; + }; + }; + + pvtm@fde90000 { + compatible = "rockchip,rk3568-npu-pvtm"; + reg = <0x0 0xfde90000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@2 { + reg = <2>; + clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>, + <&cru HCLK_NPU_PRE>; + clock-names = "clk", "pclk", "hclk"; + resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; + reset-names = "rts", "rst-p"; + thermal-zone = "soc-thermal"; + }; + }; + + vdpu: vdpu@fdea0400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xfdea0400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; + reset-names = "video_a", "video_h"; + iommus = <&vdpu_mmu>; + power-domains = <&power RK3568_PD_VPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + vdpu_mmu: iommu@fdea0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdea0800 0x0 0x40>; + interrupts = ; + interrupt-names = "vdpu_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + power-domains = <&power RK3568_PD_VPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rk_rga: rk_rga@fdeb0000 { + compatible = "rockchip,rga2"; + reg = <0x0 0xfdeb0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>; + clock-names = "aclk_rga", "hclk_rga", "clk_rga"; + power-domains = <&power RK3568_PD_RGA>; + status = "disabled"; + }; + + ebc: ebc@fdec0000 { + compatible = "rockchip,rk3568-ebc-tcon"; + reg = <0x0 0xfdec0000 0x0 0x5000>; + interrupts = ; + clocks = <&cru HCLK_EBC>, <&cru DCLK_EBC>; + clock-names = "hclk", "dclk"; + power-domains = <&power RK3568_PD_RGA>; + rockchip,grf = <&grf>; + pinctrl-names = "default"; + pinctrl-0 = <&ebc_pins>; + status = "disabled"; + }; + + jpegd: jpegd@fded0000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xfded0000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,disable-auto-freq; + resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>; + reset-names = "video_a", "video_h"; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + rockchip,resetgroup-node = <1>; + power-domains = <&power RK3568_PD_RGA>; + status = "disabled"; + }; + + jpegd_mmu: iommu@fded0480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfded0480 0x0 0x40>; + interrupts = ; + interrupt-names = "jpegd_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>; + power-domains = <&power RK3568_PD_RGA>; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu: vepu@fdee0000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xfdee0000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,disable-auto-freq; + resets = <&cru SRST_A_JENC>, <&cru SRST_H_JENC>; + reset-names = "video_a", "video_h"; + iommus = <&vepu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,resetgroup-node = <2>; + power-domains = <&power RK3568_PD_RGA>; + status = "disabled"; + }; + + vepu_mmu: iommu@fdee0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdee0800 0x0 0x40>; + interrupts = ; + interrupt-names = "vepu_mmu"; + clock-names = "aclk", "iface"; + clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>; + power-domains = <&power RK3568_PD_RGA>; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep: iep@fdef0000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xfdef0000 0x0 0x500>; + interrupts = ; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>, <&cru CLK_IEP_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_A_IEP>, <&cru SRST_H_IEP>, + <&cru SRST_IEP_CORE>; + reset-names = "rst_a", "rst_h", "rst_s"; + power-domains = <&power RK3568_PD_RGA>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <5>; + rockchip,resetgroup-node = <5>; + iommus = <&iep_mmu>; + status = "disabled"; + }; + + iep_mmu: iommu@fdef0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdef0800 0x0 0x100>; + interrupts = ; + interrupt-names = "iep_mmu"; + clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_RGA>; + //rockchip,disable-device-link-resume; + status = "disabled"; + }; + + eink: eink@fdf00000 { + compatible = "rockchip,rk3568-eink-tcon"; + reg = <0x0 0xfdf00000 0x0 0x74>; + interrupts = ; + clocks = <&cru PCLK_EINK>, <&cru HCLK_EINK>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + + rkvenc: rkvenc@fdf40000 { + compatible = "rockchip,rkv-encoder-v1"; + reg = <0x0 0xfdf40000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_enc"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, + <&cru CLK_RKVENC_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <297000000>, <0>, <297000000>; + resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>, + <&cru SRST_RKVENC_CORE>; + reset-names = "video_a", "video_h", "video_core"; + assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>; + assigned-clock-rates = <297000000>, <297000000>; + iommus = <&rkvenc_mmu>; + node-name = "rkvenc"; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <3>; + rockchip,resetgroup-node = <3>; + power-domains = <&power RK3568_PD_RKVENC>; + operating-points-v2 = <&rkvenc_opp_table>; + status = "disabled"; + }; + + rkvenc_opp_table: rkvenc-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&core_pvtm>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 91000 1 + 91001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <875000>; + opp-microvolt-L2 = <875000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <950000>; + opp-microvolt-L0 = <950000>; + opp-microvolt-L1 = <925000>; + opp-microvolt-L2 = <900000>; + }; + }; + + rkvenc_mmu: iommu@fdf40f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdf40f00 0x0 0x40>, <0x0 0xfdf40f40 0x0 0x40>; + interrupts = , + ; + interrupt-names = "rkvenc_mmu0", "rkvenc_mmu1"; + clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + #iommu-cells = <0>; + power-domains = <&power RK3568_PD_RKVENC>; + status = "disabled"; + }; + + rkvdec: rkvdec@fdf80200 { + compatible = "rockchip,rkv-decoder-rk3568", "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdf80200 0x0 0x400>, <0x0 0xfdf80100 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_dec"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru CLK_RKVDEC_CA>, <&cru CLK_RKVDEC_CORE>, + <&cru CLK_RKVDEC_HEVC_CA>; + clock-names = "aclk_vcodec", "hclk_vcodec","clk_cabac", + "clk_core", "clk_hevc_cabac"; + rockchip,normal-rates = <297000000>, <0>, <297000000>, + <297000000>, <600000000>; + rockchip,advanced-rates = <396000000>, <0>, <396000000>, + <396000000>, <600000000>; + rockchip,default-max-load = <2088960>; + resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>, + <&cru SRST_RKVDEC_CA>, <&cru SRST_RKVDEC_CORE>, + <&cru SRST_RKVDEC_HEVC_CA>; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_CA>, + <&cru CLK_RKVDEC_CORE>, <&cru CLK_RKVDEC_HEVC_CA>; + assigned-clock-rates = <297000000>, <297000000>, <297000000>, <297000000>; + reset-names = "video_a", "video_h", "video_cabac", + "video_core", "video_hevc_cabac"; + power-domains = <&power RK3568_PD_RKVDEC>; + operating-points-v2 = <&rkvdec_opp_table>; + vdec-supply = <&vdd_logic>; + iommus = <&rkvdec_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <4>; + rockchip,resetgroup-node = <4>; + rockchip,sram = <&rkvdec_sram>; + /* rcb_iova: start and size */ + rockchip,rcb-iova = <0x10000000 65536>; + rockchip,rcb-min-width = <512>; + rockchip,task-capacity = <16>; + status = "disabled"; + }; + + rkvdec_opp_table: rkvdec-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&log_leakage>, <&core_pvtm>; + nvmem-cell-names = "leakage", "pvtm"; + rockchip,leakage-voltage-sel = < + 1 80 0 + 81 254 1 + >; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 100000 1 + >; + rockchip,pvtm-ch = <0 5>; + + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <900000>; + opp-microvolt-L0 = <900000>; + opp-microvolt-L1 = <875000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + }; + + rkvdec_mmu: iommu@fdf80800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdf80800 0x0 0x40>, <0x0 0xfdf80840 0x0 0x40>; + interrupts = ; + interrupt-names = "rkvdec_mmu"; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_RKVDEC>; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi_csi2_hw: mipi-csi2-hw@fdfb0000 { + compatible = "rockchip,rk3568-mipi-csi2-hw"; + reg = <0x0 0xfdfb0000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI2HOST1>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI2HOST1>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + rkcif: rkcif@fdfe0000 { + compatible = "rockchip,rk3568-cif"; + reg = <0x0 0xfdfe0000 0x0 0x8000>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>, <&cru ICLK_VICAP_G>; + clock-names = "aclk_cif", "hclk_cif", + "dclk_cif", "iclk_cif_g"; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>, <&cru SRST_P_VICAP>, + <&cru SRST_I_VICAP>; + reset-names = "rst_cif_a", "rst_cif_h", + "rst_cif_d", "rst_cif_p", + "rst_cif_i"; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <300000000>; + power-domains = <&power RK3568_PD_VI>; + rockchip,grf = <&grf>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mmu: iommu@fdfe0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdfe0800 0x0 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_VI>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + rkcif_dvp: rkcif_dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <&rkcif>; + status = "disabled"; + }; + + rkcif_dvp_sditf: rkcif_dvp_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_dvp>; + status = "disabled"; + }; + + rkcif_mipi_lvds: rkcif_mipi_lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif_mipi_lvds_sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkisp: rkisp@fdff0000 { + compatible = "rockchip,rk3568-rkisp"; + reg = <0x0 0xfdff0000 0x0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp"; + resets = <&cru SRST_ISP>, <&cru SRST_H_ISP>; + reset-names = "isp", "isp-h"; + rockchip,grf = <&grf>; + power-domains = <&power RK3568_PD_VI>; + iommus = <&rkisp_mmu>; + rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>; + status = "disabled"; + }; + + rkisp_mmu: iommu@fdff1a00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdff1a00 0x0 0x100>; + interrupts = ; + interrupt-names = "isp_mmu"; + clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3568_PD_VI>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkisp_vir0: rkisp-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + rkisp_vir1: rkisp-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp>; + status = "disabled"; + }; + + gmac_uio1: uio@fe010000 { + compatible = "rockchip,uio-gmac"; + reg = <0x0 0xfe010000 0x0 0x10000>; + rockchip,ethernet = <&gmac1>; + status = "disabled"; + }; + + gmac1: ethernet@fe010000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe010000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>, + <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>, + <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>, + <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref", + "pclk_xpcs", "clk_xpcs_eee"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + vop: vop@fe040000 { + compatible = "rockchip,rk3568-vop"; + reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>; + reg-names = "regs", "gamma_lut"; + rockchip,grf = <&grf>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>; + clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp0>; + }; + + vp0_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp0>; + }; + + vp0_out_edp: endpoint@2 { + reg = <2>; + remote-endpoint = <&edp_in_vp0>; + }; + + vp0_out_hdmi: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_in_vp0>; + }; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp1>; + }; + + vp1_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp1>; + }; + + vp1_out_edp: endpoint@2 { + reg = <2>; + remote-endpoint = <&edp_in_vp1>; + }; + + vp1_out_hdmi: endpoint@3 { + reg = <3>; + remote-endpoint = <&hdmi_in_vp1>; + }; + + vp1_out_lvds: endpoint@4 { + reg = <4>; + remote-endpoint = <&lvds_in_vp1>; + }; + + vp1_out_lvds1: endpoint@5 { + reg = <5>; + remote-endpoint = <&lvds1_in_vp1>; + }; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <2>; + + vp2_out_lvds: endpoint@0 { + reg = <0>; + remote-endpoint = <&lvds_in_vp2>; + }; + + vp2_out_rgb: endpoint@1 { + reg = <1>; + remote-endpoint = <&rgb_in_vp2>; + }; + + vp2_out_lvds1: endpoint@2 { + reg = <2>; + remote-endpoint = <&lvds1_in_vp2>; + }; + }; + }; + }; + + vop_mmu: iommu@fe043e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + status = "disabled"; + }; + + dsi0: dsi@fe060000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x0 0xfe060000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>; + clock-names = "pclk", "hclk"; + resets = <&cru SRST_P_DSITX_0>; + reset-names = "apb"; + phys = <&video_phy0>; + phy-names = "dphy"; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi0>; + status = "disabled"; + }; + + dsi0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi0>; + status = "disabled"; + }; + }; + }; + }; + + dsi1: dsi@fe070000 { + compatible = "rockchip,rk3568-mipi-dsi"; + reg = <0x0 0xfe070000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>; + clock-names = "pclk", "hclk"; + resets = <&cru SRST_P_DSITX_1>; + reset-names = "apb"; + phys = <&video_phy1>; + phy-names = "dphy"; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dsi1>; + status = "disabled"; + }; + + dsi1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dsi1>; + status = "disabled"; + }; + }; + }; + }; + + hdmi: hdmi@fe0a0000 { + compatible = "rockchip,rk3568-dw-hdmi"; + reg = <0x0 0xfe0a0000 0x0 0x20000>; + interrupts = ; + clocks = <&cru PCLK_HDMI_HOST>, + <&cru CLK_HDMI_SFR>, + <&cru CLK_HDMI_CEC>, + <&pmucru PLL_HPLL>, + <&cru HCLK_VOP>; + clock-names = "iahb", "isfr", "cec", "ref", "hclk"; + power-domains = <&power RK3568_PD_VO>; + reg-io-width = <4>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi>; + status = "disabled"; + }; + + hdmi_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi>; + status = "disabled"; + }; + }; + }; + }; + + edp: edp@fe0c0000 { + compatible = "rockchip,rk3568-edp"; + reg = <0x0 0xfe0c0000 0x0 0x10000>; + interrupts = ; + clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDP_CTRL>, + <&cru CLK_EDP_200M>, <&cru HCLK_VO>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru SRST_EDP_24M>, <&cru SRST_P_EDP_CTRL>; + reset-names = "dp", "apb"; + phys = <&edp_phy>; + phy-names = "dp"; + power-domains = <&power RK3568_PD_VO>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + edp_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp>; + status = "disabled"; + }; + + edp_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp>; + status = "disabled"; + }; + }; + }; + }; + + nocp_cpu: nocp-cpu@fe102000 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x0 0xfe102000 0x0 0x400>; + }; + + nocp_gpu_vpu_rga_venc: nocp-gpu-vpu-rga-venc@fe102400 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x0 0xfe102400 0x0 0x400>; + }; + + nocp_npu_vdec: nocp-vdec@fe102800 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x0 0xfe102800 0x0 0x400>; + }; + + nocp_vi_usb_peri_pipe: nocp-vi-usb-peri-pipe@fe102c00 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x0 0xfe102c00 0x0 0x400>; + }; + + nocp_vo: nocp-vo@fe103000 { + compatible = "rockchip,rk3568-nocp"; + reg = <0x0 0xfe103000 0x0 0x400>; + }; + + qos_gpu: qos@fe128000 { + compatible = "syscon"; + reg = <0x0 0xfe128000 0x0 0x20>; + }; + + qos_rkvenc_rd_m0: qos@fe138080 { + compatible = "syscon"; + reg = <0x0 0xfe138080 0x0 0x20>; + }; + + qos_rkvenc_rd_m1: qos@fe138100 { + compatible = "syscon"; + reg = <0x0 0xfe138100 0x0 0x20>; + }; + + qos_rkvenc_wr_m0: qos@fe138180 { + compatible = "syscon"; + reg = <0x0 0xfe138180 0x0 0x20>; + }; + + qos_isp: qos@fe148000 { + compatible = "syscon"; + reg = <0x0 0xfe148000 0x0 0x20>; + }; + + qos_vicap0: qos@fe148080 { + compatible = "syscon"; + reg = <0x0 0xfe148080 0x0 0x20>; + }; + + qos_vicap1: qos@fe148100 { + compatible = "syscon"; + reg = <0x0 0xfe148100 0x0 0x20>; + }; + + qos_vpu: qos@fe150000 { + compatible = "syscon"; + reg = <0x0 0xfe150000 0x0 0x20>; + }; + + qos_ebc: qos@fe158000 { + compatible = "syscon"; + reg = <0x0 0xfe158000 0x0 0x20>; + }; + + qos_iep: qos@fe158100 { + compatible = "syscon"; + reg = <0x0 0xfe158100 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fe158180 { + compatible = "syscon"; + reg = <0x0 0xfe158180 0x0 0x20>; + }; + + qos_jpeg_enc: qos@fe158200 { + compatible = "syscon"; + reg = <0x0 0xfe158200 0x0 0x20>; + }; + + qos_rga_rd: qos@fe158280 { + compatible = "syscon"; + reg = <0x0 0xfe158280 0x0 0x20>; + }; + + qos_rga_wr: qos@fe158300 { + compatible = "syscon"; + reg = <0x0 0xfe158300 0x0 0x20>; + }; + + qos_npu: qos@fe180000 { + compatible = "syscon"; + reg = <0x0 0xfe180000 0x0 0x20>; + }; + + qos_pcie2x1: qos@fe190000 { + compatible = "syscon"; + reg = <0x0 0xfe190000 0x0 0x20>; + }; + + qos_pcie3x1: qos@fe190080 { + compatible = "syscon"; + reg = <0x0 0xfe190080 0x0 0x20>; + }; + + qos_pcie3x2: qos@fe190100 { + compatible = "syscon"; + reg = <0x0 0xfe190100 0x0 0x20>; + }; + + qos_sata0: qos@fe190200 { + compatible = "syscon"; + reg = <0x0 0xfe190200 0x0 0x20>; + }; + + qos_sata1: qos@fe190280 { + compatible = "syscon"; + reg = <0x0 0xfe190280 0x0 0x20>; + }; + + qos_sata2: qos@fe190300 { + compatible = "syscon"; + reg = <0x0 0xfe190300 0x0 0x20>; + }; + + qos_usb3_0: qos@fe190380 { + compatible = "syscon"; + reg = <0x0 0xfe190380 0x0 0x20>; + }; + + qos_usb3_1: qos@fe190400 { + compatible = "syscon"; + reg = <0x0 0xfe190400 0x0 0x20>; + }; + + qos_rkvdec: qos@fe198000 { + compatible = "syscon"; + reg = <0x0 0xfe198000 0x0 0x20>; + }; + + qos_hdcp: qos@fe1a8000 { + compatible = "syscon"; + reg = <0x0 0xfe1a8000 0x0 0x20>; + }; + + qos_vop_m0: qos@fe1a8080 { + compatible = "syscon"; + reg = <0x0 0xfe1a8080 0x0 0x20>; + }; + + qos_vop_m1: qos@fe1a8100 { + compatible = "syscon"; + reg = <0x0 0xfe1a8100 0x0 0x20>; + }; + + sdmmc2: dwmmc@fe000000 { + compatible = "rockchip,rk3568-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe000000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>, + <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + resets = <&cru SRST_SDMMC2>; + reset-names = "reset"; + status = "disabled"; + }; + + dfi: dfi@fe230000 { + reg = <0x00 0xfe230000 0x00 0x400>; + compatible = "rockchip,rk3568-dfi"; + rockchip,pmugrf = <&pmugrf>; + status = "disabled"; + }; + + dmc: dmc { + compatible = "rockchip,rk3568-dmc"; + interrupts = ; + interrupt-names = "complete"; + devfreq-events = <&dfi>, <&nocp_cpu>; + clocks = <&scmi_clk 3>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + vop-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 286 324000 + 287 99999 528000 + >; + vop-frame-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 620 324000 + 621 99999 780000 + >; + cpu-bw-dmc-freq = < + /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ + 0 350 324000 + 351 400 528000 + 401 99999 780000 + >; + upthreshold = <40>; + downdifferential = <20>; + system-status-level = < + /*system status freq level*/ + SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH + SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW + SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH + SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH + SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH + SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH + >; + auto-min-freq = <324000>; + auto-freq-en = <1>; + #cooling-cells = <2>; + status = "disabled"; + }; + + dmc_fsp: dmc-fsp { + compatible = "rockchip,rk3568-dmc-fsp"; + + debug_print_level = <0>; + ddr3_params = <&ddr3_params>; + ddr4_params = <&ddr4_params>; + lpddr3_params = <&lpddr3_params>; + lpddr4_params = <&lpddr4_params>; + lpddr4x_params = <&lpddr4x_params>; + + status = "okay"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>, + <&specification_serial_number>, <&remark_spec_serial_number>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info", + "specification_serial_number", "remark_spec_serial_number"; + rockchip,supported-hw; + rockchip,max-volt = <1000000>; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1560 75000 + >; + rockchip,leakage-voltage-sel = < + 1 80 0 + 81 254 1 + >; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 100000 1 + >; + rockchip,pvtm-ch = <0 5>; + + /* RK3568 dmc OPPs */ + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <900000 900000 1000000>; + opp-microvolt-L0 = <900000 900000 1000000>; + opp-microvolt-L1 = <875000 875000 1000000>; + }; + + /* RK3568J/M dmc OPPs */ + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <875000 875000 1000000>; + }; + }; + + pcie2x1: pcie@fe260000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x0 0xf>; + clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>, + <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>, + <&cru CLK_PCIE20_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, + <0 0 0 2 &pcie2x1_intc 1>, + <0 0 0 3 &pcie2x1_intc 2>, + <0 0 0 4 &pcie2x1_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <6>; + num-viewport = <8>; + num-ob-windows = <2>; + max-link-speed = <2>; + msi-map = <0x0 &its 0x0 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psq PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 + 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 + 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x1e00000 + 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>; + reg = <0x3 0xc0000000 0x0 0x400000>, + <0x0 0xfe260000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE20_POWERUP>; + reset-names = "pipe"; + status = "disabled"; + + pcie2x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie3x1: pcie@fe270000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>, + <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>, + <&cru CLK_PCIE30X1_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x1_intc 0>, + <0 0 0 2 &pcie3x1_intc 1>, + <0 0 0 3 &pcie3x1_intc 2>, + <0 0 0 4 &pcie3x1_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <6>; + num-ob-windows = <2>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x1000 &its 0x1000 0x1000>; + num-lanes = <1>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 + 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 + 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x1e00000 + 0xc3000000 0x3 0x40000000 0x3 0x40000000 0x0 0x40000000>; + reg = <0x3 0xc0400000 0x0 0x400000>, + <0x0 0xfe270000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE30X1_POWERUP>; + reset-names = "pipe"; + /* rockchip,bifurcation; lane1 when using 1+1 */ + status = "disabled"; + + pcie3x1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie3x2: pcie@fe280000 { + compatible = "rockchip,rk3568-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>, + <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>, + <&cru CLK_PCIE30X2_AUX_NDFT>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", "aux"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <6>; + num-viewport = <8>; + num-ob-windows = <2>; + max-link-speed = <3>; + msi-map = <0x2000 &its 0x2000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3568_PD_PIPE>; + ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 + 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 + 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x1e00000 + 0xc3000000 0x3 0x80000000 0x3 0x80000000 0x0 0x40000000>; + reg = <0x3 0xc0800000 0x0 0x400000>, + <0x0 0xfe280000 0x0 0x10000>; + reg-names = "pcie-dbi", "pcie-apb"; + resets = <&cru SRST_PCIE30X2_POWERUP>; + reset-names = "pipe"; + /* rockchip,bifurcation; lane0 when using 1+1 */ + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac_uio0: uio@fe2a0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + rockchip,ethernet = <&gmac0>; + status = "disabled"; + }; + + gmac0: ethernet@fe2a0000 { + compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe2a0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>, + <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>, + <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>, + <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_refout", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref", + "pclk_xpcs", "clk_xpcs_eee"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sdmmc0: dwmmc@fe2b0000 { + compatible = "rockchip,rk3568-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>, + <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + resets = <&cru SRST_SDMMC0>; + reset-names = "reset"; + status = "disabled"; + }; + + sdmmc1: dwmmc@fe2c0000 { + compatible = "rockchip,rk3568-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + max-frequency = <150000000>; + clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>, + <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + resets = <&cru SRST_SDMMC1>; + reset-names = "reset"; + status = "disabled"; + }; + + sfc: spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdhci: sdhci@fe310000 { + compatible = "rockchip,rk3568-dwcmshc", "rockchip,dwcmshc-sdhci"; + reg = <0x0 0xfe310000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + nandc0: nandc@fe330000 { + compatible = "rockchip,rk-nandc-v9"; + reg = <0x0 0xfe330000 0x0 0x4000>; + interrupts = ; + nandc_id = <0>; + clocks = <&cru NCLK_NANDC>, <&cru HCLK_NANDC>; + clock-names = "clk_nandc", "hclk_nandc"; + status = "disabled"; + }; + + crypto: crypto@fe380000 { + compatible = "rockchip,rk3568-crypto"; + reg = <0x0 0xfe380000 0x0 0x4000>; + interrupts = ; + clocks = <&cru ACLK_CRYPTO_NS>, <&cru HCLK_CRYPTO_NS>, + <&cru CLK_CRYPTO_NS_CORE>, <&cru CLK_CRYPTO_NS_PKA>; + clock-names = "aclk", "hclk", "sclk", "apb_pclk"; + assigned-clocks = <&cru CLK_CRYPTO_NS_CORE>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_CRYPTO_NS_CORE>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@fe388000 { + compatible = "rockchip,cryptov2-rng"; + reg = <0x0 0xfe388000 0x0 0x2000>; + clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>; + clock-names = "clk_trng", "hclk_trng"; + resets = <&cru SRST_TRNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + otp: otp@fe38c000 { + compatible = "rockchip,rk3568-otp"; + reg = <0x0 0xfe38c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS_USR>, <&cru CLK_OTPC_NS_SBPI>, + <&cru PCLK_OTPC_NS>, <&cru PCLK_OTPPHY>; + clock-names = "usr", "sbpi", "apb", "phy"; + resets = <&cru SRST_OTPPHY>; + reset-names = "otp_phy"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + specification_serial_number: specification-serial-number@7 { + reg = <0x07 0x1>; + bits = <0 5>; + }; + otp_cpu_version: cpu-version@8 { + reg = <0x08 0x1>; + bits = <3 3>; + }; + mbist_vmin: mbist-vmin@9 { + reg = <0x09 0x1>; + bits = <0 4>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpu_leakage: cpu-leakage@1a { + reg = <0x1a 0x1>; + }; + log_leakage: log-leakage@1b { + reg = <0x1b 0x1>; + }; + npu_leakage: npu-leakage@1c { + reg = <0x1c 0x1>; + }; + gpu_leakage: gpu-leakage@1d { + reg = <0x1d 0x1>; + }; + core_pvtm:core-pvtm@2a { + reg = <0x2a 0x2>; + }; + cpu_tsadc_trim_l: cpu-tsadc-trim-l@2e { + reg = <0x2e 0x1>; + }; + cpu_tsadc_trim_h: cpu-tsadc-trim-h@2f { + reg = <0x2f 0x1>; + bits = <0 4>; + }; + gpu_tsadc_trim_l: npu-tsadc-trim-l@30 { + reg = <0x30 0x1>; + }; + gpu_tsadc_trim_h: npu-tsadc-trim-h@31 { + reg = <0x31 0x1>; + bits = <0 4>; + }; + tsadc_trim_base_frac: tsadc-trim-base-frac@31 { + reg = <0x31 0x1>; + bits = <4 4>; + }; + tsadc_trim_base: tsadc-trim-base@32 { + reg = <0x32 0x1>; + }; + cpu_opp_info: cpu-opp-info@36 { + reg = <0x36 0x6>; + }; + gpu_opp_info: gpu-opp-info@3c { + reg = <0x3c 0x6>; + }; + npu_opp_info: npu-opp-info@42 { + reg = <0x42 0x6>; + }; + dmc_opp_info: dmc-opp-info@48 { + reg = <0x48 0x6>; + }; + remark_spec_serial_number: remark-spec-serial-number@56 { + reg = <0x56 0x1>; + bits = <0 5>; + }; + }; + + i2s0_8ch: i2s@fe400000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe400000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 0>; + dma-names = "tx"; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe410000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe410000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_sclkrx + &i2s1m0_lrcktx + &i2s1m0_lrckrx + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe420000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe420000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 4>, <&dmac1 5>; + dma-names = "tx", "rx"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,clk-trcm = <1>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2m0_sclktx + &i2s2m0_lrcktx + &i2s2m0_sdi + &i2s2m0_sdo>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>, <&cru HCLK_I2S3_2CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac1 6>, <&dmac1 7>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,clk-trcm = <1>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s3m0_sclk + &i2s3m0_lrck + &i2s3m0_sdi + &i2s3m0_sdo>; + status = "disabled"; + }; + + pdm: pdm@fe440000 { + compatible = "rockchip,rk3568-pdm", "rockchip,pdm"; + reg = <0x0 0xfe440000 0x0 0x1000>; + clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac1 9>; + dma-names = "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm0_clk + &pdmm0_clk1 + &pdmm0_sdi0 + &pdmm0_sdi1 + &pdmm0_sdi2 + &pdmm0_sdi3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + vad: vad@fe450000 { + compatible = "rockchip,rk3568-vad"; + reg = <0x0 0xfe450000 0x0 0x10000>; + reg-names = "vad"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = ; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_8ch: spdif@fe460000 { + compatible = "rockchip,rk3568-spdif"; + reg = <0x0 0xfe460000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 1>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm0_tx>; + status = "disabled"; + }; + + audpwm: audpwm@fe470000 { + compatible = "rockchip,rk3568-audio-pwm", "rockchip,audio-pwm-v1"; + reg = <0x0 0xfe470000 0x0 0x1000>; + clocks = <&cru SCLK_AUDPWM>, <&cru HCLK_AUDPWM>; + clock-names = "clk", "hclk"; + dmas = <&dmac1 8>; + dma-names = "tx"; + #sound-dai-cells = <0>; + rockchip,sample-width-bits = <11>; + rockchip,interpolat-points = <1>; + status = "disabled"; + }; + + dig_acodec: codec-digital@fe478000 { + compatible = "rockchip,rk3568-codec-digital", "rockchip,codec-digital-v1"; + reg = <0x0 0xfe478000 0x0 0x1000>; + clocks = <&cru CLK_ACDCDIG_ADC>, <&cru CLK_ACDCDIG_DAC>, + <&cru CLK_ACDCDIG_I2C>, <&cru HCLK_ACDCDIG>; + clock-names = "adc", "dac", "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&acodec_pins>; + resets = <&cru SRST_ACDCDIG>; + reset-names = "reset" ; + rockchip,grf = <&grf>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dmac0: dmac@fe530000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe530000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + dmac1: dmac@fe550000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfe550000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_BUS>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + scr: rkscr@fe560000 { + compatible = "rockchip-scr"; + reg = <0x0 0xfe560000 0x0 0x10000>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&scr_pins>; + clocks = <&cru PCLK_SCR>; + clock-names = "g_pclk_sim_card"; + status = "disabled"; + }; + + can0: can@fe570000 { + compatible = "rockchip,rk3568-can-2.0"; + reg = <0x0 0xfe570000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; + reset-names = "can", "can-apb"; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can1: can@fe580000 { + compatible = "rockchip,rk3568-can-2.0"; + reg = <0x0 0xfe580000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; + reset-names = "can", "can-apb"; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can2: can@fe590000 { + compatible = "rockchip,rk3568-can-2.0"; + reg = <0x0 0xfe590000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; + reset-names = "can", "can-apb"; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + i2c1: i2c@fe5a0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5a0000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@fe5b0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5b0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@fe5c0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5c0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@fe5d0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5d0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fe5e0000 { + compatible = "rockchip,rk3399-i2c"; + reg = <0x0 0xfe5e0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rktimer: timer@fe5f0000 { + compatible = "rockchip,rk3568-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfe5f0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@fe600000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfe600000 0x0 0x100>; + clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "okay"; + }; + + spi0: spi@fe610000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfe610000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 20>, <&dmac0 21>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + pinctrl-1 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + spi1: spi@fe620000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfe620000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 22>, <&dmac0 23>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>; + pinctrl-1 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + spi2: spi@fe630000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfe630000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 24>, <&dmac0 25>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>; + pinctrl-1 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + spi3: spi@fe640000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfe640000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 26>, <&dmac0 27>; + dma-names = "tx", "rx"; + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>; + pinctrl-1 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins_hs>; + num-cs = <2>; + status = "disabled"; + }; + + uart1: serial@fe650000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe650000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 2>, <&dmac0 3>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + status = "disabled"; + }; + + uart2: serial@fe660000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe660000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 4>, <&dmac0 5>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "disabled"; + }; + + uart3: serial@fe670000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe670000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + status = "disabled"; + }; + + uart4: serial@fe680000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe680000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + status = "disabled"; + }; + + uart5: serial@fe690000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe690000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + status = "disabled"; + }; + + uart6: serial@fe6a0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; + status = "disabled"; + }; + + uart7: serial@fe6b0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6b0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 14>, <&dmac0 15>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; + status = "disabled"; + }; + + uart8: serial@fe6c0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6c0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 16>, <&dmac0 17>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; + status = "disabled"; + }; + + uart9: serial@fe6d0000 { + compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfe6d0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 18>, <&dmac0 19>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; + status = "disabled"; + }; + + pwm4: pwm@fe6e0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@fe6e0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@fe6e0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@fe6e0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6e0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@fe6f0000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@fe6f0010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@fe6f0020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@fe6f0030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe6f0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@fe700000 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@fe700010 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@fe700020 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@fe700030 { + compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfe700030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + tsadc: tsadc@fe710000 { + compatible = "rockchip,rk3568-tsadc"; + reg = <0x0 0xfe710000 0x0 0x100>; + interrupts = ; + rockchip,grf = <&grf>; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>; + assigned-clock-rates = <17000000>, <700000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, + <&cru SRST_TSADCPHY>; + reset-names = "tsadc", "tsadc-apb", "tsadc-phy"; + #thermal-sensor-cells = <1>; + nvmem-cells = <&tsadc_trim_base>, <&tsadc_trim_base_frac>; + nvmem-cell-names = "trim_base", "trim_base_frac"; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shutorg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + tsadc@0 { + reg = <0>; + nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + tsadc@1 { + reg = <1>; + nvmem-cells = <&gpu_tsadc_trim_l>, <&gpu_tsadc_trim_h>; + nvmem-cell-names = "trim_l", "trim_h"; + }; + }; + + saradc: saradc@fe720000 { + compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc"; + reg = <0x0 0xfe720000 0x0 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + mailbox: mailbox@fe780000 { + compatible = "rockchip,rk3568-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfe780000 0x0 0x1000>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + combphy0_us: phy@fe820000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe820000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>, + <&cru PCLK_PIPE>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf0>; + status = "disabled"; + }; + + combphy1_usq: phy@fe830000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe830000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>, + <&cru PCLK_PIPE>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf1>; + status = "disabled"; + }; + + combphy2_psq: phy@fe840000 { + compatible = "rockchip,rk3568-naneng-combphy"; + reg = <0x0 0xfe840000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>, + <&cru PCLK_PIPE>; + clock-names = "refclk", "apbclk", "pipe_clk"; + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&pipegrf>; + rockchip,pipe-phy-grf = <&pipe_phy_grf2>; + status = "disabled"; + }; + + video_phy0: phy@fe850000 { + compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; + reg = <0x0 0xfe850000 0x0 0x10000>, + <0x0 0xfe060000 0x0 0x10000>; + reg-names = "phy", "host"; + clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, + <&cru PCLK_MIPIDSIPHY0>, <&cru PCLK_DSITX_0>; + clock-names = "ref", "pclk", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_MIPIDSIPHY0>; + reset-names = "apb"; + power-domains = <&power RK3568_PD_VO>; + #phy-cells = <0>; + status = "disabled"; + }; + + video_phy1: phy@fe860000 { + compatible = "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy"; + reg = <0x0 0xfe860000 0x0 0x10000>, + <0x0 0xfe070000 0x0 0x10000>; + reg-names = "phy", "host"; + clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, + <&cru PCLK_MIPIDSIPHY1>, <&cru PCLK_DSITX_1>; + clock-names = "ref", "pclk", "pclk_host"; + #clock-cells = <0>; + resets = <&cru SRST_P_MIPIDSIPHY1>; + reset-names = "apb"; + power-domains = <&power RK3568_PD_VO>; + #phy-cells = <0>; + status = "disabled"; + }; + + csi2_dphy_hw: csi2-dphy-hw@fe870000 { + compatible = "rockchip,rk3568-csi2-dphy-hw"; + reg = <0x0 0xfe870000 0x0 0x1000>; + clocks = <&cru PCLK_MIPICSIPHY>; + clock-names = "pclk"; + rockchip,grf = <&grf>; + status = "disabled"; + }; + + /* + * csi2_dphy0: used for csi2 dphy full mode, + is mutually exclusive with + csi2_dphy1 and csi2_dphy2 + * csi2_dphy1: used for csi2 dphy split mode, + physical lanes use lane0 and lane1, + can be used with csi2_dphy2 parallel + * csi2_dphy2: used for csi2 dphy split mode, + physical lanes use lane2 and lane3, + can be used with csi2_dphy1 parallel + */ + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <&csi2_dphy_hw>; + status = "disabled"; + }; + + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <&csi2_dphy_hw>; + status = "disabled"; + }; + + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rk3568-csi2-dphy"; + rockchip,hw = <&csi2_dphy_hw>; + status = "disabled"; + }; + + usb2phy0: usb2-phy@fe8a0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8a0000 0x0 0x10000>; + interrupts = ; + clocks = <&pmucru CLK_USBPHY0_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + assigned-clocks = <&cru USB480M>; + assigned-clock-parents = <&usb2phy0>; + clock-output-names = "usb480m_phy"; + rockchip,usbgrf = <&usb2phy0_grf>; + status = "disabled"; + + u2phy0_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + usb2phy1: usb2-phy@fe8b0000 { + compatible = "rockchip,rk3568-usb2phy"; + reg = <0x0 0xfe8b0000 0x0 0x10000>; + interrupts = ; + clocks = <&pmucru CLK_USBPHY1_REF>; + clock-names = "phyclk"; + #clock-cells = <0>; + rockchip,usbgrf = <&usb2phy1_grf>; + status = "disabled"; + + u2phy1_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + pcie30phy: phy@fe8c0000 { + compatible = "rockchip,rk3568-pcie3-phy"; + reg = <0x0 0xfe8c0000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, + <&cru PCLK_PCIE30PHY>; + clock-names = "refclk_m", "refclk_n", "pclk"; + resets = <&cru SRST_PCIE30PHY>; + reset-names = "phy"; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3568-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@fdd60000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfdd60000 0x0 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@fe740000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe740000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@fe750000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe750000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@fe760000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe760000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@fe770000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfe770000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3568-pinctrl.dtsi" diff --git a/rk3568m-serdes-evb-camera-csi-v10.dts b/rk3568m-serdes-evb-camera-csi-v10.dts new file mode 100644 index 0000000..3529024 --- /dev/null +++ b/rk3568m-serdes-evb-camera-csi-v10.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568m-serdes-evb-lp4x-v10-camera.dtsi" +#include "rk3568-android.dtsi" + +&rkx120_x110 { + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx120_reset_gpio>; +}; + +&serdes_camera { + local-port0 = ; + remote0-port0 = ; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <10000>; +}; diff --git a/rk3568m-serdes-evb-camera-dvp-v10.dts b/rk3568m-serdes-evb-camera-dvp-v10.dts new file mode 100644 index 0000000..199b142 --- /dev/null +++ b/rk3568m-serdes-evb-camera-dvp-v10.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3568m-serdes-evb-lp4x-v10-camera.dtsi" +#include "rk3568-android.dtsi" + +&rkx120_x110 { + enable-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx120_reset_gpio>; +}; + +&serdes_camera { + local-port0 = ; + remote0-port0 = ; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <10000>; +}; diff --git a/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts b/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts new file mode 100644 index 0000000..2c5ae27 --- /dev/null +++ b/rk3568m-serdes-evb-display-dsi0-command2dsi-lp4x-v10.dts @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi1_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts b/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts new file mode 100644 index 0000000..167547b --- /dev/null +++ b/rk3568m-serdes-evb-display-dsi0-command2lvds0-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi1_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts b/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts new file mode 100644 index 0000000..1e49df3 --- /dev/null +++ b/rk3568m-serdes-evb-display-dsi0-command2rgb-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&dsi1_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi1_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy1 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts b/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts new file mode 100644 index 0000000..52500b6 --- /dev/null +++ b/rk3568m-serdes-evb-display-dsi1-command2dsi-lp4x-v10.dts @@ -0,0 +1,409 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi0_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy0 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts b/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts new file mode 100644 index 0000000..6a8c5a2 --- /dev/null +++ b/rk3568m-serdes-evb-display-dsi1-command2lvds0-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi0_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy0 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts b/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts new file mode 100644 index 0000000..4a79bfb --- /dev/null +++ b/rk3568m-serdes-evb-display-dsi1-command2rgb-lp4x-v10.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi0_panel { + status = "okay"; + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET | + MIPI_DSI_CLOCK_NON_CONTINUOUS)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&dsi0_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&video_phy0 { + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts b/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts new file mode 100644 index 0000000..6bda338 --- /dev/null +++ b/rk3568m-serdes-evb-display-lvds2lvds-lp4x-v10.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + diff --git a/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts b/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts new file mode 100644 index 0000000..291c5a3 --- /dev/null +++ b/rk3568m-serdes-evb-display-lvds2rgb-lp4x-v10.dts @@ -0,0 +1,96 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&rkx110_reset_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; +}; + diff --git a/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts b/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts new file mode 100644 index 0000000..3c39e83 --- /dev/null +++ b/rk3568m-serdes-evb-display-rgb2dsi-lp4x-v10.dts @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts b/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts new file mode 100644 index 0000000..27837eb --- /dev/null +++ b/rk3568m-serdes-evb-display-rgb2lvds-lp4x-v10.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts b/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts new file mode 100644 index 0000000..706ad30 --- /dev/null +++ b/rk3568m-serdes-evb-display-rgb2rgb-lp4x-v10.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120 { + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&rkx110_reset_gpio>; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-evb-lp4x-v10-camera.dtsi b/rk3568m-serdes-evb-lp4x-v10-camera.dtsi new file mode 100644 index 0000000..199c55c --- /dev/null +++ b/rk3568m-serdes-evb-lp4x-v10-camera.dtsi @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568M SERDES EVB LP4X V10 Board"; + compatible = "rockchip,rk3568m-serdes-evb-lp4x-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +/* + * pin conflict with i2c2 for serdes-debug + */ +>1x { + status = "disabled"; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <100000>; + + rkx120_x110: rkx120_x110@54 { + compatible = "rockchip,rkx120"; + reg = <0x54>; + remote0-addr = <0x55>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes_camera: serdes-camera { + compatible = "rockchip,serdes-camera"; + reg = <0>; + status = "okay"; + }; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&pinctrl { + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + rkx120_reset_gpio: rkx120-reset-gpio { + rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "disabled"; +}; + +&rk809_codec { + status = "disabled"; +}; + +&sdmmc0 { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +/* OTG0 */ +&combphy0_us { + rockchip,dis-u3otg0-port; + /* OTG and SATA0 not use combphy0_us, then disabled */ + status = "disabled"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* HOST1 */ +&combphy1_usq { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; diff --git a/rk3568m-serdes-evb-lp4x-v10.dtsi b/rk3568m-serdes-evb-lp4x-v10.dtsi new file mode 100644 index 0000000..78cb019 --- /dev/null +++ b/rk3568m-serdes-evb-lp4x-v10.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568M SERDES EVB LP4X V10 Board"; + compatible = "rockchip,rk3568m-serdes-evb-lp4x-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&pinctrl { + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + rkx110_reset_gpio: rkx110-reset-gpio { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "disabled"; +}; + +&rk809_codec { + status = "disabled"; +}; + +&sdmmc0 { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +/* OTG0 */ +&combphy0_us { + rockchip,dis-u3otg0-port; + /* OTG and SATA0 not use combphy0_us, then disabled */ + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + rkx110_x120: rkx110-x120@55 { + compatible = "rockchip,rkx110"; + reg = <0x55>; + remote0-addr = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes_panel: serdes-panel { + compatible = "rockchip,serdes-panel"; + reg = <0>; + status = "okay"; + + display_timings0: display-timings { + native-mode = <&serdes_timing0>; + serdes_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* HOST1 */ +&combphy1_usq { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; diff --git a/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts new file mode 100644 index 0000000..c8344e1 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi0-command2dsi-lp4x-v10.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts new file mode 100644 index 0000000..111818c --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi0-command2dual_lvds-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <4>; + vsync-len = <5>; + vback-porch = <36>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts new file mode 100644 index 0000000..b0b1d40 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi0-command2lvds0-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts new file mode 100644 index 0000000..5017670 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi0-dsi1-command2dual_lvdsx2-lp4x-v10.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "okay"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp1_out_dsi1>; +}; + +/delete-node/ &dsi0_panel; + +&dsi1_panel { + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + panel-init-sequence = []; + panel-exit-sequence = []; +}; + +&disp_timings1 { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; +}; + + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + remote1-addr = <0x54>; +}; + +&serdes_timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + local-port1 = ; + remote0-port0 = ; + remote1-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts new file mode 100644 index 0000000..6f16477 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi1-command2dsi-lp4x-v10.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi1_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi1>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts new file mode 100644 index 0000000..ee5ecb2 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi1-command2dual_lvds-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi1_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <4>; + vsync-len = <5>; + vback-porch = <36>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts new file mode 100644 index 0000000..34e492a --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-dsi1-command2lvds0-lp4x-v10.dts @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi1_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts new file mode 100644 index 0000000..f2e5c5f --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-lvds2dsi-lp4x-v10.dts @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts new file mode 100644 index 0000000..d66f43b --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <100000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts new file mode 100644 index 0000000..eebaa23 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-lvds2dual-lvds-vehicle-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <66000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <28>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <7>; + vsync-len = <6>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts new file mode 100644 index 0000000..cbc5b31 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-lvds2lvds-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts new file mode 100644 index 0000000..2dd9385 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-lvds2rgb-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&lvds { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + lvds_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_lvds>; + }; + }; + }; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&rkx110_x120 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_lvds: endpoint { + remote-endpoint = <&lvds_out_rkx110_x120>; + }; + }; + }; +}; + +&video_phy0 { + status = "okay"; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; diff --git a/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts new file mode 100644 index 0000000..9081024 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-rgb2dsi-lp4x-v10.dts @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts new file mode 100644 index 0000000..4efba83 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-lp4x-v10.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts new file mode 100644 index 0000000..89297eb --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-rgb2dual-lvds-vehicle-lp4x-v10.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <66000000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <28>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <7>; + vsync-len = <6>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts new file mode 100644 index 0000000..3f7cc6a --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-rgb2lvds-lp4x-v10.dts @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts new file mode 100644 index 0000000..969f6d2 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-rgb2rgb-lp4x-v10.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm10 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <10000>; +}; + +&pwm10 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m1_pins>; + status = "okay"; +}; + +&rgb { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + rgb_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp2 { + status = "okay"; +}; + +&rkx110_x120_1 { + pt-config { + rk-serdes,pt = , + , + ; + }; +}; + +&serdes_timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hfront-porch = <160>; + hsync-len = <20>; + hback-porch = <140>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel1 { + local-port0 = ; + remote0-port0 = ; + + backlight = <&backlight>; + enable-gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser1_gpio &panel_enable_ser1_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts new file mode 100644 index 0000000..cedd1a5 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2dsi-lp4x-v10.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + remote1-addr = <0x54>; +}; + +&serdes_timing0 { + clock-frequency = <132000000>; + hactive = <2160>; + vactive = <1920>; + hfront-porch = <30>; + hsync-len = <4>; + hback-porch = <60>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + dsi-rx,lanes = <4>; + //dsi-rx,video-mode; + local-port0 = ; + remote0-port0 = ; + remote1-port0 = ; + split-mode; + dsi-tx,format = "rgb888"; + dsi-tx,lanes = <4>; + dsi-tx,video-mode; + + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts b/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts new file mode 100644 index 0000000..6008e97 --- /dev/null +++ b/rk3568m-serdes-v1-evb-display-super-frame-dsi0-command2lvds0-lp4x-v10.dts @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include "rk3568m-serdes-v1-evb-lp4x-v10.dtsi" +#include "rk3568-android.dtsi" + +&backlight { + pwms = <&pwm4 0 25000 0>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <10000>; +}; + +&dsi1 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "okay"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +/delete-node/ &dsi0_panel; + +&pwm4 { + pinctrl-names = "active"; + pinctrl-0 = <&pwm4_pins>; + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi0_out_rkx110_x120: endpoint { + remote-endpoint = <&rkx110_x120_in_dsi0>; + }; + }; + }; +}; + +&rkx110_x120 { + remote1-addr = <0x54>; +}; + +&serdes_timing0 { + clock-frequency = <100000000>; + hactive = <2048>; + vactive = <600>; + hfront-porch = <320>; + hsync-len = <40>; + hback-porch = <280>; + vfront-porch = <12>; + vsync-len = <3>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; +}; + +&serdes_panel { + local-port0 = ; + remote0-port0 = ; + remote1-port0 = ; + split-mode; + backlight = <&backlight>; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_reset_ser0_gpio &panel_enable_ser0_gpio>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rkx110_x120_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_rkx110_x120>; + }; + }; + }; +}; + +/* vp0 for HDMI, vp2 for rgb */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_SMART0)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1 | + 1 << ROCKCHIP_VOP2_SMART1)>; + rockchip,primary-plane = ; +}; + diff --git a/rk3568m-serdes-v1-evb-lp4x-v10.dtsi b/rk3568m-serdes-v1-evb-lp4x-v10.dtsi new file mode 100644 index 0000000..5e2b2f9 --- /dev/null +++ b/rk3568m-serdes-v1-evb-lp4x-v10.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" +#include "rk3568-evb.dtsi" + +/ { + model = "Rockchip RK3568M SERDES EVB LP4X V10 Board"; + compatible = "rockchip,rk3568m-serdes-evb-lp4x-v10", "rockchip,rk3568"; + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_us { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + gs_mxc6655xa: gs_mxc6655xa@15 { + status = "okay"; + compatible = "gs_mxc6655xa"; + pinctrl-names = "default"; + pinctrl-0 = <&mxc6655xa_irq_gpio>; + reg = <0x15>; + irq-gpio = <&gpio0 RK_PA4 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + power-off-in-suspend = <1>; + layout = <1>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&pinctrl { + mxc6655xa { + mxc6655xa_irq_gpio: mxc6655xa_irq_gpio { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + serdes_reset_ser0_gpio: serdes_reset_ser0_gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_reset_ser1_gpio: serdes_reset_ser1_gpio { + rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_enable_ser0_gpio: serdes_enable_ser0_gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_enable_ser1_gpio: serdes_enable_ser1_gpio { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_irq_ser0_gpio: serdes_irq_ser0_gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + serdes_irq_ser1_gpio: serdes_irq_ser1_gpio { + rockchip,pins = <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes_panel { + panel_reset_ser0_gpio: panel-reset-ser0-gpio { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + panel_enable_ser0_gpio: panel-enable-ser0-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + panel_reset_ser1_gpio: panel-reset-ser1-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + panel_enable_ser1_gpio: panel-enable-ser1-gpio { + rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + vccio6-supply = <&vcc_3v3>; +}; + +&pwm7 { + status = "disabled"; +}; + +&rk809_codec { + status = "disabled"; +}; + +&sdmmc0 { + status = "disabled"; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +/* OTG0 */ +&combphy0_us { + rockchip,dis-u3otg0-port; + /* OTG and SATA0 not use combphy0_us, then disabled */ + status = "disabled"; +}; + +&i2c1 { + status = "disabled"; + clock-frequency = <100000>; + + rkx110_x120: rkx110-x120@57 { + compatible = "rockchip,rkx110"; + reg = <0x57>; + remote0-addr = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + irq-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_reset_ser0_gpio &serdes_enable_ser0_gpio + &serdes_irq_ser0_gpio>; + + serdes_panel: serdes-panel { + compatible = "rockchip,serdes-panel"; + reg = <0>; + status = "okay"; + + display_timings0: display-timings { + native-mode = <&serdes_timing0>; + serdes_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; + +&i2c4 { + status = "disabled"; + clock-frequency = <100000>; + + rkx110_x120_1: rkx110-x120@57 { + compatible = "rockchip,rkx110"; + reg = <0x57>; + remote0-addr = <0x54>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>; + irq-gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&serdes_reset_ser1_gpio &serdes_enable_ser1_gpio + &serdes_irq_ser1_gpio>; + + serdes_panel1: serdes-panel { + compatible = "rockchip,serdes-panel"; + reg = <0>; + status = "okay"; + + display_timings1: display-timings { + native-mode = <&serdes_timing0>; + serdes_timing1: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <2>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + }; + }; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +/* HOST1 */ +&combphy1_usq { + status = "okay"; +}; + +&u2phy0_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; diff --git a/rk356x/dr4-rk3566.dts b/rk356x/dr4-rk3566.dts new file mode 100755 index 0000000..f25ea7b --- /dev/null +++ b/rk356x/dr4-rk3566.dts @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" + +#include "rk3566-evb-rpdzkj-rk809-syr837.dtsi" + +#include "../rk3568-linux.dtsi" +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3566.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + + +/*************************pcie***********************/ +#include "rk3568-pcie2x1.dtsi" +/***************************************************/ + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "lcd-gpio-dr4-rk3566.dtsi" + +/* HDMI only */ +//#include "rp-lcd-hdmi.dtsi" + +/** MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** mipi0 to LVDS */ +//#include "rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi" + +/** LVDS + HDMI */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" + +/** EDP */ +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + + + + + + + +/ { + model = "dr4-rk3566"; + compatible = "rpdzkj,dr4-rk3566", "rockchip,rk3566"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + + /******* sytem power en pin, donnot change it only if you know what you are doing */ + pwr_en { //vdd 12v/5v/3.3v enable + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + vdd_3g { //vdd_3G 3.3v enable + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //SPK ENABLE + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //SPK MUTE, high active, nomal low + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + hub_rst { //usb hub reset pin + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host1_5v { //host1 usb2.0 power en + gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host2_5v { //host2 usb2.0 power en + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host3_5v { //host2 usb2.0 power en + gpio_num = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb20_5v { //usb2.0 power en + gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb30_5v { //usb3.0 power en + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_5v { //OTG host power en + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_mode { //OTG SWITCH, high is mean otg_id to 0, foece host mode + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + led { //system led + gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + //fan { //fan en + // gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /***** gpio, add you want to control as blow */ + + gpio0c5 { + gpio_num = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0c7 { + gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1a4 { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + /** 24M osc clock to mcp2515 */ + osc_24m: osc24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm7 { + /** disable for used to be led control */ + status = "disabled"; +}; + + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + irq_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + + +&gmac1 { + tx_delay = <0x49>; + rx_delay = <0x2d>; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi1m0_cs0 &spi1m0_pins>; + pinctrl-1 = <&spi1m0_cs0 &spi1m0_pins_hs>; + + spi2can: mcp2515@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&osc_24m>; + interrupt-parent = <&gpio2>; + interrupts = ; + // vdd-supply = <®5v0>; + // xceiver-supply = <®5v0>; + spi-max-frequency = <10000000>; + }; +}; + +&spi2 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi2m0_cs0 &spi2m0_pins>; + pinctrl-1 = <&spi2m0_cs0 &spi2m0_pins_hs>; + + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi3 { + status = "okay"; + + /* rewrite pinctrl for cs1 used to be camera clk */ + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 &spi3m1_pins_hs>; + + spi3_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +/*************************wifi bt***********************/ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + + +/** camera config */ +&vcc_camera { + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; +}; +&gc2093 { + pwdn-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; +}; +/** pinctrl of camera power en */ +&camera_pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +/***************************************************/ + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +/** LCD configuration */ +#ifdef RP_MIPI02LVDS +//pwm and enable pin may be inverted if use mipi2lvds + +#if !defined(RP_DUALLVDS) +//but dual lvds donot need invert +&backlight4 { + pwms = <&pwm4 0 25000 1>; +}; +#else +&backlight4 { + pwms = <&pwm4 0 25000 0>; +}; + +#endif +&vcc3v3_lcd0_n { + /delete-property/ enable-active-high; + enable-active-low; +}; +#endif + + +/** pcie2x1 configuration */ +&vcc3v3_pcie { + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +}; +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; +}; + +&i2c1 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk356x/dr4-rk3568.dts b/rk356x/dr4-rk3568.dts new file mode 100755 index 0000000..219c406 --- /dev/null +++ b/rk356x/dr4-rk3568.dts @@ -0,0 +1,580 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm.dtsi" + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +#include "rp-camera-mipi-gc2093-single-2lane.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +#include "rp-can0-m0-rk3568.dtsi" +#include "rp-can1-m1-rk3568.dtsi" +#include "rp-can2-m0-rk3568.dtsi" +/**************************************************/ + +/*********************PCIE**************************/ +#include "rk3568-pcie2x1.dtsi" +#include "rk3568-pcie3x2.dtsi" +/***************************************************/ + +/*************************SATA***********************/ +#include "rk3568-sata1.dtsi" +/***************************************************/ + + + +#include "lcd-gpio-dr4-rk3568.dtsi" //gpio config for lcd + +/****** LCD config reference **/ +/** single HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/** mipi0 +hdmi */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** MIPI2LVDS + HDMI */ +//#include "rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi" + +/** LVDS + HDMI */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +#include "rp-lcd-lvds-10-1280-800-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/** EDP + HDMI */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + +/** LVDS + eDP + HDMI */ +//#include "rp-lcd-triple-lvds-7-1024-600-edp-13-1920-1080-hdmi.dtsi" + + + + +/{ + model = "dr4-rk3568"; + compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-name = "default"; + pinctrl-0 = <&rp_power>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + led { //system led + gpio_num = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + //fan { //fan + // gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + otg_mode { //OTG SWITCH, high is mean otg_id to 0, force host mode + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { //usb hub + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb_pwr0 { //host0 power en + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb_pwr1 { //host1 power en + gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb_pwr2 { //host2 power en + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb_pwr3 { //host3 power en + gpio_num = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb_pwr4 { //host4 power en + gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + vdd_3g { //4G module power en + gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /** + * gpioxxx { // the node name will display on /proc/rp_gpio, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio： 0 output, 1 input, 3 blink + * gpio_event = ; // optional property used to define gpio report event such as KEY_F14, only works incase of gpio_function = <1>; + * }; + */ + gpio0a0 { + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3c1 { + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio4c4 { + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio0c2 { + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio2d2 { + gpio_num = <&gpio2 RK_PD2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio2b2 { + gpio_num = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d0 { + gpio_num = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d1 { + gpio_num = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d2 { + gpio_num = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d3 { + gpio_num = <&gpio3 RK_PD3 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d4 { + gpio_num = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + gpio3d5 { + gpio_num = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + +&spi0 { + status = "okay"; + /** redefine pins for cs1 used to be pwm5 */ + pinctrl-0 = <&spi0m0_cs0 &spi0m0_pins>; + pinctrl-1 = <&spi0m0_cs0 &spi0m0_pins_hs>; + + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&video_phy1 { + status = "okay"; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +/*********************************************/ + + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + +/** LCD backlight + * By default, we all use backlight4 node whether it is mipi, lvds or edp, + * but when mipi1(2lvds) ports used, pwm need the pwm5, + * when edp port used, pwm need the pwm10, so fix backlight node. + * and if mutiple lcd used, we just use the backlight5, backlight10. + */ +/** LCD configuration */ +#if defined(RP_SINGLE_LCD) + + #if defined(RP_MIPI02LVDS) + &dsi0_panel { + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; //raw interface is inverse, so set to low + }; + #if defined(RP_DUALLVDS) + // dual lvds donot need invert + &backlight4 { + pwms = <&pwm5 0 25000 0>; + }; + #else + //pwm and enable pin may be inverted if use mipi to single lvds + &backlight4 { + pwms = <&pwm5 0 25000 1>; + }; + #endif + + #elif defined(RP_EDP_USED) + &backlight4 { + pwms = <&pwm10 0 25000 0>; + }; + #endif + +#else +&edp_panel { + backlight = <&backlight10>; +}; + #ifdef RP_MIPI02LVDS + &dsi0_panel { + backlight = <&backlight5>; + }; + #endif +#endif + + +/** Ethernet config*/ +&gmac1 { + tx_delay = <0x49>; + rx_delay = <0x29>; + status = "okay"; +}; + + +/** headphone detect pin */ +&rk_headset { + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; +}; + + +/** wifi/bt config */ +&sdio_pwrseq { + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&sdmmc1 { + status = "okay"; + + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + sd-uhs-sdr104; + + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; +}; + +&wireless_wlan { + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + +/** pcie2x1 */ +&vcc3v3_pcie { + /** + * delete for gpio used to be bt_wake_host + * and the vcc3v3_pcie need not control on our board. + */ + /delete-property/ gpio; +}; + +&pcie2x1 { + status = "okay"; + + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + + + +/** pcie3x2 */ +&pcie3x2 { + status = "okay"; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie3>; +}; + +&vcc3v3_pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_3v3>; + gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <8000>; //5000 is faild +}; + +/** mipi camera config */ +&vcc_camera { + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_en>; +}; +&gc2093 { + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + pinctrl-1 = <&camera_ctl>; + pwdn-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + + +&pinctrl { + rp_pins { + rp_power: rp-power { + rockchip,pins = + /* host4 power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { //redefine hp detect pin + hp_det: hp-det { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { //redefine sdio power pin + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-wlan { //redefine wlan wake host pin + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PC6 0 &pcfg_pull_down>; + }; + }; + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 0 &pcfg_pull_none>; + }; + }; + + vcc3v3-pcie3 { + pcie3_3v3: pcie3-3v3 { + rockchip,pins = + /** power supply enable pin */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + camera-pins { + camera_en: camera-en { + rockchip,pins = + /** gc2093 camera en */ + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + camera_ctl: camera-ctl { + rockchip,pins = + /** gc2093 camera power down */ + <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, + /** gc2093 camera reset */ + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + + +&wireless_bluetooth { + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk356x/lcd-gpio-dr4-rk3566.dtsi b/rk356x/lcd-gpio-dr4-rk3566.dtsi new file mode 100755 index 0000000..f3445b1 --- /dev/null +++ b/rk356x/lcd-gpio-dr4-rk3566.dtsi @@ -0,0 +1,112 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + //enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; //use on vcc3v3_lcd + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + diff --git a/rk356x/lcd-gpio-dr4-rk3568.dtsi b/rk356x/lcd-gpio-dr4-rk3568.dtsi new file mode 100755 index 0000000..07243eb --- /dev/null +++ b/rk356x/lcd-gpio-dr4-rk3568.dtsi @@ -0,0 +1,228 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 1>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight10: backlight10 { + compatible = "pwm-backlight"; + pwms = <&pwm10 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm10 { + status = "okay"; +}; + +// MIPI DSI0 or MIPI0toLVDS +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi0_pins>; + backlight = <&backlight4>; +}; + +// MIPI DSI1 +&dsi1_panel { + status = "disabled"; +}; + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; //raw interface is inverse, so set to low + // reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi0_pins>; + backlight = <&backlight4>; +}; + +// EDP +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_pins>; + enable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + backlight = <&backlight4>; +}; + + +// POWER GPIO +&vcc3v3_lcd0_n { + // gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + /delete-property/ gpio; + enable-active-high; +}; + +// TP +&i2c3 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix_rst_gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA4 IRQ_TYPE_EDGE_FALLING>; + + status = "disabled"; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix,rst-gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA4 IRQ_TYPE_EDGE_FALLING>; + + status = "disabled"; + }; +}; + +&pinctrl { + lcd_pins { + mipi0_pins: mipi1-pins { + rockchip,pins = + /** mipi0 enable */ + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, + /** mipi0 reset */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + edp_pins: edp-pins { + rockchip,pins = + /** edp enable */ + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_pins: goodix-pins { + rockchip,pins = + /** rst pin */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + /** irq pin */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/lcd-gpio-lga-rk3566.dtsi b/rk356x/lcd-gpio-lga-rk3566.dtsi new file mode 100755 index 0000000..f3445b1 --- /dev/null +++ b/rk356x/lcd-gpio-lga-rk3566.dtsi @@ -0,0 +1,112 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + //enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; //use on vcc3v3_lcd + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + diff --git a/rk356x/lcd-gpio-nano-box-rk3568.dtsi b/rk356x/lcd-gpio-nano-box-rk3568.dtsi new file mode 100755 index 0000000..7597a92 --- /dev/null +++ b/rk356x/lcd-gpio-nano-box-rk3568.dtsi @@ -0,0 +1,141 @@ +/** + * + * for compatible with different board type, this file is used to + * predefine lcd configuration cause of those pins may different on + * different board. + * + */ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + /** predefine for edp panel, will enable in edp lcd dtsi */ + edp_panel:panel { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; + }; + + /** predefine for lvds panel, will enable in lvds lcd dtsi */ + lvds_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; + +}; + + + + +/** predefine for dsi panel, will enable in mipi lcd dtsi */ +&dsi0 { + dsi0_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; +&dsi1 { + dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + + +/** enable backlight pwm channel */ +&pwm4 { + status = "okay"; +}; + + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +/** tp configuration, will enable in lcd dtsi */ +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + + + diff --git a/rk356x/lcd-gpio-nano-rk3566.dtsi b/rk356x/lcd-gpio-nano-rk3566.dtsi new file mode 100755 index 0000000..d7aa2c1 --- /dev/null +++ b/rk356x/lcd-gpio-nano-rk3566.dtsi @@ -0,0 +1,177 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +//MIPI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// MIPI1 to LVDS +&dsi1_panel { + status = "disabled"; + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; //raw interface is inverse, so set to low + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi1_pins>; + backlight = <&backlight4>; +}; + +//LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + //enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +//EDP +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +//TP +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PA3 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PA3 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd_pins { + lcd_rst_gpio: lcd_rst_gpio { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipi1_pins: mipi0_pins { + rockchip,pins = + <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + diff --git a/rk356x/lcd-gpio-nano-rk3568.dtsi b/rk356x/lcd-gpio-nano-rk3568.dtsi new file mode 100755 index 0000000..f13c78c --- /dev/null +++ b/rk356x/lcd-gpio-nano-rk3568.dtsi @@ -0,0 +1,198 @@ + +/ { + backlight5: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight8: backlight8 { + compatible = "pwm-backlight"; + pwms = <&pwm8 0 25000 1>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm8 { + status = "okay"; +}; + +// MIPI DSI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi0_pins>; + backlight = <&backlight5>; +}; + +// MIPI1toLVDS +&dsi1_panel { + status = "disabled"; + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>; //raw interface is inverse, so set to low + reset-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi1_pins>; + backlight = <&backlight5>; +}; + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + // reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi0_pins>; + backlight = <&backlight5>; +}; + +// EDP +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_pins>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + backlight = <&backlight5>; +}; + + +// POWER GPIO +&vcc3v3_lcd0_n { + // gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + /delete-property/ gpio; + enable-active-high; +}; + +// TP +&i2c1 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "disabled"; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + + status = "disabled"; + }; +}; + +&pinctrl { + lcd_pins { + mipi0_pins: mipi0-pins { + rockchip,pins = + /** mipi0 enable */ + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, + /** mipi0 reset */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipi1_pins: mipi1-pins { + rockchip,pins = + /** mipi1 enable */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + /** mipi1 reset */ + <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + edp_pins: edp-pins { + rockchip,pins = + /** edp enable */ + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_pins: goodix-pins { + rockchip,pins = + /** rst pin */ + <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>, + /** irq pin */ + <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/lcd-gpio-pro-rk3566.dtsi b/rk356x/lcd-gpio-pro-rk3566.dtsi new file mode 100755 index 0000000..fa3ffd4 --- /dev/null +++ b/rk356x/lcd-gpio-pro-rk3566.dtsi @@ -0,0 +1,148 @@ +/** + * + * for compatible with different board type, this file is used to + * predefine lcd configuration cause of those pins may different on + * different board. + * + */ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + /** predefine for edp panel, will enable in edp lcd dtsi */ + edp_panel:panel { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; + }; + + /** predefine for lvds panel, will enable in lvds lcd dtsi */ + lvds_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; + + + + +/** predefine for dsi panel, will enable in mipi lcd dtsi */ +&dsi0 { + dsi0_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; +&dsi1 { + dsi1_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; + + + +/** enable backlight pwm channel */ +&pwm4 { + status = "okay"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +/** tp configuration, will enable in lcd dtsi */ +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + + gt1x: goodix_gt1x@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + + diff --git a/rk356x/lcd-gpio-pro-rk3568.dtsi b/rk356x/lcd-gpio-pro-rk3568.dtsi new file mode 100755 index 0000000..ac16ed2 --- /dev/null +++ b/rk356x/lcd-gpio-pro-rk3568.dtsi @@ -0,0 +1,197 @@ +/** + * + * for compatible with different board type, this file is used to + * predefine lcd configuration cause of those pins may different on + * different board. + * + */ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + /** predefine for edp panel, will enable in edp lcd dtsi */ + edp_panel:panel { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight5>; + }; + + /** predefine for lvds panel, will enable in lvds lcd dtsi */ + lvds_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; + +}; + + +/** predefine for dsi panel, will enable in mipi lcd dtsi */ +&dsi0 { + dsi0_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; +&dsi1 { + dsi1_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight5>; + }; +}; + + +// EDP +&edp { + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; +}; + + +/** enable backlight pwm channel */ + +&pwm4 { + status = "okay"; +}; +&pwm5 { + status = "okay"; +}; + + + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +/** tp configuration, will enable in lcd dtsi */ +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + + gt1x: goodix_gt1x@5d { + status = "disabled"; + + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/lcd-gpio-pro3568-ahd.dtsi b/rk356x/lcd-gpio-pro3568-ahd.dtsi new file mode 100755 index 0000000..c32831d --- /dev/null +++ b/rk356x/lcd-gpio-pro3568-ahd.dtsi @@ -0,0 +1,237 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 1>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 1>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight10: backlight10 { + compatible = "pwm-backlight"; + pwms = <&pwm10 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + +&pwm10 { + status = "okay"; +}; + +// MIPI DSI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lvds_pins>; + backlight = <&backlight4>; +}; + +// MIPI DSI1 or mipi2lvds +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; //raw lvds is inverse + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi1_pins>; + backlight = <&backlight4>; +}; + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd_n>; + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; //raw interface is inverse, so set to low + // reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lvds_pins>; + backlight = <&backlight4>; +}; + +// EDP +&edp_panel { + power-supply = <&vcc3v3_lcd_n>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_pins>; + enable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + backlight = <&backlight4>; +}; + + +// POWER GPIO +&vcc3v3_lcd_n { + // gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + /delete-property/ gpio; + enable-active-high; +}; + +// TP +&i2c3 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix_rst_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA3 IRQ_TYPE_EDGE_FALLING>; + + status = "disabled"; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix,rst-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA3 IRQ_TYPE_EDGE_FALLING>; + + status = "disabled"; + }; +}; + +&pinctrl { + lcd_pins { + mipi1_pins: mipi1-pins { + rockchip,pins = + /** mipi1 enable */ + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, + /** mipi1 reset */ + <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + lvds_pins: lvds-pins { + rockchip,pins = + /** lvds enable */ + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + edp_pins: edp-pins { + rockchip,pins = + /** edp enable */ + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_pins: goodix-pins { + rockchip,pins = + /** rst pin */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, + /** irq pin */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/lcd-gpio-rp-box-rk3566.dtsi b/rk356x/lcd-gpio-rp-box-rk3566.dtsi new file mode 100755 index 0000000..a7055d2 --- /dev/null +++ b/rk356x/lcd-gpio-rp-box-rk3566.dtsi @@ -0,0 +1,143 @@ +/** + * + * for compatible with different board type, this file is used to + * predefine lcd configuration cause of those pins may different on + * different board. + * + */ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + /** predefine for edp panel, will enable in edp lcd dtsi */ + edp_panel:panel { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; + }; + + /** predefine for lvds panel, will enable in lvds lcd dtsi */ + lvds_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; + + + + +/** predefine for dsi panel, will enable in mipi lcd dtsi */ +&dsi0 { + dsi0_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; +&dsi1 { + dsi1_panel: panel@0 { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; + + + +/** enable backlight pwm channel */ +&pwm4 { + status = "okay"; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +/** tp configuration, will enable in lcd dtsi */ +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + + diff --git a/rk356x/lcd-gpio-rp-box-rk3568.dtsi b/rk356x/lcd-gpio-rp-box-rk3568.dtsi new file mode 100755 index 0000000..a21e96a --- /dev/null +++ b/rk356x/lcd-gpio-rp-box-rk3568.dtsi @@ -0,0 +1,141 @@ +/** + * + * for compatible with different board type, this file is used to + * predefine lcd configuration cause of those pins may different on + * different board. + * + */ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + /** predefine for edp panel, will enable in edp lcd dtsi */ + edp_panel:panel { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; + }; + + /** predefine for lvds panel, will enable in lvds lcd dtsi */ + lvds_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; + +}; + + + + +/** predefine for dsi panel, will enable in mipi lcd dtsi */ +&dsi0 { + dsi0_panel: panel@0 { + status = "disabled"; + + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; + }; +}; +&dsi1 { + dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + + +/** enable backlight pwm channel */ +&pwm4 { + status = "okay"; +}; + + +&vcc3v3_lcd0_n { + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +/** tp configuration, will enable in lcd dtsi */ +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + + + diff --git a/rk356x/lga-rk3566.dts b/rk356x/lga-rk3566.dts new file mode 100755 index 0000000..8b5c408 --- /dev/null +++ b/rk356x/lga-rk3566.dts @@ -0,0 +1,468 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" +#include "rk3566-evb-rpdzkj-rk809-syr837.dtsi" + + +#include "../rk3568-linux.dtsi" +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3566.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + + +/*************************pcie***********************/ +#include "rk3568-pcie2x1.dtsi" +/***************************************************/ + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "lcd-gpio-lga-rk3566.dtsi" + +/* HDMI only */ +//#include "rp-lcd-hdmi.dtsi" + +/** MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** mipi0 to LVDS */ +//#include "rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi" + +/** LVDS + HDMI */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" + +/** EDP */ +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" +//null + + + + + + + + + + +/ { + model = "lga-rk3566"; + compatible = "rpdzkj,lga-rk3566", "rockchip,rk3566"; + + vcc3v3_pcie3: gpio-regulator-pcie3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; //In the uboot phase fixed.c resolves gpio + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30>; + }; + + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + + /******* sytem power en pin, donnot change it only if you know what you are doing */ + pwr_en { //vdd 12v/5v/3.3v enable + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + vdd_3g { //vdd_3G 3.3v enable + gpio_num = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //SPK ENABLE + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //SPK MUTE, high active, nomal low + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + hub_rst { //usb hub reset pin + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host1_5v { //host1 usb2.0 power en + gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host2_5v { //host2 usb2.0 power en + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + host3_5v { //host2 usb2.0 power en + gpio_num = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb20_5v { //usb2.0 power en + gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb30_5v { //usb3.0 power en + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_5v { //OTG host power en + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_mode { //OTG SWITCH, high is mean otg_id to 0, foece host mode + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + led { //system led + gpio_num = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + //fan { //fan en + // gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /***** gpio, add you want to control as blow */ + + gpio0c5 { + gpio_num = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0c7 { + gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1a4 { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio2b4 { + gpio_num = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio2b3 { + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0d4 { + gpio_num = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio0d3 { + gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; + + /** 24M osc clock to mcp2515 */ + osc_24m: osc24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&pwm7 { + /** disable for used to be led control */ + status = "disabled"; +}; + + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + irq_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + + +&gmac1 { + tx_delay = <0x49>; + rx_delay = <0x2d>; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi1m0_cs0 &spi1m0_pins>; + pinctrl-1 = <&spi1m0_cs0 &spi1m0_pins_hs>; + + spi2can: mcp2515@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&osc_24m>; + interrupt-parent = <&gpio2>; + interrupts = ; + // vdd-supply = <®5v0>; + // xceiver-supply = <®5v0>; + spi-max-frequency = <10000000>; + }; +}; + +&spi2 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi2m0_cs0 &spi2m0_pins>; + pinctrl-1 = <&spi2m0_cs0 &spi2m0_pins_hs>; + + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi3 { + status = "okay"; + + /* rewrite pinctrl for cs1 used to be camera clk */ + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 &spi3m1_pins_hs>; + + spi3_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +/*************************wifi bt***********************/ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + + +/** camera config */ +&vcc_camera { + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; +}; +&gc2093 { + pwdn-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; +}; +/** pinctrl of camera power en */ +&camera_pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; +}; + +/***************************************************/ + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +/** LCD configuration */ +#ifdef RP_MIPI02LVDS +//pwm and enable pin may be inverted if use mipi2lvds + +#if !defined(RP_DUALLVDS) +//but dual lvds donot need invert +&backlight4 { + pwms = <&pwm4 0 25000 1>; +}; +#else +&backlight4 { + pwms = <&pwm4 0 25000 0>; +}; + +#endif +&vcc3v3_lcd0_n { + /delete-property/ enable-active-high; + enable-active-low; +}; +#endif + + +/** pcie2x1 configuration */ +&vcc3v3_pcie { + gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; +}; +&pcie2x1 { + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; +}; + +&i2c1 { + status = "okay"; +}; + + +&pinctrl { + vcc3v3-pcie3 { + vcc3v3_pcie30: vcc3v3-pcie3 { + rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/rk356x/lga-rk3568-single-lcd-gpio.dtsi b/rk356x/lga-rk3568-single-lcd-gpio.dtsi new file mode 100755 index 0000000..04c367a --- /dev/null +++ b/rk356x/lga-rk3568-single-lcd-gpio.dtsi @@ -0,0 +1,169 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + + + +// MIPI DSI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// MIPI DSI1 +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// EDP +//&edp { +// hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; +//}; +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + + +// POWER GPIO +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +// TP +&i2c1 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/lga-rk3568.dts b/rk356x/lga-rk3568.dts new file mode 100755 index 0000000..53f7ec4 --- /dev/null +++ b/rk356x/lga-rk3568.dts @@ -0,0 +1,424 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-syr837.dtsi" + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +//#include "rp-mipi-camera-gc2093-rk3568.dtsi" +#include "rp-mipi-camera-gc2093-imx334-imx415-rk3568.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +#include "rp-can1-m1-rk3568.dtsi" +#include "rp-can2-m0-rk3568.dtsi" +/**************************************************/ + +/*********************PCIE**************************/ +#include "rk3568-pcie3x1x1.dtsi" + +/*************************SATA***********************/ +#include "rk3568-sata2.dtsi" +/***************************************************/ + + + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "lga-rk3568-single-lcd-gpio.dtsi" // gpio config of lcd +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" + +/* MIPI DSI1 */ +//#include "rp-lcd-mipi1-7-1024-600.dtsi" +//#include "rp-lcd-mipi1-7-1200-1920.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1024-600.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + +/{ + + model = "lga-rk3568"; + compatible = "rpdzkj,lga-rk3568-v10", "rockchip,rk3568"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + vcc3v3_pi6c: vcc3v3_pi6c { //pcie3 clk enable for m.2 + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clk_control>; + }; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + pinctrl-1 = <&vcc5v0_otg_en>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + led { //system led + gpio_num = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + /* + fan { //fan + gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + */ + usb_pwr { //usb power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //usb hub + gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + otg_mode { //OTG SWITCH + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_en { //spk enable + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + vdd_4g { //4g power + gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio0b0 { + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio0b7 { + gpio_num = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + + +&i2c1 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + + + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; +/*********************************************/ + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + + +/** + * when single mipi1 or edp ports used, pwm need the pwm5, + * and if mutiple lcd used, we just reference the backlight5. + */ +#if (defined(RP_MIPI1_USED) || defined(RP_EDP_USED)) && defined(RP_SINGLE_LCD) +&backlight4 { + pwms = <&pwm5 0 25000 0>; +}; +#endif + +/**********************pcie***************************/ +&vcc3v3_pcie3 { + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; +}; +/******* pcie3x1x1 -m..2*****/ +&pcie3x1 { + status = "okay"; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; +}; + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; +}; + + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; + + pcie3_control{ + pcie_clk_control: pcie-clk-control { + rockchip,pins = + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + +}; + +&rk809_codec { + mic-in-differential; +}; diff --git a/rk356x/mini-pc-rk3566.dts b/rk356x/mini-pc-rk3566.dts new file mode 100755 index 0000000..760e6fd --- /dev/null +++ b/rk356x/mini-pc-rk3566.dts @@ -0,0 +1,361 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" + +#include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" + + +#include "../rk3568-linux.dtsi" +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3566.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + + +/****************** SINGLE LCD ***************/ +#include "pro-rk3566-single-lcd-gpio.dtsi" + +/* HDMI */ +#include "rp-lcd-hdmi.dtsi" + +/* MIPI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" + +/* MIPI1 */ +//#include "rp-lcd-mipi1-7-1024-600.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-10-1024-600.dtsi" +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" + + + + + + +/ { + model = "mini-pc-rk3566"; + compatible = "rpdzkj,mini-pc-rk3566", "rockchip,rk3566"; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + led { //system led + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb_pwr { //usb host power and otg power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + + usb_otg_pwr { // + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; +}; + + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + io4_c4 { // + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + test-power { + /** disable for use rk809-battery */ + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + +&cpu0_opp_table { + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1150000>; + opp-microvolt-L0 = <825000 825000 1150000>; + opp-microvolt-L1 = <800000 800000 1150000>; + opp-microvolt-L2 = <800000 800000 1150000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1150000>; + opp-microvolt-L0 = <850000 850000 1150000>; + opp-microvolt-L1 = <825000 825000 1150000>; + opp-microvolt-L2 = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-microvolt-L0 = <900000 900000 1150000>; + opp-microvolt-L1 = <875000 875000 1150000>; + opp-microvolt-L2 = <850000 850000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <950000 950000 1150000>; + opp-microvolt-L0 = <950000 950000 1150000>; + opp-microvolt-L1 = <925000 925000 1150000>; + opp-microvolt-L2 = <900000 900000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1000000 1000000 1150000>; + opp-microvolt-L0 = <1000000 1000000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <950000 950000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1050000 1050000 1150000>; + opp-microvolt-L0 = <1050000 1050000 1150000>; + opp-microvolt-L1 = <1025000 1025000 1150000>; + opp-microvolt-L2 = <1025000 1025000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1100000 1100000 1150000>; + opp-microvolt-L0 = <1100000 1100000 1150000>; + opp-microvolt-L1 = <1075000 1075000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + clock-latency-ns = <40000>; + }; + + +}; + + +&i2c1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi2 { + status = "okay"; + + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi3 { + status = "okay"; + + pinctrl-names = "default", "high_speed"; + pinctrl-0 = <&spi3m1_cs0 /*&spi3m1_cs1*/ &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 /*&spi3m1_cs1*/ &spi3m1_pins_hs>; + + spi3_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&edp { + /** delete hdp gpio that pro3566 donot use */ + /delete-property/ hpd-gpios; +}; + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + + + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + + + +&rk_headset { + status = "okay"; + headset_force_flag = <1>; + }; + + + +&pinctrl { + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/nano-box-rk3566-single-lcd-gpio.dtsi b/rk356x/nano-box-rk3566-single-lcd-gpio.dtsi new file mode 100755 index 0000000..0d6874a --- /dev/null +++ b/rk356x/nano-box-rk3566-single-lcd-gpio.dtsi @@ -0,0 +1,122 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; +/* +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; +*/ +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + + + diff --git a/rk356x/nano-box-rk3566.dts b/rk356x/nano-box-rk3566.dts new file mode 100755 index 0000000..523dfe9 --- /dev/null +++ b/rk356x/nano-box-rk3566.dts @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" + +#include "rk3566-evb-rpdzkj-rk809-syr837.dtsi" + + +#include "../rk3568-linux.dtsi" +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3566.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + +/****************** SINGLE LCD ***************/ +#include "nano-box-rk3566-single-lcd-gpio.dtsi" +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** LVDS */ +//#include"rp-lcd-lvds-10-1280-800.dtsi" +//#include"rp-lcd-lvds-7-1024-600-v2.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + + + + + + + +/ { + model = "nano-box-rk3566"; + compatible = "rpdzkj,nano-box-rk3566", "rockchip,rk3566"; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + pwr_5v_3v3 { //3.3v 5v enable + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + led { //system led + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_pwr { //usb host power and otg power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_rst { //usb hub reset + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //SPK ENABLE + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //SPK MUTE + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + usb_mode { //OTG SWITCH + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + otg_pwr { + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; +}; + + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + +/***** SPI_FLASH ********/ + gpio1d0 { + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1d1 { + gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio1d2 { + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1d3 { + gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio1d4 { + gpio_num = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + +/***** PDM ********/ + + gpio4a0 { + gpio_num = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a1 { + gpio_num = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio4a2 { + gpio_num = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a3 { + gpio_num = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&gmac1 { + tx_delay = <0x42>; + rx_delay = <0x2d>; +}; + + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi2 { + status = "okay"; + + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + + diff --git a/rk356x/nano-box-rk3568-lcd-gpio.dtsi b/rk356x/nano-box-rk3568-lcd-gpio.dtsi new file mode 100755 index 0000000..f282e5f --- /dev/null +++ b/rk356x/nano-box-rk3568-lcd-gpio.dtsi @@ -0,0 +1,117 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + + + + +/************** LCD GPIO ********************/ +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + + + + diff --git a/rk356x/nano-box-rk3568.dts b/rk356x/nano-box-rk3568.dts new file mode 100755 index 0000000..d0095b5 --- /dev/null +++ b/rk356x/nano-box-rk3568.dts @@ -0,0 +1,327 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm.dtsi" + + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3568.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +#include "rp-can1-m1-rk3568.dtsi" +#include "rp-can2-m0-rk3568.dtsi" +/**************************************************/ + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "nano-box-rk3568-lcd-gpio.dtsi" // if use lcd, must enable it +/* HDMI only */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** LVDS */ +//#include"rp-lcd-lvds-10-1280-800.dtsi" +//#include"rp-lcd-lvds-7-1024-600-v2.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + +/************************ MULTILPLE LCD *********************/ +/* EDP + MIPI0/LVDS */ +//#include "rp-lcd-triple-lvds-7-1024-600-edp-13-1920-1080-hdmi.dtsi" + + + + + +/{ + model = "nano-box-rk3568"; + + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + led { //system led + gpio_num = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + // fan { //fan + // gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // }; + usb_pwr1 { //usb host power1 + gpio_num = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb_pwr2 { //usb host power2 + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_mode { //OTG SWITCH + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + spk_enable { //spk enable + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3b5 { //gpio + gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3a7 { //gpio + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&i2c1 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + + + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ + + +&rk_headset { + status = "disabled"; +}; +&edp { + /** delete hdp gpio that nano-box-rk3568 donot use */ + /delete-property/ hpd-gpios; +}; + +&pinctrl { + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/nano-rk3566.dts b/rk356x/nano-rk3566.dts new file mode 100755 index 0000000..7cca71f --- /dev/null +++ b/rk356x/nano-rk3566.dts @@ -0,0 +1,510 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" +//#include "rk3566-base-no-rk809.dtsi" +#include "rk3566-evb-rpdzkj-pwm-pwm.dtsi" +#include "../rk3568-linux.dtsi" + + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + + +/*************************pcie***********************/ +#include "rk3568-pcie2x1.dtsi" +/***************************************************/ + +#include "rp-audio-es8311.dtsi" + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "lcd-gpio-nano-rk3566.dtsi" +/* HDMI only */ +//#include "rp-lcd-hdmi.dtsi" + +/** MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** MIPI1toLVDS + HDMI */ +//#include "rp-lcd-mipi1tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi1tolvds-gm8775c-1920-1080.dtsi" + +/** LVDS + HDMI */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/** EDP */ +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + +/ { + model = "nano-rk3566"; + compatible = "rpdzkj,nano-rk3566", "rockchip,rk3566"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pin &fan_pin &usb_pins>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + + /******* sytem power en pin, donnot change it only if you know what you are doing */ + + led { //system led + gpio_num = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + //fan { //fan en + // gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { //usb hub + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb3_pwr { //usb3 power en + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb2_vdd0 { //usb2.0_vdd0 power en + gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb2_vdd1 { //usb2.0_vdd1 power en + gpio_num = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd_4g { //4g enable + gpio_num = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3d3 { + gpio_num = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3d4 { + gpio_num = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + /***** gpio, add you want to control as blow */ + }; + + + rp-keys { + compatible = "rp-keys"; + status = "disabled"; + name = "rp-keys"; + + gpio3d3 { + gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + gpio3d4 { + label = "gpiokey3d4"; + gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + debounce_interval = <10>; + wakeup; + press_type = <0>; + code = ; + }; + }; + + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + }; + + /** 24M osc clock to mcp2515 */ + osc_24m: osc24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + +/** stm706 watchdog pinctrl clash **/ +&rk_headset { + status = "disabled"; +}; + + +&vcc3v3_sd { + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_sd_pin>; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; + +}; + +&vcc5v0_sys { + enable-active-high; + gpio = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&vcc5v0_pin>; +}; + +&pwm7 { + /** disable for used to be led control */ + status = "disabled"; +}; + + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vccio_wl>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + // irq_gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; +}; + + +&gmac1 { + status = "okay"; + snps,reset-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + &gmac1m1_clkinout + ð1m1_pins>; + + tx_delay = <0x49>; + rx_delay = <0x2d>; +}; + +&uart0 { + status = "disbled"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&spi0 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi0m0_cs0 &spi0m0_pins>; + pinctrl-1 = <&spi0m0_cs0 &spi0m0_pins_hs>; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi3 { + status = "okay"; + + /* rewrite pinctrl for cs1 used to be camera clk */ + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 &spi3m1_pins_hs>; + + spi3can: mcp2515@0 { + status = "okay"; + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&osc_24m>; + interrupt-parent = <&gpio4>; + interrupts = ; + // vdd-supply = <®5v0>; + // xceiver-supply = <®5v0>; + spi-max-frequency = <10000000>; + }; +}; + +/***************************************************/ + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + + +/** LCD backlight + * By default, we all use backlight4 node whether it is mipi, lvds or edp, + */ +/** LCD configuration */ +#if defined(RP_SINGLE_LCD) + + #if defined(RP_MIPI12LVDS) + &backlight4 { + pwms = <&pwm5 0 25000 1>; + }; + + #if defined(RP_DUALLVDS) + &backlight4 { + pwms = <&pwm5 0 25000 0>; + }; + #endif + + #endif + +#endif + +/** wifi/bt config */ +&sdio_pwrseq { + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; +}; + +&sdmmc2 { + status = "disabled"; +}; + +&sdmmc1 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&wireless_wlan { + assigned-clocks = <&pmucru CLK_WIFI>; + assigned-clock-rates = <24000000>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "soc_24M"; + pinctrl-0 = <&wifi_host_wake_irq &clk32k_out1>; + WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&uart1m0_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; +}; + + +/** pcie2x1 configuration */ +&pcie2x1 { + status = "okay"; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + + +&pinctrl { + power_pins { + vcc3v3_sd_pin: vcc3v3_sd_pin { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + vcc5v0_pin: vcc5v0-pin { + rockchip,pins = + <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + led_pin: led-pin { + rockchip,pins = + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + fan_pin: fan-pin { + rockchip,pins = + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + usb_pins: usb-pins { + rockchip,pins = + /* otg power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + /* hub reset pin */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + /* usb3.0 power en */ + <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + /* usb2.0 vdd0 en */ + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>, + /* usb2.0 vdd1 en */ + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { //redefine sdio power pin + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { //redefine wlaD4wake host pin + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB2 0 &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <2 RK_PB5 0 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/nano-rk3568.dts b/rk356x/nano-rk3568.dts new file mode 100755 index 0000000..7f14ae7 --- /dev/null +++ b/rk356x/nano-rk3568.dts @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; +//rk3568-evb1-ddr4-v10 +// #include "rk3568-evb1-ddr4-v10.dtsi" +//#include "rk3568-base-no-rk809.dtsi" + +#include "rk3568-evb-rpdzkj-pwm-pwm-syr837.dtsi" + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +#include "rp-camera-mipi-gc2093-single-2lane.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +#include "rp-can1-m1-rk3568.dtsi" +/**************************************************/ +/*********************PCIE**************************/ +#include "rk3568-pcie2x1.dtsi" +#include "rk3568-pcie3x1x1.dtsi" +#include "rk3568-pcie3x2.dtsi" +/***************************************************/ + +/*************************SATA***********************/ +//#include "rk3568-sata2.dtsi" +/***************************************************/ + +/* audio */ +#include "rp-audio-es8311.dtsi" + +#include "lcd-gpio-nano-rk3568.dtsi" //gpio config for lcd + +/****** LCD config reference **/ +/** single HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/** mipi0 +hdmi */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** MIPI1toLVDS + HDMI */ +//#include "rp-lcd-mipi1tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi1tolvds-gm8775c-1920-1080.dtsi" + +/** LVDS + HDMI */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/** EDP + HDMI */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + +/{ + model = "nano-rk3568"; + compatible = "rpdzkj,nano-rk3568", "rockchip,rk3568"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&led_pin &fan_pin &usb_pins>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + led { //system led + gpio_num = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + //fan { //fan + // gpio_num = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + otg_power { //usb otg power + gpio_num = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { //usb hub + gpio_num = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb3_pwr { //usb3 power en + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb2_vdd0 { //usb2.0_vdd0 power en + gpio_num = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + usb2_vdd1 { //usb2.0_vdd1 power en + gpio_num = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /** + * gpioxxx { // the node name will display on /proc/rp_gpio, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio： 0 output, 1 input, 3 blink + * gpio_event = ; // optional property used to define gpio report event such as KEY_F14, only works incase of gpio_function = <1>; + * }; + */ +/* + gpio3_a7 { + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3_b0 { + gpio_num = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; +*/ + gpio4_a0 { + gpio_num = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4_a1 { + gpio_num = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + }; + + + vcc3v3_pi6c: vcc3v3_pi6c { //pcie3 clk enable for m.2 + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pi6c"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_clk_control>; + }; + + vdd3v3_m2: vdd3v3_m2 { //m.2 power enable + compatible = "regulator-fixed"; + regulator-name = "vdd3v3_m2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_m2_control>; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + +&vcc5v0_sys { + enable-active-high; + gpio = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_pin>; +}; + +&vdd_3v3 { + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&vdd3v3_pin>; + gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; +}; + +&vcc3v3_sd { + // enable-active-high; //active low + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_sd_pin>; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>; +}; + +&vdd_cpu { + pinctrl-names = "default"; + pinctrl-0 = <&vsel1_gpio>; + vsel-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; +}; + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + +&i2c1 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + // irq_gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c2 +{ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; +}; + +&i2c4 +{ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; +}; + +&uart0 { + status = "disabled"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; +}; + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi2m1_cs0 &spi2m1_pins>; + pinctrl-1 = <&spi2m1_cs0 &spi2m1_pins_hs>; + + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +/*********************************************/ + + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; +}; + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; +}; + + + + +&pwm12{ + status = "disabled"; + pinctrl-0 = <&pwm12m1_pins>; + pinctrl-names = "active"; +}; + +&pwm13{ + status = "disabled"; + pinctrl-0 = <&pwm13m1_pins>; + pinctrl-names = "active"; +}; + +/** LCD backlight + * By default, we all use backlight5 node whether it is mipi, lvds or edp, + */ +/** LCD configuration */ +#if defined(RP_SINGLE_LCD) + + #if defined(RP_MIPI12LVDS) + &backlight5 { + pwms = <&pwm8 0 25000 1>; + }; + + #if defined(RP_DUALLVDS) + &backlight5 { + pwms = <&pwm8 0 25000 0>; + }; + #endif + + #endif + +#endif + + +/** headphone detect pin */ +&rk_headset { + status = "disabled"; + pinctrl-0 = <&hp_det>; +}; + +/** wifi/bt config */ +&sdio_pwrseq { + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; +}; + +&sdmmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + status = "okay"; +}; + +&sdmmc1 { + status = "disabled"; +}; + +&wireless_wlan { + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + +&uart8 { + status = "disabled"; +}; + + +/** pcie2x1 */ +&vcc3v3_pcie { + /** + * delete for gpio used to be bt_wake_host + * and the vcc3v3_pcie need not control on our board. + */ + /delete-property/ gpio; +}; + +/******* pcie2x1x1 -rtl8111hs*****/ +&pcie2x1 { + status = "okay"; + + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; +}; + +/******* pcie3x1x1 -rtl8111hs*****/ +&pcie3x1 { + status = "okay"; + reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; +}; + +/******* pcie3x2x1 -m.2*****/ +&pcie3x2 { + status = "okay"; + reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + power_pins { + vdd3v3_pin: vdd3v3-pin { + rockchip,pins = + <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vcc5v0_pin: vcc5v0-pin { + rockchip,pins = + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vcc3v3_sd_pin: vcc3v3-sd-pin { + rockchip,pins = + <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + led_pin: led-pin { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + fan_pin: fan-pin { + rockchip,pins = + <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + usb_pins: usb-pins { + rockchip,pins = + /* otg power en */ + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, + /* hub reset pin */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, + /* usb3.0 power en */ + <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, + /* usb2.0 vdd0 en */ + <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, + /* usb2.0 vdd1 en */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { //redefine hp detect pin + hp_det: hp-det { + rockchip,pins = + <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { //redefine sdio power pin + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + wireless-wlan { //redefine wlaD4wake host pin + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 0 &pcfg_pull_down>; + }; + }; + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 0 &pcfg_pull_none>; + }; + }; + + pcie3_control{ + pcie_clk_control: pcie_clk_control { + rockchip,pins = + <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + vdd_m2_control: vdd_m2_control { + rockchip,pins = + <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + diff --git a/rk356x/pro-rk3566-single-lcd-gpio.dtsi b/rk356x/pro-rk3566-single-lcd-gpio.dtsi new file mode 100755 index 0000000..9c8bfbf --- /dev/null +++ b/rk356x/pro-rk3566-single-lcd-gpio.dtsi @@ -0,0 +1,122 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + + + diff --git a/rk356x/pro-rk3566.dts b/rk356x/pro-rk3566.dts new file mode 100755 index 0000000..ccf5bf8 --- /dev/null +++ b/rk356x/pro-rk3566.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" + +#include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" + + +#include "../rk3568-linux.dtsi" +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3566.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + + +/*************************SATA***********************/ +#include "rk3568-sata2.dtsi" +/***************************************************/ + +/****************** SINGLE LCD ***************/ +#include "pro-rk3566-single-lcd-gpio.dtsi" + +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" + +/* MIPI1 */ +//#include "rp-lcd-mipi1-7-1024-600.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-10-1024-600.dtsi" +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" + + + + + + +/ { + model = "pro-rk3566"; + compatible = "rpdzkj,pro-rk3566", "rockchip,rk3566"; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + pwr_5v_3v3 { //3.3v 5v enable + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + led { //system led + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb_pwr { // usb host power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg_pwr { + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_rst { //usb hub reset + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //SPK ENABLE + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //SPK MUTE + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + usb_mode { //OTG SWITCH + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; +}; + + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + +/***** SPI_FLASH ********/ + gpio1d0 { + gpio_num = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1d1 { + gpio_num = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio1d2 { + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1d3 { + gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio1d4 { + gpio_num = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + +/***** PDM ********/ + + gpio4a0 { + gpio_num = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a1 { + gpio_num = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio4a2 { + gpio_num = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a3 { + gpio_num = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1a4 { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3c1 { + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + test-power { + /** disable for use rk809-battery */ + status = "disabled"; + }; + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <7000>; + rockchip,screen-on-voltage = <7000>; + status = "okay"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&cpu0_opp_table { + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <825000 825000 1150000>; + opp-microvolt-L0 = <825000 825000 1150000>; + opp-microvolt-L1 = <800000 800000 1150000>; + opp-microvolt-L2 = <800000 800000 1150000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <850000 850000 1150000>; + opp-microvolt-L0 = <850000 850000 1150000>; + opp-microvolt-L1 = <825000 825000 1150000>; + opp-microvolt-L2 = <825000 825000 1150000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <900000 900000 1150000>; + opp-microvolt-L0 = <900000 900000 1150000>; + opp-microvolt-L1 = <875000 875000 1150000>; + opp-microvolt-L2 = <875000 875000 1150000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1104000000 { + opp-hz = /bits/ 64 <1104000000>; + opp-microvolt = <950000 950000 1150000>; + opp-microvolt-L0 = <950000 950000 1150000>; + opp-microvolt-L1 = <925000 925000 1150000>; + opp-microvolt-L2 = <925000 925000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <1000000 1000000 1150000>; + opp-microvolt-L0 = <1000000 1000000 1150000>; + opp-microvolt-L1 = <975000 975000 1150000>; + opp-microvolt-L2 = <975000 975000 1150000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <1050000 1050000 1150000>; + opp-microvolt-L0 = <1050000 1050000 1150000>; + opp-microvolt-L1 = <1025000 1025000 1150000>; + opp-microvolt-L2 = <1025000 1025000 1150000>; + clock-latency-ns = <40000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1100000 1100000 1150000>; + opp-microvolt-L0 = <1100000 1100000 1150000>; + opp-microvolt-L1 = <1075000 1075000 1150000>; + opp-microvolt-L2 = <1075000 1075000 1150000>; + clock-latency-ns = <40000>; + }; + +}; + + +&i2c1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi2 { + status = "okay"; + + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi3 { + status = "okay"; + + num-cs = <1>; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 &spi3m1_pins_hs>; + + spi3_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&edp { + /** delete hdp gpio that pro3566 donot use */ + /delete-property/ hpd-gpios; +}; + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +&rk809 { + battery { + compatible = "rk817,battery"; + pinctrl-names = "default"; + pinctrl-0 = <&rp_bat_pins>; + + ocv_table = < 7024 7072 7080 7096 7104 7112 7120 + 7136 7152 7168 7184 7224 7264 7320 + 7392 7512 7612 7724 7828 7928 8100>; + design_capacity = <5000>; + design_qmax = <5100>; + bat_res = <100>; + sleep_enter_current = <300>; + sleep_exit_current = <300>; + sleep_filter_current = <100>; + power_off_thresd = <7024>; + zero_algorithm_vol = <7400>; + max_soc_offset = <60>; + monitor_sec = <5>; + + sample_res = <20>; + bat_res_up = <140>; + bat_res_down = <20>; + + virtual_power = <0>; //test mode, 1 to force report 66% + energy_mode = <0>; + register_chg_psy = <1>; //rk817 report charge state + + plug-det-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; //rpdzkj add for detect charge state, need register_chg_psy = 1, active state is plugin. + full-det-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; //rpdzkj add for detect charge status whether is full. + }; +}; + + + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + + + +&rk_headset { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + }; + + + +&pinctrl { + rp-pins { + rp_bat_pins: rp-bat-pins { + rockchip,pins = + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk809_codec { + mic-in-differential; +}; diff --git a/rk356x/pro-rk3568-ahd-single-lcd-gpio.dtsi b/rk356x/pro-rk3568-ahd-single-lcd-gpio.dtsi new file mode 100755 index 0000000..fc82e46 --- /dev/null +++ b/rk356x/pro-rk3568-ahd-single-lcd-gpio.dtsi @@ -0,0 +1,170 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + + + +// MIPI DSI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// MIPI DSI1 TO LVDS +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; //raw interface is inverse, so set to low + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// EDP +&edp { + /** delete hdp gpio that pro-rk3568-ahd donot use */ + /delete-property/ hpd-gpios; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + + +// POWER GPIO +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +// TP +&i2c1 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/pro-rk3568-ahd.dts b/rk356x/pro-rk3568-ahd.dts new file mode 100755 index 0000000..fb9f2fa --- /dev/null +++ b/rk356x/pro-rk3568-ahd.dts @@ -0,0 +1,432 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm.dtsi" + + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +#include "rp-mipi-camera-xs9922b-ahd.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +//#include "rp-can1-m1-rk3568.dtsi" +//#include "rp-can2-m0-rk3568.dtsi" +/**************************************************/ + + +/*************************PCIE***********************/ +#include "rk3568-pcie2x1.dtsi" +#include "rk3568-pcie3x2.dtsi" +/***************************************************/ + + + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "pro-rk3568-ahd-single-lcd-gpio.dtsi" // gpio config of lcd +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" + +/* MIPI DSI1 to LVDS*/ +//#include "rp-lcd-mipi1tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi1tolvds-gm8775c-1920-1080.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + +/{ + + model = "pro-rk3568-ahd"; + compatible = "rpdzkj,pro-rk3568-v10", "rockchip,rk3568"; + + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + vdd_5v_3v3: vdd_5v_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //注æ„驱动解æžçš„是gpio还是gpios + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_5v_3v3_control>; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + pinctrl-1 = <&vcc5v0_otg_en>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + led { //system led + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + // fan { //fan + // gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + // }; + usb_pwr { //usb power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //usb hub + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + /* + vdd_5v_3v3 { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + */ + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_en { //spk enable + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + xs9922b_31_pwr { //ahd power + gpio_num = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + xs9922b_30_pwr { //v10:need enable ahd_30 power ;Otherwise, this i2c cannot read other devices + gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd_4G{ + gpio_num = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + gps_power{ + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + + +&i2c1 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +/*open gps power*/ +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_pins>; + pinctrl-1 = <&spi0m0_cs0 &spi0m0_pins_hs>; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; +/*********************************************/ + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + + +/** + * when single [mipi1 to lvds] ports used, pwm need the pwm5, + * and if mutiple lcd used, we just reference the backlight5. + */ +#if defined(RP_MIPI12LVDS) && defined(RP_SINGLE_LCD) +&backlight4 { + pwms = <&pwm5 0 25000 0>; +}; +#endif + +/** pcie2x1 */ +&vcc3v3_pcie { + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; +}; + +/** pcie3x2 */ +&pcie3x2 { + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie3>; +}; + +&vcc3v3_pcie3 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_3v3>; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + + startup-delay-us = <8000>; //5000 is faild +}; + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; +}; + + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc3v3-pcie3 { + pcie3_3v3: pcie3-3v3 { + rockchip,pins = + /** power supply enable pin */ + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vdd-5v-3v3 { + vdd_5v_3v3_control: vdd-5v-3v3-control { + rockchip,pins = + /** power supply enable pin */ + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/pro-rk3568-dual-lcd-gpio.dtsi b/rk356x/pro-rk3568-dual-lcd-gpio.dtsi new file mode 100755 index 0000000..75e1c3e --- /dev/null +++ b/rk356x/pro-rk3568-dual-lcd-gpio.dtsi @@ -0,0 +1,43 @@ +/** + * multiple lcd config compatible + */ + +// MIPI DSI0 +&dsi0_panel { + /** delete property that conflict with other panel, they are common */ + /delete-property/ power-supply; + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + backlight = <&backlight4>; +}; + +// MIPI DSI1 +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight5>; +}; + +// LVDS +&lvds_panel { + backlight = <&backlight4>; + + /** delete property that conflict with other panel, they are common */ + /delete-property/ power-supply; + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + +// EDP +&edp_panel { + backlight = <&backlight5>; + + /** delete property that conflict with other panel, it is common */ + /delete-property/ power-supply; +}; + + diff --git a/rk356x/pro-rk3568-h-single-lcd-gpio.dtsi b/rk356x/pro-rk3568-h-single-lcd-gpio.dtsi new file mode 100755 index 0000000..49bde05 --- /dev/null +++ b/rk356x/pro-rk3568-h-single-lcd-gpio.dtsi @@ -0,0 +1,180 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + + + +// MIPI DSI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi0_pins>; + backlight = <&backlight4>; +}; + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; +// reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi0_pins>; + backlight = <&backlight4>; +}; + +// EDP +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_pins>; + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + backlight = <&backlight4>; +}; + + +// POWER GPIO +&vcc3v3_lcd0_n { + // gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + /delete-property/ gpio; + enable-active-high; +}; + +// TP +&i2c1 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; +}; + +&pinctrl { + lcd_pins { + mipi0_pins: mipi0-pins { + rockchip,pins = + /** mipi0 enable */ + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>, + /** mipi0 reset */ + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + edp_pins: edp-pins { + rockchip,pins = + /** edp enable */ + <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_pins: goodix-pins { + rockchip,pins = + /** rst pin */ + <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + /** irq pin */ + <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/pro-rk3568-h.dts b/rk356x/pro-rk3568-h.dts new file mode 100755 index 0000000..f0380de --- /dev/null +++ b/rk356x/pro-rk3568-h.dts @@ -0,0 +1,473 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm-pcie-wifi.dtsi" + + +#include "../rk3568-linux.dtsi" + +/*************************HDMI IN***********************/ +#include "rp-mipi-camera-rk628d-csi2hdmi.dtsi" +/***************************************************/ + +/*************************PCIE***********************/ +#include "rk3568-pcie2x1.dtsi" +#include "rp-pcie-5g.dtsi" +/***************************************************/ + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ + +/*************************wifi***********************/ +#include "rp-wifi-bt-ap6275p-rk3568.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +#include "rp-can1-m1-rk3568.dtsi" +#include "rp-can2-m0-rk3568.dtsi" +/**************************************************/ + + + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "pro-rk3568-h-single-lcd-gpio.dtsi" + +/* HDMI */ +//#include "rp-lcd-mipi2hdmi-lt8912.dtsi" //dsi1-lt8912-hdmi + HDMI + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" + + +/* LVDS */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1024-600.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/*MIPI TO LVDS */ +//#include "rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi" +//#include "rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi" + + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" +//null +//null +//null + + + + +#ifdef RP_TRIPLE_LCD + #include "pro-rk3568-triple-lcd-gpio.dtsi" // if use triple lcd, must enable it +#endif + +#ifdef RP_DUAL_LCD + #include "pro-rk3568-dual-lcd-gpio.dtsi" // if use dual lcd, must enable it +#endif + + + + + + +/{ + + model = "pro-rk3568-h"; + compatible = "rpdzkj,pro-rk3568-h", "rockchip,rk3568"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + vcc3v3_pcie3: gpio-regulator-pcie3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; //In the uboot phase fixed.c resolves gpio + pinctrl-names = "default"; + pinctrl-0 = <&vcc3v3_pcie30>; + }; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + pinctrl-1 = <&vcc5v0_otg_en>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + led { //system led + gpio_num = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + usb_pwr { //usb power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //usb hub + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + uart_en { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_en { //spk enable + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + 4g_power { //4g power + gpio_num = <&gpio3 RK_PD0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + HDMI_5V { + gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3b5 { //pcie power + gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3a7 { //pcie clock + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + + +&i2c1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + +&sdmmc2 { + status = "disabled"; + +}; + +&uart0 { + status = "okay"; +}; + + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_pins>; + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + + + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; +/*********************************************/ + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + + +/** + * when single mipi1 or edp ports used, pwm need the pwm5, + * and if mutiple lcd used, we just reference the backlight5. + */ +//#if (defined(RP_MIPI1_USED) || defined(RP_EDP_USED)) && defined(RP_SINGLE_LCD) +#if defined(RP_EDP_USED) && defined(RP_SINGLE_LCD) +&backlight4 { + pwms = <&pwm5 0 25000 0>; +}; +#endif + + +#if defined(RP_SINGLE_LCD) && defined(RP_MIPI02LVDS) + + &backlight4{ + pwms = <&pwm4 0 25000 0>; + }; + &dsi0_panel { + enable-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; +#endif + + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>,<&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ +&pcie2x1 { + /** + * gpio please refer to main dts: + * reset-gpios = <&gpio* ** ***>; + */ + reset-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + +}; + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; +}; + + +&pinctrl { + spi1 { + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_down>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_down>; + }; +}; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc3v3-pcie3 { + vcc3v3_pcie30: vcc3v3-pcie3 { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; diff --git a/rk356x/pro-rk3568-single-lcd-gpio.dtsi b/rk356x/pro-rk3568-single-lcd-gpio.dtsi new file mode 100755 index 0000000..edb8e48 --- /dev/null +++ b/rk356x/pro-rk3568-single-lcd-gpio.dtsi @@ -0,0 +1,169 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + backlight5: backlight5 { + compatible = "pwm-backlight"; + pwms = <&pwm5 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + + +&pwm4 { + status = "okay"; +}; + +&pwm5 { + status = "okay"; +}; + + + +// MIPI DSI0 +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// MIPI DSI1 +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// LVDS +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +// EDP +&edp { + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; +}; +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + + +// POWER GPIO +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +// TP +&i2c1 { + gt9xx: goodix_ts@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + diff --git a/rk356x/pro-rk3568-triple-lcd-gpio.dtsi b/rk356x/pro-rk3568-triple-lcd-gpio.dtsi new file mode 100755 index 0000000..0fc223a --- /dev/null +++ b/rk356x/pro-rk3568-triple-lcd-gpio.dtsi @@ -0,0 +1,36 @@ +/* + * multiple lcd config compatible + */ + +// MIPI DSI0 +&dsi0_panel { + status = "disabled"; +}; + +// MIPI DSI1 +&dsi1_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight5>; +}; + +// LVDS +&lvds_panel { + backlight = <&backlight4>; + + /** delete property that conflict with other panel, they are common */ + /delete-property/ power-supply; + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + +// EDP +&edp_panel { + /** delete property that conflict with other panel, they are common */ + /delete-property/ power-supply; + /delete-property/ backlight; +}; + diff --git a/rk356x/pro-rk3568.dts b/rk356x/pro-rk3568.dts new file mode 100755 index 0000000..8b62507 --- /dev/null +++ b/rk356x/pro-rk3568.dts @@ -0,0 +1,405 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm.dtsi" + + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +//#include "rp-mipi-camera-gc2093-rk3568.dtsi" +//#include "rp-mipi-camera-gc2093-imx334-imx415-rk3568.dtsi" +#include "rp-mipi-camera-gc2093x2-rk3568.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ + +/*************************CAN**********************/ +#include "rp-can1-m1-rk3568.dtsi" +#include "rp-can2-m0-rk3568.dtsi" +/**************************************************/ + + +/*************************SATA***********************/ +#include "rk3568-sata2.dtsi" +/***************************************************/ + + + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "pro-rk3568-single-lcd-gpio.dtsi" // gpio config of lcd +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" +#include "rp-lcd-mipi1-10-1920-1200.dtsi" + +/* MIPI DSI1 */ +//#include "rp-lcd-mipi1-7-1024-600.dtsi" +//#include "rp-lcd-mipi1-7-1200-1920.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1024-600.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + +/************************ DUAL LCD *********************/ +/* LVDS + MIPI1 */ +//#include "rp-lcd-dual-lvds-7-1024-600-mipi1-5-720-1280-v2.dtsi" +//#include "rp-lcd-dual-lvds-10-1024-600-mipi1-7-1200-1920.dtsi" + +/* MIPI0 + MIPI1 */ +//#include "rp-lcd-dual-mipi0-7-1024-600-mipi1-5-720-1280-v2.dtsi" + +/********************** TRIPLE LCD ********************/ +/* LVDS + MIPI1 + EDP */ +//#include "rp-lcd-triple-lvds-10-1024-600-mipi1-7-1024-600-edp-13-1920-1080.dtsi" + + + +#ifdef RP_TRIPLE_LCD + #include "pro-rk3568-triple-lcd-gpio.dtsi" // if use triple lcd, must enable it +#endif + +#ifdef RP_DUAL_LCD + #include "pro-rk3568-dual-lcd-gpio.dtsi" // if use dual lcd, must enable it +#endif + + + + + + +/{ + + model = "pro-rk3568"; + compatible = "rpdzkj,pro-rk3568-v10", "rockchip,rk3568"; + + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + pinctrl-1 = <&vcc5v0_otg_en>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + + led { //system led + gpio_num = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + usb_pwr { //usb power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //usb hub + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + otg_mode { //OTG SWITCH + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + otg_power { //usb otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_en { //spk enable + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3b5 { //pcie power + gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3a7 { //pcie clock + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + + +&i2c1 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + + + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; +/*********************************************/ + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + + +/** + * when single mipi1 or edp ports used, pwm need the pwm5, + * and if mutiple lcd used, we just reference the backlight5. + */ +#if (defined(RP_MIPI1_USED) || defined(RP_EDP_USED)) && defined(RP_SINGLE_LCD) +&backlight4 { + pwms = <&pwm5 0 25000 0>; +}; +#endif + + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; +}; + + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; diff --git a/rk356x/rk3566-evb-rpdzkj-pwm-pwm.dtsi b/rk356x/rk3566-evb-rpdzkj-pwm-pwm.dtsi new file mode 100755 index 0000000..a969e0c --- /dev/null +++ b/rk356x/rk3566-evb-rpdzkj-pwm-pwm.dtsi @@ -0,0 +1,1060 @@ +/** + * configure regulators that for not use rk809 + * + * most content of this file is from rk3566-evb1-ddr4-v10.dtsi + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "../rk3566.dtsi" + + +/ { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; + }; + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + +/* + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +*/ + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + + + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + //clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; + + /** + * configuration of regulator that no rk809 + */ + vcc3v3_pmu: vcc3v3-pmu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_logic_gpu_npu: vdd-logic_gpu_npu { + compatible = "pwm-regulator"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_logic_gpu_npu"; + rockchip,pwm_id = <1>; + pwms = <&pwm1 0 25000 1>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1100000>; + regulator-init-microvolt = <1000000>; + pwm-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_cpu"; + rockchip,pwm_id = <0>; + pwms = <&pwm0 0 25000 1>; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1250000>; + regulator-init-microvolt = <1000000>; + pwm-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9: vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: vccio-sd-regulator { + compatible = "regulator-gpio"; + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpios-states = <0x1>; + states = <1800000 0x0 + 3300000 0x1>; + }; + + vcca_1v8: vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: vcc3v3_sd { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_wl: vccio_wl{ + compatible = "regulator-fixed"; + regulator-name = "vccio_wl"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; +}; + +&bus_npu { + bus-supply = <&vdd_logic_gpu_npu>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_logic_gpu_npu>; + status = "okay"; +}; + + + +&gpu { + mali-supply = <&vdd_logic_gpu_npu>; + status = "okay"; +}; + + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +/* + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + vdec-supply = <&vdd_logic_gpu_npu>; + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic_gpu_npu>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_logic_gpu_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + +&audiopwmout_diff { + status = "disabled"; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + + + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + + + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; +&gpu_opp_table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 91000 1 + 91001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + opp-microvolt-L0 = <1000000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + }; + + +&npu_opp_table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 700 50000 + >; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 91000 1 + 91001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1000000 1000000 1000000>; + opp-microvolt-L0 = <975000 975000 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>; + opp-microvolt-L2 = <975000 975000 1000000>; + status = "disabled"; + }; + }; + +&rkvdec_opp_table { + compatible = "operating-points-v2"; + + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <975000>; + }; + }; + +&rkvenc_opp_table { + compatible = "operating-points-v2"; + + nvmem-cells = <&core_pvtm>; + nvmem-cell-names = "pvtm"; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 91000 1 + 91001 100000 2 + >; + rockchip,pvtm-ch = <0 5>; + + opp-297000000 { + opp-hz = /bits/ 64 <297000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + opp-microvolt-L2 = <975000>; + }; + }; + +&dmc_opp_table { + compatible = "operating-points-v2"; + + mbist-vmin = <825000 900000 950000>; + nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>; + nvmem-cell-names = "leakage", "pvtm", "mbist-vmin"; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <0>; + rockchip,low-temp-adjust-volt = < + /* MHz MHz uV */ + 0 1560 75000 + >; + rockchip,leakage-voltage-sel = < + 1 80 0 + 81 254 1 + >; + rockchip,pvtm-voltage-sel = < + 0 84000 0 + 84001 100000 1 + >; + rockchip,pvtm-ch = <0 5>; + + opp-1560000000 { + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <975000>; + opp-microvolt-L0 = <975000>; + opp-microvolt-L1 = <975000>; + }; + }; diff --git a/rk356x/rk3566-evb-rpdzkj-rk809-syr837.dtsi b/rk356x/rk3566-evb-rpdzkj-rk809-syr837.dtsi new file mode 100755 index 0000000..a54d519 --- /dev/null +++ b/rk356x/rk3566-evb-rpdzkj-rk809-syr837.dtsi @@ -0,0 +1,1044 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "../rk3566.dtsi" + +/ { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; + }; + + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + +/* + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +*/ + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + //hp-det-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + //pinctrl-names = "default"; + //pinctrl-0 = <&hp_det>; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; +/* + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; +// gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +// pinctrl-names = "default"; +// pinctrl-0 = <&vcc5v0_host_en>; + }; + + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; +// gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; +// pinctrl-names = "default"; +// pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +*/ + +/* + vcc3v3_lcd_n: vcc3v3-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +*/ + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +/* + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; +*/ + + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <50>; //3(max)-255(min) + spk-volume = <50>; //3(max)-255(min) + capture_volume = <255>; + //mic-in-differential; + status = "okay"; + }; + }; +}; + + +&i2c0 { + status = "okay"; + + vdd_cpu: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + // pinctrl-0 = <&vsel1_gpio>; + // vsel-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <1000000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +/* + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + + +&audiopwmout_diff { + status = "disabled"; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + + + +// sata usb30 pcie phys +/*&combphy0_us { + status = "okay"; +}; +*/ + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + +/* +&pinctrl { + pmic { + vsel1_gpio: vsel1-gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; +*/ + + +//gpio0_b0 for hub reset pin +/delete-node/ &xin32k; diff --git a/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi b/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi new file mode 100755 index 0000000..c5df879 --- /dev/null +++ b/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi @@ -0,0 +1,1029 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "../rk3566.dtsi" + +/ { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; + }; + + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + +/* + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +*/ + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + //hp-det-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + //pinctrl-names = "default"; + //pinctrl-0 = <&hp_det>; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; +/* + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; +// gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; +// pinctrl-names = "default"; +// pinctrl-0 = <&vcc5v0_host_en>; + }; + + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; +// gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; +// pinctrl-names = "default"; +// pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc3v3_bu: vcc3v3-bu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_bu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; +*/ + +/* + vcc3v3_lcd_n: vcc3v3-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +*/ + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + +/* + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; +*/ + + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <50>; //3(max)-255(min) + spk-volume = <50>; //3(max)-255(min) + capture_volume = <255>; + //mic-in-differential; + status = "okay"; + }; + }; +}; + + +&i2c0 { + status = "okay"; + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-init-microvolt = <1000000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +/* + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + + +&audiopwmout_diff { + status = "disabled"; +}; + +&dig_acodec { + status = "disabled"; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&audiopwm_loutp + &audiopwm_loutn + &audiopwm_routp + &audiopwm_routn + >; +}; +&pdm { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pdmm1_clk1 + &pdmm1_sdi1 + &pdmm1_sdi2 + &pdmm1_sdi3>; +}; + +&pdmics { + status = "disabled"; +}; + +&pdm_mic_array { + status = "disabled"; +}; + + + +// sata usb30 pcie phys +/*&combphy0_us { + status = "okay"; +}; +*/ + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + + + +//gpio0_b0 for hub reset pin +/delete-node/ &xin32k; diff --git a/rk356x/rk3568-evb-rpdzkj-pwm-pwm-syr837.dtsi b/rk356x/rk3568-evb-rpdzkj-pwm-pwm-syr837.dtsi new file mode 100755 index 0000000..b0d9000 --- /dev/null +++ b/rk356x/rk3568-evb-rpdzkj-pwm-pwm-syr837.dtsi @@ -0,0 +1,778 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "../rk3568.dtsi" + + / { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; + }; + + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&hdmi>; + }; +/* + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +*/ + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + //clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + //clocks = <&rk809 1>; + //clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; + + + /** + * configuration of regulator that no rk809 + */ + vcc3v3_pmu: vcc3v3-pmu { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdda_0v9: vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: vcc-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_3v3: vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: vccio-sd { + compatible = "regulator-fixed"; + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: vcc3v3-sd { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc_3v3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8: vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic: vdd-logic { + compatible = "pwm-regulator"; + regulator-always-on; + regulator-boot-on; + rockchip,pwm_id = <1>; + pwms = <&pwm1 0 25000 1>; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1000000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + pwm-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_npu: vdd-gpu-npu { + compatible = "pwm-regulator"; + rockchip,pwm_id = <2>; + pwms = <&pwm2 0 25000 1>; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1125000>; + regulator-init-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd_gpu_npu"; + pwm-supply = <&vcc3v3_sys>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_3v3: vdd-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + vin-supply = <&vcc3v3_sys>; + }; + + vdd_fixed: vdd-fixed { + compatible = "regulator-fixed"; + regulator-name = "vdd_fixed"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc3v3_sys>; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + + +&dfi { + status = "disabled"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + + + +&gpu { + mali-supply = <&vdd_fixed>; + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_fixed>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + +// sata usb30 pcie phys +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + + + +//gpio0_b0 for hub reset pin +/delete-node/ &xin32k; + + +&spdif_8ch { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spdifm1_tx>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + compatible = "bluetooth-platdata"; + //clocks = <&rk809 1>; + //clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + +&pwm1 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; +}; + + +&pwm2 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; +}; + + +&i2c0 { + status = "okay"; + + vdd_cpu: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc3v3_sys>; + regulator-compatible = "fan53555-reg"; + // pinctrl-names = "default"; + // pinctrl-0 = <&vsel1_gpio>; + // vsel-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; diff --git a/rk356x/rk3568-evb-rpdzkj-rk809-pwm-pcie-wifi.dtsi b/rk356x/rk3568-evb-rpdzkj-rk809-pwm-pcie-wifi.dtsi new file mode 100755 index 0000000..77b2b81 --- /dev/null +++ b/rk356x/rk3568-evb-rpdzkj-rk809-pwm-pcie-wifi.dtsi @@ -0,0 +1,930 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "../rk3568.dtsi" + +/ { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; + }; + + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1250000>; + regulator-init-microvolt = <1000000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip,hdmi"; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&hdmi>; + }; +/* + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +*/ + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rk809-codec"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rk809_codec>; + }; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + +/* + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + +// +// * On the module itself this is one of these (depending +// * on the actual card populated): +// * - SDIO_RESET_L_WL_REG_ON +// * - PDN (power down when low) +// + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +*/ + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <3>; //3(max)-255(min) + spk-volume = <30>; //3(max)-255(min) + capture_volume = <255>; + //mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_up>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; +/* + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; +/* +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; +*/ +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + +// sata usb30 pcie phys +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + + + +//gpio0_b0 for hub reset pin +/delete-node/ &xin32k; diff --git a/rk356x/rk3568-evb-rpdzkj-rk809-pwm.dtsi b/rk356x/rk3568-evb-rpdzkj-rk809-pwm.dtsi new file mode 100755 index 0000000..1de1d8b --- /dev/null +++ b/rk356x/rk3568-evb-rpdzkj-rk809-pwm.dtsi @@ -0,0 +1,929 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "../rk3568.dtsi" + +/ { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; + }; + + + vdd_cpu: vdd-cpu { + compatible = "pwm-regulator"; + pwms = <&pwm0 0 5000 1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1250000>; + regulator-init-microvolt = <1000000>; + regulator-ramp-delay = <6001>; + regulator-always-on; + regulator-boot-on; + regulator-settling-time-up-us = <250>; + pwm-supply = <&vcc5v0_sys>; + status = "okay"; + }; + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + //hp-det-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + //pinctrl-names = "default"; + //pinctrl-0 = <&hp_det>; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <3>; //3(max)-255(min) + spk-volume = <30>; //3(max)-255(min) + capture_volume = <255>; + //mic-in-differential; + adc-for-loopback; + status = "okay"; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +/* + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + +// sata usb30 pcie phys +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + + + +//gpio0_b0 for hub reset pin +/delete-node/ &xin32k; diff --git a/rk356x/rk3568-evb-rpdzkj-rk809-syr837.dtsi b/rk356x/rk3568-evb-rpdzkj-rk809-syr837.dtsi new file mode 100755 index 0000000..a76f5aa --- /dev/null +++ b/rk356x/rk3568-evb-rpdzkj-rk809-syr837.dtsi @@ -0,0 +1,936 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "../rk3568.dtsi" + +/ { + + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + extend_rotate_2 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_2 = "true"; + extend_rotate_3 = "0";//0 0//1 90 //2 180 //3 270 + rotation_efull_3 = "true"; + home_apk = "null"; + status = "okay"; + }; + + + edp_panel:panel { + status = "disabled"; + }; + + lvds_panel: panel@0 { + status = "disabled"; + }; + + + + audiopwmout_diff: audiopwmout-diff { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,audiopwmout-diff"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&master>; + simple-audio-card,frame-master = <&master>; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + master: simple-audio-card,codec { + sound-dai = <&dig_acodec>; + }; + }; + + + + rk_headset: rk-headset { + compatible = "rockchip_headset"; +// headset_gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + + dc_12v: dc-12v { + compatible = "regulator-fixed"; + regulator-name = "dc_12v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,hdmi"; + status = "disabled"; + + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + }; + + pdmics: dummy-codec { + status = "disabled"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + pdm_mic_array: pdm-mic-array { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,pdm-mic-array"; + simple-audio-card,cpu { + sound-dai = <&pdm>; + }; + simple-audio-card,codec { + sound-dai = <&pdmics>; + }; + }; + + rk809_sound: rk809-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-rk809"; + //hp-det-gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>; + //pinctrl-names = "default"; + //pinctrl-0 = <&hp_det>; + }; + + spdif-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "ROCKCHIP,SPDIF"; + simple-audio-card,cpu { + sound-dai = <&spdif_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_out>; + }; + }; + + spdif_out: spdif-out { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vad_sound: vad-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,rk3568-vad"; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&rk809_codec>, <&vad>; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + + vcc3v3_lcd0_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_lcd1_n: vcc3v3-lcd1-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd1_n"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; +// gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc3v3_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vcc2v5_sys: vcc2v5-ddr { + compatible = "regulator-fixed"; + regulator-name = "vcc2v5-sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + vin-supply = <&vcc3v3_sys>; + }; + + + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + rockchip,grf = <&grf>; + wifi_chip_type = "ap6398s"; + status = "okay"; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + //wifi-bt-power-toggle; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + test-power { + status = "okay"; + }; +}; + + +&i2c0 { + status = "okay"; + + vdd_cpu: syr837@40 { + compatible = "silergy,syr827"; + reg = <0x40>; + vin-supply = <&vcc3v3_sys>; + regulator-compatible = "fan53555-reg"; + // pinctrl-names = "default"; + // pinctrl-0 = <&vsel1_gpio>; + // vsel-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-initial-state = <3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&bus_npu { + bus-supply = <&vdd_logic>; + pvtm-supply = <&vdd_cpu>; + status = "okay"; +}; + +&pwm0 { + status = "okay"; + pinctrl-names = "active"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + center-supply = <&vdd_logic>; + status = "disabled"; +}; + + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + + +&i2c0 { + status = "okay"; + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep", + "pmic-power-off", "pmic-reset"; + pinctrl-0 = <&pmic_int>; + pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; + pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; + pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; + + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + //fb-inner-reg-idxs = <2>; + /* 1: rst regs (default in codes), 0: rst the pmic */ + pmic-reset-func = <0>; + /* not save the PMIC_POWER_EN register in uboot */ + not-save-power-en = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk8xx: pinctrl_rk8xx { + gpio-controller; + #gpio-cells = <2>; + + rk817_slppin_null: rk817_slppin_null { + pins = "gpio_slp"; + function = "pin_fun0"; + }; + + rk817_slppin_slp: rk817_slppin_slp { + pins = "gpio_slp"; + function = "pin_fun1"; + }; + + rk817_slppin_pwrdn: rk817_slppin_pwrdn { + pins = "gpio_slp"; + function = "pin_fun2"; + }; + + rk817_slppin_rst: rk817_slppin_rst { + pins = "gpio_slp"; + function = "pin_fun3"; + }; + }; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_logic"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + rk809_codec: codec { + #sound-dai-cells = <0>; + compatible = "rockchip,rk809-codec", "rockchip,rk817-codec"; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + hp-volume = <100>; //3(max)-255(min) + spk-volume = <100>; //3(max)-255(min) + capture_volume = <255>; + //mic-in-differential; + status = "okay"; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2s1_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&nandc0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + nand@0 { + reg = <0>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <16>; + nand-ecc-step-size = <1024>; + }; +}; + +&pinctrl { + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + soc_slppin_gpio: soc_slppin_gpio { + rockchip,pins = + <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + soc_slppin_slp: soc_slppin_slp { + rockchip,pins = + <0 RK_PA2 1 &pcfg_pull_none>; + }; + + soc_slppin_rst: soc_slppin_rst { + rockchip,pins = + <0 RK_PA2 2 &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +/* + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +*/ + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + /* + * There are 10 independent IO domains in RK3566/RK3568, including PMUIO[0:2] and VCCIO[1:7]. + * 1/ PMUIO0 and PMUIO1 are fixed-level power domains which cannot be configured; + * 2/ PMUIO2 and VCCIO1,VCCIO[3:7] domains require that their hardware power supply voltages + * must be consistent with the software configuration correspondingly + * a/ When the hardware IO level is connected to 1.8V, the software voltage configuration + * should also be configured to 1.8V accordingly; + * b/ When the hardware IO level is connected to 3.3V, the software voltage configuration + * should also be configured to 3.3V accordingly; + * 3/ VCCIO2 voltage control selection (0xFDC20140) + * BIT[0]: 0x0: from GPIO_0A7 (default) + * BIT[0]: 0x1: from GRF + * Default is determined by Pin FLASH_VOL_SEL/GPIO0_A7: + * L:VCCIO2 must supply 3.3V + * H:VCCIO2 must supply 1.8V + */ +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + + +&rk_rga { + status = "okay"; +}; + +&rkvdec { + status = "okay"; +}; + +&rkvdec_mmu { + status = "okay"; +}; + +&rkvenc { + venc-supply = <&vdd_logic>; + status = "okay"; +}; + +&rkvenc_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcca_1v8>; +}; + +&sdhci { + bus-width = <8>; + supports-emmc; + non-removable; + max-frequency = <200000000>; + status = "okay"; +}; + +&sdmmc0 { + max-frequency = <150000000>; + supports-sd; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + status = "okay"; +}; + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sfc { + status = "okay"; +}; + +&spdif_8ch { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy0_otg { +// vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_host { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy1_otg { +// phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdrd_dwc3 { + dr_mode = "otg"; + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usbdrd30 { + status = "okay"; +}; + +&usbhost_dwc3 { + status = "okay"; +}; + +&usbhost30 { + status = "okay"; +}; + +&vad { + rockchip,audio-src = <&i2s1_8ch>; + rockchip,buffer-time-ms = <128>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vepu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +}; + +&vop_mmu { + status = "okay"; +}; + +&dsi0 { +dsi0_panel: panel@0 { + status = "disabled"; + }; +}; + +&dsi1 { +dsi1_panel: panel@0 { + status = "disabled"; + }; +}; + +// sata usb30 pcie phys +&combphy0_us { + status = "okay"; +}; + +&combphy1_usq { + status = "okay"; +}; + +&combphy2_psq { + status = "okay"; +}; + + + +//gpio0_b0 for hub reset pin +/delete-node/ &xin32k; diff --git a/rk356x/rk3568-pcie2x1.dtsi b/rk356x/rk3568-pcie2x1.dtsi new file mode 100755 index 0000000..0cfe428 --- /dev/null +++ b/rk356x/rk3568-pcie2x1.dtsi @@ -0,0 +1,38 @@ +/** + * enable pcie2x1 relavent config for rk3568 + */ + +/ { + vcc3v3_pcie: gpio-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + /** + * gpio config please refer to main dts if have + * gpio = <&gpio* ** ***>; + */ + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; + +}; + + +&combphy2_psq { + status = "okay"; +}; + +&sata2 { + status = "disabled"; +}; + +&pcie2x1 { + /** + * gpio please refer to main dts: + * reset-gpios = <&gpio* ** ***>; + */ + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; diff --git a/rk356x/rk3568-pcie3x1x1.dtsi b/rk356x/rk3568-pcie3x1x1.dtsi new file mode 100755 index 0000000..9263a7a --- /dev/null +++ b/rk356x/rk3568-pcie3x1x1.dtsi @@ -0,0 +1,41 @@ +/** + * enable pcie3x2 relavent config for rk3568 + */ + +/ { + vcc3v3_pcie3: gpio-regulator-pcie3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + /** + * gpio config please refer to main dts if have + * gpio = <&gpio* ** ***>; + */ + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +/** pcie3x1 and pcie3x2*/ +&pcie3x1 { + rockchip,bifurcation; + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie3>; +}; + +&pcie3x2 { + /** + * gpio please refer to main dts: + * reset-gpios = <&gpio* ** ***>; + */ + rockchip,bifurcation; + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie3>; +}; + diff --git a/rk356x/rk3568-pcie3x2.dtsi b/rk356x/rk3568-pcie3x2.dtsi new file mode 100755 index 0000000..a24dcb9 --- /dev/null +++ b/rk356x/rk3568-pcie3x2.dtsi @@ -0,0 +1,32 @@ +/** + * enable pcie3x2 relavent config for rk3568 + */ + +/ { + vcc3v3_pcie3: gpio-regulator-pcie3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + /** + * gpio config please refer to main dts if have + * gpio = <&gpio* ** ***>; + */ + startup-delay-us = <5000>; + vin-supply = <&dc_12v>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + /** + * gpio please refer to main dts: + * reset-gpios = <&gpio* ** ***>; + */ + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie3>; +}; diff --git a/rk356x/rk3568-pinctrl.dtsi b/rk356x/rk3568-pinctrl.dtsi new file mode 100755 index 0000000..714377c --- /dev/null +++ b/rk356x/rk3568-pinctrl.dtsi @@ -0,0 +1,3117 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + acodec { + /omit-if-no-ref/ + acodec_pins: acodec-pins { + rockchip,pins = + /* acodec_adc_sync */ + <1 RK_PB1 5 &pcfg_pull_none>, + /* acodec_adcclk */ + <1 RK_PA1 5 &pcfg_pull_none>, + /* acodec_adcdata */ + <1 RK_PA0 5 &pcfg_pull_none>, + /* acodec_dac_datal */ + <1 RK_PA7 5 &pcfg_pull_none>, + /* acodec_dac_datar */ + <1 RK_PB0 5 &pcfg_pull_none>, + /* acodec_dacclk */ + <1 RK_PA3 5 &pcfg_pull_none>, + /* acodec_dacsync */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + audiopwm { + /omit-if-no-ref/ + audiopwm_lout: audiopwm-lout { + rockchip,pins = + /* audiopwm_lout */ + <1 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutn: audiopwm-loutn { + rockchip,pins = + /* audiopwm_loutn */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_loutp: audiopwm-loutp { + rockchip,pins = + /* audiopwm_loutp */ + <1 RK_PA0 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_rout: audiopwm-rout { + rockchip,pins = + /* audiopwm_rout */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routn: audiopwm-routn { + rockchip,pins = + /* audiopwm_routn */ + <1 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + audiopwm_routp: audiopwm-routp { + rockchip,pins = + /* audiopwm_routp */ + <1 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + bt656 { + /omit-if-no-ref/ + bt656m0_pins: bt656m0-pins { + rockchip,pins = + /* bt656_clkm0 */ + <3 RK_PA0 2 &pcfg_pull_none>, + /* bt656_d0m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* bt656_d1m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* bt656_d2m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* bt656_d3m0 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* bt656_d4m0 */ + <2 RK_PD4 2 &pcfg_pull_none>, + /* bt656_d5m0 */ + <2 RK_PD5 2 &pcfg_pull_none>, + /* bt656_d6m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* bt656_d7m0 */ + <2 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + bt656m1_pins: bt656m1-pins { + rockchip,pins = + /* bt656_clkm1 */ + <4 RK_PB4 5 &pcfg_pull_none>, + /* bt656_d0m1 */ + <3 RK_PC6 5 &pcfg_pull_none>, + /* bt656_d1m1 */ + <3 RK_PC7 5 &pcfg_pull_none>, + /* bt656_d2m1 */ + <3 RK_PD0 5 &pcfg_pull_none>, + /* bt656_d3m1 */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* bt656_d4m1 */ + <3 RK_PD2 5 &pcfg_pull_none>, + /* bt656_d5m1 */ + <3 RK_PD3 5 &pcfg_pull_none>, + /* bt656_d6m1 */ + <3 RK_PD4 5 &pcfg_pull_none>, + /* bt656_d7m1 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clk */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <3 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <3 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <3 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <3 RK_PB1 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <3 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <3 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <3 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <3 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <3 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <3 RK_PC1 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <3 RK_PC2 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + cam { + /omit-if-no-ref/ + cam_clkout0: cam-clkout0 { + rockchip,pins = + /* cam_clkout0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cam_clkout1: cam-clkout1 { + rockchip,pins = + /* cam_clkout1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rxm0 */ + <0 RK_PB4 2 &pcfg_pull_none>, + /* can0_txm0 */ + <0 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rxm1 */ + <2 RK_PA2 4 &pcfg_pull_none>, + /* can0_txm1 */ + <2 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rxm0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* can1_txm0 */ + <1 RK_PA1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rxm1 */ + <4 RK_PC2 3 &pcfg_pull_none>, + /* can1_txm1 */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rxm0 */ + <4 RK_PB4 3 &pcfg_pull_none>, + /* can2_txm0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rxm1 */ + <2 RK_PB1 4 &pcfg_pull_none>, + /* can2_txm1 */ + <2 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PC1 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB6 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PD6 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PD7 1 &pcfg_pull_none>, + /* cif_d10 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d11 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d12 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d13 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d14 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d15 */ + <4 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d1 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d2 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d3 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d4 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d5 */ + <3 RK_PD3 1 &pcfg_pull_none>, + /* cif_d6 */ + <3 RK_PD4 1 &pcfg_pull_none>, + /* cif_d7 */ + <3 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_avs */ + <0 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + ebc { + /omit-if-no-ref/ + ebc_extern: ebc-extern { + rockchip,pins = + /* ebc_sdce1 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* ebc_sdce2 */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* ebc_sdce3 */ + <4 RK_PB1 2 &pcfg_pull_none>, + /* ebc_sdshr */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* ebc_vcom */ + <4 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + ebc_pins: ebc-pins { + rockchip,pins = + /* ebc_gdclk */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* ebc_gdoe */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* ebc_gdsp */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* ebc_sdce0 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* ebc_sdclk */ + <4 RK_PC1 2 &pcfg_pull_none>, + /* ebc_sddo0 */ + <3 RK_PC6 2 &pcfg_pull_none>, + /* ebc_sddo1 */ + <3 RK_PC7 2 &pcfg_pull_none>, + /* ebc_sddo2 */ + <3 RK_PD0 2 &pcfg_pull_none>, + /* ebc_sddo3 */ + <3 RK_PD1 2 &pcfg_pull_none>, + /* ebc_sddo4 */ + <3 RK_PD2 2 &pcfg_pull_none>, + /* ebc_sddo5 */ + <3 RK_PD3 2 &pcfg_pull_none>, + /* ebc_sddo6 */ + <3 RK_PD4 2 &pcfg_pull_none>, + /* ebc_sddo7 */ + <3 RK_PD5 2 &pcfg_pull_none>, + /* ebc_sddo8 */ + <3 RK_PD6 2 &pcfg_pull_none>, + /* ebc_sddo9 */ + <3 RK_PD7 2 &pcfg_pull_none>, + /* ebc_sddo10 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* ebc_sddo11 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* ebc_sddo12 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* ebc_sddo13 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* ebc_sddo14 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* ebc_sddo15 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* ebc_sdle */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* ebc_sdoe */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + }; + + edpdp { + /omit-if-no-ref/ + edpdpm0_pins: edpdpm0-pins { + rockchip,pins = + /* edpdp_hpdinm0 */ + <4 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + edpdpm1_pins: edpdpm1-pins { + rockchip,pins = + /* edpdp_hpdinm1 */ + <0 RK_PC2 2 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_datastrobe: emmc-datastrobe { + rockchip,pins = + /* emmc_datastrobe */ + <1 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko25m */ + <2 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1m0_pins: eth1m0-pins { + rockchip,pins = + /* eth1_refclko25mm0 */ + <3 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + eth1m1_pins: eth1m1-pins { + rockchip,pins = + /* eth1_refclko25mm1 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + flash { + /omit-if-no-ref/ + flash_pins: flash-pins { + rockchip,pins = + /* flash_ale */ + <1 RK_PD0 2 &pcfg_pull_none>, + /* flash_cle */ + <1 RK_PC6 3 &pcfg_pull_none>, + /* flash_cs0n */ + <1 RK_PD3 2 &pcfg_pull_none>, + /* flash_cs1n */ + <1 RK_PD4 2 &pcfg_pull_none>, + /* flash_d0 */ + <1 RK_PB4 2 &pcfg_pull_none>, + /* flash_d1 */ + <1 RK_PB5 2 &pcfg_pull_none>, + /* flash_d2 */ + <1 RK_PB6 2 &pcfg_pull_none>, + /* flash_d3 */ + <1 RK_PB7 2 &pcfg_pull_none>, + /* flash_d4 */ + <1 RK_PC0 2 &pcfg_pull_none>, + /* flash_d5 */ + <1 RK_PC1 2 &pcfg_pull_none>, + /* flash_d6 */ + <1 RK_PC2 2 &pcfg_pull_none>, + /* flash_d7 */ + <1 RK_PC3 2 &pcfg_pull_none>, + /* flash_dqs */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* flash_rdn */ + <1 RK_PD2 2 &pcfg_pull_none>, + /* flash_rdy */ + <1 RK_PD1 2 &pcfg_pull_none>, + /* flash_wpn */ + <1 RK_PC7 3 &pcfg_pull_none>, + /* flash_wrn */ + <1 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD0 1 &pcfg_pull_none>, + /* fspi_cs0n */ + <1 RK_PD3 1 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PD1 1 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PD2 1 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC7 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_cs1: fspi-cs1 { + rockchip,pins = + /* fspi_cs1n */ + <1 RK_PC6 2 &pcfg_pull_up>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <2 RK_PC3 2 &pcfg_pull_none>, + /* gmac0_mdio */ + <2 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <2 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_er: gmac0-rx-er { + rockchip,pins = + /* gmac0_rxer */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PB7 2 &pcfg_pull_none>, + /* gmac0_rxdvcrs */ + <2 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_2>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1m0_miim: gmac1m0-miim { + rockchip,pins = + /* gmac1_mdcm0 */ + <3 RK_PC4 3 &pcfg_pull_none>, + /* gmac1_mdiom0 */ + <3 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_clkinout: gmac1m0-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm0 */ + <3 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_er: gmac1m0-rx-er { + rockchip,pins = + /* gmac1_rxerm0 */ + <3 RK_PB4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rx_bus2: gmac1m0-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* gmac1_rxd1m0 */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm0 */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2: gmac1m0-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk: gmac1m0-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus: gmac1m0-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_miim: gmac1m1-miim { + rockchip,pins = + /* gmac1_mdcm1 */ + <4 RK_PB6 3 &pcfg_pull_none>, + /* gmac1_mdiom1 */ + <4 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_clkinout: gmac1m1-clkinout { + rockchip,pins = + /* gmac1_mclkinoutm1 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_er: gmac1m1-rx-er { + rockchip,pins = + /* gmac1_rxerm1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rx_bus2: gmac1m1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0m1 */ + <4 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_rxd1m1 */ + <4 RK_PB0 3 &pcfg_pull_none>, + /* gmac1_rxdvcrsm1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2: gmac1m1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk: gmac1m1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_1>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus: gmac1m1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_2>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC0 2 &pcfg_pull_none>, + /* gpu_pwren */ + <0 RK_PA6 4 &pcfg_pull_none>; + }; + }; + + hdmitx { + /omit-if-no-ref/ + hdmitxm0_cec: hdmitxm0-cec { + rockchip,pins = + /* hdmitxm0_cec */ + <4 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitxm1_cec: hdmitxm1-cec { + rockchip,pins = + /* hdmitxm1_cec */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_scl: hdmitx-scl { + rockchip,pins = + /* hdmitx_scl */ + <4 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmitx_sda: hdmitx-sda { + rockchip,pins = + /* hdmitx_sda */ + <4 RK_PD0 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB1 1 &pcfg_pull_none_smt>, + /* i2c0_sda */ + <0 RK_PB2 1 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1_xfer: i2c1-xfer { + rockchip,pins = + /* i2c1_scl */ + <0 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c1_sda */ + <0 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_sclm0 */ + <0 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam0 */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_sclm1 */ + <4 RK_PB5 1 &pcfg_pull_none_smt>, + /* i2c2_sdam1 */ + <4 RK_PB4 1 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_sclm0 */ + <1 RK_PA1 1 &pcfg_pull_none_smt>, + /* i2c3_sdam0 */ + <1 RK_PA0 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_sclm1 */ + <3 RK_PB5 4 &pcfg_pull_none_smt>, + /* i2c3_sdam1 */ + <3 RK_PB6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_sclm0 */ + <4 RK_PB3 1 &pcfg_pull_none_smt>, + /* i2c4_sdam0 */ + <4 RK_PB2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_sclm1 */ + <2 RK_PB2 2 &pcfg_pull_none_smt>, + /* i2c4_sdam1 */ + <2 RK_PB1 2 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_sclm0 */ + <3 RK_PB3 4 &pcfg_pull_none_smt>, + /* i2c5_sdam0 */ + <3 RK_PB4 4 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_sclm1 */ + <4 RK_PC7 2 &pcfg_pull_none_smt>, + /* i2c5_sdam1 */ + <4 RK_PD0 2 &pcfg_pull_none_smt>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrckrx: i2s1m0-lrckrx { + rockchip,pins = + /* i2s1m0_lrckrx */ + <1 RK_PA6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_lrcktx: i2s1m0-lrcktx { + rockchip,pins = + /* i2s1m0_lrcktx */ + <1 RK_PA5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclkrx: i2s1m0-sclkrx { + rockchip,pins = + /* i2s1m0_sclkrx */ + <1 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sclktx: i2s1m0-sclktx { + rockchip,pins = + /* i2s1m0_sclktx */ + <1 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <1 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <1 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrckrx: i2s1m1-lrckrx { + rockchip,pins = + /* i2s1m1_lrckrx */ + <4 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_lrcktx: i2s1m1-lrcktx { + rockchip,pins = + /* i2s1m1_lrcktx */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <3 RK_PC6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclkrx: i2s1m1-sclkrx { + rockchip,pins = + /* i2s1m1_sclkrx */ + <4 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sclktx: i2s1m1-sclktx { + rockchip,pins = + /* i2s1m1_sclktx */ + <3 RK_PC7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <3 RK_PD2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <3 RK_PD4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <3 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <4 RK_PB0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrckrx: i2s1m2-lrckrx { + rockchip,pins = + /* i2s1m2_lrckrx */ + <3 RK_PC5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_lrcktx: i2s1m2-lrcktx { + rockchip,pins = + /* i2s1m2_lrcktx */ + <2 RK_PD2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_mclk: i2s1m2-mclk { + rockchip,pins = + /* i2s1m2_mclk */ + <2 RK_PD0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclkrx: i2s1m2-sclkrx { + rockchip,pins = + /* i2s1m2_sclkrx */ + <3 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sclktx: i2s1m2-sclktx { + rockchip,pins = + /* i2s1m2_sclktx */ + <2 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi0: i2s1m2-sdi0 { + rockchip,pins = + /* i2s1m2_sdi0 */ + <2 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi1: i2s1m2-sdi1 { + rockchip,pins = + /* i2s1m2_sdi1 */ + <2 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi2: i2s1m2-sdi2 { + rockchip,pins = + /* i2s1m2_sdi2 */ + <2 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdi3: i2s1m2-sdi3 { + rockchip,pins = + /* i2s1m2_sdi3 */ + <2 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo0: i2s1m2-sdo0 { + rockchip,pins = + /* i2s1m2_sdo0 */ + <2 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo1: i2s1m2-sdo1 { + rockchip,pins = + /* i2s1m2_sdo1 */ + <3 RK_PA0 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo2: i2s1m2-sdo2 { + rockchip,pins = + /* i2s1m2_sdo2 */ + <3 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m2_sdo3: i2s1m2-sdo3 { + rockchip,pins = + /* i2s1m2_sdo3 */ + <3 RK_PC2 5 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_lrckrx: i2s2m0-lrckrx { + rockchip,pins = + /* i2s2m0_lrckrx */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrcktx: i2s2m0-lrcktx { + rockchip,pins = + /* i2s2m0_lrcktx */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclkrx: i2s2m0-sclkrx { + rockchip,pins = + /* i2s2m0_sclkrx */ + <2 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sclktx: i2s2m0-sclktx { + rockchip,pins = + /* i2s2m0_sclktx */ + <2 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrckrx: i2s2m1-lrckrx { + rockchip,pins = + /* i2s2m1_lrckrx */ + <4 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrcktx: i2s2m1-lrcktx { + rockchip,pins = + /* i2s2m1_lrcktx */ + <4 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclkrx: i2s2m1-sclkrx { + rockchip,pins = + /* i2s2m1_sclkrx */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sclktx: i2s2m1-sclktx { + rockchip,pins = + /* i2s2m1_sclktx */ + <4 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <4 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <4 RK_PB3 5 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3m0_lrck: i2s3m0-lrck { + rockchip,pins = + /* i2s3m0_lrck */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_mclk: i2s3m0-mclk { + rockchip,pins = + /* i2s3m0_mclk */ + <3 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sclk: i2s3m0-sclk { + rockchip,pins = + /* i2s3m0_sclk */ + <3 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdi: i2s3m0-sdi { + rockchip,pins = + /* i2s3m0_sdi */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m0_sdo: i2s3m0-sdo { + rockchip,pins = + /* i2s3m0_sdo */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_lrck: i2s3m1-lrck { + rockchip,pins = + /* i2s3m1_lrck */ + <4 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_mclk: i2s3m1-mclk { + rockchip,pins = + /* i2s3m1_mclk */ + <4 RK_PC2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sclk: i2s3m1-sclk { + rockchip,pins = + /* i2s3m1_sclk */ + <4 RK_PC3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdi: i2s3m1-sdi { + rockchip,pins = + /* i2s3m1_sdi */ + <4 RK_PC6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3m1_sdo: i2s3m1-sdo { + rockchip,pins = + /* i2s3m1_sdo */ + <4 RK_PC5 5 &pcfg_pull_none>; + }; + }; + + isp { + /omit-if-no-ref/ + isp_pins: isp-pins { + rockchip,pins = + /* isp_flashtrigin */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* isp_flashtrigout */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* isp_prelighttrig */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtag_pins: jtag-pins { + rockchip,pins = + /* jtag_tck */ + <1 RK_PD7 2 &pcfg_pull_none>, + /* jtag_tms */ + <2 RK_PA0 2 &pcfg_pull_none>; + }; + }; + + lcdc { + /omit-if-no-ref/ + lcdc_ctl: lcdc-ctl { + rockchip,pins = + /* lcdc_clk */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* lcdc_d0 */ + <2 RK_PD0 1 &pcfg_pull_none>, + /* lcdc_d1 */ + <2 RK_PD1 1 &pcfg_pull_none>, + /* lcdc_d2 */ + <2 RK_PD2 1 &pcfg_pull_none>, + /* lcdc_d3 */ + <2 RK_PD3 1 &pcfg_pull_none>, + /* lcdc_d4 */ + <2 RK_PD4 1 &pcfg_pull_none>, + /* lcdc_d5 */ + <2 RK_PD5 1 &pcfg_pull_none>, + /* lcdc_d6 */ + <2 RK_PD6 1 &pcfg_pull_none>, + /* lcdc_d7 */ + <2 RK_PD7 1 &pcfg_pull_none>, + /* lcdc_d8 */ + <3 RK_PA1 1 &pcfg_pull_none>, + /* lcdc_d9 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* lcdc_d10 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* lcdc_d11 */ + <3 RK_PA4 1 &pcfg_pull_none>, + /* lcdc_d12 */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* lcdc_d13 */ + <3 RK_PA6 1 &pcfg_pull_none>, + /* lcdc_d14 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* lcdc_d15 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* lcdc_d16 */ + <3 RK_PB1 1 &pcfg_pull_none>, + /* lcdc_d17 */ + <3 RK_PB2 1 &pcfg_pull_none>, + /* lcdc_d18 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* lcdc_d19 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* lcdc_d20 */ + <3 RK_PB5 1 &pcfg_pull_none>, + /* lcdc_d21 */ + <3 RK_PB6 1 &pcfg_pull_none>, + /* lcdc_d22 */ + <3 RK_PB7 1 &pcfg_pull_none>, + /* lcdc_d23 */ + <3 RK_PC0 1 &pcfg_pull_none>, + /* lcdc_den */ + <3 RK_PC3 1 &pcfg_pull_none>, + /* lcdc_hsync */ + <3 RK_PC1 1 &pcfg_pull_none>, + /* lcdc_vsync */ + <3 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcu_pins: mcu-pins { + rockchip,pins = + /* mcu_jtagtck */ + <0 RK_PB4 4 &pcfg_pull_none>, + /* mcu_jtagtdi */ + <0 RK_PC1 4 &pcfg_pull_none>, + /* mcu_jtagtdo */ + <0 RK_PB3 4 &pcfg_pull_none>, + /* mcu_jtagtms */ + <0 RK_PC2 4 &pcfg_pull_none>, + /* mcu_jtagtrstn */ + <0 RK_PC3 4 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + pcie20 { + /omit-if-no-ref/ + pcie20m0_pins: pcie20m0-pins { + rockchip,pins = + /* pcie20_clkreqnm0 */ + <0 RK_PA5 3 &pcfg_pull_none>, + /* pcie20_perstnm0 */ + <0 RK_PB6 3 &pcfg_pull_none>, + /* pcie20_wakenm0 */ + <0 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m1_pins: pcie20m1-pins { + rockchip,pins = + /* pcie20_clkreqnm1 */ + <2 RK_PD0 4 &pcfg_pull_none>, + /* pcie20_perstnm1 */ + <3 RK_PC1 4 &pcfg_pull_none>, + /* pcie20_wakenm1 */ + <2 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20m2_pins: pcie20m2-pins { + rockchip,pins = + /* pcie20_clkreqnm2 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie20_perstnm2 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie20_wakenm2 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20_buttonrstn: pcie20-buttonrstn { + rockchip,pins = + /* pcie20_buttonrstn */ + <0 RK_PB4 3 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_clkreqnm0 */ + <0 RK_PA4 3 &pcfg_pull_none>, + /* pcie30x1_perstnm0 */ + <0 RK_PC3 3 &pcfg_pull_none>, + /* pcie30x1_wakenm0 */ + <0 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_clkreqnm1 */ + <2 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x1_perstnm1 */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* pcie30x1_wakenm1 */ + <2 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_clkreqnm2 */ + <1 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_perstnm2 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_wakenm2 */ + <1 RK_PA3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_buttonrstn: pcie30x1-buttonrstn { + rockchip,pins = + /* pcie30x1_buttonrstn */ + <0 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqnm0 */ + <0 RK_PA6 2 &pcfg_pull_none>, + /* pcie30x2_perstnm0 */ + <0 RK_PC6 3 &pcfg_pull_none>, + /* pcie30x2_wakenm0 */ + <0 RK_PC5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqnm1 */ + <2 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_perstnm1 */ + <2 RK_PD6 4 &pcfg_pull_none>, + /* pcie30x2_wakenm1 */ + <2 RK_PD5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqnm2 */ + <4 RK_PC2 4 &pcfg_pull_none>, + /* pcie30x2_perstnm2 */ + <4 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x2_wakenm2 */ + <4 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_buttonrstn: pcie30x2-buttonrstn { + rockchip,pins = + /* pcie30x2_buttonrstn */ + <0 RK_PB0 3 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdmm0_clk: pdmm0-clk { + rockchip,pins = + /* pdm_clk0m0 */ + <1 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_clk1: pdmm0-clk1 { + rockchip,pins = + /* pdmm0_clk1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi0: pdmm0-sdi0 { + rockchip,pins = + /* pdmm0_sdi0 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi1: pdmm0-sdi1 { + rockchip,pins = + /* pdmm0_sdi1 */ + <1 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi2: pdmm0-sdi2 { + rockchip,pins = + /* pdmm0_sdi2 */ + <1 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm0_sdi3: pdmm0-sdi3 { + rockchip,pins = + /* pdmm0_sdi3 */ + <1 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk: pdmm1-clk { + rockchip,pins = + /* pdm_clk0m1 */ + <3 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_clk1: pdmm1-clk1 { + rockchip,pins = + /* pdmm1_clk1 */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi0: pdmm1-sdi0 { + rockchip,pins = + /* pdmm1_sdi0 */ + <3 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi1: pdmm1-sdi1 { + rockchip,pins = + /* pdmm1_sdi1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi2: pdmm1-sdi2 { + rockchip,pins = + /* pdmm1_sdi2 */ + <4 RK_PA2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm1_sdi3: pdmm1-sdi3 { + rockchip,pins = + /* pdmm1_sdi3 */ + <4 RK_PA3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_clk1: pdmm2-clk1 { + rockchip,pins = + /* pdmm2_clk1 */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi0: pdmm2-sdi0 { + rockchip,pins = + /* pdmm2_sdi0 */ + <3 RK_PB3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi1: pdmm2-sdi1 { + rockchip,pins = + /* pdmm2_sdi1 */ + <3 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi2: pdmm2-sdi2 { + rockchip,pins = + /* pdmm2_sdi2 */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdmm2_sdi3: pdmm2-sdi3 { + rockchip,pins = + /* pdmm2_sdi3 */ + <3 RK_PC0 5 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_sleep */ + <0 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug0 */ + <0 RK_PA5 4 &pcfg_pull_none>, + /* pmu_debug1 */ + <0 RK_PA6 3 &pcfg_pull_none>, + /* pmu_debug2 */ + <0 RK_PC4 4 &pcfg_pull_none>, + /* pmu_debug3 */ + <0 RK_PC5 4 &pcfg_pull_none>, + /* pmu_debug4 */ + <0 RK_PC6 4 &pcfg_pull_none>, + /* pmu_debug5 */ + <0 RK_PC7 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <0 RK_PB5 4 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <0 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3_pins: pwm3-pins { + rockchip,pins = + /* pwm3_ir */ + <0 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4_pins: pwm4-pins { + rockchip,pins = + /* pwm4 */ + <0 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5_pins: pwm5-pins { + rockchip,pins = + /* pwm5 */ + <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6_pins: pwm6-pins { + rockchip,pins = + /* pwm6 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7_pins: pwm7-pins { + rockchip,pins = + /* pwm7_ir */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PB1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <1 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB2 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <1 RK_PD6 4 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <2 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_irm0 */ + <3 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_irm1 */ + <4 RK_PC0 3 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_irm0 */ + <3 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_irm1 */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_ou */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cpdet */ + <0 RK_PA4 2 &pcfg_pull_none>, + /* sata_cppod */ + <0 RK_PA6 1 &pcfg_pull_none>, + /* sata_mpswitch */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0_pins: sata0-pins { + rockchip,pins = + /* sata0_actled */ + <4 RK_PC6 3 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1_pins: sata1-pins { + rockchip,pins = + /* sata1_actled */ + <4 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2_pins: sata2-pins { + rockchip,pins = + /* sata2_actled */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scr_pins: scr-pins { + rockchip,pins = + /* scr_clk */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_det */ + <1 RK_PA7 3 &pcfg_pull_up>, + /* scr_io */ + <1 RK_PA3 3 &pcfg_pull_up>, + /* scr_rst */ + <1 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PD7 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + /* sdmmc0_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = + /* sdmmc0_pwren */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <2 RK_PA6 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <2 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <2 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + /* sdmmc1_det */ + <2 RK_PB2 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc1_pwren: sdmmc1-pwren { + rockchip,pins = + /* sdmmc1_pwren */ + <2 RK_PB1 1 &pcfg_pull_none>; + }; + }; + + sdmmc2 { + /omit-if-no-ref/ + sdmmc2m0_bus4: sdmmc2m0-bus4 { + rockchip,pins = + /* sdmmc2_d0m0 */ + <3 RK_PC6 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m0 */ + <3 RK_PC7 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m0 */ + <3 RK_PD0 3 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m0 */ + <3 RK_PD1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_clk: sdmmc2m0-clk { + rockchip,pins = + /* sdmmc2_clkm0 */ + <3 RK_PD3 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_cmd: sdmmc2m0-cmd { + rockchip,pins = + /* sdmmc2_cmdm0 */ + <3 RK_PD2 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m0_det: sdmmc2m0-det { + rockchip,pins = + /* sdmmc2_detm0 */ + <3 RK_PD4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m0_pwren: sdmmc2m0-pwren { + rockchip,pins = + /* sdmmc2m0_pwren */ + <3 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sdmmc2m1_bus4: sdmmc2m1-bus4 { + rockchip,pins = + /* sdmmc2_d0m1 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d1m1 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d2m1 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>, + /* sdmmc2_d3m1 */ + <3 RK_PA4 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_clk: sdmmc2m1-clk { + rockchip,pins = + /* sdmmc2_clkm1 */ + <3 RK_PA6 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_cmd: sdmmc2m1-cmd { + rockchip,pins = + /* sdmmc2_cmdm1 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc2m1_det: sdmmc2m1-det { + rockchip,pins = + /* sdmmc2_detm1 */ + <3 RK_PA7 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc2m1_pwren: sdmmc2m1-pwren { + rockchip,pins = + /* sdmmc2m1_pwren */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_tx: spdifm0-tx { + rockchip,pins = + /* spdifm0_tx */ + <1 RK_PA4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_tx: spdifm1-tx { + rockchip,pins = + /* spdifm1_tx */ + <3 RK_PC5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_tx: spdifm2-tx { + rockchip,pins = + /* spdifm2_tx */ + <4 RK_PC4 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_none>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_none>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_none>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_none>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_none>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_none>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_none>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_none>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_none>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_none>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_none>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_none>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_none>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_none>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_none>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm0_shut: tsadcm0-shut { + rockchip,pins = + /* tsadcm0_shut */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shutorg: tsadc-shutorg { + rockchip,pins = + /* tsadc_shutorg */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <0 RK_PC0 3 &pcfg_pull_up>, + /* uart0_tx */ + <0 RK_PC1 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PC7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rxm0 */ + <2 RK_PB3 2 &pcfg_pull_up>, + /* uart1_txm0 */ + <2 RK_PB4 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rxm1 */ + <3 RK_PD7 4 &pcfg_pull_up>, + /* uart1_txm1 */ + <3 RK_PD6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <4 RK_PC1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <4 RK_PB6 4 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rxm0 */ + <0 RK_PD0 1 &pcfg_pull_up>, + /* uart2_txm0 */ + <0 RK_PD1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rxm1 */ + <1 RK_PD6 2 &pcfg_pull_up>, + /* uart2_txm1 */ + <1 RK_PD5 2 &pcfg_pull_up>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rxm0 */ + <1 RK_PA0 2 &pcfg_pull_up>, + /* uart3_txm0 */ + <1 RK_PA1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m0_ctsn: uart3m0-ctsn { + rockchip,pins = + /* uart3m0_ctsn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m0_rtsn: uart3m0-rtsn { + rockchip,pins = + /* uart3m0_rtsn */ + <1 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rxm1 */ + <3 RK_PC0 4 &pcfg_pull_up>, + /* uart3_txm1 */ + <3 RK_PB7 4 &pcfg_pull_up>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rxm0 */ + <1 RK_PA4 2 &pcfg_pull_up>, + /* uart4_txm0 */ + <1 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m0_ctsn: uart4m0-ctsn { + rockchip,pins = + /* uart4m0_ctsn */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m0_rtsn: uart4m0-rtsn { + rockchip,pins = + /* uart4m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rxm1 */ + <3 RK_PB1 4 &pcfg_pull_up>, + /* uart4_txm1 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rxm0 */ + <2 RK_PA1 3 &pcfg_pull_up>, + /* uart5_txm0 */ + <2 RK_PA2 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PD7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rxm1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart5_txm1 */ + <3 RK_PC2 4 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rxm0 */ + <2 RK_PA3 3 &pcfg_pull_up>, + /* uart6_txm0 */ + <2 RK_PA4 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rxm1 */ + <1 RK_PD6 3 &pcfg_pull_up>, + /* uart6_txm1 */ + <1 RK_PD5 3 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rxm0 */ + <2 RK_PA5 3 &pcfg_pull_up>, + /* uart7_txm0 */ + <2 RK_PA6 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <2 RK_PC2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <2 RK_PC1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rxm1 */ + <3 RK_PC5 4 &pcfg_pull_up>, + /* uart7_txm1 */ + <3 RK_PC4 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rxm2 */ + <4 RK_PA3 4 &pcfg_pull_up>, + /* uart7_txm2 */ + <4 RK_PA2 4 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rxm0 */ + <2 RK_PC6 2 &pcfg_pull_up>, + /* uart8_txm0 */ + <2 RK_PC5 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <2 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <2 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rxm1 */ + <3 RK_PA0 4 &pcfg_pull_up>, + /* uart8_txm1 */ + <2 RK_PD7 4 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rxm0 */ + <2 RK_PA7 3 &pcfg_pull_up>, + /* uart9_txm0 */ + <2 RK_PB0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <2 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <2 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rxm1 */ + <4 RK_PC6 4 &pcfg_pull_up>, + /* uart9_txm1 */ + <4 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rxm2 */ + <4 RK_PA5 4 &pcfg_pull_up>, + /* uart9_txm2 */ + <4 RK_PA4 4 &pcfg_pull_up>; + }; + }; + + vop { + /omit-if-no-ref/ + vopm0_pins: vopm0-pins { + rockchip,pins = + /* vop_pwmm0 */ + <0 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + vopm1_pins: vopm1-pins { + rockchip,pins = + /* vop_pwmm1 */ + <3 RK_PC4 2 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + spi0-hs { + /omit-if-no-ref/ + spi0m0_pins_hs: spi0m0-pins { + rockchip,pins = + /* spi0_clkm0 */ + <0 RK_PB5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_misom0 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim0 */ + <0 RK_PB6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs0_hs: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0m0 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m0_cs1_hs: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1m0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_pins_hs: spi0m1-pins { + rockchip,pins = + /* spi0_clkm1 */ + <2 RK_PD3 3 &pcfg_pull_up_drv_level_1>, + /* spi0_misom1 */ + <2 RK_PD0 3 &pcfg_pull_up_drv_level_1>, + /* spi0_mosim1 */ + <2 RK_PD1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi0m1_cs0_hs: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0m1 */ + <2 RK_PD2 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi1-hs { + /omit-if-no-ref/ + spi1m0_pins_hs: spi1m0-pins { + rockchip,pins = + /* spi1_clkm0 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom0 */ + <2 RK_PB6 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim0 */ + <2 RK_PB7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0_hs: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0m0 */ + <2 RK_PC0 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1_hs: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1m0 */ + <2 RK_PC6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_pins_hs: spi1m1-pins { + rockchip,pins = + /* spi1_clkm1 */ + <3 RK_PC3 3 &pcfg_pull_up_drv_level_1>, + /* spi1_misom1 */ + <3 RK_PC2 3 &pcfg_pull_up_drv_level_1>, + /* spi1_mosim1 */ + <3 RK_PC1 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m1_cs0_hs: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0m1 */ + <3 RK_PA1 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi2-hs { + /omit-if-no-ref/ + spi2m0_pins_hs: spi2m0-pins { + rockchip,pins = + /* spi2_clkm0 */ + <2 RK_PC1 4 &pcfg_pull_up_drv_level_1>, + /* spi2_misom0 */ + <2 RK_PC2 4 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim0 */ + <2 RK_PC3 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs0_hs: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0m0 */ + <2 RK_PC4 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m0_cs1_hs: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1m0 */ + <2 RK_PC5 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_pins_hs: spi2m1-pins { + rockchip,pins = + /* spi2_clkm1 */ + <3 RK_PA0 3 &pcfg_pull_up_drv_level_1>, + /* spi2_misom1 */ + <2 RK_PD7 3 &pcfg_pull_up_drv_level_1>, + /* spi2_mosim1 */ + <2 RK_PD6 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs0_hs: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0m1 */ + <2 RK_PD5 3 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m1_cs1_hs: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1m1 */ + <2 RK_PD4 3 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3-hs { + /omit-if-no-ref/ + spi3m0_pins_hs: spi3m0-pins { + rockchip,pins = + /* spi3_clkm0 */ + <4 RK_PB3 4 &pcfg_pull_up_drv_level_1>, + /* spi3_misom0 */ + <4 RK_PB0 4 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim0 */ + <4 RK_PB2 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0_hs: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0m0 */ + <4 RK_PA6 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1_hs: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1m0 */ + <4 RK_PA7 4 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_pins_hs: spi3m1-pins { + rockchip,pins = + /* spi3_clkm1 */ + <4 RK_PC2 2 &pcfg_pull_up_drv_level_1>, + /* spi3_misom1 */ + <4 RK_PC5 2 &pcfg_pull_up_drv_level_1>, + /* spi3_mosim1 */ + <4 RK_PC3 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs0_hs: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0m1 */ + <4 RK_PC6 2 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m1_cs1_hs: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1m1 */ + <4 RK_PD1 2 &pcfg_pull_up_drv_level_1>; + }; + }; + + gmac-txd-level3 { + /omit-if-no-ref/ + gmac0_tx_bus2_level3: gmac0-tx-bus2-level3 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB3 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd1 */ + <2 RK_PB4 1 &pcfg_pull_none_drv_level_3>, + /* gmac0_txen */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus_level3: gmac0-rgmii-bus-level3 { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PA6 2 &pcfg_pull_none_drv_level_3>, + /* gmac0_txd3 */ + <2 RK_PA7 2 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m0_tx_bus2_level3: gmac1m0-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m0 */ + <3 RK_PB5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m0 */ + <3 RK_PB6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm0 */ + <3 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_bus_level3: gmac1m0-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* gmac1_rxd3m0 */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* gmac1_txd2m0 */ + <3 RK_PA2 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m0 */ + <3 RK_PA3 3 &pcfg_pull_none_drv_level_3>; + }; + + /omit-if-no-ref/ + gmac1m1_tx_bus2_level3: gmac1m1-tx-bus2-level3 { + rockchip,pins = + /* gmac1_txd0m1 */ + <4 RK_PA4 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd1m1 */ + <4 RK_PA5 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txenm1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_bus_level3: gmac1m1-rgmii-bus-level3 { + rockchip,pins = + /* gmac1_rxd2m1 */ + <4 RK_PA1 3 &pcfg_pull_none>, + /* gmac1_rxd3m1 */ + <4 RK_PA2 3 &pcfg_pull_none>, + /* gmac1_txd2m1 */ + <3 RK_PD6 3 &pcfg_pull_none_drv_level_3>, + /* gmac1_txd3m1 */ + <3 RK_PD7 3 &pcfg_pull_none_drv_level_3>; + }; + }; + + gmac-txc-level2 { + /omit-if-no-ref/ + gmac0_rgmii_clk_level2: gmac0-rgmii-clk-level2 { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PA5 2 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m0_rgmii_clk_level2: gmac1m0-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm0 */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* gmac1_txclkm0 */ + <3 RK_PA6 3 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + gmac1m1_rgmii_clk_level2: gmac1m1-rgmii-clk-level2 { + rockchip,pins = + /* gmac1_rxclkm1 */ + <4 RK_PA3 3 &pcfg_pull_none>, + /* gmac1_txclkm1 */ + <4 RK_PA0 3 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/rk3568-sata1.dtsi b/rk356x/rk3568-sata1.dtsi new file mode 100755 index 0000000..ef6d69a --- /dev/null +++ b/rk356x/rk3568-sata1.dtsi @@ -0,0 +1,18 @@ +/** + * enable sata1 relavent config for rk3568 + */ + + + +&usbhost_dwc3 { + /** redefine for combphy used to be sata */ + phys = <&u2phy0_host>; +}; + +&combphy1_usq { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; diff --git a/rk356x/rk3568-sata2.dtsi b/rk356x/rk3568-sata2.dtsi new file mode 100755 index 0000000..4e80be3 --- /dev/null +++ b/rk356x/rk3568-sata2.dtsi @@ -0,0 +1,13 @@ +/** + * enable sata2 relavent config for rk3568 + */ + + + +&combphy2_psq { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; diff --git a/rk356x/rp-adc-key.dtsi b/rk356x/rp-adc-key.dtsi new file mode 100755 index 0000000..353c974 --- /dev/null +++ b/rk356x/rp-adc-key.dtsi @@ -0,0 +1,34 @@ +/ { + + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <297500>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <980000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1305500>; + }; + }; +}; \ No newline at end of file diff --git a/rk356x/rp-audio-es8311.dtsi b/rk356x/rp-audio-es8311.dtsi new file mode 100755 index 0000000..d4ab0c6 --- /dev/null +++ b/rk356x/rp-audio-es8311.dtsi @@ -0,0 +1,49 @@ + +/ { + i2s1_sound: i2s1-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8311"; + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&es8311>; + }; + }; +}; + +&i2s1_8ch { + status = "okay"; + pinctrl-0 = <&i2s1m0_sclktx + &i2s1m0_lrcktx + &i2s1m0_sdi0 + &i2s1m0_sdo0>; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + es8311: es8311@18 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x18>; + clocks = <&cru I2S1_MCLKOUT>; + clock-names = "mclk"; + adc-pga-gain = <6>; /* 18dB */ + adc-volume = <0xbf>; /* 0dB */ + dac-volume = <0xbf>; /* 0dB */ + aec-mode = "dac left, adc right"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + assigned-clocks = <&cru I2S1_MCLKOUT>, <&cru I2S1_MCLK_TX_IOE>; + assigned-clock-rates = <12288000>; + assigned-clock-parents = <&cru I2S1_MCLKOUT_TX>, <&cru I2S1_MCLKOUT_TX>; + //spk-ctl-gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + diff --git a/rk356x/rp-box-rk3566-lcd-gpio.dtsi b/rk356x/rp-box-rk3566-lcd-gpio.dtsi new file mode 100755 index 0000000..ca5ba8b --- /dev/null +++ b/rk356x/rp-box-rk3566-lcd-gpio.dtsi @@ -0,0 +1,110 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd0_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + diff --git a/rk356x/rp-box-rk3566.dts b/rk356x/rp-box-rk3566.dts new file mode 100755 index 0000000..b7b1a6c --- /dev/null +++ b/rk356x/rp-box-rk3566.dts @@ -0,0 +1,393 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3566-evb1-ddr4-v10 +//#include "rk3566-evb1-ddr4-v10.dtsi" + +#include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" + + +#include "../rk3568-linux.dtsi" +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3566.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac1-m0-pro-rk3566.dtsi" +/***************************************************/ + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "rp-box-rk3566-lcd-gpio.dtsi" +/* HDMI only */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/** LVDS */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + + + + + + + +/ { + model = "rp-box-rk3566"; + compatible = "rpdzkj,rp-box-rk3566", "rockchip,rk3566"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + + /******* sytem power en pin, donnot change it only if you know what you are doing */ + pwr_5v_3v3 { //vdd 3.3v enable + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + pwr_4g { //vdd_3G 3.3v enable + gpio_num = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + led { //system led + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + + usb_host_pwr { //usb 2.0 3.0 power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_pwr { //usb and otg power + gpio_num = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + hub_rst { //usb hub reset + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //SPK ENABLE + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //SPK MUTE, hish active, nomal low + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + otg_mode { //OTG SWITCH, high is mean otg_id to 0, foece host mode + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + + + /***** gpio, add you want to control as blow */ + + gpio4a0 { + gpio_num = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a1 { + gpio_num = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio4a2 { + gpio_num = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio4a3 { + gpio_num = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1b2 { + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3c1 { + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1b0 { + gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0c4 { + gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1a4 { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio2b4 { + gpio_num = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + + +&i2c1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + +&i2c5 { + status = "disabled"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi1m0_cs0 &spi1m0_pins>; + pinctrl-1 = <&spi1m0_cs0 &spi1m0_pins_hs>; + + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi2 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi2m0_cs0 &spi2m0_pins>; + pinctrl-1 = <&spi2m0_cs0 &spi2m0_pins_hs>; + + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi3 { + status = "okay"; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_pins>; + pinctrl-1 = <&spi3m1_cs0 &spi3m1_pins_hs>; + + spi3_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + +&gmac1 { + tx_delay = <0x42>; + rx_delay = <0x2d>; +}; + + +&sdmmc2 { + max-frequency = <150000000>; + supports-sdio; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; + sd-uhs-sdr104; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; +}; + + +&wireless_bluetooth { + uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart1m1_rtsn>; + pinctrl-1 = <&uart1_gpios>; + BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + + + +&rk_headset { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + }; + + +&pinctrl { + + headphone { + hp_det: hp-det { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart1_gpios: uart1-gpios { + rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/rp-box-rk3568-lcd-gpio.dtsi b/rk356x/rp-box-rk3568-lcd-gpio.dtsi new file mode 100755 index 0000000..fedc90c --- /dev/null +++ b/rk356x/rp-box-rk3568-lcd-gpio.dtsi @@ -0,0 +1,117 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + + + + +/************** LCD GPIO ********************/ +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + enable-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + + + + diff --git a/rk356x/rp-box-rk3568.dts b/rk356x/rp-box-rk3568.dts new file mode 100755 index 0000000..d6d9db1 --- /dev/null +++ b/rk356x/rp-box-rk3568.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm.dtsi" + + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3568.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "rp-box-rk3568-lcd-gpio.dtsi" // if use lcd, must enable it +/* HDMI only */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +#include "rp-lcd-mipi1-10-1920-1200.dtsi" + +/** LVDS */ +//#include "rp-lcd-lvds-10-1024-600-raw.dtsi" +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" +/************************ MULTILPLE LCD *********************/ +/* EDP + MIPI0/lvds */ +//#include "rp-lcd-triple-lvds-10-1024-600-edp-13-1920-1080-hdmi.dtsi" + + + + + + + + + +/{ + model = "rp-box-rk3568"; + compatible = "rpdzkj,rp-box-rk3568", "rockchip,rk3568"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + + //#define GPIO_FUNCTION_OUTPUT 0 + //#define GPIO_FUNCTION_INPUT 1 + //#define GPIO_FUNCTION_IRQ 2 + //#define GPIO_FUNCTION_FLASH 3 + //#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + /** + * gpioxxx { // the node name will display on /proc/rp_power, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio, refer to above define. + * }; + */ + + + pwr_5v_3v3 { //vdd5v vdd3v3 en + gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + pwr_4g { //vdd_3G 3.3v enable + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + led { //system led + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + usb_pwr { //usb power + gpio_num = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //hub reset + gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + otg_mode { //OTG SWITCH, high is mean otg_id to 0, force host mode + gpio_num = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + otg_power { //usb otg power + gpio_num = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + /** + * gpioxxx { // the node name will display on /proc/rp_gpio, you can define any character string + * gpio_num = <>; // gpio you want ot control + * gpio_function = <>; // function of current gpio£º 0 output, 1 input, 3 blink + * gpio_event = ; // optional property used to define gpio report event such as KEY_F14, only works in case of gpio_function = <1>; + * }; + */ + + + /****** GPIO, place you want to control as below + * gpio_name { + * gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + * gpio_function = <4>; + * }; + */ + + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + +&gmac0 { + status = "okay"; + tx_delay = <0x3a>; + rx_delay = <0x2e>; + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + //max-speed = <100>; /* set eth maximal speed, default automatically adapt */ +}; +&gmac1 { + status = "okay"; + tx_delay = <0x42>; + rx_delay = <0x27>; + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; +}; + +&i2c1 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi1 { + status = "disabled"; +}; + + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; +/*********************************************/ + + +&pwm7 { + status = "disabled"; +}; + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; +}; + + + + +/****** rp3568 camera configuration adjustment ******/ +&vcc_camera { + pinctrl-0 = <&camera_pwr>; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; +}; +&gc2093 { + pwdn-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; +}; + + +&edp { + /** delete hdp gpio that rp-box-rk3568 donot use */ + /delete-property/ hpd-gpios; +}; + +&pinctrl { + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + rp_pin { + otg_5ven: otg-5ven { + rockchip,pins = + /* otg port host power en */ + <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + host_5ven: host-5ven { + rockchip,pins = + /* usb host power en */ + <2 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vdd3g_en: vdd3g-en { + rockchip,pins = + /* 4G module power en */ + <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rk809_sound { + /delete-property/ simple-audio-card,hp-det-gpio; + /delete-property/ simple-audio-card,widgets; +}; diff --git a/rk356x/rp-camera-mipi-gc2093-single-2lane.dtsi b/rk356x/rp-camera-mipi-gc2093-single-2lane.dtsi new file mode 100755 index 0000000..616c8b9 --- /dev/null +++ b/rk356x/rp-camera-mipi-gc2093-single-2lane.dtsi @@ -0,0 +1,114 @@ + +/ { + + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + /** + * gpio config please refer to main dts if have + + * gpio = <&gpio* *** GPIO_ACTIVE_HIGH>; + * pinctrl-names = "default"; + * pinctrl-0 = <&***>; + */ + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + +}; + +&i2c4 { + status = "okay"; + gc2093: gc2093@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + /** + * gpio config please refer to main dts if have + + * pinctrl-names = "default"; + * pinctrl-0 = <&cif_clk>; + * pwdn-gpios = <&gpio* *** GPIO_ACTIVE_HIGH>; + * reset-gpios = <&gpio* *** GPIO_ACTIVE_LOW>; + */ + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "SIDB205300385-VA"; + rockchip,camera-module-lens-name = "default"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + + + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + diff --git a/rk356x/rp-can0-m0-rk3568.dtsi b/rk356x/rp-can0-m0-rk3568.dtsi new file mode 100755 index 0000000..f85d3df --- /dev/null +++ b/rk356x/rp-can0-m0-rk3568.dtsi @@ -0,0 +1,15 @@ + + +&can0 { + compatible = "rockchip,rk3568-can-2.0"; + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + status = "okay"; +}; + +&i2c1 { + /** disabled for used to be can0 */ + status = "disabled"; +}; diff --git a/rk356x/rp-can1-m1-rk3568.dtsi b/rk356x/rp-can1-m1-rk3568.dtsi new file mode 100755 index 0000000..7c1acd1 --- /dev/null +++ b/rk356x/rp-can1-m1-rk3568.dtsi @@ -0,0 +1,11 @@ + + +&can1 { + compatible = "rockchip,rk3568-can-2.0"; + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; + status = "okay"; +}; + diff --git a/rk356x/rp-can2-m0-rk3568.dtsi b/rk356x/rp-can2-m0-rk3568.dtsi new file mode 100755 index 0000000..2c83d45 --- /dev/null +++ b/rk356x/rp-can2-m0-rk3568.dtsi @@ -0,0 +1,11 @@ + + +&can2 { + compatible = "rockchip,rk3568-can-2.0"; + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + status = "okay"; +}; + diff --git a/rk356x/rp-gmac0-pro-rk3568.dtsi b/rk356x/rp-gmac0-pro-rk3568.dtsi new file mode 100755 index 0000000..90bcfe4 --- /dev/null +++ b/rk356x/rp-gmac0-pro-rk3568.dtsi @@ -0,0 +1,37 @@ + +&gmac0 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins + &gmac0_clkinout>; + + tx_delay = <0x2d>; + rx_delay = <0x2c>; + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + + +&mdio0 { + rgmii_phy0: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC0_OUT>; + }; +}; \ No newline at end of file diff --git a/rk356x/rp-gmac1-m0-pro-rk3566.dtsi b/rk356x/rp-gmac1-m0-pro-rk3566.dtsi new file mode 100755 index 0000000..8d4fc1a --- /dev/null +++ b/rk356x/rp-gmac1-m0-pro-rk3566.dtsi @@ -0,0 +1,39 @@ + + + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>,<&gmac1_clkin>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_rgmii_bus + &gmac1m0_clkinout + ð1m0_pins>; + + tx_delay = <0x3a>; + rx_delay = <0x29>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC1_OUT>; + }; +}; + diff --git a/rk356x/rp-gmac1-m1-pro-rk3568.dtsi b/rk356x/rp-gmac1-m1-pro-rk3568.dtsi new file mode 100755 index 0000000..b5c14e4 --- /dev/null +++ b/rk356x/rp-gmac1-m1-pro-rk3568.dtsi @@ -0,0 +1,38 @@ + +&gmac1 { + phy-mode = "rgmii"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>,<&gmac1_clkin>, <&cru CLK_MAC1_2TOP>; + assigned-clock-rates = <0>, <125000000>, <25000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus + ð1m0_pins + &gmac1m1_clkinout>; + + tx_delay = <0x3a>; + rx_delay = <0x29>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + + +&mdio1 { + rgmii_phy1: phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + clocks = <&cru CLK_MAC1_OUT>; + }; +}; + diff --git a/rk356x/rp-ir-pwm.dtsi b/rk356x/rp-ir-pwm.dtsi new file mode 100755 index 0000000..701b3b1 --- /dev/null +++ b/rk356x/rp-ir-pwm.dtsi @@ -0,0 +1,105 @@ + +&pwm7 { + status = "okay"; + + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm7_pins>; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_VOLUMEDOWN>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; diff --git a/rk356x/rp-lcd-dual-lvds-10-1024-600-mipi1-10-800-1280.dtsi b/rk356x/rp-lcd-dual-lvds-10-1024-600-mipi1-10-800-1280.dtsi new file mode 100755 index 0000000..9524b2e --- /dev/null +++ b/rk356x/rp-lcd-dual-lvds-10-1024-600-mipi1-10-800-1280.dtsi @@ -0,0 +1,526 @@ +#include + +#define RP_DUAL_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 E0 04 + 15 00 02 2D 03 + 15 00 02 E0 00 + 15 00 02 80 03 + 15 00 02 70 02 + 15 00 02 71 23 + 15 00 02 72 06 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 66 + 15 00 02 03 00 + 15 00 02 04 6D + 15 00 02 17 00 + 15 00 02 18 BF + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B BF + 15 00 02 1C 00 + 15 00 02 1F 3E + 15 00 02 20 28 + 15 00 02 21 28 + 15 00 02 22 0E + 15 00 02 37 09 + 15 00 02 38 04 + 15 00 02 39 08 + 15 00 02 3A 12 + 15 00 02 3C 78 + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F 7F + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 55 0F + 15 00 02 56 01 + 15 00 02 57 69 + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 29 + 15 00 02 5B 15 + 15 00 02 5D 7C + 15 00 02 5E 65 + 15 00 02 5F 55 + 15 00 02 60 49 + 15 00 02 61 44 + 15 00 02 62 35 + 15 00 02 63 3A + 15 00 02 64 23 + 15 00 02 65 3D + 15 00 02 66 3C + 15 00 02 67 3D + 15 00 02 68 5D + 15 00 02 69 4D + 15 00 02 6A 56 + 15 00 02 6B 48 + 15 00 02 6C 45 + 15 00 02 6D 38 + 15 00 02 6E 25 + 15 00 02 6F 00 + 15 00 02 70 7C + 15 00 02 71 65 + 15 00 02 72 55 + 15 00 02 73 49 + 15 00 02 74 44 + 15 00 02 75 35 + 15 00 02 76 3A + 15 00 02 77 23 + 15 00 02 78 3D + 15 00 02 79 3C + 15 00 02 7A 3D + 15 00 02 7B 5D + 15 00 02 7C 4D + 15 00 02 7D 56 + 15 00 02 7E 48 + 15 00 02 7F 45 + 15 00 02 80 38 + 15 00 02 81 25 + 15 00 02 82 00 + 15 00 02 E0 02 + 15 00 02 00 1E + 15 00 02 01 1E + 15 00 02 02 41 + 15 00 02 03 41 + 15 00 02 04 43 + 15 00 02 05 43 + 15 00 02 06 1F + 15 00 02 07 1F + 15 00 02 08 1F + 15 00 02 09 1F + 15 00 02 0A 1E + 15 00 02 0B 1E + 15 00 02 0C 1F + 15 00 02 0D 47 + 15 00 02 0E 47 + 15 00 02 0F 45 + 15 00 02 10 45 + 15 00 02 11 4B + 15 00 02 12 4B + 15 00 02 13 49 + 15 00 02 14 49 + 15 00 02 15 1F + 15 00 02 16 1E + 15 00 02 17 1E + 15 00 02 18 40 + 15 00 02 19 40 + 15 00 02 1A 42 + 15 00 02 1B 42 + 15 00 02 1C 1F + 15 00 02 1D 1F + 15 00 02 1E 1F + 15 00 02 1F 1f + 15 00 02 20 1E + 15 00 02 21 1E + 15 00 02 22 1f + 15 00 02 23 46 + 15 00 02 24 46 + 15 00 02 25 44 + 15 00 02 26 44 + 15 00 02 27 4A + 15 00 02 28 4A + 15 00 02 29 48 + 15 00 02 2A 48 + 15 00 02 2B 1f + 15 00 02 2C 1F + 15 00 02 2D 1F + 15 00 02 2E 42 + 15 00 02 2F 42 + 15 00 02 30 40 + 15 00 02 31 40 + 15 00 02 32 1E + 15 00 02 33 1E + 15 00 02 34 1F + 15 00 02 35 1F + 15 00 02 36 1E + 15 00 02 37 1E + 15 00 02 38 1F + 15 00 02 39 48 + 15 00 02 3A 48 + 15 00 02 3B 4A + 15 00 02 3C 4A + 15 00 02 3D 44 + 15 00 02 3E 44 + 15 00 02 3F 46 + 15 00 02 40 46 + 15 00 02 41 1F + 15 00 02 42 1F + 15 00 02 43 1F + 15 00 02 44 43 + 15 00 02 45 43 + 15 00 02 46 41 + 15 00 02 47 41 + 15 00 02 48 1E + 15 00 02 49 1E + 15 00 02 4A 1E + 15 00 02 4B 1F + 15 00 02 4C 1E + 15 00 02 4D 1E + 15 00 02 4E 1F + 15 00 02 4F 49 + 15 00 02 50 49 + 15 00 02 51 4B + 15 00 02 52 4B + 15 00 02 53 45 + 15 00 02 54 45 + 15 00 02 55 47 + 15 00 02 56 47 + 15 00 02 57 1F + 15 00 02 58 10 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 30 + 15 00 02 5C 02 + 15 00 02 5D 40 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 30 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 6A + 15 00 02 64 6A + 15 00 02 65 05 + 15 00 02 66 12 + 15 00 02 67 74 + 15 00 02 68 04 + 15 00 02 69 6A + 15 00 02 6A 6A + 15 00 02 6B 08 + 15 00 02 6C 00 + 15 00 02 6D 06 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 07 + 15 00 02 76 00 + 15 00 02 77 5D + 15 00 02 78 17 + 15 00 02 79 1F + 15 00 02 7A 00 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 04 + 15 00 02 2B 2B + 15 00 02 2E 44 + 15 00 02 E0 01 + 15 00 02 0E 01 + 15 00 02 E0 03 + 15 00 02 98 2F + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 02 + + 05 78 01 11 + 05 05 01 29 + 15 0a 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <18>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + + + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; + + + + diff --git a/rk356x/rp-lcd-dual-lvds-10-1024-600-mipi1-7-1200-1920.dtsi b/rk356x/rp-lcd-dual-lvds-10-1024-600-mipi1-7-1200-1920.dtsi new file mode 100755 index 0000000..04a12c7 --- /dev/null +++ b/rk356x/rp-lcd-dual-lvds-10-1024-600-mipi1-7-1200-1920.dtsi @@ -0,0 +1,342 @@ +#include + +#define RP_DUAL_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 14 42 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 de 03 00 + 39 60 03 c9 02 23 + + 39 00 02 b0 00 + 39 00 06 14 08 b0 00 22 00 + 39 30 02 b4 0c + 39 40 03 b6 3a d3 + 39 50 02 51 e6 + 39 30 02 53 2c + + 05 78 01 29 + 05 78 01 11 + + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 8c 83 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 c9 02 23 + 39 60 03 ca 01 23 + 39 10 03 cb 10 05 + 39 10 03 cc 05 10 + 39 10 03 d0 00 00 + + + 39 10 03 b6 03 00 + 39 10 03 de 03 00 + 39 10 03 d6 05 00 + 39 60 03 b7 4b 02 + + 05 00 01 2c + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + + + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; + + + + diff --git a/rk356x/rp-lcd-dual-lvds-7-1024-600-mipi1-5-720-1280-v2.dtsi b/rk356x/rp-lcd-dual-lvds-7-1024-600-mipi1-5-720-1280-v2.dtsi new file mode 100755 index 0000000..b717d1e --- /dev/null +++ b/rk356x/rp-lcd-dual-lvds-7-1024-600-mipi1-5-720-1280-v2.dtsi @@ -0,0 +1,327 @@ +#include + +#define RP_DUAL_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "LVDS-1"; + extend_device = "DSI-1"; + extend_rotate = "1"; + extend_rotate_2 = "0"; + rotation_efull = "true"; + rotation_efull_2 = "false"; + home_apk = "null"; + status = "okay"; +}; + + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + + + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 5A 00 04 58 02 05 3D 00 01 + 08 32 0F 5A 32 03 05 00 00 + 00 00 02 00 00 18 1A 1E 14 + 87 29 0A 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 + 2B FF 7F 19 46 32 3C 78 94 + D5 02 08 00 00 04 98 40 00 + 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 + 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 02 04 06 08 0A + 0C 0E 10 12 14 FF FF FF FF + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 1D 1E 1F 20 + 21 22 24 26 28 29 2A FF FF + FF FF FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6F 01 + ]; +}; + + + + diff --git a/rk356x/rp-lcd-dual-mipi0-7-1024-600-edp-13-1920-1080.dtsi b/rk356x/rp-lcd-dual-mipi0-7-1024-600-edp-13-1920-1080.dtsi new file mode 100755 index 0000000..333adde --- /dev/null +++ b/rk356x/rp-lcd-dual-mipi0-7-1024-600-edp-13-1920-1080.dtsi @@ -0,0 +1,348 @@ +#include + +#define RP_DUAL_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + + + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 {//EDP 13.3 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 15.6 LP156WF6 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + +&edp { + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + + + +&lvds_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + + + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + + + + +&video_phy0 { + status = "okay"; +}; + + +&edp_phy { + status = "okay"; +}; + + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + +&route_lvds { + status = "disabled"; + connect = <&vp2_out_lvds>; +}; + +&route_edp { + status = "okay"; + connect = <&vp0_out_edp>; +}; + + + + +&pinctrl { + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ //old touch + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + goodix,cfg-group5 = [ //new touch + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; + +}; + + + + diff --git a/rk356x/rp-lcd-dual-mipi0-7-1024-600-mipi1-10-800-1280.dtsi b/rk356x/rp-lcd-dual-mipi0-7-1024-600-mipi1-10-800-1280.dtsi new file mode 100755 index 0000000..2bfd84f --- /dev/null +++ b/rk356x/rp-lcd-dual-mipi0-7-1024-600-mipi1-10-800-1280.dtsi @@ -0,0 +1,528 @@ +#include + +#define RP_DUAL_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing1 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 E0 04 + 15 00 02 2D 03 + 15 00 02 E0 00 + 15 00 02 80 03 + 15 00 02 70 02 + 15 00 02 71 23 + 15 00 02 72 06 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 66 + 15 00 02 03 00 + 15 00 02 04 6D + 15 00 02 17 00 + 15 00 02 18 BF + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B BF + 15 00 02 1C 00 + 15 00 02 1F 3E + 15 00 02 20 28 + 15 00 02 21 28 + 15 00 02 22 0E + 15 00 02 37 09 + 15 00 02 38 04 + 15 00 02 39 08 + 15 00 02 3A 12 + 15 00 02 3C 78 + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F 7F + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 55 0F + 15 00 02 56 01 + 15 00 02 57 69 + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 29 + 15 00 02 5B 15 + 15 00 02 5D 7C + 15 00 02 5E 65 + 15 00 02 5F 55 + 15 00 02 60 49 + 15 00 02 61 44 + 15 00 02 62 35 + 15 00 02 63 3A + 15 00 02 64 23 + 15 00 02 65 3D + 15 00 02 66 3C + 15 00 02 67 3D + 15 00 02 68 5D + 15 00 02 69 4D + 15 00 02 6A 56 + 15 00 02 6B 48 + 15 00 02 6C 45 + 15 00 02 6D 38 + 15 00 02 6E 25 + 15 00 02 6F 00 + 15 00 02 70 7C + 15 00 02 71 65 + 15 00 02 72 55 + 15 00 02 73 49 + 15 00 02 74 44 + 15 00 02 75 35 + 15 00 02 76 3A + 15 00 02 77 23 + 15 00 02 78 3D + 15 00 02 79 3C + 15 00 02 7A 3D + 15 00 02 7B 5D + 15 00 02 7C 4D + 15 00 02 7D 56 + 15 00 02 7E 48 + 15 00 02 7F 45 + 15 00 02 80 38 + 15 00 02 81 25 + 15 00 02 82 00 + 15 00 02 E0 02 + 15 00 02 00 1E + 15 00 02 01 1E + 15 00 02 02 41 + 15 00 02 03 41 + 15 00 02 04 43 + 15 00 02 05 43 + 15 00 02 06 1F + 15 00 02 07 1F + 15 00 02 08 1F + 15 00 02 09 1F + 15 00 02 0A 1E + 15 00 02 0B 1E + 15 00 02 0C 1F + 15 00 02 0D 47 + 15 00 02 0E 47 + 15 00 02 0F 45 + 15 00 02 10 45 + 15 00 02 11 4B + 15 00 02 12 4B + 15 00 02 13 49 + 15 00 02 14 49 + 15 00 02 15 1F + 15 00 02 16 1E + 15 00 02 17 1E + 15 00 02 18 40 + 15 00 02 19 40 + 15 00 02 1A 42 + 15 00 02 1B 42 + 15 00 02 1C 1F + 15 00 02 1D 1F + 15 00 02 1E 1F + 15 00 02 1F 1f + 15 00 02 20 1E + 15 00 02 21 1E + 15 00 02 22 1f + 15 00 02 23 46 + 15 00 02 24 46 + 15 00 02 25 44 + 15 00 02 26 44 + 15 00 02 27 4A + 15 00 02 28 4A + 15 00 02 29 48 + 15 00 02 2A 48 + 15 00 02 2B 1f + 15 00 02 2C 1F + 15 00 02 2D 1F + 15 00 02 2E 42 + 15 00 02 2F 42 + 15 00 02 30 40 + 15 00 02 31 40 + 15 00 02 32 1E + 15 00 02 33 1E + 15 00 02 34 1F + 15 00 02 35 1F + 15 00 02 36 1E + 15 00 02 37 1E + 15 00 02 38 1F + 15 00 02 39 48 + 15 00 02 3A 48 + 15 00 02 3B 4A + 15 00 02 3C 4A + 15 00 02 3D 44 + 15 00 02 3E 44 + 15 00 02 3F 46 + 15 00 02 40 46 + 15 00 02 41 1F + 15 00 02 42 1F + 15 00 02 43 1F + 15 00 02 44 43 + 15 00 02 45 43 + 15 00 02 46 41 + 15 00 02 47 41 + 15 00 02 48 1E + 15 00 02 49 1E + 15 00 02 4A 1E + 15 00 02 4B 1F + 15 00 02 4C 1E + 15 00 02 4D 1E + 15 00 02 4E 1F + 15 00 02 4F 49 + 15 00 02 50 49 + 15 00 02 51 4B + 15 00 02 52 4B + 15 00 02 53 45 + 15 00 02 54 45 + 15 00 02 55 47 + 15 00 02 56 47 + 15 00 02 57 1F + 15 00 02 58 10 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 30 + 15 00 02 5C 02 + 15 00 02 5D 40 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 30 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 6A + 15 00 02 64 6A + 15 00 02 65 05 + 15 00 02 66 12 + 15 00 02 67 74 + 15 00 02 68 04 + 15 00 02 69 6A + 15 00 02 6A 6A + 15 00 02 6B 08 + 15 00 02 6C 00 + 15 00 02 6D 06 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 07 + 15 00 02 76 00 + 15 00 02 77 5D + 15 00 02 78 17 + 15 00 02 79 1F + 15 00 02 7A 00 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 04 + 15 00 02 2B 2B + 15 00 02 2E 44 + 15 00 02 E0 01 + 15 00 02 0E 01 + 15 00 02 E0 03 + 15 00 02 98 2F + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 02 + + 05 78 01 11 + 05 05 01 29 + 15 0a 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <18>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; + + + + diff --git a/rk356x/rp-lcd-dual-mipi0-7-1024-600-mipi1-5-720-1280-v2.dtsi b/rk356x/rp-lcd-dual-mipi0-7-1024-600-mipi1-5-720-1280-v2.dtsi new file mode 100755 index 0000000..afd54fd --- /dev/null +++ b/rk356x/rp-lcd-dual-mipi0-7-1024-600-mipi1-5-720-1280-v2.dtsi @@ -0,0 +1,350 @@ +#include + +#define RP_DUAL_LCD + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "160"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "DSI"; + extend_rotate = "1"; + extend_rotate_2 = "0"; + rotation_efull = "true"; + rotation_efull_2 = "false"; + home_apk = "null"; + status = "okay"; +}; + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing1 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + goodix,cfg-group5 = [ + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; +}; + + + + diff --git a/rk356x/rp-lcd-duallcd-mipi0-10-800-1280-mipi1-10-800-1280.dtsi b/rk356x/rp-lcd-duallcd-mipi0-10-800-1280-mipi1-10-800-1280.dtsi new file mode 100755 index 0000000..1317246 --- /dev/null +++ b/rk356x/rp-lcd-duallcd-mipi0-10-800-1280-mipi1-10-800-1280.dtsi @@ -0,0 +1,762 @@ +/** + * rpdzkj lcd configuration + */ + +#define RP_DUAL_LCD + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + //=========_1===========// + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 53 + 39 00 02 04 13 + 39 00 02 05 00 + 39 00 02 06 04 + 39 00 02 07 00 + 39 00 02 08 00 + 39 00 02 09 22 + 39 00 02 0a 22 + 39 00 02 0b 00 + 39 00 02 0c 01 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 23 + 39 00 02 10 23 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 44 + 39 00 02 1f 80 + 39 00 02 20 02 + 39 00 02 21 03 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 03 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 04 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 3C + 39 00 02 39 00 + 39 00 02 3a 40 + 39 00 02 3b 40 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + + + + //=========_2===========// + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + //=========_3===========// + 39 00 02 5e 11 + + 39 00 02 5f 01 + 39 00 02 60 00 + 39 00 02 61 15 + 39 00 02 62 14 + 39 00 02 63 0C + 39 00 02 64 0D + 39 00 02 65 0E + 39 00 02 66 0F + 39 00 02 67 06 + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 08 + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 02 + 39 00 02 72 02 + 39 00 02 73 02 + 39 00 02 74 02 + + 39 00 02 75 01 + 39 00 02 76 00 + 39 00 02 77 15 + 39 00 02 78 14 + 39 00 02 79 0C + 39 00 02 7a 0D + 39 00 02 7b 0E + 39 00 02 7c 0F + 39 00 02 7D 08 + 39 00 02 7E 02 + 39 00 02 7F 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 06 + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 02 + 39 00 02 88 02 + 39 00 02 89 02 + 39 00 02 8A 02 + + + //CMD_Page + 39 00 04 FF 98 81 04 + 39 00 02 6C 15 + 39 00 02 6E 3B + 39 00 02 6F 73 + 39 00 02 3A 24 + 39 00 02 8D 14 + 39 00 02 87 BA + 39 00 02 26 76 + 39 00 02 B2 D1 + 39 00 02 B5 27 + 39 00 02 31 75 + 39 00 02 30 03 + 39 00 02 3B 98 + 39 00 02 35 1f + 39 00 02 33 14 + 39 00 02 7A 0F + 39 00 02 38 02 + 39 00 02 39 00 + + + //CMD_Page + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 0A + 39 00 02 35 07 + 39 00 02 52 00 + 39 00 02 53 5A + 39 00 02 54 00 + 39 00 02 55 59 + 39 00 02 50 83 + 39 00 02 51 80 + 39 00 02 60 20 + 39 00 02 61 01 + 39 00 02 62 07 + 39 00 02 63 00 + + //GammaP + 39 00 02 A0 08 + 39 00 02 A1 0F + 39 00 02 A2 15 + 39 00 02 A3 0E + 39 00 02 A4 0D + 39 00 02 A5 1B + 39 00 02 A6 0F + 39 00 02 A7 14 + 39 00 02 A8 33 + 39 00 02 A9 17 + 39 00 02 AA 23 + 39 00 02 AB 3F + 39 00 02 AC 22 + 39 00 02 AD 24 + 39 00 02 AE 59 + 39 00 02 AF 2B + 39 00 02 B0 2E + 39 00 02 B1 4C + 39 00 02 B2 5C + 39 00 02 B3 33 + + //GammaN + 39 00 02 C0 08 + 39 00 02 C1 0F + 39 00 02 C2 15 + 39 00 02 C3 0E + 39 00 02 C4 0D + 39 00 02 C5 1B + 39 00 02 C6 0F + 39 00 02 C7 14 + 39 00 02 C8 33 + 39 00 02 C9 17 + 39 00 02 CA 23 + 39 00 02 CB 3F + 39 00 02 CC 22 + 39 00 02 CD 24 + 39 00 02 CE 59 + 39 00 02 CF 2B + 39 00 02 D0 2E + 39 00 02 D1 4C + 39 00 02 D2 5C + 39 00 02 D3 33 + + + //CMD_Page + 39 00 04 FF 98 81 00 + 05 78 01 11 //sleep out + + 05 00 01 29 //display on + 05 00 01 35 //TE on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi1 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + //=========_1===========// + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 53 + 39 00 02 04 13 + 39 00 02 05 00 + 39 00 02 06 04 + 39 00 02 07 00 + 39 00 02 08 00 + 39 00 02 09 22 + 39 00 02 0a 22 + 39 00 02 0b 00 + 39 00 02 0c 01 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 23 + 39 00 02 10 23 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 44 + 39 00 02 1f 80 + 39 00 02 20 02 + 39 00 02 21 03 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 03 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 04 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 3C + 39 00 02 39 00 + 39 00 02 3a 40 + 39 00 02 3b 40 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + + + + //=========_2===========// + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + //=========_3===========// + 39 00 02 5e 11 + + 39 00 02 5f 01 + 39 00 02 60 00 + 39 00 02 61 15 + 39 00 02 62 14 + 39 00 02 63 0C + 39 00 02 64 0D + 39 00 02 65 0E + 39 00 02 66 0F + 39 00 02 67 06 + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 08 + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 02 + 39 00 02 72 02 + 39 00 02 73 02 + 39 00 02 74 02 + + 39 00 02 75 01 + 39 00 02 76 00 + 39 00 02 77 15 + 39 00 02 78 14 + 39 00 02 79 0C + 39 00 02 7a 0D + 39 00 02 7b 0E + 39 00 02 7c 0F + 39 00 02 7D 08 + 39 00 02 7E 02 + 39 00 02 7F 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 06 + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 02 + 39 00 02 88 02 + 39 00 02 89 02 + 39 00 02 8A 02 + + + //CMD_Page + 39 00 04 FF 98 81 04 + 39 00 02 6C 15 + 39 00 02 6E 3B + 39 00 02 6F 73 + 39 00 02 3A 24 + 39 00 02 8D 14 + 39 00 02 87 BA + 39 00 02 26 76 + 39 00 02 B2 D1 + 39 00 02 B5 27 + 39 00 02 31 75 + 39 00 02 30 03 + 39 00 02 3B 98 + 39 00 02 35 1f + 39 00 02 33 14 + 39 00 02 7A 0F + 39 00 02 38 02 + 39 00 02 39 00 + + + //CMD_Page + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 0A + 39 00 02 35 07 + 39 00 02 52 00 + 39 00 02 53 5A + 39 00 02 54 00 + 39 00 02 55 59 + 39 00 02 50 83 + 39 00 02 51 80 + 39 00 02 60 20 + 39 00 02 61 01 + 39 00 02 62 07 + 39 00 02 63 00 + + //GammaP + 39 00 02 A0 08 + 39 00 02 A1 0F + 39 00 02 A2 15 + 39 00 02 A3 0E + 39 00 02 A4 0D + 39 00 02 A5 1B + 39 00 02 A6 0F + 39 00 02 A7 14 + 39 00 02 A8 33 + 39 00 02 A9 17 + 39 00 02 AA 23 + 39 00 02 AB 3F + 39 00 02 AC 22 + 39 00 02 AD 24 + 39 00 02 AE 59 + 39 00 02 AF 2B + 39 00 02 B0 2E + 39 00 02 B1 4C + 39 00 02 B2 5C + 39 00 02 B3 33 + + //GammaN + 39 00 02 C0 08 + 39 00 02 C1 0F + 39 00 02 C2 15 + 39 00 02 C3 0E + 39 00 02 C4 0D + 39 00 02 C5 1B + 39 00 02 C6 0F + 39 00 02 C7 14 + 39 00 02 C8 33 + 39 00 02 C9 17 + 39 00 02 CA 23 + 39 00 02 CB 3F + 39 00 02 CC 22 + 39 00 02 CD 24 + 39 00 02 CE 59 + 39 00 02 CF 2B + 39 00 02 D0 2E + 39 00 02 D1 4C + 39 00 02 D2 5C + 39 00 02 D3 33 + + + //CMD_Page + 39 00 04 FF 98 81 00 + 05 78 01 11 //sleep out + + 05 00 01 29 //display on + 05 00 01 35 //TE on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing1 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ +#if 0 + /* old touchscreen sensor_id0, reserve for some customer maybe using */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +#endif + /** ic 9271_1020 sensor_id0, v3 add 20211104 */ + goodix,cfg-group0 = [ + 59 20 03 00 05 0A 05 00 01 08 + 28 05 5A 46 03 05 00 00 00 00 + 00 00 00 17 19 1B 14 8E 2E 99 + 37 39 D3 07 00 00 01 81 02 2D + 00 00 00 00 00 00 00 00 00 00 + 00 28 78 94 C5 02 07 00 00 04 + 9A 2C 00 80 37 00 6B 45 00 5C + 56 00 50 6C 00 50 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 17 16 15 14 11 10 0F 0E + 0D 0C 09 08 07 06 05 04 01 00 + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0D 0F 10 11 12 28 27 26 25 24 + 23 22 21 20 1F 1E 1C 1B 19 13 + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 BF 01 + ]; + + /* touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; +}; + + + + diff --git a/rk356x/rp-lcd-edp-13-1920-1080.dtsi b/rk356x/rp-lcd-edp-13-1920-1080.dtsi new file mode 100755 index 0000000..8697124 --- /dev/null +++ b/rk356x/rp-lcd-edp-13-1920-1080.dtsi @@ -0,0 +1,148 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_EDP_USED + + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 {//EDP 15.6 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 13.3 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + + +&edp { + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; +&hdmi_in_vp1 { + status = "okay"; +}; + +&route_edp { + status = "okay"; + connect = <&vp0_out_edp>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 64 80 07 38 04 0A 3D 00 01 C8 28 0F + 55 37 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 90 30 AA 25 27 0F 0A 00 00 + 00 5A 03 11 00 00 00 00 00 00 00 00 + 00 25 00 19 37 94 D5 02 08 14 00 04 + 9B 1B 00 8E 1F 00 80 25 00 76 2B 00 + 6E 32 00 6E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 10 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + 00 00 00 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 19 1B 1C 1E 1F 20 21 22 23 24 + 25 26 27 28 29 2A 00 00 00 00 00 00 + 00 00 00 00 B7 01 + ]; +}; diff --git a/rk356x/rp-lcd-edp-13.3-15.6-1920-1080.dtsi b/rk356x/rp-lcd-edp-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..f0fc592 --- /dev/null +++ b/rk356x/rp-lcd-edp-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,152 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_EDP_USED + + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 {//EDP 15.6 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 13.3 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + + +&edp { + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; +&hdmi_in_vp1 { + status = "okay"; +}; + +&route_edp { + status = "okay"; + connect = <&vp0_out_edp>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; + diff --git a/rk356x/rp-lcd-edp-15-1366-768.dtsi b/rk356x/rp-lcd-edp-15-1366-768.dtsi new file mode 100755 index 0000000..4dee1e1 --- /dev/null +++ b/rk356x/rp-lcd-edp-15-1366-768.dtsi @@ -0,0 +1,155 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_EDP_USED + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 {//EDP 15.6 1366x768 + clock-frequency = <72300000>; + hactive = <1366>; + vactive = <768>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <14>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 13.3 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + + +&edp { + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + +&edp_in_vp0 { + status = "okay"; +}; + +&edp_in_vp1 { + status = "disabled"; +}; + +&hdmi_in_vp0 { + status = "disabled"; +}; +&hdmi_in_vp1 { + status = "okay"; +}; + +&route_edp { + status = "okay"; + connect = <&vp0_out_edp>; +}; + + + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1366>; + gtp_resolution_y = <768>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 41 80 07 38 04 0A 2D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 04 17 19 1D 14 95 35 FF + 4C 4E B5 06 00 00 00 00 03 2D + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 61 30 00 57 37 00 4D 3F 00 45 + 49 00 3E 54 00 3E 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A EA 01 + ]; +}; + + diff --git a/rk356x/rp-lcd-hdmi.dtsi b/rk356x/rp-lcd-hdmi.dtsi new file mode 100755 index 0000000..baef17a --- /dev/null +++ b/rk356x/rp-lcd-hdmi.dtsi @@ -0,0 +1,33 @@ +/** + * enable hdmi dispaly + */ + +&hdmi { + status = "okay"; +}; + +&hdmi_in_vp0 { + status = "okay"; +}; + +&hdmi_in_vp1 { + status = "disabled"; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&hdmi { + rockchip,phy-table = + <92812500 0x8009 0x0000 0x0270>, + <165000000 0x800b 0x0000 0x026d>, + <185625000 0x800b 0x0000 0x01ed>, + <297000000 0x800b 0x0000 0x01ad>, + <594000000 0x8029 0x0000 0x0088>, + <000000000 0x0000 0x0000 0x0000>; +}; diff --git a/rk356x/rp-lcd-lvds-10-1024-600-raw.dtsi b/rk356x/rp-lcd-lvds-10-1024-600-raw.dtsi new file mode 100755 index 0000000..dbe26a3 --- /dev/null +++ b/rk356x/rp-lcd-lvds-10-1024-600-raw.dtsi @@ -0,0 +1,177 @@ +#include +#include "rp-lcd-hdmi.dtsi" + +&backlight4{ + pwms = <&pwm4 0 25000 1>; /** pwm polarity of raw lvds screen is inverse */ +}; + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + + +&pwm4 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; diff --git a/rk356x/rp-lcd-lvds-10-1024-600.dtsi b/rk356x/rp-lcd-lvds-10-1024-600.dtsi new file mode 100755 index 0000000..bd7168a --- /dev/null +++ b/rk356x/rp-lcd-lvds-10-1024-600.dtsi @@ -0,0 +1,174 @@ +#include +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + +&backlight4{ + default-brightness-level=<255>; +}; + +&pwm4 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; diff --git a/rk356x/rp-lcd-lvds-10-1280-800-v2.dtsi b/rk356x/rp-lcd-lvds-10-1280-800-v2.dtsi new file mode 100755 index 0000000..ad5d17d --- /dev/null +++ b/rk356x/rp-lcd-lvds-10-1280-800-v2.dtsi @@ -0,0 +1,197 @@ +#include +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <138>; + hfront-porch = <136>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm4 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1280>; + gtp_resolution_y = <800>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + goodix,cfg-group3 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 +]; + goodix,cfg-group2 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; +}; + diff --git a/rk356x/rp-lcd-lvds-10-1280-800.dtsi b/rk356x/rp-lcd-lvds-10-1280-800.dtsi new file mode 100755 index 0000000..b3d2e15 --- /dev/null +++ b/rk356x/rp-lcd-lvds-10-1280-800.dtsi @@ -0,0 +1,170 @@ +#include +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <72000000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <138>; + hfront-porch = <136>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + +&pwm4 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1280>; + gtp_resolution_y = <800>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + goodix,cfg-group2 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; + goodix,cfg-group3 = [ + 5A 00 05 20 03 02 0D 00 01 0A 28 + 0A 50 32 03 05 00 00 00 00 00 00 + 08 00 00 00 00 8C 2E 0E 30 32 34 + 06 00 00 00 82 02 1D 00 01 00 00 + 00 00 00 00 00 00 00 24 60 94 C5 + 02 07 00 00 04 97 27 00 80 30 00 + 6D 3B 00 60 47 00 54 57 00 54 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 14 13 12 10 0F 0C 0A 08 06 + 04 02 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 D4 01 + ]; +}; + diff --git a/rk356x/rp-lcd-lvds-7-1024-600-v2.dtsi b/rk356x/rp-lcd-lvds-7-1024-600-v2.dtsi new file mode 100755 index 0000000..f04f4ef --- /dev/null +++ b/rk356x/rp-lcd-lvds-7-1024-600-v2.dtsi @@ -0,0 +1,183 @@ +#include +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "180"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + +&pwm4 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 5A 00 04 58 02 05 3D 00 01 + 08 32 0F 5A 32 03 05 00 00 + 00 00 02 00 00 18 1A 1E 14 + 87 29 0A 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 + 2B FF 7F 19 46 32 3C 78 94 + D5 02 08 00 00 04 98 40 00 + 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 + 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 02 04 06 08 0A + 0C 0E 10 12 14 FF FF FF FF + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 1D 1E 1F 20 + 21 22 24 26 28 29 2A FF FF + FF FF FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6F 01 + ]; + }; + diff --git a/rk356x/rp-lcd-lvds-7-1024-600.dtsi b/rk356x/rp-lcd-lvds-7-1024-600.dtsi new file mode 100755 index 0000000..0f0e9aa --- /dev/null +++ b/rk356x/rp-lcd-lvds-7-1024-600.dtsi @@ -0,0 +1,161 @@ +/** + * rpdzkj lcd configuration + */ + +#include +#include "rp-lcd-hdmi.dtsi" //include for default support hdmi display +#define RP_SINGLE_LCD + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /* + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&lvds { + status = "okay"; + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + +&pwm4 { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + +&video_phy0 { + status = "okay"; +}; + +&lvds_in_vp1 { + status = "okay"; +}; + +&lvds_in_vp2 { + status = "disabled"; +}; + +&route_lvds { + status = "okay"; + connect = <&vp1_out_lvds>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + //goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + //goodix_irq_gpio = <&gpio0 RK_PA5 IRQ_TYPE_EDGE_FALLING>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 5A 00 04 58 02 05 3D 00 01 + 08 32 0F 5A 32 03 05 00 00 + 00 00 02 00 00 18 1A 1E 14 + 87 29 0A 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 + 2B FF 7F 19 46 32 3C 78 94 + D5 02 08 00 00 04 98 40 00 + 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 + 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 02 04 06 08 0A + 0C 0E 10 12 14 FF FF FF FF + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 1D 1E 1F 20 + 21 22 24 26 28 29 2A FF FF + FF FF FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6F 01 + ]; + +}; diff --git a/rk356x/rp-lcd-mipi0-10-1200-1920.dtsi b/rk356x/rp-lcd-mipi0-10-1200-1920.dtsi new file mode 100755 index 0000000..851c042 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-10-1200-1920.dtsi @@ -0,0 +1,162 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + // reset-delay-ms = <60>; + // init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + // unprepare-delay-ms = <60>; + // disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + //MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; +}; + diff --git a/rk356x/rp-lcd-mipi0-10-1920-1200.dtsi b/rk356x/rp-lcd-mipi0-10-1920-1200.dtsi new file mode 100755 index 0000000..2bb5fa3 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-10-1920-1200.dtsi @@ -0,0 +1,141 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1200>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + // reset-delay-ms = <60>; + // init-delay-ms = <60>; + enable-delay-ms = <160>; + prepare-delay-ms = <200>; + // unprepare-delay-ms = <60>; + // disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <60>; //60 + hfront-porch = <16>; //16 + vback-porch = <23>; //23 + vfront-porch = <12>; //12 + hsync-len = <20>; //20 + vsync-len = <3>; //3 + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <1>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1200>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 55 80 07 B0 04 0A 3D 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 8E 2F 99 17 15 31 + 0D 00 00 02 9B 03 1D 00 00 00 00 + 00 00 00 00 00 00 00 1E 78 94 C5 + 02 08 00 00 00 5B 22 00 4C 2D 00 + 41 3C 00 38 4F 00 32 69 00 32 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 0C + 0D 0E 0F 10 11 14 15 16 17 FF FF + 00 00 00 00 00 00 00 00 00 00 00 + 02 04 06 07 08 0A 0C 0D 0F 10 11 + 12 13 19 1B 1C 1E 1F 20 21 22 23 + 24 25 26 27 28 29 FF FF FF 00 00 + 00 00 00 00 00 00 00 00 6B 01]; +}; diff --git a/rk356x/rp-lcd-mipi0-10-800-1280-v2.dtsi b/rk356x/rp-lcd-mipi0-10-800-1280-v2.dtsi new file mode 100755 index 0000000..2e822ac --- /dev/null +++ b/rk356x/rp-lcd-mipi0-10-800-1280-v2.dtsi @@ -0,0 +1,432 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + //=========_1===========// + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 53 + 39 00 02 04 13 + 39 00 02 05 00 + 39 00 02 06 04 + 39 00 02 07 00 + 39 00 02 08 00 + 39 00 02 09 22 + 39 00 02 0a 22 + 39 00 02 0b 00 + 39 00 02 0c 01 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 23 + 39 00 02 10 23 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 44 + 39 00 02 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02 61 15 + 39 00 02 62 14 + 39 00 02 63 0C + 39 00 02 64 0D + 39 00 02 65 0E + 39 00 02 66 0F + 39 00 02 67 06 + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 08 + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 02 + 39 00 02 72 02 + 39 00 02 73 02 + 39 00 02 74 02 + + 39 00 02 75 01 + 39 00 02 76 00 + 39 00 02 77 15 + 39 00 02 78 14 + 39 00 02 79 0C + 39 00 02 7a 0D + 39 00 02 7b 0E + 39 00 02 7c 0F + 39 00 02 7D 08 + 39 00 02 7E 02 + 39 00 02 7F 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 06 + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 02 + 39 00 02 88 02 + 39 00 02 89 02 + 39 00 02 8A 02 + + + //CMD_Page + 39 00 04 FF 98 81 04 + 39 00 02 6C 15 + 39 00 02 6E 3B + 39 00 02 6F 73 + 39 00 02 3A 24 + 39 00 02 8D 14 + 39 00 02 87 BA + 39 00 02 26 76 + 39 00 02 B2 D1 + 39 00 02 B5 27 + 39 00 02 31 75 + 39 00 02 30 03 + 39 00 02 3B 98 + 39 00 02 35 1f + 39 00 02 33 14 + 39 00 02 7A 0F + 39 00 02 38 02 + 39 00 02 39 00 + + + //CMD_Page + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 0A + 39 00 02 35 07 + 39 00 02 52 00 + 39 00 02 53 5A + 39 00 02 54 00 + 39 00 02 55 59 + 39 00 02 50 83 + 39 00 02 51 80 + 39 00 02 60 20 + 39 00 02 61 01 + 39 00 02 62 07 + 39 00 02 63 00 + + //GammaP + 39 00 02 A0 08 + 39 00 02 A1 0F + 39 00 02 A2 15 + 39 00 02 A3 0E + 39 00 02 A4 0D + 39 00 02 A5 1B + 39 00 02 A6 0F + 39 00 02 A7 14 + 39 00 02 A8 33 + 39 00 02 A9 17 + 39 00 02 AA 23 + 39 00 02 AB 3F + 39 00 02 AC 22 + 39 00 02 AD 24 + 39 00 02 AE 59 + 39 00 02 AF 2B + 39 00 02 B0 2E + 39 00 02 B1 4C + 39 00 02 B2 5C + 39 00 02 B3 33 + + //GammaN + 39 00 02 C0 08 + 39 00 02 C1 0F + 39 00 02 C2 15 + 39 00 02 C3 0E + 39 00 02 C4 0D + 39 00 02 C5 1B + 39 00 02 C6 0F + 39 00 02 C7 14 + 39 00 02 C8 33 + 39 00 02 C9 17 + 39 00 02 CA 23 + 39 00 02 CB 3F + 39 00 02 CC 22 + 39 00 02 CD 24 + 39 00 02 CE 59 + 39 00 02 CF 2B + 39 00 02 D0 2E + 39 00 02 D1 4C + 39 00 02 D2 5C + 39 00 02 D3 33 + + + //CMD_Page + 39 00 04 FF 98 81 00 + 05 78 01 11 //sleep out + + 05 00 01 29 //display on + 05 00 01 35 //TE on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ +#if 0 + /* old touchscreen sensor_id0, reserve for some customer maybe using */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +#endif + /** ic 9271_1020 sensor_id0, v3 add 20211104 */ + goodix,cfg-group0 = [ + 70 20 03 00 05 0A 05 00 01 08 + 28 05 5A 46 03 05 00 00 00 00 + 00 00 00 17 19 1B 14 8E 2E 99 + 37 39 D3 07 00 00 00 80 02 2D + 00 00 00 00 00 00 00 00 00 00 + 00 28 78 94 C5 02 07 00 00 04 + 9A 2C 00 80 37 00 6B 45 00 5C + 56 00 50 6C 00 50 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 17 16 15 14 11 10 0F 0E + 0D 0C 09 08 07 06 05 04 01 00 + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0D 0F 10 11 12 28 27 26 25 24 + 23 22 21 20 1F 1E 1C 1B 19 13 + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 AA 01 + ]; + + /* touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; +}; diff --git a/rk356x/rp-lcd-mipi0-10-800-1280-v3.dtsi b/rk356x/rp-lcd-mipi0-10-800-1280-v3.dtsi new file mode 100755 index 0000000..2b1685e --- /dev/null +++ b/rk356x/rp-lcd-mipi0-10-800-1280-v3.dtsi @@ -0,0 +1,155 @@ +#define RP_SINGLE_LCD +#include "rp-lcd-hdmi.dtsi" + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group2 = [ + 49 20 03 00 05 0A 35 00 01 06 23 08 + 37 2D 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 53 55 0C 08 00 00 + 00 01 03 1C 00 00 00 00 00 00 00 00 + 00 00 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B 61 00 + 7A 70 00 7B 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 24 01 + ]; +}; + + + diff --git a/rk356x/rp-lcd-mipi0-10-800-1280.dtsi b/rk356x/rp-lcd-mipi0-10-800-1280.dtsi new file mode 100755 index 0000000..1e1d584 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-10-800-1280.dtsi @@ -0,0 +1,405 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 E0 04 + 15 00 02 2D 03 + 15 00 02 E0 00 + 15 00 02 80 03 + 15 00 02 70 02 + 15 00 02 71 23 + 15 00 02 72 06 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 66 + 15 00 02 03 00 + 15 00 02 04 6D + 15 00 02 17 00 + 15 00 02 18 BF + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B BF + 15 00 02 1C 00 + 15 00 02 1F 3E + 15 00 02 20 28 + 15 00 02 21 28 + 15 00 02 22 0E + 15 00 02 37 09 + 15 00 02 38 04 + 15 00 02 39 08 + 15 00 02 3A 12 + 15 00 02 3C 78 + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F 7F + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 55 0F + 15 00 02 56 01 + 15 00 02 57 69 + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 29 + 15 00 02 5B 15 + 15 00 02 5D 7C + 15 00 02 5E 65 + 15 00 02 5F 55 + 15 00 02 60 49 + 15 00 02 61 44 + 15 00 02 62 35 + 15 00 02 63 3A + 15 00 02 64 23 + 15 00 02 65 3D + 15 00 02 66 3C + 15 00 02 67 3D + 15 00 02 68 5D + 15 00 02 69 4D + 15 00 02 6A 56 + 15 00 02 6B 48 + 15 00 02 6C 45 + 15 00 02 6D 38 + 15 00 02 6E 25 + 15 00 02 6F 00 + 15 00 02 70 7C + 15 00 02 71 65 + 15 00 02 72 55 + 15 00 02 73 49 + 15 00 02 74 44 + 15 00 02 75 35 + 15 00 02 76 3A + 15 00 02 77 23 + 15 00 02 78 3D + 15 00 02 79 3C + 15 00 02 7A 3D + 15 00 02 7B 5D + 15 00 02 7C 4D + 15 00 02 7D 56 + 15 00 02 7E 48 + 15 00 02 7F 45 + 15 00 02 80 38 + 15 00 02 81 25 + 15 00 02 82 00 + 15 00 02 E0 02 + 15 00 02 00 1E + 15 00 02 01 1E + 15 00 02 02 41 + 15 00 02 03 41 + 15 00 02 04 43 + 15 00 02 05 43 + 15 00 02 06 1F + 15 00 02 07 1F + 15 00 02 08 1F + 15 00 02 09 1F + 15 00 02 0A 1E + 15 00 02 0B 1E + 15 00 02 0C 1F + 15 00 02 0D 47 + 15 00 02 0E 47 + 15 00 02 0F 45 + 15 00 02 10 45 + 15 00 02 11 4B + 15 00 02 12 4B + 15 00 02 13 49 + 15 00 02 14 49 + 15 00 02 15 1F + 15 00 02 16 1E + 15 00 02 17 1E + 15 00 02 18 40 + 15 00 02 19 40 + 15 00 02 1A 42 + 15 00 02 1B 42 + 15 00 02 1C 1F + 15 00 02 1D 1F + 15 00 02 1E 1F + 15 00 02 1F 1f + 15 00 02 20 1E + 15 00 02 21 1E + 15 00 02 22 1f + 15 00 02 23 46 + 15 00 02 24 46 + 15 00 02 25 44 + 15 00 02 26 44 + 15 00 02 27 4A + 15 00 02 28 4A + 15 00 02 29 48 + 15 00 02 2A 48 + 15 00 02 2B 1f + 15 00 02 2C 1F + 15 00 02 2D 1F + 15 00 02 2E 42 + 15 00 02 2F 42 + 15 00 02 30 40 + 15 00 02 31 40 + 15 00 02 32 1E + 15 00 02 33 1E + 15 00 02 34 1F + 15 00 02 35 1F + 15 00 02 36 1E + 15 00 02 37 1E + 15 00 02 38 1F + 15 00 02 39 48 + 15 00 02 3A 48 + 15 00 02 3B 4A + 15 00 02 3C 4A + 15 00 02 3D 44 + 15 00 02 3E 44 + 15 00 02 3F 46 + 15 00 02 40 46 + 15 00 02 41 1F + 15 00 02 42 1F + 15 00 02 43 1F + 15 00 02 44 43 + 15 00 02 45 43 + 15 00 02 46 41 + 15 00 02 47 41 + 15 00 02 48 1E + 15 00 02 49 1E + 15 00 02 4A 1E + 15 00 02 4B 1F + 15 00 02 4C 1E + 15 00 02 4D 1E + 15 00 02 4E 1F + 15 00 02 4F 49 + 15 00 02 50 49 + 15 00 02 51 4B + 15 00 02 52 4B + 15 00 02 53 45 + 15 00 02 54 45 + 15 00 02 55 47 + 15 00 02 56 47 + 15 00 02 57 1F + 15 00 02 58 10 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 30 + 15 00 02 5C 02 + 15 00 02 5D 40 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 30 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 6A + 15 00 02 64 6A + 15 00 02 65 05 + 15 00 02 66 12 + 15 00 02 67 74 + 15 00 02 68 04 + 15 00 02 69 6A + 15 00 02 6A 6A + 15 00 02 6B 08 + 15 00 02 6C 00 + 15 00 02 6D 06 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 07 + 15 00 02 76 00 + 15 00 02 77 5D + 15 00 02 78 17 + 15 00 02 79 1F + 15 00 02 7A 00 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 04 + 15 00 02 2B 2B + 15 00 02 2E 44 + 15 00 02 E0 01 + 15 00 02 0E 01 + 15 00 02 E0 03 + 15 00 02 98 2F + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 02 + + 05 78 01 11 + 05 05 01 29 + 15 0a 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <18>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + /* old touchscreen sensor_id0 */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; + /* new touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; +}; + + + diff --git a/rk356x/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi b/rk356x/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi new file mode 100755 index 0000000..7ed4ba1 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi @@ -0,0 +1,197 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; +// rockchip,lane-rate = <480>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + //MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <45>; + hfront-porch = <45>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 4D D0 02 00 05 05 35 00 01 08 32 + 08 5A 3C 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 29 0A 55 57 B5 + 06 00 00 00 41 22 10 00 01 00 0F + 00 2A 00 00 19 50 32 3C 78 94 D5 + 02 08 00 00 04 A2 40 00 8F 4A 00 + 80 55 00 73 61 00 67 70 00 67 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 + 06 08 0A 0F 10 12 FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF 8D 01 + ]; +}; diff --git a/rk356x/rp-lcd-mipi0-5-720-1280-v2.dtsi b/rk356x/rp-lcd-mipi0-5-720-1280-v2.dtsi new file mode 100755 index 0000000..c1fd115 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-5-720-1280-v2.dtsi @@ -0,0 +1,188 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + +&dsi0 { + status = "okay"; +// rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 D0 02 00 05 05 35 01 01 08 1E 0F 5A 3C + 03 05 00 00 00 00 11 11 00 19 1B 1E 14 89 + 29 0A 41 43 D3 07 00 00 00 9A 02 11 00 01 + 05 00 00 00 00 09 11 00 00 36 4A 94 45 00 + 00 00 00 00 94 37 00 8B 3B 00 83 3F 00 7C + 43 00 76 47 00 76 10 30 48 00 F0 4A 3A FF + FF 27 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 08 0A 0C 0E 10 12 14 16 18 1A 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 0E 0C 0A 08 06 05 04 02 00 1D 1E 1F + 20 22 24 28 29 2A 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 84 01]; +}; diff --git a/rk356x/rp-lcd-mipi0-5-720-1280.dtsi b/rk356x/rp-lcd-mipi0-5-720-1280.dtsi new file mode 100755 index 0000000..5877a3a --- /dev/null +++ b/rk356x/rp-lcd-mipi0-5-720-1280.dtsi @@ -0,0 +1,420 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; +// rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <2>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 02 FE 01 + 39 00 02 24 00 + 39 00 02 25 53 + 39 00 02 26 00 + 39 00 02 27 0A + 39 00 02 29 0A + 39 00 02 2B E5 + 39 00 02 16 52 + 39 00 02 2F 54 + 39 00 02 34 59 + 39 00 02 1B 50 + 39 00 02 12 02 +// 39 00 02 1B 20 +// 39 00 02 12 08 + 39 00 02 1A 06 + 39 00 02 46 5F + 39 00 02 52 70 + 39 00 02 53 00 + 39 00 02 54 70 + 39 00 02 55 00 + 39 00 02 5F 11 + 39 00 02 FE 03 + 39 00 02 00 05 + 39 00 02 01 16 + 39 00 02 02 0B + 39 00 02 03 0F + 39 00 02 04 7D + 39 00 02 05 00 + 39 00 02 06 50 + 39 00 02 07 05 + 39 00 02 08 16 + 39 00 02 09 0D + 39 00 02 0A 11 + 39 00 02 0B 7D + 39 00 02 0C 00 + 39 00 02 0D 50 + 39 00 02 0E 07 + 39 00 02 0F 08 + 39 00 02 10 01 + 39 00 02 11 02 + 39 00 02 12 00 + 39 00 02 13 7D + 39 00 02 14 00 + 39 00 02 15 85 + 39 00 02 16 08 + 39 00 02 17 03 + 39 00 02 18 04 + 39 00 02 19 05 + 39 00 02 1A 06 + 39 00 02 1B 00 + 39 00 02 1C 7D + 39 00 02 1D 00 + 39 00 02 1E 85 + 39 00 02 1F 08 + 39 00 02 20 00 + 39 00 02 21 00 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 00 + 39 00 02 29 00 + 39 00 02 2A 07 + 39 00 02 2B 08 + 39 00 02 2D 01 + 39 00 02 2F 02 + 39 00 02 30 00 + 39 00 02 31 40 + 39 00 02 32 05 + 39 00 02 33 08 + 39 00 02 34 54 + 39 00 02 35 7D + 39 00 02 36 00 + 39 00 02 37 03 + 39 00 02 38 04 + 39 00 02 39 05 + 39 00 02 3A 06 + 39 00 02 3B 00 + 39 00 02 3D 40 + 39 00 02 3F 05 + 39 00 02 40 08 + 39 00 02 41 54 + 39 00 02 42 7D + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 45 00 + 39 00 02 46 00 + 39 00 02 47 00 + 39 00 02 48 00 + 39 00 02 49 00 + 39 00 02 4A 00 + 39 00 02 4B 00 + 39 00 02 4C 00 + 39 00 02 4D 00 + 39 00 02 4E 00 + 39 00 02 4F 00 + 39 00 02 50 00 + 39 00 02 51 00 + 39 00 02 52 00 + 39 00 02 53 00 + 39 00 02 54 00 + 39 00 02 55 00 + 39 00 02 56 00 + 39 00 02 58 00 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 00 + 39 00 02 5C 00 + 39 00 02 5D 00 + 39 00 02 5E 00 + 39 00 02 5F 00 + 39 00 02 60 00 + 39 00 02 61 00 + 39 00 02 62 00 + 39 00 02 63 00 + 39 00 02 64 00 + 39 00 02 65 00 + 39 00 02 66 00 + 39 00 02 67 00 + 39 00 02 68 00 + 39 00 02 69 00 + 39 00 02 6A 00 + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 20 + 39 00 02 73 00 + 39 00 02 74 08 + 39 00 02 75 08 + 39 00 02 76 08 + 39 00 02 77 08 + 39 00 02 78 08 + 39 00 02 79 08 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 00 + 39 00 02 7E BF + 39 00 02 7F 3F + 39 00 02 80 3F + 39 00 02 81 3F + 39 00 02 82 3F + 39 00 02 83 3F + 39 00 02 84 3F + 39 00 02 85 02 + 39 00 02 86 06 + 39 00 02 87 3F + 39 00 02 88 14 + 39 00 02 89 10 + 39 00 02 8A 16 + 39 00 02 8B 12 + 39 00 02 8C 08 + 39 00 02 8D 0C + 39 00 02 8E 0A + 39 00 02 8F 0E + 39 00 02 90 00 + 39 00 02 91 04 + 39 00 02 92 3F + 39 00 02 93 3F + 39 00 02 94 3F + 39 00 02 95 3F + 39 00 02 96 05 + 39 00 02 97 01 + 39 00 02 98 0F + 39 00 02 99 0B + 39 00 02 9A 0D + 39 00 02 9B 09 + 39 00 02 9C 13 + 39 00 02 9D 17 + 39 00 02 9E 11 + 39 00 02 9F 15 + 39 00 02 A0 3F + 39 00 02 A2 07 + 39 00 02 A3 03 + 39 00 02 A4 3F + 39 00 02 A5 3F + 39 00 02 A6 3F + 39 00 02 A7 3F + 39 00 02 A9 3F + 39 00 02 AA 3F + 39 00 02 AB 3F + 39 00 02 AC 3F + 39 00 02 AD 3F + 39 00 02 AE 3F + 39 00 02 AF 3F + 39 00 02 B0 3F + 39 00 02 B1 3F + 39 00 02 B2 3F + 39 00 02 B3 05 + 39 00 02 B4 01 + 39 00 02 B5 3F + 39 00 02 B6 17 + 39 00 02 B7 13 + 39 00 02 B8 15 + 39 00 02 B9 11 + 39 00 02 BA 0F + 39 00 02 BB 0B + 39 00 02 BC 0D + 39 00 02 BD 09 + 39 00 02 BE 07 + 39 00 02 BF 03 + 39 00 02 C0 3F + 39 00 02 C1 3F + 39 00 02 C2 3F + 39 00 02 C3 3F + 39 00 02 C4 02 + 39 00 02 C5 06 + 39 00 02 C6 08 + 39 00 02 C7 0C + 39 00 02 C8 0A + 39 00 02 C9 0E + 39 00 02 CA 10 + 39 00 02 CB 14 + 39 00 02 CC 12 + 39 00 02 CD 16 + 39 00 02 CE 3F + 39 00 02 CF 00 + 39 00 02 D0 04 + 39 00 02 D1 3F + 39 00 02 D2 3F + 39 00 02 D3 3F + 39 00 02 D4 3F + 39 00 02 D5 3F + 39 00 02 D6 3F + 39 00 02 D7 3F + 39 00 02 DC 02 + 39 00 02 DE 12 + 39 00 02 FE 0E + 39 00 02 01 75 + 39 00 02 FE 04 + 39 00 02 60 00 + 39 00 02 61 08 + 39 00 02 62 0E + 39 00 02 63 0D + 39 00 02 64 05 + 39 00 02 65 10 + 39 00 02 66 0E + 39 00 02 67 0A + 39 00 02 68 16 + 39 00 02 69 0C + 39 00 02 6A 10 + 39 00 02 6B 07 + 39 00 02 6C 0E + 39 00 02 6D 13 + 39 00 02 6E 0C + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 08 + 39 00 02 72 0E + 39 00 02 73 0D + 39 00 02 74 05 + 39 00 02 75 10 + 39 00 02 76 0E + 39 00 02 77 0A + 39 00 02 78 16 + 39 00 02 79 0C + 39 00 02 7A 10 + 39 00 02 7B 07 + 39 00 02 7C 0E + 39 00 02 7D 13 + 39 00 02 7E 0C + 39 78 02 7F 00 + + 39 00 02 FE 00 + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <30>; + hfront-porch = <64>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 D0 02 00 05 05 35 01 01 08 1E 0F 5A 3C + 03 05 00 00 00 00 11 11 00 19 1B 1E 14 89 + 29 0A 41 43 D3 07 00 00 00 9A 02 11 00 01 + 05 00 00 00 00 09 11 00 00 36 4A 94 45 00 + 00 00 00 00 94 37 00 8B 3B 00 83 3F 00 7C + 43 00 76 47 00 76 10 30 48 00 F0 4A 3A FF + FF 27 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 08 0A 0C 0E 10 12 14 16 18 1A 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 0E 0C 0A 08 06 05 04 02 00 1D 1E 1F + 20 22 24 28 29 2A 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 84 01]; +}; diff --git a/rk356x/rp-lcd-mipi0-5.5-1080-1920.dtsi b/rk356x/rp-lcd-mipi0-5.5-1080-1920.dtsi new file mode 100755 index 0000000..20f9ff6 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-5.5-1080-1920.dtsi @@ -0,0 +1,162 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + +&dsi0 { + status = "okay"; + // rockchip,lane-rate = <480>; + dsi0_panel:panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 15 00 02 FE 00 + 15 00 02 C2 08 + 15 00 02 35 00 + 15 00 02 53 20 + 15 00 02 51 FF + + 05 78 01 01 //add for reboot init fail + + 05 78 01 29 + 05 78 01 11 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0:timing0 { + clock-frequency = <138000000>; + hactive = <1080>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <36>; + vback-porch = <6>; + vfront-porch = <6>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi:endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel:endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1080>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 47 38 04 80 07 0A 05 00 + 01 08 28 05 50 32 03 05 + 00 00 00 00 00 00 00 00 + 00 00 00 8B 2B 0D 17 15 + 31 0D 00 00 00 9A 03 2D + 00 00 00 00 00 03 64 32 + 00 00 00 0F 2C 94 C5 02 + 07 00 00 04 9E 10 00 82 + 14 00 6B 19 00 57 20 00 + 4A 27 00 4A 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 FF 00 00 + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 0F 10 12 + 13 26 24 22 21 20 1F 1E + 1D 1C 18 16 FF FF FF FF + 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 + 8C 01 + ]; +}; diff --git a/rk356x/rp-lcd-mipi0-5.5-720-1280-v2.dtsi b/rk356x/rp-lcd-mipi0-5.5-720-1280-v2.dtsi new file mode 100755 index 0000000..4fc6150 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-5.5-720-1280-v2.dtsi @@ -0,0 +1,145 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + 39 00 05 B8 26 22 20 03 + 39 00 04 BF 02 11 00 + 39 00 0B B3 0C 10 0A 50 03 FF 00 00 00 00 + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + 39 00 02 BC 46 + 39 00 02 CC 0B + 39 00 02 B4 80 + 39 00 04 B2 C8 12 30 + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 00 C0 10 + 39 00 0D C1 53 00 1E 1E 77 C1 FF FF AF AF 7F 7F + 39 00 03 B5 07 07 + 39 00 03 B6 70 70 + 39 00 07 C6 00 00 FF FF 01 FF + 39 00 40 E9 C2 10 05 04 FE 02 81 12 31 45 3F 83 12 91 3B 2A 08 05 00 00 00 00 08 05 00 00 00 00 FF 02 46 02 48 68 88 88 88 80 88 FF 13 57 13 58 78 88 88 88 81 88 00 00 00 00 00 12 B1 3B 00 00 00 00 00 + 39 00 3E EA 00 1A 00 00 00 00 00 00 00 00 00 00 FF 31 75 31 18 78 88 88 88 85 88 FF 20 64 20 08 68 88 88 88 84 88 20 10 00 00 54 00 00 00 00 00 00 00 C0 00 00 0C 00 00 00 00 30 02 A1 00 00 00 00 + 39 00 23 E0 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A 00 05 07 1A 39 3F 33 2C 06 0B 0D 11 13 12 14 10 1A + 05 ff 01 11 + 05 78 01 29 + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <42>; + hfront-porch = <44>; + vback-porch = <10>; + vfront-porch = <14>; + hsync-len = <2>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>1x { + status = "okay"; + compatible = "goodix,gt1x"; + reg = <0x5d>; + + /** + * goodix,rst-gpio = <>; + * goodix,irq-gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + +}; diff --git a/rk356x/rp-lcd-mipi0-5.5-720-1280.dtsi b/rk356x/rp-lcd-mipi0-5.5-720-1280.dtsi new file mode 100755 index 0000000..9623697 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-5.5-720-1280.dtsi @@ -0,0 +1,393 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <20>; + init-delay-ms = <20>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 02 FE 01 + 39 00 02 24 C0 + 39 00 02 25 53 + 39 00 02 26 00 + 39 00 02 2B E5 + 39 00 02 27 0A + 39 00 02 29 0A + 39 00 02 16 52 + 39 00 02 2F 53 + 39 00 02 34 5A + 39 00 02 1B 00 + 39 00 02 12 0A + 39 00 02 1A 06 + 39 00 02 46 4F + 39 00 02 52 A0 + 39 00 02 53 00 + 39 00 02 54 A0 + 39 00 02 55 00 + 39 00 02 FE 03 + 39 00 02 00 05 + 39 00 02 01 16 + 39 00 02 02 0B + 39 00 02 03 0F + 39 00 02 04 7D + 39 00 02 05 00 + 39 00 02 06 50 + 39 00 02 07 05 + 39 00 02 08 16 + 39 00 02 09 0D + 39 00 02 0A 11 + 39 00 02 0B 7D + 39 00 02 0C 00 + 39 00 02 0D 50 + 39 00 02 0E 07 + 39 00 02 0F 08 + 39 00 02 10 01 + 39 00 02 11 02 + 39 00 02 12 00 + 39 00 02 13 7D + 39 00 02 14 00 + 39 00 02 15 85 + 39 00 02 16 08 + 39 00 02 17 03 + 39 00 02 18 04 + 39 00 02 19 05 + 39 00 02 1A 06 + 39 00 02 1B 00 + 39 00 02 1C 7D + 39 00 02 1D 00 + 39 00 02 1E 85 + 39 00 02 1F 08 + 39 00 02 20 00 + 39 00 02 21 00 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 00 + 39 00 02 29 00 + 39 00 02 2A 07 + 39 00 02 2B 08 + 39 00 02 2D 01 + 39 00 02 2F 02 + 39 00 02 30 00 + 39 00 02 31 40 + 39 00 02 32 05 + 39 00 02 33 08 + 39 00 02 34 54 + 39 00 02 35 7D + 39 00 02 36 00 + 39 00 02 37 03 + 39 00 02 38 04 + 39 00 02 39 05 + 39 00 02 3A 06 + 39 00 02 3B 00 + 39 00 02 3D 40 + 39 00 02 3F 05 + 39 00 02 40 08 + 39 00 02 41 54 + 39 00 02 42 7D + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 45 00 + 39 00 02 46 00 + 39 00 02 47 00 + 39 00 02 48 00 + 39 00 02 49 00 + 39 00 02 4A 00 + 39 00 02 4B 00 + 39 00 02 4C 00 + 39 00 02 4D 00 + 39 00 02 4E 00 + 39 00 02 4F 00 + 39 00 02 50 00 + 39 00 02 51 00 + 39 00 02 52 00 + 39 00 02 53 00 + 39 00 02 54 00 + 39 00 02 55 00 + 39 00 02 56 00 + 39 00 02 58 00 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 00 + 39 00 02 5C 00 + 39 00 02 5D 00 + 39 00 02 5E 00 + 39 00 02 5F 00 + 39 00 02 60 00 + 39 00 02 61 00 + 39 00 02 62 00 + 39 00 02 63 00 + 39 00 02 64 00 + 39 00 02 65 00 + 39 00 02 66 00 + 39 00 02 67 00 + 39 00 02 68 00 + 39 00 02 69 00 + 39 00 02 6A 00 + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 20 + 39 00 02 73 00 + 39 00 02 74 08 + 39 00 02 75 08 + 39 00 02 76 08 + 39 00 02 77 08 + 39 00 02 78 08 + 39 00 02 79 08 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 00 + 39 00 02 7E BF + 39 00 02 7F 02 + 39 00 02 80 06 + 39 00 02 81 14 + 39 00 02 82 10 + 39 00 02 83 16 + 39 00 02 84 12 + 39 00 02 85 08 + 39 00 02 86 3F + 39 00 02 87 3F + 39 00 02 88 3F + 39 00 02 89 3F + 39 00 02 8A 3F + 39 00 02 8B 0C + 39 00 02 8C 0A + 39 00 02 8D 0E + 39 00 02 8E 3F + 39 00 02 8F 3F + 39 00 02 90 00 + 39 00 02 91 04 + 39 00 02 92 3F + 39 00 02 93 3F + 39 00 02 94 3F + 39 00 02 95 3F + 39 00 02 96 05 + 39 00 02 97 01 + 39 00 02 98 3F + 39 00 02 99 3F + 39 00 02 9A 0F + 39 00 02 9B 0B + 39 00 02 9C 0D + 39 00 02 9D 3F + 39 00 02 9E 3F + 39 00 02 9F 3F + 39 00 02 A0 3F + 39 00 02 A2 3F + 39 00 02 A3 09 + 39 00 02 A4 13 + 39 00 02 A5 17 + 39 00 02 A6 11 + 39 00 02 A7 15 + 39 00 02 A9 07 + 39 00 02 AA 03 + 39 00 02 AB 3F + 39 00 02 AC 3F + 39 00 02 AD 05 + 39 00 02 AE 01 + 39 00 02 AF 17 + 39 00 02 B0 13 + 39 00 02 B1 15 + 39 00 02 B2 11 + 39 00 02 B3 0F + 39 00 02 B4 3F + 39 00 02 B5 3F + 39 00 02 B6 3F + 39 00 02 B7 3F + 39 00 02 B8 3F + 39 00 02 B9 0B + 39 00 02 BA 0D + 39 00 02 BB 09 + 39 00 02 BC 3F + 39 00 02 BD 3F + 39 00 02 BE 07 + 39 00 02 BF 03 + 39 00 02 C0 3F + 39 00 02 C1 3F + 39 00 02 C2 3F + 39 00 02 C3 3F + 39 00 02 C4 02 + 39 00 02 C5 06 + 39 00 02 C6 3F + 39 00 02 C7 3F + 39 00 02 C8 08 + 39 00 02 C9 0C + 39 00 02 CA 0A + 39 00 02 CB 3F + 39 00 02 CC 3F + 39 00 02 CD 3F + 39 00 02 CE 3F + 39 00 02 CF 3F + 39 00 02 D0 0E + 39 00 02 D1 10 + 39 00 02 D2 14 + 39 00 02 D3 12 + 39 00 02 D4 16 + 39 00 02 D5 00 + 39 00 02 D6 04 + 39 00 02 D7 3F + 39 00 02 DC 02 + 39 00 02 DE 12 + 39 00 02 FE 0E + 39 00 02 01 75 + 39 00 02 54 01 + 39 00 02 FE 04 + 39 00 02 60 00 + 39 00 02 61 0C + 39 00 02 62 12 + 39 00 02 63 0E + 39 00 02 64 06 + 39 00 02 65 12 + 39 00 02 66 0E + 39 00 02 67 0B + 39 00 02 68 15 + 39 00 02 69 0B + 39 00 02 6A 10 + 39 00 02 6B 07 + 39 00 02 6C 0F + 39 00 02 6D 12 + 39 00 02 6E 0C + 39 00 02 6F 00 + 39 00 02 70 00 + 39 00 02 71 0C + 39 00 02 72 12 + 39 00 02 73 0E + 39 00 02 74 06 + 39 00 02 75 12 + 39 00 02 76 0E + 39 00 02 77 0B + 39 00 02 78 15 + 39 00 02 79 0B + 39 00 02 7A 10 + 39 00 02 7B 07 + 39 00 02 7C 0F + 39 00 02 7D 12 + 39 00 02 7E 0C + 39 00 02 7F 00 + 39 00 02 FE 00 + 39 00 02 58 AD + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <64000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <32>; + hfront-porch = <32>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>1x { + status = "okay"; + compatible = "goodix,gt1x"; + reg = <0x5d>; + + /** + * goodix,rst-gpio = <>; + * goodix,irq-gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + +}; diff --git a/rk356x/rp-lcd-mipi0-7-1024-600.dtsi b/rk356x/rp-lcd-mipi0-7-1024-600.dtsi new file mode 100755 index 0000000..ab7fd2a --- /dev/null +++ b/rk356x/rp-lcd-mipi0-7-1024-600.dtsi @@ -0,0 +1,176 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ //old touch + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + goodix,cfg-group5 = [ //new touch + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; +}; diff --git a/rk356x/rp-lcd-mipi0-7-1200-1920.dtsi b/rk356x/rp-lcd-mipi0-7-1200-1920.dtsi new file mode 100755 index 0000000..bf8c67a --- /dev/null +++ b/rk356x/rp-lcd-mipi0-7-1200-1920.dtsi @@ -0,0 +1,232 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <900>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 14 42 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 de 03 00 + 39 60 03 c9 02 23 + + 39 00 02 b0 00 + 39 00 06 14 08 b0 00 22 00 + 39 30 02 b4 0c + 39 40 03 b6 3a d3 + 39 50 02 51 e6 + 39 30 02 53 2c + + 05 78 01 29 + 05 78 01 11 + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 8c 83 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 c9 02 23 + 39 60 03 ca 01 23 + 39 10 03 cb 10 05 + 39 10 03 cc 05 10 + 39 10 03 d0 00 00 + + + 39 10 03 b6 03 00 + 39 10 03 de 03 00 + 39 10 03 d6 05 00 + 39 60 03 b7 4b 02 + + 05 00 01 2c + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + goodix,cfg-group0 = [ //sensor id 0 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + + + goodix,cfg-group2 = [ //sensor id 2 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + goodix,cfg-group5 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01 + ]; +}; + diff --git a/rk356x/rp-lcd-mipi0-7-720-1280.dtsi b/rk356x/rp-lcd-mipi0-7-720-1280.dtsi new file mode 100755 index 0000000..dc69f13 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-7-720-1280.dtsi @@ -0,0 +1,410 @@ +#include "rp-lcd-hdmi.dtsi" + + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 75 03 + + 39 00 02 E0 01 + // 39 00 02 4A 30 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 0A 07 + 39 00 02 0C 74 + 39 00 02 17 00 + 39 00 02 18 D7 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B D7 + 39 00 02 1C 01 + 39 00 02 1F 74 + 39 00 02 20 19 + 39 00 02 21 19 + 39 00 02 22 0E + 39 00 02 27 43 + + 39 00 02 37 09 + 39 00 02 38 04 + 39 00 02 39 08 + 39 00 02 3A 18 + 39 00 02 3B 18 + 39 00 02 3C 72 + 39 00 02 3E FF + 39 00 02 3E FF + 39 00 02 3F FF + 39 00 02 40 04 + 39 00 02 41 A0 + 39 00 02 43 08 + 39 00 02 44 07 + 39 00 02 45 30 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 65 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 0F + + 39 00 02 5D 7C + 39 00 02 5E 5F + 39 00 02 5F 4D + 39 00 02 60 3F + 39 00 02 61 39 + 39 00 02 62 29 + 39 00 02 63 2B + 39 00 02 64 12 + 39 00 02 65 28 + 39 00 02 66 24 + 39 00 02 67 22 + 39 00 02 68 3E + 39 00 02 69 2C + 39 00 02 6A 33 + 39 00 02 6B 26 + 39 00 02 6C 23 + 39 00 02 6D 18 + 39 00 02 6E 09 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 5F + 39 00 02 72 4D + 39 00 02 73 3F + 39 00 02 74 39 + 39 00 02 75 29 + 39 00 02 76 2B + 39 00 02 77 12 + 39 00 02 78 28 + 39 00 02 79 24 + 39 00 02 7A 22 + 39 00 02 7B 3E + 39 00 02 7C 2C + 39 00 02 7D 33 + 39 00 02 7E 26 + 39 00 02 7F 23 + 39 00 02 80 18 + 39 00 02 81 09 + 39 00 02 82 00 + + 39 00 02 E0 02 + 39 00 02 00 37 + 39 00 02 01 17 + 39 00 02 02 0A + 39 00 02 03 06 + 39 00 02 04 08 + 39 00 02 05 04 + 39 00 02 06 00 + 39 00 02 07 1F + 39 00 02 08 1F + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 1F + 39 00 02 10 3F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1E + 39 00 02 14 10 + 39 00 02 15 1F + + 39 00 02 16 37 + 39 00 02 17 17 + 39 00 02 18 0B + 39 00 02 19 07 + 39 00 02 1A 09 + 39 00 02 1B 05 + 39 00 02 1C 01 + 39 00 02 1D 1F + 39 00 02 1E 1F + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 1F + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1E + 39 00 02 2A 11 + 39 00 02 2B 1F + 39 00 02 2C 37 + 39 00 02 2D 17 + 39 00 02 2E 05 + 39 00 02 2F 09 + 39 00 02 30 07 + 39 00 02 31 0B + 39 00 02 32 11 + 39 00 02 33 1F + 39 00 02 34 1F + 39 00 02 35 1F + 39 00 02 36 1F + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 3F + 39 00 02 3D 1F + 39 00 02 3E 1E + 39 00 02 3F 1F + 39 00 02 40 01 + + 39 00 02 41 1F + 39 00 02 42 38 + 39 00 02 43 18 + 39 00 02 44 04 + 39 00 02 45 08 + 39 00 02 46 06 + 39 00 02 47 0A + 39 00 02 48 10 + 39 00 02 49 1F + 39 00 02 4A 1F + 39 00 02 4B 1F + 39 00 02 4C 1F + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1E + 39 00 02 55 1F + 39 00 02 56 00 + 39 00 02 57 1F + 39 00 02 58 10 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 10 + 39 00 02 5C 01 + 39 00 02 5D 50 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 30 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 06 + 39 00 02 64 6A + 39 00 02 65 55 + 39 00 02 66 08 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 08 + 39 00 02 6A 6E + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 80 + 39 00 02 76 00 + 39 00 02 77 0D + 39 00 02 78 18 + 39 00 02 79 00 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 04 + 39 00 02 04 01 + 39 00 02 0E 38 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E6 02 + // 39 00 02 36 00 + 39 C8 02 11 00 + 39 C8 02 29 00 + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <70000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <34>; + hfront-porch = <34>; + vback-porch = <6>; + vfront-porch = <20>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 57 58 02 00 04 05 35 00 01 08 32 0F + 5A 32 03 05 00 00 00 00 02 00 00 18 + 1A 1E 14 8A 2A 0C 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 2B FF 7F + 19 46 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 40 30 FF + FF 27 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 24 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0F 10 12 13 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 81 01 + ]; + goodix,cfg-group2 = [ + 5A 58 02 00 04 05 35 00 01 08 + 32 0F 5A 32 03 05 00 00 00 00 + 02 00 00 18 1A 1E 14 8A 2A 0C + 55 57 B5 06 00 00 00 20 33 1C + 14 01 00 0F 00 2B FF 7F 19 46 + 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 + 61 00 6F 70 00 6F 00 00 00 00 + F0 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 08 0A 0F 10 + 12 13 24 22 21 20 1F 1E 1D 1C + 18 16 FF FF FF FF FF FF 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 5E 01 + ]; + +}; diff --git a/rk356x/rp-lcd-mipi0-8-1200-1920-v2.dtsi b/rk356x/rp-lcd-mipi0-8-1200-1920-v2.dtsi new file mode 100755 index 0000000..3c9ed5a --- /dev/null +++ b/rk356x/rp-lcd-mipi0-8-1200-1920-v2.dtsi @@ -0,0 +1,157 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + // reset-delay-ms = <60>; + // init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + // unprepare-delay-ms = <60>; + // disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + //MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + + ]; +}; + diff --git a/rk356x/rp-lcd-mipi0-8-1200-1920.dtsi b/rk356x/rp-lcd-mipi0-8-1200-1920.dtsi new file mode 100755 index 0000000..caa3339 --- /dev/null +++ b/rk356x/rp-lcd-mipi0-8-1200-1920.dtsi @@ -0,0 +1,174 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <940>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <35>; + hsync-len = <1>; + vsync-len = <1>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + + goodix,cfg-group0 = [ + 5E B0 04 80 07 05 05 00 01 0F 28 05 + 50 32 03 05 00 00 00 00 00 00 00 00 + 00 00 00 8C 2C 0E 52 54 31 0D 00 00 + 01 80 04 1C 00 00 00 00 00 03 64 32 + 00 00 00 52 66 94 C5 02 07 00 00 04 + 83 53 00 82 57 00 80 5B 00 7F 5F 00 + 7E 63 00 7E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 08 0A 0C 0F 10 12 13 14 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 22 01 + ]; + + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + + ]; +}; + diff --git a/rk356x/rp-lcd-mipi0-8-800-1280-v2.dtsi b/rk356x/rp-lcd-mipi0-8-800-1280-v2.dtsi new file mode 100755 index 0000000..9a7e37e --- /dev/null +++ b/rk356x/rp-lcd-mipi0-8-800-1280-v2.dtsi @@ -0,0 +1,370 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <510>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 73 + 39 00 02 04 D7 + 39 00 02 05 00 + 39 00 02 06 08 + 39 00 02 07 11 + 39 00 02 08 00 + 39 00 02 09 3F + 39 00 02 0a 00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F + 39 00 02 10 3F + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 00 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 44 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + 39 00 02 5e 00 + 39 00 02 5f 0C + 39 00 02 60 0C + 39 00 02 61 0F + 39 00 02 62 0F + 39 00 02 63 0E + 39 00 02 64 0E + 39 00 02 65 06 + 39 00 02 66 07 + 39 00 02 67 0D + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 0D + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 05 + 39 00 02 72 01 + 39 00 02 73 08 + 39 00 02 74 00 + 39 00 02 75 0C + 39 00 02 76 0C + 39 00 02 77 0F + 39 00 02 78 0F + 39 00 02 79 0E + 39 00 02 7a 0E + 39 00 02 7b 06 + 39 00 02 7c 07 + 39 00 02 7d 0D + 39 00 02 7e 02 + 39 00 02 7f 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 0D + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 05 + 39 00 02 88 01 + 39 00 02 89 08 + 39 00 02 8A 00 + + 39 00 04 FF 98 81 04 + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 7B + 39 00 02 55 40 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 27 + 39 00 02 62 20 + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 20 + 39 00 02 A3 13 + 39 00 02 A4 14 + 39 00 02 A5 27 + 39 00 02 A6 1D + 39 00 02 A7 1F + 39 00 02 A8 7C + 39 00 02 A9 1D + 39 00 02 AA 2A + 39 00 02 AB 6B + 39 00 02 AC 1A + 39 00 02 AD 18 + 39 00 02 AE 4E + 39 00 02 AF 24 + 39 00 02 B0 2A + 39 00 02 B1 4D + 39 00 02 B2 5B + 39 00 02 B3 23 + 39 00 02 C0 00 + 39 00 02 C1 13 + 39 00 02 C2 20 + 39 00 02 C3 12 + 39 00 02 C4 15 + 39 00 02 C5 28 + 39 00 02 C6 1C + 39 00 02 C7 1E + 39 00 02 C8 7B + 39 00 02 C9 1E + 39 00 02 CA 29 + 39 00 02 CB 6C + 39 00 02 CC 1A + 39 00 02 CD 19 + 39 00 02 CE 4D + 39 00 02 CF 22 + 39 00 02 D0 2A + 39 00 02 D1 4D + 39 00 02 D2 5B + 39 00 02 D3 23 + 39 00 04 FF 98 81 00 + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <80000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <6>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 + 1E 0F 50 32 03 05 00 00 00 00 + 00 00 04 18 1A 1E 14 8C 2E 0E + 1E 20 EB 04 00 00 00 BA 02 2D + 00 00 00 00 00 03 00 00 00 00 + 00 0F 2D 94 D5 02 07 00 00 04 + E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0C 0F 10 12 13 14 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 CB 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01]; +}; diff --git a/rk356x/rp-lcd-mipi0-8-800-1280-v3.dtsi b/rk356x/rp-lcd-mipi0-8-800-1280-v3.dtsi new file mode 100755 index 0000000..1507ced --- /dev/null +++ b/rk356x/rp-lcd-mipi0-8-800-1280-v3.dtsi @@ -0,0 +1,400 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + + 39 00 04 FF 98 81 03 + + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 57 //54 + 39 00 02 04 D3 //D4 + 39 00 02 05 00 + 39 00 02 06 11 + 39 00 02 07 08 //09 + 39 00 02 08 00 + 39 00 02 09 00 + 39 00 02 0a 3F //00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F //00 + 39 00 02 10 3F //00 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 78 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 //GCH/L + 39 00 02 44 00 + + + 39 00 02 50 00 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + 39 00 02 5e 00 + 39 00 02 5f 0D //FW_CGOUT_L[1] + 39 00 02 60 0D //FW_CGOUT_L[2] + 39 00 02 61 0C //FW_CGOUT_L[3] + 39 00 02 62 0C //FW_CGOUT_L[4] + 39 00 02 63 0F //FW_CGOUT_L[5] + 39 00 02 64 0F //FW_CGOUT_L[6] + 39 00 02 65 0E //FW_CGOUT_L[7] + 39 00 02 66 0E //FW_CGOUT_L[8] + 39 00 02 67 08 //FW_CGOUT_L[9] + 39 00 02 68 02 //FW_CGOUT_L[10] + 39 00 02 69 02 //FW_CGOUT_L[11] + 39 00 02 6a 02 //FW_CGOUT_L[12] + 39 00 02 6b 02 //FW_CGOUT_L[13] + 39 00 02 6c 02 //FW_CGOUT_L[14] + 39 00 02 6d 02 //FW_CGOUT_L[15] + 39 00 02 6e 02 //FW_CGOUT_L[16] + 39 00 02 6f 02 //FW_CGOUT_L[17] + 39 00 02 70 14 //FW_CGOUT_L[18] + 39 00 02 71 15 //FW_CGOUT_L[19] + 39 00 02 72 06 //FW_CGOUT_L[20] + 39 00 02 73 02 //FW_CGOUT_L[21] + 39 00 02 74 02 //FW_CGOUT_L[22] + + 39 00 02 75 0D //BW_CGOUT_L[1] + 39 00 02 76 0D //BW_CGOUT_L[2] + 39 00 02 77 0C //BW_CGOUT_L[3] + 39 00 02 78 0C //BW_CGOUT_L[4] + 39 00 02 79 0F //BW_CGOUT_L[5] + 39 00 02 7a 0F //BW_CGOUT_L[6] + 39 00 02 7b 0E //BW_CGOUT_L[7] + 39 00 02 7c 0E //BW_CGOUT_L[8] + 39 00 02 7d 08 //BW_CGOUT_L[9] + 39 00 02 7e 02 //BW_CGOUT_L[10] + 39 00 02 7f 02 //BW_CGOUT_L[11] + 39 00 02 80 02 //BW_CGOUT_L[12] + 39 00 02 81 02 //BW_CGOUT_L[13] + 39 00 02 82 02 //BW_CGOUT_L[14] + 39 00 02 83 02 //BW_CGOUT_L[15] + 39 00 02 84 02 //BW_CGOUT_L[16] + 39 00 02 85 02 //BW_CGOUT_L[17] + 39 00 02 86 14 //BW_CGOUT_L[18] + 39 00 02 87 15 //BW_CGOUT_L[19] + 39 00 02 88 06 //BW_CGOUT_L[20] + 39 00 02 89 02 //BW_CGOUT_L[21] + 39 00 02 8A 02 //BW_CGOUT_L[22] + + + + 39 00 04 FF 98 81 04 + + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 87 + 39 00 02 55 84 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 10 + 39 00 02 62 00 + + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 1F + 39 00 02 A3 12 + 39 00 02 A4 16 + 39 00 02 A5 29 + 39 00 02 A6 1E + 39 00 02 A7 1F + 39 00 02 A8 7E + 39 00 02 A9 1B + 39 00 02 AA 28 + 39 00 02 AB 6D + 39 00 02 AC 19 + 39 00 02 AD 18 + 39 00 02 AE 4C + 39 00 02 AF 1E + 39 00 02 B0 23 + 39 00 02 B1 52 + 39 00 02 B2 6D + 39 00 02 B3 3F + + 39 00 02 C0 00 + 39 00 02 C1 12 + 39 00 02 C2 20 + 39 00 02 C3 10 + 39 00 02 C4 13 + 39 00 02 C5 27 + 39 00 02 C6 1B + 39 00 02 C7 1D + 39 00 02 C8 75 + 39 00 02 C9 1F + 39 00 02 CA 28 + 39 00 02 CB 68 + 39 00 02 CC 1A + 39 00 02 CD 18 + 39 00 02 CE 4D + 39 00 02 CF 25 + 39 00 02 D0 2E + 39 00 02 D1 53 + 39 00 02 D2 60 + 39 00 02 D3 3F + + 39 00 04 FF 98 81 00 + 39 00 02 35 00 + 05 80 01 11 + 05 20 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <70>; + hfront-porch = <70>; + vback-porch = <22>; + vfront-porch = <16>; + hsync-len = <20>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + + /** jc */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01 + ]; + +}; diff --git a/rk356x/rp-lcd-mipi0-8-800-1280.dtsi b/rk356x/rp-lcd-mipi0-8-800-1280.dtsi new file mode 100755 index 0000000..80eb99b --- /dev/null +++ b/rk356x/rp-lcd-mipi0-8-800-1280.dtsi @@ -0,0 +1,399 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <510>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 15 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 01 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 17 00 + 39 00 02 18 B1 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B B1 + 39 00 02 1C 01 + 39 00 02 1F 3E + 39 00 02 20 2D + 39 00 02 21 2D + 39 00 02 22 0E + 39 00 02 37 19 + 39 00 02 38 05 + 39 00 02 39 08 + 39 00 02 3A 12 + 39 00 02 3C 78 + 39 00 02 3E 80 + 39 00 02 3F 80 + 39 00 02 40 06 + 39 00 02 41 A0 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 69 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 19 + 39 00 02 5D 7C + 39 00 02 5E 65 + 39 00 02 5F 53 + 39 00 02 60 48 + 39 00 02 61 43 + 39 00 02 62 35 + 39 00 02 63 39 + 39 00 02 64 23 + 39 00 02 65 3D + 39 00 02 66 3C + 39 00 02 67 3D + 39 00 02 68 5A + 39 00 02 69 46 + 39 00 02 6A 57 + 39 00 02 6B 4B + 39 00 02 6C 49 + 39 00 02 6D 2F + 39 00 02 6E 03 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 65 + 39 00 02 72 53 + 39 00 02 73 48 + 39 00 02 74 43 + 39 00 02 75 35 + 39 00 02 76 39 + 39 00 02 77 23 + 39 00 02 78 3D + 39 00 02 79 3C + 39 00 02 7A 3D + 39 00 02 7B 5A + 39 00 02 7C 46 + 39 00 02 7D 57 + 39 00 02 7E 4B + 39 00 02 7F 49 + 39 00 02 80 2F + 39 00 02 81 03 + 39 00 02 82 00 + 39 00 02 E0 02 + 39 00 02 00 47 + 39 00 02 01 47 + 39 00 02 02 45 + 39 00 02 03 45 + 39 00 02 04 4B + 39 00 02 05 4B + 39 00 02 06 49 + 39 00 02 07 49 + 39 00 02 08 41 + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 43 + 39 00 02 10 1F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1F + 39 00 02 14 1F + 39 00 02 15 1F + 39 00 02 16 46 + 39 00 02 17 46 + 39 00 02 18 44 + 39 00 02 19 44 + 39 00 02 1A 4A + 39 00 02 1B 4A + 39 00 02 1C 48 + 39 00 02 1D 48 + 39 00 02 1E 40 + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 42 + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1F + 39 00 02 2A 1F + 39 00 02 2B 1F + 39 00 02 2C 11 + 39 00 02 2D 0F + 39 00 02 2E 0D + 39 00 02 2F 0B + 39 00 02 30 09 + 39 00 02 31 07 + 39 00 02 32 05 + 39 00 02 33 18 + 39 00 02 34 17 + 39 00 02 35 1F + 39 00 02 36 01 + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 1F + 39 00 02 3D 1F + 39 00 02 3E 1F + 39 00 02 3F 13 + 39 00 02 40 1F + 39 00 02 41 1F + 39 00 02 42 10 + 39 00 02 43 0E + 39 00 02 44 0C + 39 00 02 45 0A + 39 00 02 46 08 + 39 00 02 47 06 + 39 00 02 48 04 + 39 00 02 49 18 + 39 00 02 4A 17 + 39 00 02 4B 1F + 39 00 02 4C 00 + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1F + 39 00 02 55 12 + 39 00 02 56 1F + 39 00 02 57 1F + 39 00 02 58 40 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 30 + 39 00 02 5C 03 + 39 00 02 5D 30 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 00 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 03 + 39 00 02 64 6B + 39 00 02 65 00 + 39 00 02 66 00 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 06 + 39 00 02 6A 6B + 39 00 02 6B 08 + 39 00 02 6C 00 + 39 00 02 6D 04 + 39 00 02 6E 04 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 07 + 39 00 02 76 00 + 39 00 02 77 5D + 39 00 02 78 17 + 39 00 02 79 1F + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 01 + 39 00 02 0E 01 + 39 00 02 E0 03 + 39 00 02 98 2F + 39 00 02 E0 04 + 39 00 02 09 10 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E7 02 + + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <90000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <96>; + hfront-porch = <96>; + vback-porch = <8>; + vfront-porch = <8>; + hsync-len = <6>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 + 1E 0F 50 32 03 05 00 00 00 00 + 00 00 04 18 1A 1E 14 8C 2E 0E + 1E 20 EB 04 00 00 00 BA 02 2D + 00 00 00 00 00 03 00 00 00 00 + 00 0F 2D 94 D5 02 07 00 00 04 + E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0C 0F 10 12 13 14 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 CB 01 + ]; + + goodix,cfg-group5 = [ + 00 20 03 00 05 0A 05 00 01 08 28 08 + 50 32 03 05 00 00 00 00 00 00 00 18 + 1A 1E 14 8C 2C 0E 17 15 31 0D 00 00 + 02 9B 04 1D 00 00 00 00 00 03 64 32 + 00 00 00 11 25 94 C5 02 07 00 00 04 + 60 12 00 5D 15 00 57 19 00 54 1D 00 + 4F 22 00 4F 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 14 13 + 00 02 04 06 08 0A 0C 0F 10 12 FF FF + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 2F 01]; +}; diff --git a/rk356x/rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi b/rk356x/rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi new file mode 100755 index 0000000..4ab4cda --- /dev/null +++ b/rk356x/rp-lcd-mipi0tolvds-gm8775c-10-1024-600-raw.dtsi @@ -0,0 +1,213 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI02LVDS + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <445>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + init-delay-ms = <120>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01 + ]; +}; diff --git a/rk356x/rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi b/rk356x/rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi new file mode 100755 index 0000000..967a9dd --- /dev/null +++ b/rk356x/rp-lcd-mipi0tolvds-gm8775c-1920-1080.dtsi @@ -0,0 +1,157 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI02LVDS +#define RP_DUALLVDS + + + +&dsi0 { + status = "okay"; + // rockchip,lane-rate = <480>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + init-delay-ms = <120>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 80 + 23 08 02 02 38 + 23 08 02 03 47 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 13 + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 63 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 34 + 23 08 02 19 20 + 23 08 02 1A 10 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + + dsi0_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + + +//touch todo. + + + + + + diff --git a/rk356x/rp-lcd-mipi1-10-1920-1200.dtsi b/rk356x/rp-lcd-mipi1-10-1920-1200.dtsi new file mode 100644 index 0000000..3109f8d --- /dev/null +++ b/rk356x/rp-lcd-mipi1-10-1920-1200.dtsi @@ -0,0 +1,141 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <1200>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + // reset-delay-ms = <60>; + // init-delay-ms = <60>; + enable-delay-ms = <160>; + prepare-delay-ms = <200>; + // unprepare-delay-ms = <60>; + // disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE)>; + dsi,format = ; + + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <32>; //60 + hfront-porch = <110>; //16 + vback-porch = <14>; //23 + vfront-porch = <11>; //12 + hsync-len = <1>; //20 + vsync-len = <1>; //3 + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <1>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "okay"; +}; + +&video_phy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp1_out_dsi0>; +}; + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1200>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 55 80 07 B0 04 0A 3D 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 8E 2F 99 17 15 31 + 0D 00 00 02 9B 03 1D 00 00 00 00 + 00 00 00 00 00 00 00 1E 78 94 C5 + 02 08 00 00 00 5B 22 00 4C 2D 00 + 41 3C 00 38 4F 00 32 69 00 32 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 0C + 0D 0E 0F 10 11 14 15 16 17 FF FF + 00 00 00 00 00 00 00 00 00 00 00 + 02 04 06 07 08 0A 0C 0D 0F 10 11 + 12 13 19 1B 1C 1E 1F 20 21 22 23 + 24 25 26 27 28 29 FF FF FF 00 00 + 00 00 00 00 00 00 00 00 6B 01]; +}; diff --git a/rk356x/rp-lcd-mipi1-10-800-1280.dtsi b/rk356x/rp-lcd-mipi1-10-800-1280.dtsi new file mode 100755 index 0000000..a4728d8 --- /dev/null +++ b/rk356x/rp-lcd-mipi1-10-800-1280.dtsi @@ -0,0 +1,406 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI1_USED + + + + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + init-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 15 00 02 E0 00 + 15 00 02 E1 93 + 15 00 02 E2 65 + 15 00 02 E3 F8 + 15 00 02 E0 04 + 15 00 02 2D 03 + 15 00 02 E0 00 + 15 00 02 80 03 + 15 00 02 70 02 + 15 00 02 71 23 + 15 00 02 72 06 + 15 00 02 E0 01 + 15 00 02 00 00 + 15 00 02 01 66 + 15 00 02 03 00 + 15 00 02 04 6D + 15 00 02 17 00 + 15 00 02 18 BF + 15 00 02 19 00 + 15 00 02 1A 00 + 15 00 02 1B BF + 15 00 02 1C 00 + 15 00 02 1F 3E + 15 00 02 20 28 + 15 00 02 21 28 + 15 00 02 22 0E + 15 00 02 37 09 + 15 00 02 38 04 + 15 00 02 39 08 + 15 00 02 3A 12 + 15 00 02 3C 78 + 15 00 02 3D FF + 15 00 02 3E FF + 15 00 02 3F 7F + 15 00 02 40 06 + 15 00 02 41 A0 + 15 00 02 55 0F + 15 00 02 56 01 + 15 00 02 57 69 + 15 00 02 58 0A + 15 00 02 59 0A + 15 00 02 5A 29 + 15 00 02 5B 15 + 15 00 02 5D 7C + 15 00 02 5E 65 + 15 00 02 5F 55 + 15 00 02 60 49 + 15 00 02 61 44 + 15 00 02 62 35 + 15 00 02 63 3A + 15 00 02 64 23 + 15 00 02 65 3D + 15 00 02 66 3C + 15 00 02 67 3D + 15 00 02 68 5D + 15 00 02 69 4D + 15 00 02 6A 56 + 15 00 02 6B 48 + 15 00 02 6C 45 + 15 00 02 6D 38 + 15 00 02 6E 25 + 15 00 02 6F 00 + 15 00 02 70 7C + 15 00 02 71 65 + 15 00 02 72 55 + 15 00 02 73 49 + 15 00 02 74 44 + 15 00 02 75 35 + 15 00 02 76 3A + 15 00 02 77 23 + 15 00 02 78 3D + 15 00 02 79 3C + 15 00 02 7A 3D + 15 00 02 7B 5D + 15 00 02 7C 4D + 15 00 02 7D 56 + 15 00 02 7E 48 + 15 00 02 7F 45 + 15 00 02 80 38 + 15 00 02 81 25 + 15 00 02 82 00 + 15 00 02 E0 02 + 15 00 02 00 1E + 15 00 02 01 1E + 15 00 02 02 41 + 15 00 02 03 41 + 15 00 02 04 43 + 15 00 02 05 43 + 15 00 02 06 1F + 15 00 02 07 1F + 15 00 02 08 1F + 15 00 02 09 1F + 15 00 02 0A 1E + 15 00 02 0B 1E + 15 00 02 0C 1F + 15 00 02 0D 47 + 15 00 02 0E 47 + 15 00 02 0F 45 + 15 00 02 10 45 + 15 00 02 11 4B + 15 00 02 12 4B + 15 00 02 13 49 + 15 00 02 14 49 + 15 00 02 15 1F + 15 00 02 16 1E + 15 00 02 17 1E + 15 00 02 18 40 + 15 00 02 19 40 + 15 00 02 1A 42 + 15 00 02 1B 42 + 15 00 02 1C 1F + 15 00 02 1D 1F + 15 00 02 1E 1F + 15 00 02 1F 1f + 15 00 02 20 1E + 15 00 02 21 1E + 15 00 02 22 1f + 15 00 02 23 46 + 15 00 02 24 46 + 15 00 02 25 44 + 15 00 02 26 44 + 15 00 02 27 4A + 15 00 02 28 4A + 15 00 02 29 48 + 15 00 02 2A 48 + 15 00 02 2B 1f + 15 00 02 2C 1F + 15 00 02 2D 1F + 15 00 02 2E 42 + 15 00 02 2F 42 + 15 00 02 30 40 + 15 00 02 31 40 + 15 00 02 32 1E + 15 00 02 33 1E + 15 00 02 34 1F + 15 00 02 35 1F + 15 00 02 36 1E + 15 00 02 37 1E + 15 00 02 38 1F + 15 00 02 39 48 + 15 00 02 3A 48 + 15 00 02 3B 4A + 15 00 02 3C 4A + 15 00 02 3D 44 + 15 00 02 3E 44 + 15 00 02 3F 46 + 15 00 02 40 46 + 15 00 02 41 1F + 15 00 02 42 1F + 15 00 02 43 1F + 15 00 02 44 43 + 15 00 02 45 43 + 15 00 02 46 41 + 15 00 02 47 41 + 15 00 02 48 1E + 15 00 02 49 1E + 15 00 02 4A 1E + 15 00 02 4B 1F + 15 00 02 4C 1E + 15 00 02 4D 1E + 15 00 02 4E 1F + 15 00 02 4F 49 + 15 00 02 50 49 + 15 00 02 51 4B + 15 00 02 52 4B + 15 00 02 53 45 + 15 00 02 54 45 + 15 00 02 55 47 + 15 00 02 56 47 + 15 00 02 57 1F + 15 00 02 58 10 + 15 00 02 59 00 + 15 00 02 5A 00 + 15 00 02 5B 30 + 15 00 02 5C 02 + 15 00 02 5D 40 + 15 00 02 5E 01 + 15 00 02 5F 02 + 15 00 02 60 30 + 15 00 02 61 01 + 15 00 02 62 02 + 15 00 02 63 6A + 15 00 02 64 6A + 15 00 02 65 05 + 15 00 02 66 12 + 15 00 02 67 74 + 15 00 02 68 04 + 15 00 02 69 6A + 15 00 02 6A 6A + 15 00 02 6B 08 + 15 00 02 6C 00 + 15 00 02 6D 06 + 15 00 02 6E 00 + 15 00 02 6F 88 + 15 00 02 70 00 + 15 00 02 71 00 + 15 00 02 72 06 + 15 00 02 73 7B + 15 00 02 74 00 + 15 00 02 75 07 + 15 00 02 76 00 + 15 00 02 77 5D + 15 00 02 78 17 + 15 00 02 79 1F + 15 00 02 7A 00 + 15 00 02 7B 00 + 15 00 02 7C 00 + 15 00 02 7D 03 + 15 00 02 7E 7B + 15 00 02 E0 04 + 15 00 02 2B 2B + 15 00 02 2E 44 + 15 00 02 E0 01 + 15 00 02 0E 01 + 15 00 02 E0 03 + 15 00 02 98 2F + 15 00 02 E0 00 + 15 00 02 E6 02 + 15 00 02 E7 02 + + 05 78 01 11 + 05 05 01 29 + 15 0a 02 35 00 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <18>; + hfront-porch = <18>; + vback-porch = <8>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&video_phy1{ + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + /* old touchscreen sensor_id0 */ + goodix,cfg-group0 = [ + 00 20 03 00 05 0A 05 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 90 30 AA + 17 15 31 0D 00 00 01 B9 04 25 + 00 00 00 00 00 00 00 00 00 00 + 00 0F 23 94 C5 02 07 00 00 04 + 9F 10 00 8B 13 00 7C 16 00 6B + 1B 00 60 20 00 60 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 + 11 12 13 14 00 00 00 00 00 00 + 00 00 00 00 96 01 + ]; +/* new touchscreen sensor_id2 */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 35 00 00 + 05 28 08 55 41 03 05 00 00 + 00 00 00 00 00 1A 1C 1E 14 + 8E 2E 99 14 16 D3 07 00 00 + 00 9B 02 2D 00 00 00 00 00 + 00 00 00 00 00 00 0F 23 94 + D5 02 07 00 00 04 9D 10 00 + 86 13 00 75 16 00 61 1B 00 + 53 20 00 53 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 17 16 15 14 11 + 10 0F 0E 0D 0C 09 08 07 06 + 05 04 01 00 FF FF 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 07 08 0A 0C 0D 0F 10 + 11 12 13 28 27 26 25 24 23 + 22 21 20 1F 1E 1C 1B 19 FF + FF FF FF 00 00 00 00 00 00 + 00 00 00 00 4D 01 + ]; +}; + + + diff --git a/rk356x/rp-lcd-mipi1-7-1024-600.dtsi b/rk356x/rp-lcd-mipi1-7-1024-600.dtsi new file mode 100755 index 0000000..afe01ed --- /dev/null +++ b/rk356x/rp-lcd-mipi1-7-1024-600.dtsi @@ -0,0 +1,175 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI1_USED + + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <51000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&video_phy1{ + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ //old touch + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + goodix,cfg-group5 = [ //new touch + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; +}; + diff --git a/rk356x/rp-lcd-mipi1-7-1200-1920.dtsi b/rk356x/rp-lcd-mipi1-7-1200-1920.dtsi new file mode 100755 index 0000000..8960a4a --- /dev/null +++ b/rk356x/rp-lcd-mipi1-7-1200-1920.dtsi @@ -0,0 +1,235 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI1_USED + + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 14 42 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 de 03 00 + 39 60 03 c9 02 23 + + 39 00 02 b0 00 + 39 00 06 14 08 b0 00 22 00 + 39 30 02 b4 0c + 39 40 03 b6 3a d3 + 39 50 02 51 e6 + 39 30 02 53 2c + + 05 78 01 29 + 05 78 01 11 + + + 39 00 03 b7 50 00 + 39 00 03 b8 00 00 + 39 10 03 b9 00 00 + 39 10 03 ba 8c 83 + 39 10 03 bb 03 00 + 39 60 03 b9 01 00 + 39 10 03 c9 02 23 + 39 60 03 ca 01 23 + 39 10 03 cb 10 05 + 39 10 03 cc 05 10 + 39 10 03 d0 00 00 + + + 39 10 03 b6 03 00 + 39 10 03 de 03 00 + 39 10 03 d6 05 00 + 39 60 03 b7 4b 02 + + 05 00 01 2c + + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <140000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <30>; + hfront-porch = <60>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + + + +>9xx { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ //sensor id 0 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + + + goodix,cfg-group2 = [ //sensor id 2 for new tp + 44 B0 04 80 07 05 45 00 02 08 28 + 08 46 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E B0 B2 B2 + 04 00 00 00 20 03 1C 00 01 00 00 + 00 00 00 32 00 00 00 96 D2 94 D5 + 02 00 00 00 04 8D 9B 00 85 A6 00 + 7F B1 00 79 BD 00 73 CB 00 73 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 16 18 1A 1C FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 + 02 04 06 08 0A 0C 0F 10 12 13 14 + 28 26 24 22 21 20 1F 1E 1D 1C 18 + 16 FF FF FF FF FF 00 00 00 00 00 + 00 00 00 00 00 00 00 00 34 01 + ]; + goodix,cfg-group5 = [ + 5C B0 04 80 07 05 45 00 02 08 + 28 08 46 32 03 05 00 00 00 00 + 00 00 00 00 00 00 00 8C 2C 0E + 22 24 BB 0A 00 00 02 01 03 1C + 00 01 00 00 00 00 00 32 00 00 + 00 14 46 94 C5 02 00 00 00 04 + E3 16 00 B4 1D 00 8D 25 00 72 + 30 00 5D 3E 00 5D 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 + 12 14 16 18 1A 1C FF FF FF FF + FF FF FF FF FF FF FF FF FF FF + FF FF 00 02 04 06 08 0A 0C 0F + 10 12 13 14 28 26 24 22 21 20 + 1F 1E 1D 1C 18 16 FF FF FF FF + FF 00 00 00 00 00 00 00 00 00 + 00 00 00 00 B8 01 + ]; +}; + + + diff --git a/rk356x/rp-lcd-mipi1-to-hdmi-lt8912-bridge.dtsi b/rk356x/rp-lcd-mipi1-to-hdmi-lt8912-bridge.dtsi new file mode 100755 index 0000000..4b91f59 --- /dev/null +++ b/rk356x/rp-lcd-mipi1-to-hdmi-lt8912-bridge.dtsi @@ -0,0 +1,142 @@ + +#include "rp-lcd-hdmi.dtsi" +//#define RP_MIPI1_USED + +#define RP_SINGLE_LCD +#define RP_MIPI1_USED + + +&rpdzkj { + compatible = "rp_config"; + user_version = "rpdzkj"; + system_rotate = "0"; + csi_camera_rotate = "0"; //all csi camera rotation //0 90 180 270 //no effect + csi_camera_facing = "0"; //0:auto 1:all front 2:all back //no effect + usb_camera_rotate = "0"; //all usb camera rotation //0 90 180 270 + usb_camera_facing = "0"; //0:auto 1:all front 2:all back + lcd_density = "240"; + language = "zh-CN"; //zh-CN //en-US + time_zone = "Asia/Shanghai"; //Asia/Shanghai = +8 //Europe/London = +1 //Africa/Casablanca = +0; + not_navigation_bar = "false"; + not_status_bar = "false"; + default_launcher = "true"; + has_root = "true"; + usb_not_permission = "true"; + gps_use = "false"; + gps_serial_port = "/dev/ttyS4"; + primary_device = "DSI"; + extend_device = "HDMI-A"; + extend_rotate = "0"; + rotation_efull = "false"; + home_apk = "null"; + status = "okay"; +}; + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "lontium,lt8912","rpdzkj-bridge"; +// compatible = "simple-panel-dsi"; + + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + + i2c-bus = <&i2c4>; + + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <88>; + hsync-len = <44>; + hback-porch = <148>; + vfront-porch = <4>; + vsync-len = <5>; + vback-porch = <36>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + + + +&video_phy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp1_out_dsi1>; +}; + + + + + + + + diff --git a/rk356x/rp-lcd-mipi1tolvds-gm8775c-10-1024-600-raw.dtsi b/rk356x/rp-lcd-mipi1tolvds-gm8775c-10-1024-600-raw.dtsi new file mode 100755 index 0000000..f44b94e --- /dev/null +++ b/rk356x/rp-lcd-mipi1tolvds-gm8775c-10-1024-600-raw.dtsi @@ -0,0 +1,230 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI12LVDS + + +&dsi1 { + status = "okay"; + rockchip,lane-rate = <480>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + init-delay-ms = <120>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + +/* +&mipi_dphy1 { + status = "okay"; +}; + +&mipi_dphy0 { + status = "disabled"; +}; +*/ + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp1_out_dsi1>; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01 + ]; +}; + + + + diff --git a/rk356x/rp-lcd-mipi1tolvds-gm8775c-1920-1080.dtsi b/rk356x/rp-lcd-mipi1tolvds-gm8775c-1920-1080.dtsi new file mode 100755 index 0000000..b105631 --- /dev/null +++ b/rk356x/rp-lcd-mipi1tolvds-gm8775c-1920-1080.dtsi @@ -0,0 +1,151 @@ +#include "rp-lcd-hdmi.dtsi" +#define RP_SINGLE_LCD +#define RP_MIPI12LVDS +#define RP_DUALLVDS + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + init-delay-ms = <120>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 80 + 23 08 02 02 38 + 23 08 02 03 47 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 13 + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 63 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 34 + 23 08 02 19 20 + 23 08 02 1A 10 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + + + +&video_phy1 { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + + diff --git a/rk356x/rp-lcd-mipi2hdmi-lt8912.dtsi b/rk356x/rp-lcd-mipi2hdmi-lt8912.dtsi new file mode 100755 index 0000000..154cb9e --- /dev/null +++ b/rk356x/rp-lcd-mipi2hdmi-lt8912.dtsi @@ -0,0 +1,138 @@ +#include "rp-lcd-hdmi.dtsi" + + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + init-delay-ms = <120>; + reset-delay-ms = <120>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; +// dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | +// MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + +// dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | +// MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_VIDEO_HBP | MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET)>; + + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 05 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <148500000>;//140000000 + hactive = <1920>; + vactive = <1080>; + hback-porch = <148>;//60 + hfront-porch = <88>; + vback-porch = <36>;//23 + vfront-porch = <4>;//12 + hsync-len = <44>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "okay"; +}; + + + +&video_phy1 { + status = "okay"; +}; + +&video_phy0 { + status = "disabled"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp1_out_dsi1>; +}; + + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + clock-frequency = <100000>; + + /delete-node/ gt1x@14; + lt89121: lt89121@48 { + status = "okay"; + compatible = "lt8912_i2c"; + reg = <0x48>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; + }; +}; + + diff --git a/rk356x/rp-lcd-triple-lvds-10-1024-600-edp-13-1920-1080-hdmi.dtsi b/rk356x/rp-lcd-triple-lvds-10-1024-600-edp-13-1920-1080-hdmi.dtsi new file mode 100755 index 0000000..76811c5 --- /dev/null +++ b/rk356x/rp-lcd-triple-lvds-10-1024-600-edp-13-1920-1080-hdmi.dtsi @@ -0,0 +1,298 @@ +#include +#include "rp-lcd-hdmi.dtsi" + +#define RP_TRIPLE_LCD + + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing2>; + + timing2: timing2 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + + + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 {//EDP 13.3 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 15.6 LP156WF6 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + +&edp { + //hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + + + +&lvds_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + + + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + + +&edp_phy { + status = "okay"; +}; + + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&route_lvds { + /****** + * cannot enable cause of resolution is different from other two device, + * otherwish, the lvds will abnormal after into bootanimotaion. + *******/ + status = "disabled"; + connect = <&vp2_out_lvds>; +}; + +&route_edp { + status = "okay"; + connect = <&vp1_out_edp>; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; + + + diff --git a/rk356x/rp-lcd-triple-lvds-10-1024-600-mipi1-7-1024-600-edp-13-1920-1080.dtsi b/rk356x/rp-lcd-triple-lvds-10-1024-600-mipi1-7-1024-600-edp-13-1920-1080.dtsi new file mode 100755 index 0000000..931594d --- /dev/null +++ b/rk356x/rp-lcd-triple-lvds-10-1024-600-mipi1-7-1024-600-edp-13-1920-1080.dtsi @@ -0,0 +1,376 @@ +#include + +#define RP_TRIPLE_LCD + + + + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing2>; + + timing2: timing2 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <480>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + panel-init-sequence = [ + 05 78 01 11 + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + + + + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 {//EDP 13.3 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 15.6 LP156WF6 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + +&edp { + //hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + + + +&dsi1_in_vp0 { + status = "okay"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + + + +&lvds_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + + + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "okay"; +}; + + + +&video_phy0 { + status = "okay"; +}; + +&video_phy1 { + status = "okay"; +}; + + +&edp_phy { + status = "okay"; +}; + + + +&route_dsi1 { + status = "okay"; + connect = <&vp0_out_dsi1>; +}; + +&route_lvds { + status = "okay"; + connect = <&vp2_out_lvds>; +}; + +&route_edp { + status = "okay"; + connect = <&vp1_out_edp>; +}; + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + goodix,cfg-group3 = [ + 46 00 04 58 02 0A 3D 00 01 08 + 28 05 50 32 03 05 00 00 00 00 + 00 00 00 18 1A 1E 14 8D 2D 88 + 17 15 31 0D 00 00 01 9B 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 1E 5A 94 C5 02 08 00 00 00 + 61 21 00 57 29 00 4E 34 00 48 + 41 00 43 51 00 43 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 01 04 05 06 07 08 09 + 0C 0D 0E 0F 10 11 14 15 FF FF + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0F 10 11 12 13 19 1B 1C 1E 1F + 20 21 22 23 24 25 26 27 FF FF + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 FD 01]; + +}; + + + diff --git a/rk356x/rp-lcd-triple-lvds-7-1024-600-edp-13-1920-1080-hdmi.dtsi b/rk356x/rp-lcd-triple-lvds-7-1024-600-edp-13-1920-1080-hdmi.dtsi new file mode 100755 index 0000000..419c243 --- /dev/null +++ b/rk356x/rp-lcd-triple-lvds-7-1024-600-edp-13-1920-1080-hdmi.dtsi @@ -0,0 +1,280 @@ +#include +#include "rp-lcd-hdmi.dtsi" + +#define RP_TRIPLE_LCD + + +&lvds_panel { + status = "okay"; + compatible = "simple-panel"; + + enable-delay-ms = <20>; + prepare-delay-ms = <20>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + bus-format = ; + width-mm = <217>; + height-mm = <136>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing2>; + + timing2: timing2 { + clock-frequency = <45000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <160>; + vback-porch = <23>; + vfront-porch = <12>; + hsync-len = <20>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-even-pixels; + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + + +&lvds { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; +}; + + + + + + +&edp_panel { + status = "okay"; + compatible = "simple-panel"; + + prepare-delay-ms = <20>; + enable-delay-ms = <20>; + disable-delay-ms = <20>; + unprepare-delay-ms = <20>; + + /** + * power-supply = <>; + * reset-gpios = <>; + * + * lcd reset pin and power supply + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + display-timings { + native-mode = <&timing1>; + + timing0: timing0 {//EDP 13.3 + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing1: timing1 {// EDP 15.6 LP156WF6 + clock-frequency = <138000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; +}; + + +&edp { + //hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + force-hpd; + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + + +&dsi0_in_vp0 { + status = "disabled"; +}; + +&dsi0_in_vp1 { + status = "disabled"; +}; + + + +&dsi1_in_vp0 { + status = "disabled"; +}; + +&dsi1_in_vp1 { + status = "disabled"; +}; + + + +&lvds_in_vp1 { + status = "disabled"; +}; + +&lvds_in_vp2 { + status = "okay"; +}; + + + +&edp_in_vp0 { + status = "disabled"; +}; + +&edp_in_vp1 { + status = "okay"; +}; + + +&video_phy0 { + status = "okay"; +}; + + +&edp_phy { + status = "okay"; +}; + + +&route_hdmi { + status = "okay"; + connect = <&vp0_out_hdmi>; +}; + +&route_lvds { + /****** + * cannot enable cause of resolution is different from other two device, + * otherwish, the lvds will abnormal after into bootanimotaion. + *******/ + status = "disabled"; + connect = <&vp2_out_lvds>; +}; + +&route_edp { + status = "okay"; + connect = <&vp1_out_edp>; +}; + + + +>9xx { + status = "okay"; + + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + /** + * goodix_rst_gpio = <>; + * goodix_irq_gpio = <>; + * + * touch panel interrupt and reset pin + * please refer to ***-lcd-gpio.dtsi + * that included in main dts. + */ + + goodix,cfg-group0 = [ + 5A 00 04 58 02 05 3D 00 01 + 08 32 0F 5A 32 03 05 00 00 + 00 00 02 00 00 18 1A 1E 14 + 87 29 0A 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 + 2B FF 7F 19 46 32 3C 78 94 + D5 02 08 00 00 04 98 40 00 + 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 + 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 02 04 06 08 0A + 0C 0E 10 12 14 FF FF FF FF + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 02 + 04 06 08 0A 0C 1D 1E 1F 20 + 21 22 24 26 28 29 2A FF FF + FF FF FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6F 01 + ]; +}; + + + + diff --git a/rk356x/rp-mipi-camera-gc2093-imx334-imx415-rk3568.dtsi b/rk356x/rp-mipi-camera-gc2093-imx334-imx415-rk3568.dtsi new file mode 100755 index 0000000..6c60568 --- /dev/null +++ b/rk356x/rp-mipi-camera-gc2093-imx334-imx415-rk3568.dtsi @@ -0,0 +1,172 @@ + +/ { + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c4 { + status = "okay"; + gc2093: gc2093@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "SIDB205300385-VA"; + rockchip,camera-module-lens-name = "default"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + imx334: imx334@1a { + compatible = "sony,imx334"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + // conflict with csi-ctl-gpios// + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1522-FG3"; + rockchip,camera-module-lens-name = "CS-P1150-IRC-8M-FAU"; + + port { + ucam_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + imx415: imx415@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1607-FV1"; + rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16"; + port { + ucam_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + + + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@0 { + reg = <0>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2 3 4>; + }; + + mipi_in_ucam2: endpoint@2 { + reg = <2>; + remote-endpoint = <&ucam_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/rp-mipi-camera-gc2093-rk3566.dtsi b/rk356x/rp-mipi-camera-gc2093-rk3566.dtsi new file mode 100755 index 0000000..ff3b6aa --- /dev/null +++ b/rk356x/rp-mipi-camera-gc2093-rk3566.dtsi @@ -0,0 +1,115 @@ +/ { + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + +}; + + + +&i2c2 { + status = "okay"; + pinctrl-name = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + gc2093: gc2093@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_clkout0>; + pwdn-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "SIDB205300385-VA"; + rockchip,camera-module-lens-name = "default"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + + + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/rp-mipi-camera-gc2093-rk3568.dtsi b/rk356x/rp-mipi-camera-gc2093-rk3568.dtsi new file mode 100755 index 0000000..56780df --- /dev/null +++ b/rk356x/rp-mipi-camera-gc2093-rk3568.dtsi @@ -0,0 +1,113 @@ + +/ { + + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + +}; + +&i2c4 { + status = "okay"; + gc2093: gc2093@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "SIDB205300385-VA"; + rockchip,camera-module-lens-name = "default"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out>; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + + + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/rp-mipi-camera-gc2093x2-rk3568.dtsi b/rk356x/rp-mipi-camera-gc2093x2-rk3568.dtsi new file mode 100755 index 0000000..da28cfc --- /dev/null +++ b/rk356x/rp-mipi-camera-gc2093x2-rk3568.dtsi @@ -0,0 +1,254 @@ +#define RP_GC2093x2_CAMERA + +/ { + + + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + +}; + +&i2c4 { + status = "okay"; + gc2093_0: gc2093_0@37 { + compatible = "galaxycore,gc2093"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_CIF_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "SIDB205300385-VA"; + rockchip,camera-module-lens-name = "default"; + //rockchip,camera-module-name = "DW-RV2093-V1.0"; + //rockchip,camera-module-lens-name = "JZ-7070AS-A1"; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + gc2093_clk_24m_0: gc2093_clk_24m_0@7e { + compatible = "galaxycore,gc2093_clk_24m"; + status = "okay"; + reg = <0x7e>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + pwdn-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_LOW>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "DW-RV2093-V1.0"; + rockchip,camera-module-lens-name = "JZ-7070AS-A1"; + port { + ucam_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "disabled"; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + + +&csi2_dphy2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&mipi_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy_out1>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in>; + data-lanes = <1 2>; + }; + }; +}; + + +&rkisp_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy_out0>; + }; + }; +}; + + + +&rkisp_vir1 { + status = "okay"; + + ports { + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + isp1_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; + }; +}; + + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + + +&pinctrl { + cam { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk356x/rp-mipi-camera-rk628d-csi2hdmi.dtsi b/rk356x/rp-mipi-camera-rk628d-csi2hdmi.dtsi new file mode 100755 index 0000000..cee1ca2 --- /dev/null +++ b/rk356x/rp-mipi-camera-rk628d-csi2hdmi.dtsi @@ -0,0 +1,101 @@ + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + pinctrl-0 = <&i2c5m0_xfer>; + + rk628_csi_v4l2: rk628_csi_v4l2@50 { + status = "okay"; + reg = <0x50>; + compatible = "rockchip,rk628-csi-v4l2"; + + pinctrl-names = "default"; + pinctrl-0 = <&refclk_pins>; + assigned-clocks = <&pmucru CLK_WIFI>; + assigned-clock-rates = <24000000>; + clocks = <&pmucru CLK_WIFI>; + clock-names = "soc_24M"; + + interrupt-parent = <&gpio2>; + interrupts = ; + enable-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; + //hdcp-enable = <1>; + scaler-en = <1>; + + /* + * If the hpd output level is inverted on the circuit, + * the following configuration needs to be enabled. + */ + + /* hpd-output-inverted; */ + plugin-det-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + //power-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK628-CSI"; + rockchip,camera-module-lens-name = "NC"; + + port { + hdmiin_out0: endpoint { + remote-endpoint = <&mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmiin_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_in>; + }; + }; + }; +}; + +&rkisp { + status = "okay"; +}; + +&rkisp_mmu { + status = "okay"; +}; + +&rkisp_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidphy0_out>; + }; + }; +}; + diff --git a/rk356x/rp-mipi-camera-xs9922b-ahd.dtsi b/rk356x/rp-mipi-camera-xs9922b-ahd.dtsi new file mode 100755 index 0000000..b99fe4f --- /dev/null +++ b/rk356x/rp-mipi-camera-xs9922b-ahd.dtsi @@ -0,0 +1,132 @@ +/** + * mipi csi to xs9922b config + */ + + +&i2c5 { + status = "okay"; + xs9922: xs9922@31 { + compatible = "xs9922"; + status = "okay"; + reg = <0x31>; + clocks = <&cru CLK_CAM0_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3568_PD_VI>; + //pinctrl-names = "default"; + // pinctrl-0 = <&cif_clk>; + pinctrl-names = "default"; + pinctrl-0 = <&xs9922_pwr>; + reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>; + // power-gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,default_rect= <1920 1080>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_csi2_input>; + }; + }; + }; +}; + +&mipi_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + rockchip,cif-monitor = <3 2 5 1000 5>; + + port { + cif_mipi_in: endpoint { + remote-endpoint = <&mipi_csi2_output>; + data-lanes = <1 2 3 4>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + xs9922 { + xs9922_pwr: camera-pwr { + rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk356x/rp-pcie-5g.dtsi b/rk356x/rp-pcie-5g.dtsi new file mode 100755 index 0000000..9e5bbac --- /dev/null +++ b/rk356x/rp-pcie-5g.dtsi @@ -0,0 +1,46 @@ +/{ + vdd_5G: vdd-5G{ + compatible = "regulator-fixed"; + regulator-name = "vdd_5G"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x2 { + status = "okay"; + vpcie3v3-supply = <&vcc3v3_pcie3>; + phys = <&pcie30phy PHY_TYPE_PCIE>; + // reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + //modem-pwr-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + modem-en-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + // pcie-waken-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&modem_pwr>,<&modem_en>; +}; + + +&pinctrl { + modem { + modem_pwr: modem-pwr { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + modem_en: modem-en { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; + }; +// modem_rst: modem-rst { +// rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +// }; +// modem_wakup: modem-wakup { +// rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; +// }; + }; +}; + diff --git a/rk356x/rp-rk3566-single-lcd-gpio.dtsi b/rk356x/rp-rk3566-single-lcd-gpio.dtsi new file mode 100755 index 0000000..2540882 --- /dev/null +++ b/rk356x/rp-rk3566-single-lcd-gpio.dtsi @@ -0,0 +1,110 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + +/************** LCD GPIO ********************/ +&vcc3v3_lcd_n { + gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp_panel { + power-supply = <&vcc3v3_lcd_n>; + backlight = <&backlight4>; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + diff --git a/rk356x/rp-rk3566.dts b/rk356x/rp-rk3566.dts new file mode 100755 index 0000000..abb8c84 --- /dev/null +++ b/rk356x/rp-rk3566.dts @@ -0,0 +1,307 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + */ + +//rk3566-evb1-ddr4-v10 +#include "rk3566-evb1-ddr4-v10.dtsi" +#include "../rk3568-linux.dtsi" +#include "rp-mipi-camera-gc2093-rk3566.dtsi" + +/****************** SINGLE LCD ***************/ +#include "rp-rk3566-single-lcd-gpio.dtsi" +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-8-800-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-10-1024-600.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + + + + +/ { + model = "rp-rk3566"; + compatible = "rpdzkj,rp-rk3566", "rockchip,rk3566"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + temperature-device = "soc-thermal"; + temp-on = <60000>; + time = <10000>; + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + +/******* SYSTEM POWER **********/ + pwer_5v_3v3 { //vdd 3.3v 5v enable + gpio_num = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + led { //system led + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_pwr { //usb host and otg power + gpio_num = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //usb hub reset + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //SPK ENABLE + gpio_num = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_mute { //SPK MUTE, hish active, nomal low + gpio_num = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + otg_mode { //OTG SWITCH, high is mean otg_id to 0, foece host mode + gpio_num = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + gpio_function = <0>; + }; + + //fan { //fan en + // gpio_num = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + }; + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + + +/***** gpio ********/ + + gpio4a0 { + gpio_num = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a1 { + gpio_num = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio4a2 { + gpio_num = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio4a3 { + gpio_num = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1b2 { + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3c1 { + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1b0 { + gpio_num = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0c4 { + gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1a4 { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0c5 { + gpio_num = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio2b4 { + gpio_num = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_3v3>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&i2c5 { + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + vdd_cpu: tcs4525@1c { + compatible = "tcs,tcs452x"; + reg = <0x1c>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "fan53555-reg"; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1390000>; + regulator-ramp-delay = <2300>; + fcs,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&gmac1 { + tx_delay = <0x3a>; + rx_delay = <0x2a>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m0_xfer>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer>; +}; + +&spi1 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi1m0_cs0 &spi1m0_pins>; + pinctrl-1 = <&spi1m0_cs0 &spi1m0_pins_hs>; + spi1_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +&spi2 { + status = "okay"; + /* rewrite pinctrl, for cs1 used to be gpio */ + pinctrl-0 = <&spi2m0_cs0 &spi2m0_pins>; + pinctrl-1 = <&spi2m0_cs0 &spi2m0_pins_hs>; + spi2_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + + +}; + +&spi3 { + status = "okay"; + spi3_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; + +}; + +/****** rp3566 camera configuration adjustment ******/ +&spi3 { + /* rewrite pinctrl for cs1 used to be camera clk */ + pinctrl-0 = <&spi3m0_cs0 &spi3m0_pins>; + pinctrl-1 = <&spi3m0_cs0 &spi3m0_pins_hs>; +}; +/***************************************************/ + +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; + + diff --git a/rk356x/rp-rk3568-single-lcd-gpio.dtsi b/rk356x/rp-rk3568-single-lcd-gpio.dtsi new file mode 100755 index 0000000..9ce61a0 --- /dev/null +++ b/rk356x/rp-rk3568-single-lcd-gpio.dtsi @@ -0,0 +1,120 @@ + +/ { + backlight4: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm4 { + status = "okay"; +}; + + + + + +/************** LCD GPIO ********************/ +&dsi0_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&lvds_panel { + power-supply = <&vcc3v3_lcd0_n>; + reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight4>; +}; + +&edp { + hpd-gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; +}; +&edp_panel { + power-supply = <&vcc3v3_lcd0_n>; + backlight = <&backlight4>; +}; + +&vcc3v3_lcd0_n { + gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; + +&i2c1 { + gt9xx: goodix_ts@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix_rst_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; + gt1x: goodix_gt1x@5d { + status = "disabled"; + /***** tp pin ******/ + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + goodix,rst-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PA2 IRQ_TYPE_EDGE_FALLING>; + }; +}; + + +&pinctrl { + lcd1 { + lcd_rst_gpio: lcd1-rst-gpio { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; +/********************************************/ + + + + diff --git a/rk356x/rp-rk3568.dts b/rk356x/rp-rk3568.dts new file mode 100755 index 0000000..24a70c1 --- /dev/null +++ b/rk356x/rp-rk3568.dts @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +//rk3568-evb1-ddr4-v10 +//#include "rk3568-evb1-ddr4-v10.dtsi" + +#include "rk3568-evb-rpdzkj-rk809-pwm.dtsi" + + +#include "../rk3568-linux.dtsi" + +/*************************camera***********************/ +#include "rp-mipi-camera-gc2093-rk3568.dtsi" +/***************************************************/ + + +/*************************adc key***********************/ +#include "rp-adc-key.dtsi" +/***************************************************/ + +/*************************gmac***********************/ +#include "rp-gmac0-pro-rk3568.dtsi" +#include "rp-gmac1-m1-pro-rk3568.dtsi" +/***************************************************/ + +/*************************SATA***********************/ +#include "rk3568-sata2.dtsi" +/***************************************************/ +//#include "rp-can0-m0-rk3568.dtsi" +//#include "rp-can1-m1-rk3568.dtsi" + + +/***************** SINGLE LCD (LCD + HDMI) ****************/ +#include "rp-rk3568-single-lcd-gpio.dtsi" // if use lcd, must enable it +/* HDMI */ +//#include "rp-lcd-hdmi.dtsi" + +/* MIPI DSI0 */ +//#include "rp-lcd-mipi0-5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280.dtsi" +//#include "rp-lcd-mipi0-5.5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5.5-1080-1920.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-7-1200-1920.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" + +/* LVDS */ +//#include "rp-lcd-lvds-7-1024-600-v2.dtsi" +//#include "rp-lcd-lvds-10-1024-600.dtsi" +//#include "rp-lcd-lvds-10-1280-800.dtsi" + +/* EDP */ +//#include "rp-lcd-edp-13-1920-1080.dtsi" +//#include "rp-lcd-edp-13.3-15.6-1920-1080.dtsi" + +/************************ DUAL LCD *********************/ +/* EDP + MIPI0 */ +//#include "rp-lcd-dual-mipi0-7-1024-600-edp-13-1920-1080.dtsi" + + +/********************** TRIPLE LCD ********************/ +/* EDP + LVDS + HDMI */ +//#include "rp-lcd-triple-lvds-10-1024-600-edp-13-1920-1080-hdmi.dtsi" + + + + +/{ + model = "rp-rk3568"; + compatible = "rpdzkj,rp-rk3568-v10", "rockchip,rk3568"; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + +/******* SYSTEM POWER **********/ + pwr_5v_3v3 { //vdd5v vdd3v3 en + gpio_num = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + led { //system led + gpio_num = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + //fan { //fan + // gpio_num = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + usb_pwr { //usb power + gpio_num = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + hub_rst { //hub reset + gpio_num = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + otg_mode { //OTG SWITCH, high is mean otg_id to 0, foece host mode + gpio_num = <&gpio2 RK_PD6 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + otg_power { //OTG power + gpio_num = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_en { //spk enable + gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + }; + + + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + }; + + fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; +}; + + +&pmu_io_domains { + status = "okay"; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + + +&i2c1 { + status = "okay"; +}; + + +&i2c3 { + status = "okay"; +}; + + +&i2c5 { + status = "okay"; + rtc@51 { + status = "okay"; + compatible = "rtc,hym8563"; + reg = <0x51>; + }; +}; + + +&uart0 { + status = "okay"; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; +}; + + +&spi0 { + status = "okay"; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&spi1 { + status = "disabled"; +}; + + +/******** must be close,if not system no run ******/ +&dmc { + status = "disabled"; +}; + +&dfi { + status = "disabled"; +}; +/*********************************************/ + + +&pwm7 { + /****** disable for gpio used to be spi0_cs0 */ + status = "disabled"; +}; + + +/*************************wifi bt***********************/ +&wireless_wlan { + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; +}; + + +&wireless_bluetooth { + BT,reset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/******************************************************/ + + +&rk_headset { + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + headset_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; +}; + + + + +/****** rp3568 camera configuration adjustment ******/ +&vcc_camera { + pinctrl-0 = <&camera_pwr>; + gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; +}; +&gc2093 { + pwdn-gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; +}; + + +&pinctrl { + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + + + + diff --git a/rk356x/rp-wifi-bt-ap6275p-rk3568.dtsi b/rk356x/rp-wifi-bt-ap6275p-rk3568.dtsi new file mode 100755 index 0000000..0165761 --- /dev/null +++ b/rk356x/rp-wifi-bt-ap6275p-rk3568.dtsi @@ -0,0 +1,46 @@ + +/ { + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m0_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + rockchip,grf = <&grf>; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x1 { + rockchip,bifurcation; + reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie3>; + status = "okay"; +}; + +&pinctrl { + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588-amp.dtsi b/rk3588-amp.dtsi new file mode 100644 index 0000000..1d5e504 --- /dev/null +++ b/rk3588-amp.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + rockchip_amp: rockchip-amp { + compatible = "rockchip,amp"; + clocks = <&cru HCLK_PMU_CM0_ROOT>, <&cru FCLK_PMU_CM0_CORE>, + <&cru CLK_PMU_CM0_RTC>, <&cru PCLK_PMUCM0_INTMUX>, + <&cru SCLK_UART5>, <&cru PCLK_UART5>, + <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER4>, <&cru CLK_BUSTIMER5>, + <&cru PCLK_BUSTIMER1>, <&cru CLK_BUSTIMER10>, <&cru CLK_BUSTIMER11>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* remote amp core address */ + amp_shmem_reserved: amp-shmem@7800000 { + reg = <0x0 0x7800000 0x0 0x400000>; + no-map; + }; + + rpmsg_reserved: rpmsg@7c00000 { + reg = <0x0 0x07c00000 0x0 0x400000>; + no-map; + }; + + rpmsg_dma_reserved: rpmsg-dma@8000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x08000000 0x0 0x100000>; + no-map; + }; + + /* mcu address */ + mcu_reserved: mcu@8200000 { + reg = <0x0 0x8200000 0x0 0x100000>; + no-map; + }; + }; + + rpmsg: rpmsg@7c00000 { + compatible = "rockchip,rpmsg"; + mbox-names = "rpmsg-rx", "rpmsg-tx"; + mboxes = <&mailbox0 0 &mailbox0 3>; + rockchip,vdev-nums = <1>; + rockchip,link-id = <0x03>; + reg = <0x0 0x7c00000 0x0 0x20000>; + memory-region = <&rpmsg_dma_reserved>; + + status = "okay"; + }; +}; + +&mailbox0 { + rockchip,txpoll-period-ms = <1>; + status = "okay"; +}; diff --git a/rk3588-android.dtsi b/rk3588-android.dtsi new file mode 100644 index 0000000..174001f --- /dev/null +++ b/rk3588-android.dtsi @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 rcupdate.rcu_expedited=1 rcu_nocbs=all"; + }; + + cspmu: cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd10c000 0x0 0x1000>, + <0x0 0xfd10d000 0x0 0x1000>, + <0x0 0xfd10e000 0x0 0x1000>, + <0x0 0xfd10f000 0x0 0x1000>, + <0x0 0xfd12c000 0x0 0x1000>, + <0x0 0xfd12d000 0x0 0x1000>, + <0x0 0xfd12e000 0x0 0x1000>, + <0x0 0xfd12f000 0x0 0x1000>; + }; + + debug: debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd104000 0x0 0x1000>, + <0x0 0xfd105000 0x0 0x1000>, + <0x0 0xfd106000 0x0 0x1000>, + <0x0 0xfd107000 0x0 0x1000>, + <0x0 0xfd124000 0x0 0x1000>, + <0x0 0xfd125000 0x0 0x1000>, + <0x0 0xfd126000 0x0 0x1000>, + <0x0 0xfd127000 0x0 0x1000>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + minidump: minidump { + compatible = "rockchip,minidump"; + smem-region = <&minidump_smem>; + minidump-region = <&minidump_mem>; + status = "disabled"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 (8 * 0x100000)>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + vendor_storage_rm: vendor-storage-rm@00000000 { + compatible = "rockchip,vendor-storage-rm"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + + minidump_smem: minidump-smem@1f0000 { + reg = <0x0 0x1f0000 0x0 0x100>; /* do not change */ + no-map; + status = "disabled"; + }; + + minidump_mem: minidump-mem@c000000 { + reg = <0x0 0x0c000000 0x0 0x2000000>; /* changing according to your project */ + no-map; + status = "disabled"; + }; + }; + + vendor_storage: vendor-storage { + compatible = "rockchip,ram-vendor-storage"; + memory-region = <&vendor_storage_rm>; + status = "okay"; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>; + memory-region-names = "drm-logo"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rng { + status = "okay"; +}; + +&vop { + support-multi-area; +}; diff --git a/rk3588-cpu-swap.dtsi b/rk3588-cpu-swap.dtsi new file mode 100644 index 0000000..a64ec7c --- /dev/null +++ b/rk3588-cpu-swap.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +/delete-node/ &cpu_l0; +/delete-node/ &cpu_l1; +/delete-node/ &cpu_l2; +/delete-node/ &cpu_l3; + +/ { + cpus { + cpu_l0: cpu@0000 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <100>; + }; + + cpu_l1: cpu@0100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + cpu_l2: cpu@0200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + cpu_l3: cpu@0300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + }; +}; diff --git a/rk3588-evb.dtsi b/rk3588-evb.dtsi new file mode 100644 index 0000000..edaac39 --- /dev/null +++ b/rk3588-evb.dtsi @@ -0,0 +1,1258 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + spdif_tx0_dc: spdif-tx0-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx0_sound: spdif-tx0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx0"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx0>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx0_dc>; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <60>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588-evb1-cam-6x.dtsi b/rk3588-evb1-cam-6x.dtsi new file mode 100644 index 0000000..d8f1744 --- /dev/null +++ b/rk3588-evb1-cam-6x.dtsi @@ -0,0 +1,766 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out1>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out2>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out3>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam4: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out4>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy5 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam5: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out5>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy5_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + /* module 77/79 0x1a 78/80 0x36 */ + imx464_2: imx464-2@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_3: imx464-3@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out3: endpoint { + remote-endpoint = <&mipi_in_ucam3>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m3_xfer>; + + /* 77/79 0x1a 78/80 0x36 */ + imx464_4: imx464-4@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + avdd-supply = <&vcc_mipicsi1>; + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out4: endpoint { + remote-endpoint = <&mipi_in_ucam4>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_5: imx464-5@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi1>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out5: endpoint { + remote-endpoint = <&mipi_in_ucam5>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + /* 77/79 0x1a 78/80 0x36 */ + imx464_0: imx464-0@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + avdd-supply = <&vcc_mipidcphy0>; + rockchip,camera-module-index = <4>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_1: imx464-1@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + pwdn-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidcphy0>; + rockchip,camera-module-index = <5>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&mipi3_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + +&mipi5_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy5_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in5>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds3 { + status = "okay"; + + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds3_sditf { + status = "okay"; + + port { + mipi3_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir2>; + }; + }; +}; + +&rkcif_mipi_lvds5 { + status = "okay"; + + port { + cif_mipi_in5: endpoint { + remote-endpoint = <&mipi5_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds5_sditf { + status = "okay"; + + port { + mipi5_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_lvds_sditf>; + }; + }; +}; + + +&rkisp1_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_lvds_sditf>; + }; + }; +}; diff --git a/rk3588-evb1-imx415.dtsi b/rk3588-evb1-imx415.dtsi new file mode 100644 index 0000000..abf2eb0 --- /dev/null +++ b/rk3588-evb1-imx415.dtsi @@ -0,0 +1,158 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + ircut-close-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidcphy0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&cam_ircut0>; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; diff --git a/rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts b/rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts new file mode 100644 index 0000000..4e48b92 --- /dev/null +++ b/rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1.dts @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board + DSI DSC PANEL MV2100UZ1 DISPLAY Ext Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1", "rockchip,rk3588"; +}; + +&backlight { + status = "okay"; + default-brightness-level = <20>; +}; + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1200000>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <50>; + enable-delay-ms = <50>; + init-delay-ms = <20>; + prepare-delay-ms = <50>; + unprepare-delay-ms = <20>; + disable-delay-ms = <20>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; + + dsi,format = ; + dsi,lanes = <4>; + + compressed-data; + slice-width = <1140>; + slice-height = <2280>; + version-major = <1>; + version-minor = <1>; + + panel-init-sequence = [ + /* PPS Setting */ + 0A 00 58 11 00 00 89 30 80 08 E8 08 E8 08 E8 04 74 04 74 02 00 03 C9 00 20 F7 C5 00 0F 00 0F 00 0E 00 06 18 00 10 F0 03 0C 20 00 06 0B 0B 33 0E 1C 2A 38 46 54 62 69 70 77 79 7B 7D 7E 01 02 01 00 09 40 09 BE 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 2A F6 2B 34 2B 74 3B 74 6B F4 + 39 00 02 FF 20 + 39 00 02 E0 10 + 39 00 02 7A 07 + 39 00 02 7D 0C + 39 00 02 7E 0C + 39 00 02 FB 01 + + 39 00 02 FF E0 + 39 00 02 66 00 + 39 00 02 23 07 + 39 00 02 FB 01 + + /* CMD2 page 5 */ + 39 00 02 FF 25 + + /* OSC TRACE for MIPI H 4.748us */ + 39 00 02 2F 20 + 39 00 02 0D 07 + 39 00 02 0E 6B + 39 00 02 11 11 + 39 00 02 13 00 + 39 00 02 14 01 + 39 00 02 25 20 + 39 00 02 0F 09 + 39 00 02 10 A5 + 39 00 02 12 17 + 39 00 02 15 01 + 39 00 02 0C 01 + 39 00 02 09 10 + 39 00 02 38 03 + 39 00 02 0A 00 + 39 00 02 07 02 + + /* MIPI VFP */ + 39 00 02 BC FF + 39 00 02 BD FF + 39 00 02 BE FF + 39 00 02 BF FF + 39 00 02 C0 FF + 39 00 02 C1 FF + 39 00 02 C2 FF + 39 00 02 C3 FF + + 39 00 02 FB 01 + + 39 00 02 FF 10 + 39 00 05 2A 00 00 08 E7 + 39 00 05 2B 00 00 08 E7 + 39 00 02 03 01 + 39 00 02 BB 13 + 39 00 02 C0 03 + 39 00 11 C1 89 28 08 E8 F2 00 03 C9 F7 C5 00 0F 00 0E 00 06 + 39 00 03 C2 10 F0 + 39 00 02 35 00 + 39 00 03 44 00 00 + 39 00 02 51 FF + 39 00 02 53 24 + 39 00 02 FB 01 + + 15 64 01 11 + 15 14 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <506000000>; + hactive = <2280>; + vactive = <2280>; + hfront-porch = <52>; + hsync-len = <20>; + hback-porch = <52>; + vfront-porch = <44>; + vsync-len = <2>; + vback-porch = <14>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; +}; + +&dp0 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; diff --git a/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts b/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts new file mode 100644 index 0000000..65afa35 --- /dev/null +++ b/rk3588-evb1-lp4-v10-edp-8lanes-M280DCA.dts @@ -0,0 +1,229 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board + RK3588 EDP 8LANES V10 Ext Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10-edp-8lanes-M280DCA", "rockchip,rk3588"; + + panel-edp { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_edp>; + enable-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + + display-timings { + native-mode = <&timing_4kp144>; + timing_4kp144: timing0 { + clock-frequency = <1360800000>; + hactive = <3840>; + vactive = <2160>; + hfront-porch = <160>; + hsync-len = <40>; + hback-porch = <160>; + vfront-porch = <40>; + vsync-len = <10>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + timing_4kp120: timing1 { + clock-frequency = <1188000000>; + hactive = <3840>; + vactive = <2160>; + hfront-porch = <240>; + hsync-len = <80>; + hback-porch = <240>; + vfront-porch = <40>; + vsync-len = <10>; + vback-porch = <40>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + + vcc3v3_edp_bl: vcc3v3-edp-bl { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_edp_bl"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_edp: vcc3v3-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_edp"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&bt_sco { + status = "okay"; +}; + +&bt_sound { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; +}; + +&edp0 { + force-hpd; + status = "okay"; +}; + +&edp0_in_vp0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "disabled"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "okay"; + dual-channel; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "okay"; +}; + +&edp1_in_vp1 { + status = "disabled"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2s2_2ch { + status = "okay"; +}; + +&route_dsi0 { + status = "disabled"; +}; + +&route_edp0 { + status = "okay"; + connect = <&vp0_out_edp0>; +}; + +&route_edp1 { + status = "okay"; + connect = <&vp0_out_edp1>; +}; + +&route_hdmi0 { + status = "disabled"; +}; + +&route_hdmi1 { + status = "disabled"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; +}; + +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp2 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; diff --git a/rk3588-evb1-lp4-v10-ipc-6x-linux.dts b/rk3588-evb1-lp4-v10-ipc-6x-linux.dts new file mode 100644 index 0000000..2dcef19 --- /dev/null +++ b/rk3588-evb1-lp4-v10-ipc-6x-linux.dts @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-ipc.dtsi" +#include "rk3588-evb1-cam-6x.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; +}; + +&backlight { + status = "disabled"; +}; + +&combphy0_ps { + status = "disabled"; +}; + +&combphy1_ps { + status = "disabled"; +}; + +&combphy2_psu { + status = "disabled"; +}; + +&dp0 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi0_panel { + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; +}; + +>1x { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; +}; + +&i2s5_8ch { + status = "disabled"; +}; + +&i2s6_8ch { + status = "disabled"; +}; + +&jpegd { + status = "disabled"; +}; + +&jpegd_mmu { + status = "disabled"; +}; + +&leds { + status = "disabled"; +}; + +&pcie2x1l0 { + status = "disabled"; +}; + +&pcie2x1l1 { + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&rkvdec0 { + status = "disabled"; +}; + +&rkvdec0_mmu { + status = "disabled"; +}; + +&rkvdec1_mmu { + status = "disabled"; +}; + +&rkvdec_ccu { + status = "disabled"; +}; + +&rk_headset { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&uart8 { + status = "disabled"; +}; + +&usbdp_phy1 { + status = "disabled"; +}; + +&usbdp_phy1_dp { + status = "disabled"; +}; + +&usbdp_phy1_u3 { + status = "disabled"; +}; + +&usbdrd3_1 { + status = "disabled"; +}; + +&usbdrd_dwc3_1 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&u2phy1 { + status = "disabled"; +}; + +&u2phy1_otg { + status = "disabled"; +}; + +&u2phy2 { + status = "disabled"; +}; + +&u2phy2_host { + status = "disabled"; +}; + +&u2phy3 { + status = "disabled"; +}; + +&u2phy3_host { + status = "disabled"; +}; + +&vdpu { + status = "disabled"; +}; + +&vdpu_mmu { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; +}; diff --git a/rk3588-evb1-lp4-v10-linux-amp.dts b/rk3588-evb1-lp4-v10-linux-amp.dts new file mode 100644 index 0000000..23ec157 --- /dev/null +++ b/rk3588-evb1-lp4-v10-linux-amp.dts @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-amp.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; + + cpus { + cpu-map { + cluster0 { + /delete-node/ core3; + }; + }; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x02000000 0x0 0x06400000>, + <0x0 0x09400000 0x0 0xe6c00000>, + <0x1 0x00000000 0x1 0x00000000>, + <0x2 0xf0000000 0x0 0x10000000>; + }; +}; + +&arm_pmu { + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, + <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; +}; + +/delete-node/ &cpu_l3; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&vcc_1v8_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + diff --git a/rk3588-evb1-lp4-v10-linux-ipc.dts b/rk3588-evb1-lp4-v10-linux-ipc.dts new file mode 100644 index 0000000..20fe7f6 --- /dev/null +++ b/rk3588-evb1-lp4-v10-linux-ipc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-ipc.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10-linux-ipc", "rockchip,rk3588"; +}; diff --git a/rk3588-evb1-lp4-v10-linux.dts b/rk3588-evb1-lp4-v10-linux.dts new file mode 100644 index 0000000..955fd53 --- /dev/null +++ b/rk3588-evb1-lp4-v10-linux.dts @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&vcc_1v8_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vcc_3v3_s0 { + /delete-property/ regulator-state-mem; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; diff --git a/rk3588-evb1-lp4-v10-lt6911uxc-dual-mipi.dts b/rk3588-evb1-lp4-v10-lt6911uxc-dual-mipi.dts new file mode 100644 index 0000000..4894f1b --- /dev/null +++ b/rk3588-evb1-lp4-v10-lt6911uxc-dual-mipi.dts @@ -0,0 +1,326 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK3588 EVB V10 Extboard"; + compatible = "rockchip,rk3588-evb1-lp4-lt6911uxc-dual-mipi", "rockchip,rk3588"; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "CLK_CAMERA_24MHZ"; + #clock-cells = <0>; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <<6911uxc_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi_in1: endpoint@1 { + reg = <1>; + remote-endpoint = <<6911uxc_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + lt6911uxc: lt6911uxc@2b { + compatible = "lontium,lt6911uxc"; + status = "okay"; + reg = <0x2b>; + clocks = <&ext_cam_clk>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <<6911uxc_pin_1>; + interrupt-parent = <&gpio1>; + interrupts = ; + // reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + // power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HDMI-MIPI2"; + rockchip,camera-module-lens-name = "LT6911UXC-2"; + + multi-dev-info { + dev-idx-l = <4>; + dev-idx-r = <2>; + combine-idx = <2>; + pixel-offset = <0>; + dev-num = <2>; + }; + + port { + lt6911uxc_out0: endpoint { + remote-endpoint = <&hdmi_mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + lt6911uxc_1: lt6911uxc_1@2b { + compatible = "lontium,lt6911uxc"; + status = "okay"; + reg = <0x2b>; + clocks = <&ext_cam_clk>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <<6911uxc_pin>; + interrupt-parent = <&gpio1>; + interrupts = ; + // reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + // power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + // plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "HDMI-MIPI0"; + rockchip,camera-module-lens-name = "LT6911UXC-1"; + + multi-dev-info { + dev-idx-l = <1>; + dev-idx-r = <0>; + combine-idx = <0>; + pixel-offset = <0>; + dev-num = <2>; + }; + + port { + lt6911uxc_out1: endpoint { + remote-endpoint = <&hdmi_mipi_in1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&mipi0_csi2_hw { + status = "okay"; +}; + +&mipi1_csi2_hw { + status = "okay"; +}; + +&mipi2_csi2_hw { + status = "okay"; +}; + +&mipi3_csi2_hw { + status = "okay"; +}; + +&mipi4_csi2_hw { + status = "okay"; +}; + +&mipi5_csi2_hw { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + hdmiin { + lt6911uxc_pin: lt6911uxc-pin { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lt6911uxc_pin_1: lt6911uxc-pin-1 { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588-evb1-lp4-v10-lt6911uxe.dts b/rk3588-evb1-lp4-v10-lt6911uxe.dts new file mode 100644 index 0000000..d33e2bf --- /dev/null +++ b/rk3588-evb1-lp4-v10-lt6911uxe.dts @@ -0,0 +1,277 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK3588 EVB V10 Extboard"; + compatible = "rockchip,rk3588-evb1-lp4-v10-lt6911uxe", "rockchip,rk3588"; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; + + ext_cam_clk: external-camera-clock { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "CLK_CAMERA_24MHZ"; + #clock-cells = <0>; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <<6911uxe_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <<6911uxe_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + lt6911uxe_1: lt6911uxe_1@2b { + compatible = "lontium,lt6911uxe"; + status = "okay"; + reg = <0x2b>; + clocks = <&ext_cam_clk>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <<6911uxe_pin_1>; + interrupt-parent = <&gpio1>; + interrupts = ; + // reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + // power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HDMI-MIPI2"; + rockchip,camera-module-lens-name = "LT6911UXE-2"; + port { + lt6911uxe_out1: endpoint { + remote-endpoint = <&hdmi_mipi2_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + lt6911uxe: lt6911uxe@2b { + compatible = "lontium,lt6911uxe"; + status = "okay"; + reg = <0x2b>; + clocks = <&ext_cam_clk>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <<6911uxe_pin>; + interrupt-parent = <&gpio1>; + interrupts = ; + // reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + // power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + // plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "HDMI-MIPI0"; + rockchip,camera-module-lens-name = "LT6911UXC-0"; + + port { + lt6911uxe_out0: endpoint { + remote-endpoint = <&hdmi_mipi0_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + hdmiin { + lt6911uxe_pin: lt6911uxe-pin { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + lt6911uxe_pin_1: lt6911uxe-pin-1 { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts b/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts new file mode 100644 index 0000000..9922343 --- /dev/null +++ b/rk3588-evb1-lp4-v10-rk628-hdmi2csi.dts @@ -0,0 +1,264 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK628 HDMI to MIPI Extboard"; + compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + /delete-property/ gpio; + /delete-property/ pinctrl-0; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + /delete-property/ gpio; + /delete-property/ pinctrl-0; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + /delete-property/ gpio; + /delete-property/ pinctrl-0; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmiin_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi_mipi0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&hdmiin_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + rk628_csi_1: rk628_csi_1@50 { + reg = <0x50>; + compatible = "rockchip,rk628-csi-v4l2"; + status = "okay"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&rk628_pin_1>; + interrupt-parent = <&gpio1>; + interrupts = ; + enable-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>; + continues-clk = <1>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HDMI-MIPI2"; + rockchip,camera-module-lens-name = "RK628-CSI"; + port { + hdmiin_out1: endpoint { + remote-endpoint = <&hdmi_mipi2_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + rk628_csi: rk628_csi@50 { + reg = <0x50>; + compatible = "rockchip,rk628-csi-v4l2"; + status = "okay"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&rk628_pin>; + interrupt-parent = <&gpio2>; + interrupts = ; + enable-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>; + continues-clk = <1>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HDMI-MIPI"; + rockchip,camera-module-lens-name = "RK628-CSI"; + port { + hdmiin_out0: endpoint { + remote-endpoint = <&hdmi_mipi0_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + hdmiin { + rk628_pin: rk628-pin { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + rk628_pin_1: rk628-pin-1 { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588-evb1-lp4-v10.dts b/rk3588-evb1-lp4-v10.dts new file mode 100644 index 0000000..b053e92 --- /dev/null +++ b/rk3588-evb1-lp4-v10.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb1-lp4.dtsi" +#include "rk3588-evb1-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB1 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb1-lp4-v10", "rockchip,rk3588"; +}; + +&bt_sco { + status = "okay"; +}; + +&bt_sound { + status = "okay"; +}; + +&i2s2_2ch { + status = "okay"; +}; diff --git a/rk3588-evb1-lp4.dtsi b/rk3588-evb1-lp4.dtsi new file mode 100644 index 0000000..a10dad3 --- /dev/null +++ b/rk3588-evb1-lp4.dtsi @@ -0,0 +1,783 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-dual.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm9 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1_hpd>; + hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x43>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c6 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm9 { + pinctrl-0 = <&pwm9m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; +}; + +&sata0 { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588-evb2-imx415.dtsi b/rk3588-evb2-imx415.dtsi new file mode 100644 index 0000000..acff4ea --- /dev/null +++ b/rk3588-evb2-imx415.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + ircut-close-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + vcc_mipidphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidphy0_pwr>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidphy0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&cam_ircut0>; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&pinctrl { + cam { + mipidphy0_pwr: mipidphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/rk3588-evb2-lp4-v10-edp.dts b/rk3588-evb2-lp4-v10-edp.dts new file mode 100644 index 0000000..9ea5036 --- /dev/null +++ b/rk3588-evb2-lp4-v10-edp.dts @@ -0,0 +1,137 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Rockchip Electronics Co., Ltd. + +/dts-v1/; + +#include "rk3588-evb2-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB2 LP4 V10 eDP Board"; + compatible = "rockchip,rk3588-evb2-lp4-v10-edp", "rockchip,rk3588"; + + panel-edp1 { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <120>; + height-mm = <160>; + + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp1: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + + vcc3v3_lcd: vcc3v3-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + vin-supply = <&vcc_3v3_s0>; + }; +}; + +&backlight { + enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1_in_vp0 { + status = "disabled"; +}; + +&dp1_in_vp1 { + status = "okay"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp1>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "disabled"; +}; + +&edp1_in_vp2 { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2c6 { + clock-frequency = <400000>; + status = "okay"; + + gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + }; +}; + +&vcc3v3_lcd_n { + /delete-property/ gpio; +}; diff --git a/rk3588-evb2-lp4-v10-edp2dp.dts b/rk3588-evb2-lp4-v10-edp2dp.dts new file mode 100644 index 0000000..83090d7 --- /dev/null +++ b/rk3588-evb2-lp4-v10-edp2dp.dts @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Rockchip Electronics Co., Ltd. + +/dts-v1/; + +#include "rk3588-evb2-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB2 LP4 V10 eDP to DP Board"; + compatible = "rockchip,rk3588-evb2-lp4-v10-edp2dp", "rockchip,rk3588"; + + dp-con { + compatible = "dp-connector"; + status = "okay"; + + port { + dp_con_in_edp0: endpoint { + remote-endpoint = <&edp0_out_dp_con>; + }; + }; + }; + + edp0-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip-edp-sound"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx3>; + }; + + simple-audio-card,codec { + sound-dai = <&edp0 1>; + }; + }; +}; + +&edp0 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_hpd>; + #sound-dai-cells = <1>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_dp_con: endpoint { + remote-endpoint = <&dp_con_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&spdif_tx3 { + status = "okay"; +}; diff --git a/rk3588-evb2-lp4-v10-linux.dts b/rk3588-evb2-lp4-v10-linux.dts new file mode 100644 index 0000000..6f2ba93 --- /dev/null +++ b/rk3588-evb2-lp4-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb2-lp4.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB2 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb2-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb2-lp4-v10.dts b/rk3588-evb2-lp4-v10.dts new file mode 100644 index 0000000..56e9448 --- /dev/null +++ b/rk3588-evb2-lp4-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb2-lp4.dtsi" +#include "rk3588-evb2-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB2 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb2-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb2-lp4.dtsi b/rk3588-evb2-lp4.dtsi new file mode 100644 index 0000000..809c487 --- /dev/null +++ b/rk3588-evb2-lp4.dtsi @@ -0,0 +1,549 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-dual.dtsi" + +/ { + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm9 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_LOW>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm3 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + pinctrl-0 = <&dp0m2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound { + status = "okay"; +}; + +&dp1 { + pinctrl-0 = <&dp1m2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x45>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c6 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclk &i2s2m0_lrck &i2s2m0_sdi &i2s2m0_sdo>; + status = "disabled"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pdm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm0m0_clk + &pdm0m0_sdi0>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm3 { + status = "okay"; + pinctrl-0 = <&pwm3m1_pins>; +}; + +&pwm9 { + pinctrl-0 = <&pwm9m2_pins>; + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + +&vcc3v3_lcd_n { + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + enable-active-high; +}; diff --git a/rk3588-evb3-imx415.dtsi b/rk3588-evb3-imx415.dtsi new file mode 100644 index 0000000..acff4ea --- /dev/null +++ b/rk3588-evb3-imx415.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + ircut-close-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + vcc_mipidphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidphy0_pwr>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidphy0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&cam_ircut0>; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&pinctrl { + cam { + mipidphy0_pwr: mipidphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/rk3588-evb3-lp5-v10-edp-linux.dts b/rk3588-evb3-lp5-v10-edp-linux.dts new file mode 100644 index 0000000..9d27fbf --- /dev/null +++ b/rk3588-evb3-lp5-v10-edp-linux.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Rockchip Electronics Co., Ltd. + +/dts-v1/; + +#include "rk3588-evb3-lp5.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB3 LP5 V10 EDP Board"; + compatible = "rockchip,rk3588-evb3-lp5-v10-edp-linux", "rockchip,rk3588"; + + panel-edp0 { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <120>; + height-mm = <160>; + + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + + vcc3v3_lcd: vcc3v3-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + vin-supply = <&vcc_3v3_s0>; + }; +}; + +&backlight { + enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; +}; + +&dsi0 { + status = "disabled"; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&hdptxphy0 { + lane-polarity-invert = <0 1 0 0>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + }; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m1_pins>; +}; + +&vcc3v3_lcd_n { + /delete-property/ gpio; +}; diff --git a/rk3588-evb3-lp5-v10-edp.dts b/rk3588-evb3-lp5-v10-edp.dts new file mode 100644 index 0000000..a5ee38a --- /dev/null +++ b/rk3588-evb3-lp5-v10-edp.dts @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2021 Rockchip Electronics Co., Ltd. + +/dts-v1/; + +#include "rk3588-evb3-lp5.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB3 LP5 V10 EDP Board"; + compatible = "rockchip,rk3588-evb3-lp5-v10-edp", "rockchip,rk3588"; + + panel-edp0 { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <120>; + height-mm = <160>; + + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + + vcc3v3_lcd: vcc3v3-lcd { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + vin-supply = <&vcc_3v3_s0>; + }; +}; + +&backlight { + enable-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; +}; + +&dsi0 { + status = "disabled"; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +>1x { + status = "disabled"; +}; + +&hdptxphy0 { + lane-polarity-invert = <0 1 0 0>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + }; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m1_pins>; +}; + +&vcc3v3_lcd_n { + /delete-property/ gpio; +}; diff --git a/rk3588-evb3-lp5-v10-linux.dts b/rk3588-evb3-lp5-v10-linux.dts new file mode 100644 index 0000000..26d6a69 --- /dev/null +++ b/rk3588-evb3-lp5-v10-linux.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb3-lp5.dtsi" +#include "rk3588-linux.dtsi" +#include "rk3588-evb3-imx415.dtsi" + +/ { + model = "Rockchip RK3588 EVB3 LP5 V10 Board"; + compatible = "rockchip,rk3588-evb3-lp5-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb3-lp5-v10.dts b/rk3588-evb3-lp5-v10.dts new file mode 100644 index 0000000..95f3057 --- /dev/null +++ b/rk3588-evb3-lp5-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb3-lp5.dtsi" +#include "rk3588-android.dtsi" +#include "rk3588-evb3-imx415.dtsi" + +/ { + model = "Rockchip RK3588 EVB3 LP5 V10 Board"; + compatible = "rockchip,rk3588-evb3-lp5-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb3-lp5.dtsi b/rk3588-evb3-lp5.dtsi new file mode 100644 index 0000000..3603c26 --- /dev/null +++ b/rk3588-evb3-lp5.dtsi @@ -0,0 +1,1240 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-dual.dtsi" + +/ { + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm5 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio0 RK_PD2 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&backlight { + pwms = <&pwm15 0 25000 0>; + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp1_sound { + status = "okay"; +}; + +&dp1 { + pinctrl-0 = <&dp1m2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio4 RK_PA3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + phy-c-option; + dsi,lanes = <3>; + + panel-init-sequence = [ + 23 00 02 FF 20 + 23 00 02 FB 01 + 23 00 02 05 D9 + /* VGH=17V */ + 23 00 02 07 78 + /* VGL=-14V */ + 23 00 02 08 5A + /* EN_VMODGATE2=1 */ + 23 00 02 0D 63 + /* VGH=16V */ + 23 00 02 0E 91 + /* VGL=-13V */ + 23 00 02 0F 73 + /* GVDD=5.2V */ + 23 00 02 95 EB + 23 00 02 96 EB + /* Disable VDDI LV */ + 23 00 02 30 11 + /* ISOP */ + 23 00 02 6D 66 + /* EN_GMACP */ + 23 00 02 75 A2 + /* V128 */ + 23 00 02 77 3B + /* R(+) */ + 29 00 11 B0 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B1 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B2 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B3 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* G(+) */ + 29 00 11 B4 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B5 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B6 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B7 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* B(+) */ + 29 00 11 B8 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B9 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 BA 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D BB 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* CMD2_Page1 */ + 23 00 02 FF 21 + 23 00 02 FB 01 + /* R(-) */ + 29 00 11 B0 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B1 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B2 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B3 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* G(-) */ + 29 00 11 B4 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B5 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B6 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B7 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* B(-) */ + 29 00 11 B8 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B9 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 BA 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D BB 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + + 29 00 02 FF 24 + 29 00 02 FB 01 + /* VGL */ + 29 00 02 00 00 + 29 00 02 01 00 + /* VDDO */ + 29 00 02 02 1C + 29 00 02 03 1C + /* VDDE */ + 29 00 02 04 1D + 29 00 02 05 1D + /* STV0 */ + 29 00 02 06 04 + 29 00 02 07 04 + /* CLK8 */ + 29 00 02 08 0F + 29 00 02 09 0F + /* CLK6 */ + 29 00 02 0A 0E + 29 00 02 0B 0E + /* CLK4 */ + 29 00 02 0C 0D + 29 00 02 0D 0D + /* CLK2 */ + 29 00 02 0E 0C + 29 00 02 0F 0C + /* STV2 */ + 29 00 02 10 08 + 29 00 02 11 08 + + 29 00 02 12 00 + 29 00 02 13 00 + 29 00 02 14 00 + 29 00 02 15 00 + /* VGL */ + 29 00 02 16 00 + 29 00 02 17 00 + /* VDDO */ + 29 00 02 18 1C + 29 00 02 19 1C + /* VDDE */ + 29 00 02 1A 1D + 29 00 02 1B 1D + /* STV0 */ + 29 00 02 1C 04 + 29 00 02 1D 04 + /* CLK7 */ + 29 00 02 1E 0F + 29 00 02 1F 0F + /* CLK5 */ + 29 00 02 20 0E + 29 00 02 21 0E + /* CLK3 */ + 29 00 02 22 0D + 29 00 02 23 0D + /* CLK1 */ + 29 00 02 24 0C + 29 00 02 25 0C + /* STV1 */ + 29 00 02 26 08 + 29 00 02 27 08 + + 29 00 02 28 00 + 29 00 02 29 00 + 29 00 02 2A 00 + 29 00 02 2B 00 + /* STV0 */ + 29 00 02 2D 20 + 29 00 02 2F 0A + 29 00 02 30 44 + 29 00 02 33 0C + 29 00 02 34 32 + + 29 00 02 37 44 + 29 00 02 38 40 + 29 00 02 39 00 + 29 00 02 3A 50 + 29 00 02 3B 50 + 29 00 02 3D 42 + /* STV */ + 29 00 02 3F 06 + 29 00 02 43 06 + + 29 00 02 47 66 + 29 00 02 4A 50 + 29 00 02 4B 50 + 29 00 02 4C 91 + /* GCK */ + 29 00 02 4D 21 + 29 00 02 4E 43 + 29 00 02 51 12 + 29 00 02 52 34 + 29 00 03 55 82 02 + 29 00 02 56 04 + 29 00 02 58 21 + 29 00 02 59 30 + 29 00 02 5A 50 + 29 00 02 5B 50 + 29 00 03 5E 00 06 + 29 00 02 5F 00 + /* EN_LFD_SOURCE=0 */ + 29 00 02 65 82 + /* VDDO, VDDE */ + 29 00 02 7E 20 + 29 00 02 7F 3C + 29 00 02 82 04 + 29 00 02 97 C0 + + 29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00 + /* qclk=96/5 Mhz */ + 29 00 02 91 44 + 29 00 02 92 55 + 29 00 02 93 1A + 29 00 02 94 5F + /* SOG_HBP */ + 29 00 02 D7 55 + 29 00 02 DA 0A + 29 00 02 DE 08 + /* Normal */ + 29 00 02 DB 05 + 29 00 02 DC 55 + 29 00 02 DD 22 + /* Line N */ + 29 00 02 DF 05 + 29 00 02 E0 55 + /* Line N+1 */ + 29 00 02 E1 05 + 29 00 02 E2 55 + /* TP0 */ + 29 00 02 E3 05 + 29 00 02 E4 55 + /* TP3 */ + 29 00 02 E5 05 + 29 00 02 E6 55 + /* Gate EQ */ + 29 00 02 5C 00 + 29 00 02 5D 00 + /* TP3 */ + 29 00 02 8D 00 + 29 00 02 8E 00 + /* No Sync @ TP */ + 29 00 02 B5 90 + + 29 00 02 FF 25 + 29 00 02 FB 01 + /* disable auto_vbp_vfp */ + 29 00 02 05 00 + /* ESD_DET_ERR_SEL */ + 29 00 02 19 07 + /* DP_N_GCK */ + 29 00 02 1F 50 + 29 00 02 20 50 + /* DP_N_1_GCK */ + 29 00 02 26 50 + 29 00 02 27 50 + /* TP0_GCK */ + 29 00 02 33 50 + 29 00 02 34 50 + /* TP3 GCK/MUX=1 */ + 29 00 02 3F E0 + /* TP3_GCK_START_LINE */ + 29 00 02 40 00 + /* TP3_STV */ + 29 00 02 44 00 + 29 00 02 45 40 + /* TP3_GCK */ + 29 00 02 48 50 + 29 00 02 49 50 + /* LSTP0 */ + 29 00 02 5B 00 + 29 00 02 5C 00 + 29 00 02 5D 00 + 29 00 02 5E D0 + + 29 00 02 61 50 + 29 00 02 62 50 + /* en_vfp_addvsync */ + 29 00 02 F1 10 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + /* PWRONOFF */ + /* STV */ + 29 00 02 64 16 + /* CLR */ + 29 00 02 67 16 + /* GCK */ + 29 00 02 6A 16 + /* POL */ + 29 00 02 70 30 + /* ABOFF */ + 29 00 02 A2 F3 + 29 00 02 A3 FF + 29 00 02 A4 FF + 29 00 02 A5 FF + /* Long_V_TIMING disable */ + 29 00 02 D6 08 + /* CMD2,Page6 */ + 29 00 02 FF 26 + 29 00 02 FB 01 + /* TPEN */ + 29 00 02 00 81 + /* 90Hz */ + 29 00 02 01 30 + + 29 00 02 02 31 + 29 00 02 0A F2 + //Table A (90Hz) + 29 00 02 04 28 + 29 00 02 06 3C + 29 00 02 0C 0B + 29 00 02 0D 0C + 29 00 02 0F 00 + 29 00 02 11 00 + 29 00 02 12 50 + 29 00 02 13 AE + 29 00 02 14 A6 + 29 00 02 16 10 + 29 00 02 19 08 + 29 00 02 1A FF + 29 00 02 1B 08 + 29 00 02 1C 80 + 29 00 02 22 00 + 29 00 02 23 00 + 29 00 02 2A 08 + 29 00 02 2B FF + + 29 00 02 1D 00 + 29 00 02 1E 55 + 29 00 02 1F 55 + 29 00 02 24 00 + 29 00 02 25 55 + 29 00 02 2F 05 + 29 00 02 30 55 + 29 00 02 31 05 + 29 00 02 32 6D + 29 00 02 39 00 + 29 00 02 3A 55 + /* Table B (60Hz,81*1+101*19=2000, Extra=20) */ + 29 00 02 8B 28 + 29 00 02 8C 13 + 29 00 02 8D 0A + 29 00 02 8F 0A + 29 00 02 91 00 + 29 00 02 92 50 + 29 00 02 93 51 + 29 00 02 94 65 + 29 00 02 96 10 + 29 00 02 99 0A + 29 00 02 9A 7F + 29 00 02 9B 0A + 29 00 02 9C 0C + 29 00 02 9D 0A + 29 00 02 9E 7F + + 29 00 02 3F 00 + 29 00 02 40 75 + 29 00 02 41 75 + 29 00 02 42 75 + 29 00 02 43 00 + 29 00 02 44 75 + 29 00 02 45 05 + 29 00 02 46 75 + 29 00 02 47 05 + 29 00 02 48 8D + 29 00 02 49 00 + 29 00 02 4A 75 + /* STV0 */ + 29 00 02 4D 5D + 29 00 02 4E 60 + /* STV */ + 29 00 02 4F 5D + 29 00 02 50 60 + /* GCK */ + 29 00 02 51 70 + 29 00 02 52 60 + /* DP_N_GCK */ + 29 00 02 56 70 + 29 00 02 58 60 + /* DP_N_1_GCK */ + 29 00 02 5B 70 + 29 00 02 5C 60 + /* TP0_GCK */ + 29 00 02 60 70 + 29 00 02 61 60 + /* TP3_GCK */ + 29 00 02 64 70 + 29 00 02 65 60 + /* LSTP0 */ + 29 00 02 72 70 + 29 00 02 73 60 + /* PRZ1 */ + 29 00 02 20 01 + /* PRZ3 */ + /* Rescan=3 */ + 29 00 02 33 11 + 29 00 02 34 78 + 29 00 02 35 16 + /* DLH */ + 29 00 02 C8 04 + 29 00 02 C9 80 + 29 00 02 CA 4E + 29 00 02 CB 00 + 29 00 02 A9 4C + 29 00 02 AA 47 + /* CMD2,Page7 */ + 29 00 02 FF 27 + 29 00 02 FB 01 + /* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */ + 29 00 02 56 06 + /* FR0(60Hz) */ + 29 00 02 58 80 + 29 00 02 59 53 + 29 00 02 5A 00 + 29 00 02 5B 14 + 29 00 02 5C 00 + 29 00 02 5D 01 + 29 00 02 5E 20 + 29 00 02 5F 10 + 29 00 02 60 00 + 29 00 02 61 1D + 29 00 02 62 00 + 29 00 02 63 01 + 29 00 02 64 24 + 29 00 02 65 1C + 29 00 02 66 00 + 29 00 02 67 01 + 29 00 02 68 25 + /* FR1(90Hz) */ + 29 00 02 78 80 + 29 00 02 79 73 + 29 00 02 7A 00 + 29 00 02 7B 14 + 29 00 02 7C 00 + 29 00 02 7D 02 + 29 00 02 7E 20 + 29 00 02 7F 21 + 29 00 02 80 00 + 29 00 02 81 2A + 29 00 02 82 00 + 29 00 02 83 01 + 29 00 02 84 1C + 29 00 02 85 28 + 29 00 02 86 00 + 29 00 02 87 01 + 29 00 02 88 1D + + 29 00 02 00 00 + 29 00 02 C3 00 + /* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */ + 29 00 02 D1 24 + 29 00 02 D2 53 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + 29 00 02 01 05 + 29 00 02 02 55 + /* TP0 */ + 29 00 02 03 05 + 29 00 02 04 75 + /* TP3 */ + 29 00 02 05 05 + 29 00 02 06 75 + /* PEN_EN=1, UL_FREQ=0 */ + 29 00 02 22 2F + /* 90Hz */ + 29 00 02 23 11 + /* FR0 (60Hz) */ + 29 00 02 24 00 + 29 00 02 25 75 + 29 00 02 27 00 + 29 00 02 28 1A + 29 00 02 29 00 + 29 00 02 2A 1A + 29 00 02 2B 00 + 29 00 02 2D 1A + /* FR1 (90Hz) */ + 29 00 02 2F 00 + 29 00 02 30 55 + 29 00 02 32 00 + 29 00 02 33 1A + 29 00 02 34 00 + 29 00 02 35 1A + 29 00 02 36 00 + 29 00 02 37 1A + /* CMD2,Page3 */ + 29 00 02 FF 23 + 29 00 02 FB 01 + /* DBV=12 bit */ + 29 00 02 00 80 + /* PWM frequency */ + 29 00 02 07 00 + /* CMD3,PageA */ + 29 00 02 FF E0 + 29 00 02 FB 01 + /* VCOM Driving Ability */ + 29 00 02 14 60 + 29 00 02 16 C0 + /* CMD3,PageB */ + 29 00 02 FF F0 + 29 00 02 FB 01 + /* slave osc workaround */ + 29 00 02 3A 08 + /* CMD3,PageC */ + 29 00 02 FF D0 + 29 00 02 FB 01 + 29 00 02 1C 88 + 29 00 02 1D 08 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Only Write Slave */ + 29 00 02 B9 01 + /* CMD2,Page0 */ + 29 00 02 FF 20 + 29 00 02 FB 01 + 29 00 02 18 40 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Write Master & Slave */ + 29 00 02 B9 02 + 29 00 02 35 00 + 29 00 03 51 00 FF + 29 00 02 53 24 + 29 00 02 55 00 + 29 00 02 BB 13 + /* VBP+VFP=121 */ + 29 00 06 3B 03 5F 1A 04 04 + /* CMD2,Page5 */ + 29 00 02 FF 25 + /* FRM */ + 29 00 02 EC 00 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + 05 FF 01 11 + 05 FF 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <241300000>; + hactive = <1200>; + vactive = <2000>; + hfront-porch = <31>; + hsync-len = <4>; + hback-porch = <32>; + vfront-porch = <26>; + vsync-len = <2>; + vback-porch = <93>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0m1_xfer>; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "okay"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "okay"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio2_b2>; + //irq-gpio = <&gpio2 RK_PB2 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + status = "okay"; + reg = <0x68>; + irq-gpio = <&gpio2 RK_PB5 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <9>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + status = "okay"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <9>; + }; +}; + +&i2c2 { + status = "okay"; + + usbc0: husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m4_xfer>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio4 RK_PB1 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c7 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pdm0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pdm0m0_clk + &pdm0m0_sdi0>; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sensor { + mh248_irq_gpio: mh248-irq-gpio { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + mpu6500_irq_gpio: mpu6500_irq_gpio { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm5 { + pinctrl-0 = <&pwm5m1_pins>; + status = "okay"; +}; + +&pwm15 { + pinctrl-0 = <&pwm15m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&sata1 { + status = "okay"; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588-evb4-lp4-v10-linux.dts b/rk3588-evb4-lp4-v10-linux.dts new file mode 100644 index 0000000..5969ecc --- /dev/null +++ b/rk3588-evb4-lp4-v10-linux.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb4-lp4.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB4 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/rk3588-evb4-lp4-v10.dts b/rk3588-evb4-lp4-v10.dts new file mode 100644 index 0000000..043e77e --- /dev/null +++ b/rk3588-evb4-lp4-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb4-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB4 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb4-lp4.dtsi b/rk3588-evb4-lp4.dtsi new file mode 100644 index 0000000..ef5dd89 --- /dev/null +++ b/rk3588-evb4-lp4.dtsi @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm14 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_au5426: vcc3v3-au5426 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_au5426"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; +}; + +&backlight { + pwms = <&pwm3 0 25000 0>; + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m3_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + compatible = "rockchip,rk3588-pcie-ep"; + memory-region = <&dma_trans>; + busno = <1>; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&u2phy2 { + status = "disabled"; +}; + +&u2phy3 { + status = "disabled"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + status = "disabled"; +}; + +&u2phy3_host { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588-evb5-lp4-v10-linux.dts b/rk3588-evb5-lp4-v10-linux.dts new file mode 100644 index 0000000..6900d3b --- /dev/null +++ b/rk3588-evb5-lp4-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb5-lp4.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB4 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb5-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb5-lp4-v10.dts b/rk3588-evb5-lp4-v10.dts new file mode 100644 index 0000000..70e7803 --- /dev/null +++ b/rk3588-evb5-lp4-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb5-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB4 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb5-lp4.dtsi b/rk3588-evb5-lp4.dtsi new file mode 100644 index 0000000..07aaf22 --- /dev/null +++ b/rk3588-evb5-lp4.dtsi @@ -0,0 +1,300 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-dual.dtsi" + +/ { + dsm_sound: dsm-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,dsm-sound"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + sndcpu: simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + sndcodec: simple-audio-card,codec { + sound-dai = <&acdcdig_dsm>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm9 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&acdcdig_dsm { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp0 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2s3_2ch { + status = "okay"; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x2 { + reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <2>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pinctrl { + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm9 { + pinctrl-0 = <&pwm9m2_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&spdif_tx1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m0_tx>; +}; + +&spdif_tx1_dc { + status = "okay"; +}; + +&spdif_tx1_sound { + status = "okay"; +}; + +&usbdp_phy0 { + status = "disabled"; +}; + +&usbdp_phy0_dp { + status = "disabled"; +}; + +&usbdp_phy0_u3 { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588-evb6-lp4-v10-linux.dts b/rk3588-evb6-lp4-v10-linux.dts new file mode 100644 index 0000000..ab7a51b --- /dev/null +++ b/rk3588-evb6-lp4-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb6-lp4.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB6 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb6-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb6-lp4-v10.dts b/rk3588-evb6-lp4-v10.dts new file mode 100644 index 0000000..1a846ac --- /dev/null +++ b/rk3588-evb6-lp4-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb6-lp4.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB6 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb6-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb6-lp4.dtsi b/rk3588-evb6-lp4.dtsi new file mode 100644 index 0000000..96b7406 --- /dev/null +++ b/rk3588-evb6-lp4.dtsi @@ -0,0 +1,518 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-dual.dtsi" + +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&avdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; +}; + +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1_hpd>; + hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c6 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&sata0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588-evb7-cam-8x.dtsi b/rk3588-evb7-cam-8x.dtsi new file mode 100644 index 0000000..3923d71 --- /dev/null +++ b/rk3588-evb7-cam-8x.dtsi @@ -0,0 +1,1198 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include +#define LINK_FREQ 700000000 + + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&rk1608_dphy0_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out0>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out1>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out2>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy5 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out3>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy5_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_csi2_input>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&mipi3_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + +&mipi5_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy5_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in5>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + rockchip,combine-index = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds_sditf_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out7>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds_sditf: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_vir0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds_sditf_vir1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + rockchip,combine-index = <1>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds_sditf_vir1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out6>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds_sditf_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&isp0_vir3>; + }; + }; + }; +}; + +&rkcif_mipi_lvds_sditf_vir2 { + address-cells = <1>; + #size-cells = <0>; + status = "okay"; + rockchip,combine-index = <2>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds_sditf_vir2_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out5>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi_lvds_sditf_vir2: endpoint { + remote-endpoint = <&isp1_vir3>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds3 { + status = "okay"; + + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds3_sditf { + status = "okay"; + + port { + mipi3_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir2>; + }; + }; +}; + +&rkcif_mipi_lvds5 { + status = "okay"; + + port { + cif_mipi_in5: endpoint { + remote-endpoint = <&mipi5_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds5_sditf { + status = "okay"; + + port { + mipi5_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir3 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir3: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf_vir1>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_lvds_sditf>; + }; + }; +}; + +&rkisp1_vir2 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir2: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_lvds_sditf>; + }; + }; +}; + +&rkisp1_vir3 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir3: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf_vir2>; + }; + }; +}; + +&pinctrl { + cam { + vcc_cam_2_3_pwr: vcc_cam_2_3_pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc_cam_4_5_pwr: vcc_cam_4_5_pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc_cam_8_9_pwr: vcc_cam_8_9_pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + +/ { + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + vcc_cam_2_3: vcc-cam-2-3 { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam_2_3_pwr>; + regulator-name = "vcc_cam_2_3"; + enable-active-high; + }; + + vcc_cam_4_5: vcc-cam-4-5 { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam_4_5_pwr>; + regulator-name = "vcc_cam_4_5"; + enable-active-high; + }; + + vcc_cam_8_9: vcc-cam-8-9 { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_cam_8_9_pwr>; + regulator-name = "vcc_cam_8_9"; + enable-active-high; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-0 = <&i2c7m0_xfer>; + + /* hardware cam 1 */ + imx464: imx464@10 { + compatible = "sony,imx464"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipicsi1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out: endpoint { + remote-endpoint = <&csidcphy1_in>; + data-lanes = <1 2>; + }; + }; + }; + + /* hardware cam 2 */ + imx464_0: imx464-0@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + avdd-supply = <&vcc_cam_2_3>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out0: endpoint { + remote-endpoint = <&csidphy1_in>; + data-lanes = <1 2>; + }; + }; + }; + + /* hardware cam 3 */ + imx464_1: imx464-1@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + //pinctrl-names = "default"; + //pinctrl-0 = <&mipim0_camera3_clk>; //same + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_cam_2_3>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out1: endpoint { + remote-endpoint = <&csidphy2_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m1_xfer>; + + /* hardware cam 4 */ + imx464_2: imx464-2@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + avdd-supply = <&vcc_cam_4_5>; + pwdn-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out2: endpoint { + remote-endpoint = <&csidphy4_in>; + data-lanes = <1 2>; + }; + }; + }; + + /* hardware cam 5 */ + imx464_3: imx464-3@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + //pinctrl-names = "default"; + //pinctrl-0 = <&mipim0_camera4_clk>; + avdd-supply = <&vcc_cam_4_5>; + pwdn-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <4>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out3: endpoint { + remote-endpoint = <&csidphy5_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-0 = <&i2c2m4_xfer>; + + /* hardware cam 6 */ + imx464_4: imx464-4@1a { + compatible = "sony,imx464"; + status = "disabled"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + //pinctrl-names = "default"; + //pinctrl-0 = <&mipim0_camera1_clk>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <8>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out4: endpoint { + //remote-endpoint = <&mipi_lvds_sditf_vir3>; + data-lanes = <1 2>; + }; + }; + }; + + /* hardware cam 7 */ + imx464_5: imx464-5@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <7>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out5: endpoint { + remote-endpoint = <&mipi_lvds_sditf_vir2_in>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-0 = <&i2c3m0_xfer>; + + /* hardware cam 8 */ + imx464_6: imx464-6@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + //pinctrl-names = "default"; + //pinctrl-0 = <&mipim0_camera1_clk>; + avdd-supply = <&vcc_cam_8_9>; + pwdn-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <6>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out6: endpoint { + remote-endpoint = <&mipi_lvds_sditf_vir1_in>; + data-lanes = <1 2>; + }; + }; + }; + + /* hardware cam 9 */ + imx464_7: imx464-7@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + //pinctrl-names = "default"; + //pinctrl-0 = <&mipim0_camera1_clk>; + avdd-supply = <&vcc_cam_8_9>; + pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <5>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out7: endpoint { + remote-endpoint = <&mipi_lvds_sditf_in>; + data-lanes = <1 2>; + }; + }; + }; + + preisp_dmy: preisp_dmy@37 { + status = "okay"; + compatible = "pisp_dmy"; + reg = <0x37>; + + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + + rockchip,camera-module-index = <10>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + preisp_dmy_out0: endpoint { + remote-endpoint = <&rk1608_in0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&spi4 { + status = "okay"; + //assigned-clocks = <&cru CLK_SPI0>; + //assigned-clock-rates = <100000000>; + //rx-sample-delay-ns = <10>; + //dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m1_cs0 &spi4m1_cs1 &spi4m1_pins>; + + spi_rk1608@0 { + compatible = "rockchip,rk1608"; + status = "okay"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-min-frequency = <16000000>; + + clocks = <&cru CLK_SPI4>; + clock-names = "mclk"; + + firmware-names = "rk1608.rkl"; + + reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + irq-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + //wake-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pwren-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&preisp_irq_gpios &preisp_pwren_gpios + &preisp_reset_gpios &refclk_pins>; + + /* regulator config */ + vdd-core-regulator = "vdd_preisp"; + vdd-core-microvolt = <1150000>; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <0>; + rk1608_out0: endpoint@0 { + reg = <0>; + remote-endpoint = <&rk1608_dphy0_in>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + rk1608_in0: endpoint@0 { + reg = <0>; + remote-endpoint = <&preisp_dmy_out0>; + }; + }; + }; + }; +}; + +&pinctrl { + rk1608_gpios { + preisp_irq_gpios: preisp-irq-gpios { + rockchip,pins = + <1 RK_PC4 0 &pcfg_pull_up>; + }; + preisp_reset_gpios: preisp-reset-gpios { + rockchip,pins = + <1 RK_PD5 0 &pcfg_output_low>; + }; + preisp_pwren_gpios: preisp-pwren-gpios { + rockchip,pins = + <1 RK_PC7 0 &pcfg_pull_up>; + }; + }; +}; + +/{ + mipidphy0: mipidphy0 { + compatible = "rockchip,rk1608-dphy"; + status = "okay"; + //rockchip,grf = <&grf>; + id = <0>; + + cam_nums = <1>; + in_mipi = <1>; + out_mipi = <0>; + link-freqs = /bits/ 64 ; + + /* rk1608 i2c mode */ + sensor_i2c_bus = <3>; + sensor_i2c_addr = <0x36>; + sensor-name = "IMX464"; + + rockchip,camera-module-index = <9>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "TongJu"; + rockchip,camera-module-lens-name = "CHT842-MD"; + + /* virtual-sensor mode */ + link-sensor = <&imx464_7>; + virtual-sub-sensor-config-0 { + id = <1>; + in_mipi = <2>; + out_mipi = <1>; + }; + virtual-sub-sensor-config-1 { + id = <2>; + in_mipi = <3>; + out_mipi = <1>; + }; + /* multi-sensor mode end */ + + format-config-0 { + data_type = <0x2b>; + mipi_lane = <2>; + mipi_lane_out = <4>; + field = <1>; + colorspace = <8>; + code = ; + width = <2712>; + height= <1538>; + hactive = <2712>; + vactive = <4614>; + htotal = <3616>; + vtotal = <4710>; + inch0-info = <2712 1538 0x2b 0x2b 1>; + outch0-info = <2712 4614 0x2b 0x2b 1>; + hcrop = <2560>; + vcrop = <1520>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + rk1608_dphy0_in: endpoint { + remote-endpoint = <&rk1608_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + rk1608_dphy0_out: endpoint { + remote-endpoint = <&csidcphy0_in>; + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + clock-noncontinuous; + link-freqs = /bits/ 64 ; + }; + }; + }; + }; +}; diff --git a/rk3588-evb7-imx415.dtsi b/rk3588-evb7-imx415.dtsi new file mode 100644 index 0000000..f538989 --- /dev/null +++ b/rk3588-evb7-imx415.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/ { + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + vcc_mipidphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidphy0_pwr>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidphy0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&cam_ircut0>; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&pinctrl { + cam { + mipidphy0_pwr: mipidphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/rk3588-evb7-lp4-v10-linux.dts b/rk3588-evb7-lp4-v10-linux.dts new file mode 100644 index 0000000..6d740f1 --- /dev/null +++ b/rk3588-evb7-lp4-v10-linux.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb7-lp4.dtsi" +#include "rk3588-evb7-imx415.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB7 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb7-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts b/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts new file mode 100644 index 0000000..fc23e31 --- /dev/null +++ b/rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux.dts @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb7-lp4.dtsi" +#include "rk3588-ipc.dtsi" +#include "rk3588-evb7-cam-8x.dtsi" + +/ { + model = "Rockchip RK3588-RK1608 EVB7 LP4 V10 Board"; + compatible = "rk3588-evb7-lp4-v10-rk1608-ipc-8x-linux", "rockchip,rk3588"; +}; + +&backlight { + status = "disabled"; +}; + +&dp0 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi0_panel { + status = "disabled"; +}; + +&dsi1_panel { + status = "disabled"; +}; + +>1x { + status = "disabled"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp1 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c6 { + status = "disabled"; +}; + +&i2s5_8ch { + status = "disabled"; +}; + +&i2s6_8ch { + status = "disabled"; +}; + +&jpegd { + status = "disabled"; +}; + +&jpegd_mmu { + status = "disabled"; +}; + +&leds { + status = "disabled"; +}; + +&pwm2 { + status = "disabled"; +}; + +&rkvdec0 { + status = "disabled"; +}; + +&rkvdec0_mmu { + status = "disabled"; +}; + +&rkvdec1_mmu { + status = "disabled"; +}; + +&rkvdec_ccu { + status = "disabled"; +}; + +&rk_headset { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&uart8 { + status = "disabled"; +}; + +&vdpu { + status = "disabled"; +}; + +&vdpu_mmu { + status = "disabled"; +}; + +&wireless_bluetooth { + status = "disabled"; +}; + +&wireless_wlan { + status = "disabled"; +}; + +&es8388_sound { + status = "disabled"; +}; + +&hdmirx_ctrler { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&uart9 { + status = "disabled"; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&sdio { + status = "disabled"; +}; + +&sdio_pwrseq { + status = "disabled"; +}; diff --git a/rk3588-evb7-lp4-v10.dts b/rk3588-evb7-lp4-v10.dts new file mode 100644 index 0000000..a574681 --- /dev/null +++ b/rk3588-evb7-lp4-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb7-lp4.dtsi" +#include "rk3588-evb7-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB7 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb7-lp4-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-evb7-lp4-v11-linux-ipc.dts b/rk3588-evb7-lp4-v11-linux-ipc.dts new file mode 100644 index 0000000..74cf867 --- /dev/null +++ b/rk3588-evb7-lp4-v11-linux-ipc.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb7-lp4.dtsi" +#include "rk3588-evb7-imx415.dtsi" +#include "rk3588-ipc.dtsi" + +/ { + model = "Rockchip RK3588 EVB7 LP4 V11 Board"; + compatible = "rockchip,rk3588-evb7-lp4-v11-linux-ipc", "rockchip,rk3588"; +}; diff --git a/rk3588-evb7-lp4.dtsi b/rk3588-evb7-lp4.dtsi new file mode 100644 index 0000000..9e41ea8 --- /dev/null +++ b/rk3588-evb7-lp4.dtsi @@ -0,0 +1,854 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm1 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + pinctrl-names = "default"; + pinctrl-0 = <&vga_hpdin_l>; + hpd-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1m0_pins>; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x43>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m1_xfer>; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + icm42607_acc: icm_acc@68 { + status = "okay"; + compatible = "icm42607_acc"; + reg = <0x68>; + irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + }; + + icm42607_gyro: icm_gyro@68 { + status = "okay"; + compatible = "icm42607_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + }; +}; + +&i2c5 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c6 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m0_sclk &i2s2m0_lrck &i2s2m0_sdi &i2s2m0_sdo>; + status = "disabled"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vga { + vga_hpdin_l: vga-hpdin-l { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; diff --git a/rk3588-evb7-v11-imx415.dtsi b/rk3588-evb7-v11-imx415.dtsi new file mode 100644 index 0000000..d5772eb --- /dev/null +++ b/rk3588-evb7-v11-imx415.dtsi @@ -0,0 +1,176 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + cam_ircut0: cam_ircut { + status = "okay"; + compatible = "rockchip,ircut"; + ircut-open-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + ircut-close-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + vcc_mipidphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidphy0_pwr>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + imx415: imx415@1a { + compatible = "sony,imx415"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidphy0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + lens-focus = <&cam_ircut0>; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&pinctrl { + cam { + mipidphy0_pwr: mipidphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; diff --git a/rk3588-evb7-v11-linux.dts b/rk3588-evb7-v11-linux.dts new file mode 100644 index 0000000..f4051df --- /dev/null +++ b/rk3588-evb7-v11-linux.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb7-v11.dtsi" +#include "rk3588-evb7-v11-imx415.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB7 V11 Board"; + compatible = "rockchip,rk3588-evb7-v11", "rockchip,rk3588"; +}; diff --git a/rk3588-evb7-v11.dts b/rk3588-evb7-v11.dts new file mode 100644 index 0000000..24ef507 --- /dev/null +++ b/rk3588-evb7-v11.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-evb7-v11.dtsi" +#include "rk3588-evb7-v11-imx415.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 EVB7 V11 Board"; + compatible = "rockchip,rk3588-evb7-v11", "rockchip,rk3588"; +}; diff --git a/rk3588-evb7-v11.dtsi b/rk3588-evb7-v11.dtsi new file mode 100644 index 0000000..5bef210 --- /dev/null +++ b/rk3588-evb7-v11.dtsi @@ -0,0 +1,949 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-evb.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmiin-sound { + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,format = "i2s"; + rockchip,bitclock-master = <&hdmirx_ctrler>; + rockchip,frame-master = <&hdmirx_ctrler>; + rockchip,card-name = "rockchip,hdmiin"; + rockchip,cpu = <&i2s7_8ch>; + rockchip,codec = <&hdmirx_ctrler 0>; + rockchip,jack-det; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm1 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1m0_pins>; + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x43>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + #sound-dai-cells = <1>; + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m1_xfer>; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + icm42607_acc: icm_acc@68 { + status = "okay"; + compatible = "icm42607_acc"; + reg = <0x68>; + irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + }; + + icm42607_gyro: icm_gyro@68 { + status = "okay"; + compatible = "icm42607_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <0>; + }; +}; + +&i2c5 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c6 { + status = "okay"; + + usbc0: husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie20x1_0_clkreqn_m1>; + status = "okay"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_leds_gpio: work-leds-gpio { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + pcie { + pcie20x1_0_clkreqn_m1: pcie20x1-0-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&work_led { + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&work_leds_gpio>; +}; diff --git a/rk3588-ipc.dtsi b/rk3588-ipc.dtsi new file mode 100644 index 0000000..6882afa --- /dev/null +++ b/rk3588-ipc.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588-linux.dtsi" + +&CPU_SLEEP { + status = "disabled"; +}; + +&cluster0_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cluster1_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; + /delete-node/ opp-2256000000; + /delete-node/ opp-2304000000; + /delete-node/ opp-2352000000; + /delete-node/ opp-2400000000; +}; + +&cluster2_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; + /delete-node/ opp-2256000000; + /delete-node/ opp-2304000000; + /delete-node/ opp-2352000000; + /delete-node/ opp-2400000000; +}; + +&dfi { + status = "disabled"; +}; + +&dmc { + status = "disabled"; +}; diff --git a/rk3588-linux.dtsi b/rk3588-linux.dtsi new file mode 100644 index 0000000..97345c0 --- /dev/null +++ b/rk3588-linux.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait rcupdate.rcu_expedited=1 rcu_nocbs=all"; + }; + + cspmu: cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd10c000 0x0 0x1000>, + <0x0 0xfd10d000 0x0 0x1000>, + <0x0 0xfd10e000 0x0 0x1000>, + <0x0 0xfd10f000 0x0 0x1000>, + <0x0 0xfd12c000 0x0 0x1000>, + <0x0 0xfd12d000 0x0 0x1000>, + <0x0 0xfd12e000 0x0 0x1000>, + <0x0 0xfd12f000 0x0 0x1000>; + }; + + debug: debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd104000 0x0 0x1000>, + <0x0 0xfd105000 0x0 0x1000>, + <0x0 0xfd106000 0x0 0x1000>, + <0x0 0xfd107000 0x0 0x1000>, + <0x0 0xfd124000 0x0 0x1000>, + <0x0 0xfd125000 0x0 0x1000>, + <0x0 0xfd126000 0x0 0x1000>, + <0x0 0xfd127000 0x0 0x1000>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + //status = "disabled"; + }; + }; + + minidump: minidump { + compatible = "rockchip,minidump"; + smem-region = <&minidump_smem>; + minidump-region = <&minidump_mem>; + status = "disabled"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 (8 * 0x100000)>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + /* 0x110000 to 0x1f0000 is for ramoops */ + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; /* do not change */ + boot-log-count = <0x1>; /* do not change */ + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + + minidump_smem: minidump-smem@1f0000 { + reg = <0x0 0x1f0000 0x0 0x100>; /* do not change */ + no-map; + status = "disabled"; + }; + + minidump_mem: minidump-mem@c000000 { + reg = <0x0 0x0c000000 0x0 0x2000000>; /* changing according to your project */ + no-map; + status = "disabled"; + }; + + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>; + memory-region-names = "drm-logo"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rng { + status = "okay"; +}; diff --git a/rk3588-nvr-demo-v10-android.dts b/rk3588-nvr-demo-v10-android.dts new file mode 100644 index 0000000..217101b --- /dev/null +++ b/rk3588-nvr-demo-v10-android.dts @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO LP4 V10 Android Board"; + compatible = "rockchip,rk3588-nvr-demo-v10-android", "rockchip,rk3588"; +}; + +&avsd { + status = "okay"; +}; + +&dp0 { + status = "disabled"; +}; + +&dp1_in_vp0 { + status = "disabled"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2s6_8ch { + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&route_dp0 { + status = "okay"; + connect = <&vp2_out_dp0>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&route_dp1 { + status = "disabled"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; + /delete-property/ force-output; + /delete-node/ force_timing; +}; + +&route_hdmi1 { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon = <&u2phy0>; + status = "okay"; +}; diff --git a/rk3588-nvr-demo-v10-cam-4x.dtsi b/rk3588-nvr-demo-v10-cam-4x.dtsi new file mode 100644 index 0000000..708a54b --- /dev/null +++ b/rk3588-nvr-demo-v10-cam-4x.dtsi @@ -0,0 +1,565 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ +/ { + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out2>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out3>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy2_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy4 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam4: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out4>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy4_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy5 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam5: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx464_out5>; + data-lanes = <1 2>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy5_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_csi2_input>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + pinctrl-0 = <&i2c5m3_xfer>; + /* module 77/79 0x1a 78/80 0x36 */ + imx464_2: imx464-2@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + avdd-supply = <&vcc_mipicsi0>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "internal_master"; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_3: imx464-3@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "external_master"; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out3: endpoint { + remote-endpoint = <&mipi_in_ucam3>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&i2c4 { + status = "okay"; + + pinctrl-0 = <&i2c4m3_xfer>; + /* 77/79 0x1a 78/80 0x36 */ + imx464_4: imx464-4@1a { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + avdd-supply = <&vcc_mipicsi1>; + reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "external_master"; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out4: endpoint { + remote-endpoint = <&mipi_in_ucam4>; + data-lanes = <1 2>; + }; + }; + }; + + imx464_5: imx464-5@36 { + compatible = "sony,imx464"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi1>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-sync-mode = "external_master"; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT1980-PX1"; + rockchip,camera-module-lens-name = "SHG102"; + port { + imx464_out5: endpoint { + remote-endpoint = <&mipi_in_ucam5>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&mipi3_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy2_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi3_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in3>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy4_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + +&mipi5_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy5_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi5_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in5>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds3 { + status = "okay"; + + port { + cif_mipi_in3: endpoint { + remote-endpoint = <&mipi3_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds3_sditf { + status = "okay"; + + port { + mipi3_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkcif_mipi_lvds5 { + status = "okay"; + + port { + cif_mipi_in5: endpoint { + remote-endpoint = <&mipi5_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds5_sditf { + status = "okay"; + + port { + mipi5_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + +&rkisp0_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi3_lvds_sditf>; + }; + }; +}; + +&rkisp1_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi5_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588-nvr-demo-v10-ipc-4x-linux.dts b/rk3588-nvr-demo-v10-ipc-4x-linux.dts new file mode 100644 index 0000000..00310c5 --- /dev/null +++ b/rk3588-nvr-demo-v10-ipc-4x-linux.dts @@ -0,0 +1,213 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo.dtsi" +#include "rk3588-ipc.dtsi" +#include "rk3588-nvr-demo-v10-cam-4x.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO LP4 V10 Board"; + compatible = "rockchip,rk3588-nvr-demo-v10-ipc-4x", + "rockchip,rk3588-nvr-demo-v10", "rockchip,rk3588"; +}; + +&combphy0_ps { + status = "disabled"; +}; + +&combphy1_ps { + status = "disabled"; +}; + +&combphy2_psu { + status = "disabled"; +}; + +&dp0 { + status = "disabled"; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dp1_in_vp0 { + status = "disabled"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&gmac1 { + status = "disabled"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi0_sound { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi0_in_vp0 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2s5_8ch { + status = "disabled"; +}; + +&pcie2x1l0 { + status = "disabled"; +}; + +&pcie2x1l1 { + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&rkvdec_ccu { + status = "disabled"; +}; + +&rkvdec0 { + status = "disabled"; +}; + +&rkvdec0_mmu { + status = "disabled"; +}; + +&rkvdec1 { + status = "disabled"; +}; + +&rkvdec1_mmu { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + +&usbdp_phy1 { + status = "disabled"; +}; + +&usbdrd3_1 { + status = "disabled"; +}; + +&usbdrd_dwc3_1 { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&u2phy1 { + status = "disabled"; +}; + +&u2phy1_otg { + status = "disabled"; +}; + +&u2phy2 { + status = "disabled"; +}; + +&u2phy2_host { + status = "disabled"; +}; + +&u2phy3 { + status = "disabled"; +}; + +&u2phy3_host { + status = "disabled"; +}; diff --git a/rk3588-nvr-demo-v10-spi-nand.dts b/rk3588-nvr-demo-v10-spi-nand.dts new file mode 100644 index 0000000..49d5fbe --- /dev/null +++ b/rk3588-nvr-demo-v10-spi-nand.dts @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO LP4 SPI NAND Board"; + compatible = "rockchip,rk3588-nvr-demo-v10-spi-nand", "rockchip,rk3588"; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 clk_gate.always_on=1 pm_domains.always_on=1 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw rootwait"; + }; +}; + +&sfc { + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; diff --git a/rk3588-nvr-demo-v10.dts b/rk3588-nvr-demo-v10.dts new file mode 100644 index 0000000..9a1dc1f --- /dev/null +++ b/rk3588-nvr-demo-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO LP4 V10 Board"; + compatible = "rockchip,rk3588-nvr-demo-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-nvr-demo.dtsi b/rk3588-nvr-demo.dtsi new file mode 100644 index 0000000..925a81e --- /dev/null +++ b/rk3588-nvr-demo.dtsi @@ -0,0 +1,849 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" +#include "rk3588-nvr.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + i2s0_sound: i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8311"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8311>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + hdd_led: hdd-led { + gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + net_led: net-led { + gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + work_led: work-led { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&vdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <7500>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy0_ps { + pinctrl-names = "default"; + pinctrl-0 = <&sata0_pm_reset>; + status = "okay"; +}; + +&combphy1_ps { + pinctrl-names = "default"; + pinctrl-0 = <&sata1_pm_reset>; + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + pinctrl-0 = <&dp0m2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp1 { + pinctrl-0 = <&dp1m2_pins &dp1_hdmi_ctl>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp1_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "okay"; +}; + +&dp1_in_vp2 { + status = "okay"; +}; + +&dp1_sound { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x42>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_in_vp1 { + status = "okay"; +}; + +&hdmi0_in_vp2 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp0 { + status = "okay"; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_in_vp2 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + es8311: es8311@18 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x18>; + #sound-dai-cells = <0>; + adc-pga-gain = <6>; /* 18dB */ + adc-volume = <0xbf>; /* 0dB */ + dac-volume = <0xbf>; /* 0dB */ + aec-mode = "adc left, adc right"; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x4_clkreqn_m1>; + status = "okay"; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&rk806single { + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + + regulators { + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + }; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; + rockchip,virtual-poweroff = <1>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; +}; + +&route_dp0 { + status = "okay"; + force-output; + connect = <&vp2_out_dp0>; + + force_timing { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hsync-len = <136>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <6>; + vback-porch = <29>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + +}; + +&route_dp1 { + status = "okay"; + force-output; + connect = <&vp2_out_dp1>; + + force_timing { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hsync-len = <136>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <6>; + vback-porch = <29>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + +}; + +&route_hdmi0 { + status = "okay"; + force-output; + connect = <&vp2_out_hdmi0>; + + force_timing { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hsync-len = <136>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <6>; + vback-porch = <29>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + +}; + +&route_hdmi1 { + status = "okay"; + force-output; + connect = <&vp2_out_hdmi1>; + + force_timing { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hsync-len = <136>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <6>; + vback-porch = <29>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spdif_tx5 { + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hdmi_ctl: dp-hdmi-ctl { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pcie30x4 { + pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + + rtc { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sata { + sata0_pm_reset: sata0-pm-reset { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; + }; + sata1_pm_reset: sata1-pm-reset { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = < 2 3 >; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = < 0 1 2 3 >; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; +}; + +&vdd_vdenc_s0 { + regulator-init-microvolt = <750000>; +}; + diff --git a/rk3588-nvr-demo1-v21-android.dts b/rk3588-nvr-demo1-v21-android.dts new file mode 100644 index 0000000..9e83cb4 --- /dev/null +++ b/rk3588-nvr-demo1-v21-android.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo1-v21.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO1 LP4 V21 Android Board"; + compatible = "rockchip,rk3588-nvr-demo1-v21", "rockchip,rk3588"; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&i2s6_8ch { + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + diff --git a/rk3588-nvr-demo1-v21.dts b/rk3588-nvr-demo1-v21.dts new file mode 100644 index 0000000..76826eb --- /dev/null +++ b/rk3588-nvr-demo1-v21.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo1-v21.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO1 LP4 V21 Board"; + compatible = "rockchip,rk3588-nvr-demo1-v21", "rockchip,rk3588"; +}; diff --git a/rk3588-nvr-demo1-v21.dtsi b/rk3588-nvr-demo1-v21.dtsi new file mode 100644 index 0000000..b073e38 --- /dev/null +++ b/rk3588-nvr-demo1-v21.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ +#include "dt-bindings/usb/pd.h" +#include "rk3588-nvr-demo.dtsi" + + +/ { + ite_pwr_en: ite-pwr-en { + compatible = "regulator-fixed"; + regulator-name = "ITE-PWR_EN"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + }; +}; + +&dp0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "okay"; +}; + +&dp0_sound { + status = "okay"; +}; + +&dp1 { + pinctrl-0 = <&dp1m2_pins &dp1_hdmi_reset>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp2 { + status = "okay"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; + + it6161: it6161@6c { + status = "okay"; + compatible = "ite,it6161"; + #sound-dai-cells = <0>; + reg = <0x6c>; + it6161-addr-hdmi-tx = <0x4C>; + it6161-addr-cec = <0x4E>; + interrupt-parent = <&gpio0>; + interrupts = ; + enable-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vcc5v0_otg>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hdmi_reset: dp-hdmi-reset { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588-nvr-demo3-v10-android.dts b/rk3588-nvr-demo3-v10-android.dts new file mode 100644 index 0000000..246f0f0 --- /dev/null +++ b/rk3588-nvr-demo3-v10-android.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo3-v10.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO3 LP4 V10 Android Board"; + compatible = "rockchip,rk3588-nvr-demo3-v10", "rockchip,rk3588"; +}; + +&dp0_in_vp0 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; +}; + +&hdmi0_in_vp1 { + status = "disabled"; +}; + +&hdmi0_in_vp2 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdmi1_in_vp0 { + status = "disabled"; +}; + +&hdmi1_in_vp2 { + status = "disabled"; +}; + +&hdmi1_sound { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&i2s6_8ch { + status = "disabled"; +}; + +&pcie30phy { + status = "disabled"; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sata1 { + status = "disabled"; +}; + diff --git a/rk3588-nvr-demo3-v10.dts b/rk3588-nvr-demo3-v10.dts new file mode 100644 index 0000000..ef72167 --- /dev/null +++ b/rk3588-nvr-demo3-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-nvr-demo3-v10.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 NVR DEMO3 LP4 V10 Board"; + compatible = "rockchip,rk3588-nvr-demo3-v10", "rockchip,rk3588"; +}; diff --git a/rk3588-nvr-demo3-v10.dtsi b/rk3588-nvr-demo3-v10.dtsi new file mode 100644 index 0000000..2f6821d --- /dev/null +++ b/rk3588-nvr-demo3-v10.dtsi @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588-nvr-demo1-v21.dtsi" + +&dsi1 { + status = "disabled"; +}; + +&i2c0 { + /delete-node/ rk8603@43; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "disabled"; + /delete-node/ rk8602@42; +}; + +&rkvenc0 { + venc-supply = <&vdd_log_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_log_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&spi2 { + rk806single@0 { + regulators { + /delete-node/ DCDC_REG4; + + vdd_npu_s0: vdd_npu_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <2500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/rk3588-nvr.dtsi b/rk3588-nvr.dtsi new file mode 100644 index 0000000..0301d6f --- /dev/null +++ b/rk3588-nvr.dtsi @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include "rk3588-cpu-swap.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <1750>; + }; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + test-power { + status = "okay"; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&CPU_SLEEP { + status = "disabled"; +}; + +&cluster0_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; +}; + +&cluster1_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; + /delete-node/ opp-2256000000; + /delete-node/ opp-2304000000; + /delete-node/ opp-2352000000; + /delete-node/ opp-2400000000; +}; + +&cluster2_opp_table { + /delete-node/ opp-408000000; + /delete-node/ opp-600000000; + /delete-node/ opp-816000000; + /delete-node/ opp-1008000000; + /delete-node/ opp-2256000000; + /delete-node/ opp-2304000000; + /delete-node/ opp-2352000000; + /delete-node/ opp-2400000000; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&display_subsystem { + clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; + clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&gpu_opp_table { + /delete-node/ opp-198000000; + /delete-node/ opp-297000000; + /delete-node/ opp-396000000; + /delete-node/ opp-500000000; + /delete-node/ opp-1000000000; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <800000000>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588-pc.dtsi b/rk3588-pc.dtsi new file mode 100644 index 0000000..bd0c9b7 --- /dev/null +++ b/rk3588-pc.dtsi @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include + +/ { + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&gpu_opp_table { + /delete-node/ opp-198000000; + /delete-node/ opp-297000000; + /delete-node/ opp-396000000; + /delete-node/ opp-594000000; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + disable-win-move; + assigned-clocks = <&cru DCLK_VOP0_SRC>, + <&cru DCLK_VOP1_SRC>, + <&cru DCLK_VOP2_SRC>, + <&cru DCLK_VOP3>; + assigned-clock-parents = <0>, <0>, <&cru PLL_V0PLL>, <0>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; diff --git a/rk3588-pcie-ep-demo-v11-linux.dts b/rk3588-pcie-ep-demo-v11-linux.dts new file mode 100644 index 0000000..4e160c2 --- /dev/null +++ b/rk3588-pcie-ep-demo-v11-linux.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-pcie-ep-demo.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 PCIE EP Demo V11 Board"; + compatible = "rockchip,rk3588-pcie-ep-demo-v11", "rockchip,rk3588"; +}; + +&hdmi1_in_vp2 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; + force-output; + connect = <&vp2_out_hdmi1>; + + force_timing { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hfront-porch = <24>; + hsync-len = <136>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <6>; + vback-porch = <29>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + +}; diff --git a/rk3588-pcie-ep-demo-v11.dts b/rk3588-pcie-ep-demo-v11.dts new file mode 100644 index 0000000..eb5b4f8 --- /dev/null +++ b/rk3588-pcie-ep-demo-v11.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-pcie-ep-demo.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 PCIE EP Demo V11 Board"; + compatible = "rockchip,rk3588-pcie-ep-demo-v11", "rockchip,rk3588"; +}; diff --git a/rk3588-pcie-ep-demo.dtsi b/rk3588-pcie-ep-demo.dtsi new file mode 100644 index 0000000..f44fd9e --- /dev/null +++ b/rk3588-pcie-ep-demo.dtsi @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include +#include +#include +#include +#include +#include +#include "rk3588-rk806-single.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + bar0_region: bar0-region@3c000000 { + reg = <0x0 0x3c000000 0x0 0x00400000>; + }; + bar2_region: bar2-region@40000000 { + reg = <0x0 0x40000000 0x0 0x04000000>; + }; + }; + + test-power { + status = "okay"; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim1_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in_vp0 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + ð0_pins>; + + tx_delay = <0x44>; + /* rx_delay = <0x4f>; */ + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_ETH0_OUT>; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + compatible = "rockchip,rk3588-pcie-std-ep"; + memory-region = <&bar0_region>, <&bar2_region>; + memory-region-names = "bar0", "bar2"; + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + status = "okay"; + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&pinctrl { + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588-rk806-dual.dtsi b/rk3588-rk806-dual.dtsi new file mode 100644 index 0000000..431b037 --- /dev/null +++ b/rk3588-rk806-dual.dtsi @@ -0,0 +1,782 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + rk806master: rk806master@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_mem_s0: DCDC_REG5 { + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_mem_s0: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_codec_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_codec_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_1v8_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_0v75_hdmi_edp_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdd_0v75_hdmi_edp_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + rk806slave: rk806slave@1 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x01>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "disabled"; + }; + + pinctrl_slave_rk806: pinctrl_slave_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_slave_dvs1_null: rk806_slave_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs1_slp: rk806_slave_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_slave_dvs1_rst: rk806_slave_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_slave_dvs2_null: rk806_slave_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_slp: rk806_slave_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_slave_dvs2_rst: rk806_slave_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_slave_dvs3_null: rk806_slave_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_slp: rk806_slave_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_slave_dvs3_rst: rk806_slave_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_cpu_big1_s0: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_mem_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v85_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/rk3588-rk806-single.dtsi b/rk3588-rk806-single.dtsi new file mode 100644 index 0000000..62f3403 --- /dev/null +++ b/rk3588-rk806-single.dtsi @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single: rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/rk3588-toybrick-edp-x0.dtsi b/rk3588-toybrick-edp-x0.dtsi new file mode 100644 index 0000000..1dbb39c --- /dev/null +++ b/rk3588-toybrick-edp-x0.dtsi @@ -0,0 +1,770 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-toybrick.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + es8388_sound: es8388-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8388-codec"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8388>; + }; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>;//csq + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + rk_headset: rk-headset { + status = "okay"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi0_pwr>; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipicsi1_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + panel-edp { + compatible = "innolux,p120zdg-bf4", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <500>; + disable-delay-ms = <120>; + width-mm = <254>; + height-mm = <169>; + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_edp"; + gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + pinctrl-names = "default"; + pinctrl-0 = <&dp1_hpd>; + hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "okay"; + ports { + port@1 { + reg = <1>; + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp1_in_vp2 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x43>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; + }; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + extcon = <&rk_headset>; + }; +}; + +&hdmirx_ctrler { + status = "okay"; + hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "disabled"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + diff --git a/rk3588-toybrick-imx258.dtsi b/rk3588-toybrick-imx258.dtsi new file mode 100644 index 0000000..3f3c10e --- /dev/null +++ b/rk3588-toybrick-imx258.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + dw9714: dw9714@c { + compatible = "silicon touch,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <120>; + rockchip,vcm-step-mode = <13>; + }; + + imx258_eeprom: imx258_eeprom@50 { + compatible = "otp,imx258_eeprom"; + status = "okay"; + reg = <0x50>; + }; + + imx258: imx258@10 { + compatible = "sony,imx258"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipicsi0>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "GEIR180089"; + rockchip,camera-module-lens-name = "LG500627G"; + eeprom-ctrl = <&imx258_eeprom>; + lens-focus = <&dw9714>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&csi2_dcphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_1_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx258_1_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + dw9714_1: dw9714_1@c { + compatible = "silicon touch,dw9714"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <120>; + rockchip,vcm-step-mode = <13>; + }; + + imx258_1_eeprom: imx258_1_eeprom@50 { + compatible = "otp,imx258_eeprom"; + status = "okay"; + reg = <0x50>; + }; + + imx258_1: imx258_1@1a { + compatible = "sony,imx258"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + power-domains = <&power RK3588_PD_VI>; + avdd-supply = <&vcc_mipidcphy0>; + pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "GEIR180089"; + rockchip,camera-module-lens-name = "LG500627G"; + eeprom-ctrl = <&imx258_1_eeprom>; + lens-focus = <&dw9714_1>; + port { + imx258_1_out0: endpoint { + remote-endpoint = <&mipi_in_1_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +// use dcphy0 isp1 +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +#if 0 + +&rkcif_mipi_lvds_sditf { + status = "okay"; + port { + mipi_lvds_sditf_1: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0_vir1 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf_1>; + }; + }; +}; + +#endif + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; diff --git a/rk3588-toybrick-x0-android.dts b/rk3588-toybrick-x0-android.dts new file mode 100644 index 0000000..a7f7e39 --- /dev/null +++ b/rk3588-toybrick-x0-android.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-toybrick-x0.dtsi" +#include "rk3588-android.dtsi" +#include "rk3588-toybrick-imx258.dtsi" + +/ { + model = "Rockchip RK3588 TOYBRICK LP4 X10 Board"; + compatible = "rockchip,rk3588-toybrick-x10-android", "rockchip,rk3588"; +}; diff --git a/rk3588-toybrick-x0-linux.dts b/rk3588-toybrick-x0-linux.dts new file mode 100644 index 0000000..e7f40c0 --- /dev/null +++ b/rk3588-toybrick-x0-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-toybrick-x0.dtsi" +#include "rk3588-linux.dtsi" +//#include "rk3588-toybrick-imx258.dtsi" +/ { + model = "Rockchip RK3588 TOYBRICK X10 Board"; + compatible = "rockchip,rk3588-toybrick-x10-linux", "rockchip,rk3588"; +}; diff --git a/rk3588-toybrick-x0.dtsi b/rk3588-toybrick-x0.dtsi new file mode 100644 index 0000000..b404fd1 --- /dev/null +++ b/rk3588-toybrick-x0.dtsi @@ -0,0 +1,754 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588.dtsi" +#include "rk3588-toybrick.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm9 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,es8388"; + hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipicsi0: vcc-mipicsi0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi0"; + enable-active-high; + }; + + vcc_mipicsi1: vcc-mipicsi1-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_mipicsi1"; + enable-active-high; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm2 0 25000 0>; + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x43>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +/* Should work with at least 128MB cma reserved above. */ +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim1_rx &hdmirx_det>; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <400000>; + + usbc0: husb311@4e { + compatible = "hynetek,husb311"; + reg = <0x4e>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + }; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "disabled"; + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; + + gsl3673: gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8111_isolate>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + num-lanes=<2>; + status = "okay"; +}; + +&pinctrl { + hdmi { + hdmirx_det: hdmirx-det { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8111 { + rtl8111_isolate: rtl8111-isolate { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm9 { + pinctrl-0 = <&pwm9m1_pins>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588-toybrick.dtsi b/rk3588-toybrick.dtsi new file mode 100644 index 0000000..a76bedc --- /dev/null +++ b/rk3588-toybrick.dtsi @@ -0,0 +1,1267 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; + + /* + *in TB-RK3588 gpio0 RK_PB6 for MIPI dsi tp + */ + + spi2: spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <2>; + status = "okay"; + }; + + + /* + *just for rk3588s-evb4 in rk3588-rk806-single.dtsi + *in TB-RK3588 gpio1 RK_PA6 for edp tp + */ + vcc_1v2_cam_s0: vcc-1v2-cam-s0 { + status = "disabled"; + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_cam_s0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; diff --git a/rk3588-vccio3-pinctrl.dtsi b/rk3588-vccio3-pinctrl.dtsi new file mode 100644 index 0000000..d1a1f26 --- /dev/null +++ b/rk3588-vccio3-pinctrl.dtsi @@ -0,0 +1,525 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk32k { + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + /* clk32k_out1 */ + <2 RK_PC5 1 &pcfg_pull_none>; + }; + + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + /* eth0_refclko_25m */ + <2 RK_PC3 1 &pcfg_pull_none>; + }; + + }; + + fspi { + /omit-if-no-ref/ + fspim1_pins: fspim1-pins { + rockchip,pins = + /* fspi_clk_m1 */ + <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m1 */ + <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m1 */ + <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m1 */ + <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m1 */ + <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m1 */ + <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim1_cs1: fspim1-cs1 { + rockchip,pins = + /* fspi_cs1n_m1 */ + <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + /* gmac0_mdc */ + <4 RK_PC4 1 &pcfg_pull_none>, + /* gmac0_mdio */ + <4 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + /* gmac0_mclkinout */ + <4 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + /* gmac0_rxd0 */ + <2 RK_PC1 1 &pcfg_pull_none>, + /* gmac0_rxd1 */ + <2 RK_PC2 1 &pcfg_pull_none>, + /* gmac0_rxdv_crs */ + <4 RK_PC2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + /* gmac0_txd0 */ + <2 RK_PB6 1 &pcfg_pull_none>, + /* gmac0_txd1 */ + <2 RK_PB7 1 &pcfg_pull_none>, + /* gmac0_txen */ + <2 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + /* gmac0_rxclk */ + <2 RK_PB0 1 &pcfg_pull_none>, + /* gmac0_txclk */ + <2 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + /* gmac0_rxd2 */ + <2 RK_PA6 1 &pcfg_pull_none>, + /* gmac0_rxd3 */ + <2 RK_PA7 1 &pcfg_pull_none>, + /* gmac0_txd2 */ + <2 RK_PB1 1 &pcfg_pull_none>, + /* gmac0_txd3 */ + <2 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppsclk: gmac0-ppsclk { + rockchip,pins = + /* gmac0_ppsclk */ + <2 RK_PC4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppstring: gmac0-ppstring { + rockchip,pins = + /* gmac0_ppstring */ + <2 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ptp_refclk: gmac0-ptp-refclk { + rockchip,pins = + /* gmac0_ptp_refclk */ + <2 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_txer: gmac0-txer { + rockchip,pins = + /* gmac0_txer */ + <4 RK_PC6 1 &pcfg_pull_none>; + }; + + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_tx1_cec: hdmim0-tx1-cec { + rockchip,pins = + /* hdmim0_tx1_cec */ + <2 RK_PC4 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_scl: hdmim0-tx1-scl { + rockchip,pins = + /* hdmim0_tx1_scl */ + <2 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_sda: hdmim0-tx1-sda { + rockchip,pins = + /* hdmim0_tx1_sda */ + <2 RK_PB4 4 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <2 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <2 RK_PC0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m3_xfer: i2c3m3-xfer { + rockchip,pins = + /* i2c3_scl_m3 */ + <2 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m3 */ + <2 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + /* i2c4_scl_m1 */ + <2 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m1 */ + <2 RK_PB4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m4_xfer: i2c5m4-xfer { + rockchip,pins = + /* i2c5_scl_m4 */ + <2 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m4 */ + <2 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m2_xfer: i2c6m2-xfer { + rockchip,pins = + /* i2c6_scl_m2 */ + <2 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m2 */ + <2 RK_PC2 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m1_xfer: i2c7m1-xfer { + rockchip,pins = + /* i2c7_scl_m1 */ + <4 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m1 */ + <4 RK_PC4 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m1_xfer: i2c8m1-xfer { + rockchip,pins = + /* i2c8_scl_m1 */ + <2 RK_PB0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m1 */ + <2 RK_PB1 9 &pcfg_pull_none_smt>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_idle: i2s2m0-idle { + rockchip,pins = + /* i2s2m0_lrck_gpio */ + <2 RK_PC0 0 &pcfg_pull_none>, + /* i2s2m0_sclk_gpio */ + <2 RK_PB7 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + /* i2s2m0_lrck */ + <2 RK_PC0 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + /* i2s2m0_mclk */ + <2 RK_PB6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + /* i2s2m0_sclk */ + <2 RK_PB7 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + /* i2s2m0_sdi */ + <2 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + /* i2s2m0_sdo */ + <4 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m2_pins: pwm2m2-pins { + rockchip,pins = + /* pwm2_m2 */ + <4 RK_PC2 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <4 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m2_pins: pwm5m2-pins { + rockchip,pins = + /* pwm5_m2 */ + <4 RK_PC4 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <4 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m3_pins: pwm7m3-pins { + rockchip,pins = + /* pwm7_ir_m3 */ + <4 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom0_pins: sdiom0-pins { + rockchip,pins = + /* sdio_clk_m0 */ + <2 RK_PB3 2 &pcfg_pull_none>, + /* sdio_cmd_m0 */ + <2 RK_PB2 2 &pcfg_pull_up>, + /* sdio_d0_m0 */ + <2 RK_PA6 2 &pcfg_pull_up>, + /* sdio_d1_m0 */ + <2 RK_PA7 2 &pcfg_pull_up>, + /* sdio_d2_m0 */ + <2 RK_PB0 2 &pcfg_pull_up>, + /* sdio_d3_m0 */ + <2 RK_PB1 2 &pcfg_pull_up>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + /* spi1_clk_m0 */ + <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, + /* spi1_miso_m0 */ + <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, + /* spi1_mosi_m0 */ + <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + /* spi1_cs0_m0 */ + <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + /* spi1_cs1_m0 */ + <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + /* spi3_clk_m0 */ + <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, + /* spi3_miso_m0 */ + <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, + /* spi3_mosi_m0 */ + <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + /* spi3_cs0_m0 */ + <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + /* spi3_cs1_m0 */ + <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <2 RK_PB6 10 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <2 RK_PB7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + /* uart1m0_ctsn */ + <2 RK_PC1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + /* uart1m0_rtsn */ + <2 RK_PC0 10 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <2 RK_PA6 10 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <2 RK_PA7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + /* uart6m0_ctsn */ + <2 RK_PB1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + /* uart6m0_rtsn */ + <2 RK_PB0 10 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <2 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <2 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <4 RK_PC6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <4 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + /* uart9_rx_m0 */ + <2 RK_PC4 10 &pcfg_pull_up>, + /* uart9_tx_m0 */ + <2 RK_PC2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + /* uart9m0_ctsn */ + <4 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + /* uart9m0_rtsn */ + <4 RK_PC4 10 &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588-vehicle-adsp-audio-s66.dtsi b/rk3588-vehicle-adsp-audio-s66.dtsi new file mode 100644 index 0000000..5f281ea --- /dev/null +++ b/rk3588-vehicle-adsp-audio-s66.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dummy_codec: dummy-codec { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + status = "okay"; + }; + + sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,tdm"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + status = "okay"; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; + + bt_codec: bt-codec { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,format = "i2s"; + simple-audio-card,cpu { + sound-dai = <&i2s3_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_codec 1>; + }; + }; +}; + +&i2s1_8ch { + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2>; + i2s-lrck-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + tdm-fsync-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,tdm-multi-lanes; + rockchip,tdm-tx-lanes = <3>; + rockchip,tdm-rx-lanes = <2>; + rockchip,clk-trcm = <1>; + status = "okay"; +}; + +&i2s3_2ch { + assigned-clocks = <&cru CLK_I2S3_2CH>; + assigned-clock-parents = <&mclkin_i2s3>; + pinctrl-0 = <&i2s3_sdi + &i2s3_sdo + &i2s3_lrck + &i2s3_sclk + &i2s3_mclk>; + status = "okay"; +}; + +&mclkin_i2s3 { + clock-frequency = <24576000>; +}; + +&spi3 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI3>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + pinctrl-0 = <&spi3m2_cs0 + &spi3m2_cs1 + &spi3m2_pins>; + + flash: is25lp032@1 { + compatible = "issi,is25lp032", "jedec,spi-nor"; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <5000000>; + m25p,fast-read; + }; +}; diff --git a/rk3588-vehicle-evb-image-reverse.dtsi b/rk3588-vehicle-evb-image-reverse.dtsi new file mode 100644 index 0000000..9bcce71 --- /dev/null +++ b/rk3588-vehicle-evb-image-reverse.dtsi @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/{ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + drm_vehicle: drm-vehicle@20000000{ + compatible = "shared-dma-pool"; + inactive; + reusable; + reg = <0x0 (512 * 0x100000) 0x0 (256 * 0x100000)>;//512M ~ 512M+256M + linux,cma-default; + }; + }; + + gpio_det: gpio-det { + compatible = "gpio-detection"; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&vehicle_gpios>; + + car-reverse { + car-reverse-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + linux,debounce-ms = <5>; + label = "car-reverse"; + gpio,wakeup; + }; + + }; + + vehicle: vehicle { + compatible = "rockchip,vehicle"; + status = "okay"; + + // pinctrl-names = "default"; + // pinctrl-0 = <&mipim1_camera1_clk>; + + clocks = <&cru ACLK_VICAP>, + <&cru HCLK_VICAP>, + <&cru DCLK_VICAP>; + clock-names = "aclk_cif", + "hclk_cif", + "dclk_cif"; + resets = <&cru SRST_A_VICAP>, + <&cru SRST_H_VICAP>, + <&cru SRST_D_VICAP>; + reset-names = "rst_cif_a", + "rst_cif_h", + "rst_cif_d"; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <600000000>; + power-domains = <&power RK3588_PD_VI>; + cif,drop-frames = <4>; //frames to drop + cif,chip-id = <1>; /*0:rk3568 1:rk3588*/ + rockchip,grf = <&sys_grf>; + rockchip,cru = <&cru>; + rockchip,cif = <&rkcif>; + rockchip,gpio-det = <&gpio_det>; + rockchip,cif-sensor = <&cif_sensor>; + rockchip,cif-phy = <&cif_phy>; + ad,fix-format = <0>;//0:auto detect,1:pal;2:ntsc;3:720p50;4:720p30;5:720p25 + /*0:no, 1:90; 2:180; 4:270; 0x10:mirror-y; 0x20:mirror-x*/ + vehicle,rotate-mirror = <0x00>; + vehicle,crtc_name = "video_port3"; + vehicle,plane_name = "Esmart3-win0"; + }; + + cif_phy: cif_phy { + status = "okay"; + + csi2_dcphy0 { + status = "disabled"; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>, + <&cru PCLK_MIPI_DCPHY0>, + <&cru PCLK_CSI_HOST_0>, + <&cru ICLK_CSIHOST0>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host", + "iclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_0>, + <&cru SRST_CSIHOST0_VICAP>; + reset-names = "srst_csihost_p", + "srst_csihost_vicap"; + csihost-idx = <0>; + rockchip,csi2 = <&mipi0_csi2>; + phys = <&mipi_dcphy0>; + phy-names = "dcphy"; + }; + csi2_dcphy1 { + status = "disabled"; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>, + <&cru PCLK_MIPI_DCPHY1>, + <&cru PCLK_CSI_HOST_1>, + <&cru ICLK_CSIHOST1>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host", + "iclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_1>, + <&cru SRST_CSIHOST1_VICAP>; + reset-names = "srst_csihost_p", + "srst_csihost_vicap"; + csihost-idx = <1>; + rockchip,csi2 = <&mipi1_csi2>; + phys = <&mipi_dcphy1>; + phy-names = "dcphy"; + }; + csi2_dphy0 { + status = "okay"; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>, + <&cru PCLK_CSIPHY0>, + <&cru PCLK_CSI_HOST_2>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host"; + resets = <&cru SRST_CSIPHY0>, + <&cru SRST_P_CSIPHY0>, + <&cru SRST_P_CSI_HOST_2>, + <&cru SRST_CSIHOST2_VICAP>; + reset-names = "srst_csiphy", + "srst_p_csiphy", + "srst_csihost_p", + "srst_csihost_vicap"; + csihost-idx = <2>; + rockchip,dphy-grf = <&mipidphy0_grf>; + rockchip,csi2-dphy = <&csi2_dphy0_hw>; + rockchip,csi2 = <&mipi2_csi2>; + }; + /* only rk3588 */ + csi2_dphy3 { + status = "disabled"; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>, + <&cru PCLK_CSIPHY1>, + <&cru PCLK_CSI_HOST_4>; + clock-names = "xvclk", + "pclk", + "pclk_csi2host"; + resets = <&cru SRST_CSIPHY1>, + <&cru SRST_P_CSIPHY1>, + <&cru SRST_P_CSI_HOST_4>, + <&cru SRST_CSIHOST4_VICAP>; + reset-names = "srst_csiphy", + "srst_p_csiphy", + "srst_csihost_p", + "srst_csihost_vicap"; + csihost-idx = <4>; + rockchip,dphy-grf = <&mipidphy1_grf>; + rockchip,csi2-dphy = <&csi2_dphy1_hw>; + rockchip,csi2 = <&mipi4_csi2>; + }; + rkcif_dvp { + status = "disabled"; + clocks = <&cru CLK_CIFOUT_OUT>; + clock-names = "xvclk"; + }; + }; + + cif_sensor: cif_sensor { + compatible = "rockchip,sensor"; + status = "okay"; + + nvp6188 { + is_front = <0>; + status = "okay"; + + /*dphy0*/ + powerdown-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + pwdn_active = <1>; + mir = <0>; + flash_attach = <0>; + orientation = <90>; + i2c_add = <0x66>; + i2c_chl = <7>; + cif_chl = <0>; + ad_chl = <0>; + mclk_rate = <24>; + rockchip,camera-module-defrect0 = <1920 1080 0 0 1920 1080>; + rockchip,camera-module-interface0 = "bt601_8"; + rockchip,camera-module-defrect1 = <1280 720 0 0 1280 720>; + rockchip,camera-module-interface1 = "bt601_8"; + }; + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>, <&drm_vehicle>; + memory-region-names = "drm-logo", "drm-vehicle"; +}; + +&i2c7 { + status = "okay"; +}; + +&pinctrl { + vehicle { + vehicle_gpios: vehicle-gpios { + /* gpios */ + rockchip,pins = + /* car-reverse */ + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96712-dcphy0.dtsi b/rk3588-vehicle-evb-maxim-max96712-dcphy0.dtsi new file mode 100644 index 0000000..b349599 --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96712-dcphy0.dtsi @@ -0,0 +1,734 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96712_dcphy0_osc: max96712-dcphy0-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dcphy0-osc"; + }; + + max96712_dcphy0_vcc1v2: max96712-dcphy0-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dcphy0_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96712_dcphy0_vcc1v8: max96712-dcphy0-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dcphy0_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96712_dcphy0_poc: max96712-dcphy0-poc { + compatible = "regulator-fixed"; + regulator-name = "max96712_dcphy0_poc"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1050>; + off-on-delay-us = <515000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dcphy0_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dcphy0_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + max96712_dcphy0: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dcphy0_osc 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dcphy0_pwdn>, <&max96712_dcphy0_errb>, <&max96712_dcphy0_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vcc1v2-supply = <&max96712_dcphy0_vcc1v2>; + vcc1v8-supply = <&max96712_dcphy0_vcc1v8>; + poc-supply = <&max96712_dcphy0_poc>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_dcphy0_out: endpoint { + remote-endpoint = <&mipi_dcphy0_in_max96712>; + data-lanes = <1 2>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1280>; + sensor-height = <800>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <24>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dcphy0_link0_in: endpoint { + remote-endpoint = <&max96712_dcphy0_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + 0B 06 ef 00 00 // HIM on + 0B 07 84 00 00 // Enable HVEN and DBL + 0B 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dcphy0_link1_in: endpoint { + remote-endpoint = <&max96712_dcphy0_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + 0C 06 ef 00 00 // HIM on + 0C 07 84 00 00 // Enable HVEN and DBL + 0C 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dcphy0_link2_in: endpoint { + remote-endpoint = <&max96712_dcphy0_remote2_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + 0D 06 ef 00 00 // HIM on + 0D 07 84 00 00 // Enable HVEN and DBL + 0D 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dcphy0_link3_in: endpoint { + remote-endpoint = <&max96712_dcphy0_remote3_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + 0E 06 ef 00 00 // HIM on + 0E 07 84 00 00 // Enable HVEN and DBL + 0E 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 0 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 0 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 0 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 0 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <1>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <0>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x00>; + data-lane-num = <2>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max96715"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96712_dcphy0_remote0_out: endpoint { + remote-endpoint = <&max96712_dcphy0_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max96715"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96712_dcphy0_remote1_out: endpoint { + remote-endpoint = <&max96712_dcphy0_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-2 { + compatible = "maxim4c,link2,max96715"; + status = "okay"; + + remote-id = <2>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x43>; // 0: disable remap + + port { + max96712_dcphy0_remote2_out: endpoint { + remote-endpoint = <&max96712_dcphy0_link2_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-3 { + compatible = "maxim4c,link3,max96715"; + status = "okay"; + + remote-id = <3>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x44>; // 0: disable remap + + port { + max96712_dcphy0_remote3_out: endpoint { + remote-endpoint = <&max96712_dcphy0_link3_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi0_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi0_in: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dcphy0 { + max96712_dcphy0_pwdn: max96712-dcphy0-pwdn { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dcphy0_errb: max96712-dcphy0-errb { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dcphy0_lock: max96712-dcphy0-lock { + rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96712-dcphy1.dtsi b/rk3588-vehicle-evb-maxim-max96712-dcphy1.dtsi new file mode 100644 index 0000000..6564020 --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96712-dcphy1.dtsi @@ -0,0 +1,504 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96712_dcphy1_osc: max96712-dcphy1-oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dcphy1-osc"; + }; + + max96712_dcphy1_vcc1v2: max96712-dcphy1-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dcphy1_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96712_dcphy1_vcc1v8: max96712-dcphy1-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dcphy1_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96712_dcphy1_poc: max96712-dcphy1-poc { + compatible = "regulator-fixed"; + regulator-name = "max96712_dcphy1_poc"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1050>; + off-on-delay-us = <515000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dcphy1_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dcphy1_out>; + data-lanes = <1 2>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + max96712_dcphy1: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dcphy1_osc 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dcphy1_pwdn>, <&max96712_dcphy1_errb>, <&max96712_dcphy1_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>; + vcc1v2-supply = <&max96712_dcphy1_vcc1v2>; + vcc1v8-supply = <&max96712_dcphy1_vcc1v8>; + poc-supply = <&max96712_dcphy1_poc>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_dcphy1_out: endpoint { + remote-endpoint = <&mipi_dcphy1_in_max96712>; + data-lanes = <1 2>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1600>; + sensor-height = <1300>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <24>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dcphy1_link0_in: endpoint { + remote-endpoint = <&max96712_dcphy1_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dcphy1_link1_in: endpoint { + remote-endpoint = <&max96712_dcphy1_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 0 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + // pipe Cross + 01 D9 59 00 00 // pipe 0: Inverts Cross VS + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 0 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + // pipe Cross + 01 F9 59 00 00 // pipe 1: Inverts Cross VS + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <1>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <0>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x00>; + data-lane-num = <2>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max9295"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96712_dcphy1_remote0_out: endpoint { + remote-endpoint = <&max96712_dcphy1_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max9295"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96712_dcphy1_remote1_out: endpoint { + remote-endpoint = <&max96712_dcphy1_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi1_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi1_in: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dcphy1 { + max96712_dcphy1_pwdn: max96712-dcphy1-pwdn { + rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dcphy1_errb: max96712-dcphy1-errb { + rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dcphy1_lock: max96712-dcphy1-lock { + rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96712-dphy0.dtsi b/rk3588-vehicle-evb-maxim-max96712-dphy0.dtsi new file mode 100644 index 0000000..d5e2cc8 --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96712-dphy0.dtsi @@ -0,0 +1,746 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96712_dphy0_osc0: max96712-dphy0-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dphy0-osc0"; + }; + + max96712_dphy0_vcc1v2: max96712-dphy0-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96712_dphy0_vcc1v8: max96712-dphy0-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96712_dphy0_poc: max96712-dphy0-poc { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy0_poc"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1050>; + off-on-delay-us = <515000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + + max96712_dphy0: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dphy0_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy0_pwdn>, <&max96712_dphy0_errb>, <&max96712_dphy0_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + vcc1v2-supply = <&max96712_dphy0_vcc1v2>; + vcc1v8-supply = <&max96712_dphy0_vcc1v8>; + poc-supply = <&max96712_dphy0_poc>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_dphy0_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1280>; + sensor-height = <800>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link0_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + 0B 06 ef 00 00 // HIM on + 0B 07 84 00 00 // Enable HVEN and DBL + 0B 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link1_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + 0C 06 ef 00 00 // HIM on + 0C 07 84 00 00 // Enable HVEN and DBL + 0C 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link2_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote2_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + 0D 06 ef 00 00 // HIM on + 0D 07 84 00 00 // Enable HVEN and DBL + 0D 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link3_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote3_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + 0E 06 ef 00 00 // HIM on + 0E 07 84 00 00 // Enable HVEN and DBL + 0E 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <1>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max96715"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96712_dphy0_remote0_out: endpoint { + remote-endpoint = <&max96712_dphy0_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max96715"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96712_dphy0_remote1_out: endpoint { + remote-endpoint = <&max96712_dphy0_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-2 { + compatible = "maxim4c,link2,max96715"; + status = "okay"; + + remote-id = <2>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x43>; // 0: disable remap + + port { + max96712_dphy0_remote2_out: endpoint { + remote-endpoint = <&max96712_dphy0_link2_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-3 { + compatible = "maxim4c,link3,max96715"; + status = "okay"; + + remote-id = <3>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x44>; // 0: disable remap + + port { + max96712_dphy0_remote3_out: endpoint { + remote-endpoint = <&max96712_dphy0_link3_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dphy0 { + max96712_dphy0_pwdn: max96712-dphy0-pwdn { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy0_errb: max96712-dphy0-errb { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy0_lock: max96712-dphy0-lock { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi b/rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi new file mode 100644 index 0000000..720b3ec --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96712_dphy3_osc0: max96712-dphy3-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dphy3-osc0"; + }; + + max96712_dphy3_vcc1v2: max96712-dphy3-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96712_dphy3_vcc1v8: max96712-dphy3-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96712_dphy3_poc: max96712-dphy3-poc { + compatible = "regulator-fixed"; + regulator-name = "max96712_dphy3_poc"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1050>; + off-on-delay-us = <515000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy3_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy3_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + max96712_dphy3: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dphy3_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy3_pwdn>, <&max96712_dphy3_errb>, <&max96712_dphy3_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + vcc1v2-supply = <&max96712_dphy3_vcc1v2>; + vcc1v8-supply = <&max96712_dphy3_vcc1v8>; + poc-supply = <&max96712_dphy3_poc>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_dphy3_out: endpoint { + remote-endpoint = <&mipi_dphy3_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1920>; + sensor-height = <1440>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <1>; + link-tx-rate = <0>; + + port { + max96712_dphy3_link0_in: endpoint { + remote-endpoint = <&max96712_dphy3_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <1>; + link-tx-rate = <0>; + + port { + max96712_dphy3_link1_in: endpoint { + remote-endpoint = <&max96712_dphy3_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <1>; + link-tx-rate = <0>; + + port { + max96712_dphy3_link2_in: endpoint { + remote-endpoint = <&max96712_dphy3_remote2_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <1>; + link-tx-rate = <0>; + + port { + max96712_dphy3_link3_in: endpoint { + remote-endpoint = <&max96712_dphy3_remote3_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <2>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <1>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max96717"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + // Camera i2c 7bit address remap + cam-i2c-addr-def = <0x30>; + cam-i2c-addr-map = <0x31>; // 0: disable remap + + port { + max96712_dphy3_remote0_out: endpoint { + remote-endpoint = <&max96712_dphy3_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max96717"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + // Camera i2c 7bit address remap + cam-i2c-addr-def = <0x30>; + cam-i2c-addr-map = <0x32>; // 0: disable remap + + port { + max96712_dphy3_remote1_out: endpoint { + remote-endpoint = <&max96712_dphy3_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + serdes-remote-device-2 { + compatible = "maxim4c,link2,max96717"; + status = "okay"; + + remote-id = <2>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x43>; // 0: disable remap + + // Camera i2c 7bit address remap + cam-i2c-addr-def = <0x30>; + cam-i2c-addr-map = <0x33>; // 0: disable remap + + port { + max96712_dphy3_remote2_out: endpoint { + remote-endpoint = <&max96712_dphy3_link2_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + + serdes-remote-device-3 { + compatible = "maxim4c,link3,max96717"; + status = "okay"; + + remote-id = <3>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x44>; // 0: disable remap + + // Camera i2c 7bit address remap + cam-i2c-addr-def = <0x30>; + cam-i2c-addr-map = <0x34>; // 0: disable remap + + port { + max96712_dphy3_remote3_out: endpoint { + remote-endpoint = <&max96712_dphy3_link3_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 03 02 10 00 00 + 14 17 00 00 00 + 14 32 7f 00 00 + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi4_in: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dphy3 { + max96712_dphy3_pwdn: max96712-dphy3-pwdn { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy3_errb: max96712-dphy3-errb { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy3_lock: max96712-dphy3-lock { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96712.dtsi b/rk3588-vehicle-evb-maxim-max96712.dtsi new file mode 100644 index 0000000..586c869 --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96712.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + max96712_dphy3_osc0: max96712-dphy3-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dphy3-osc0"; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy3_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy3_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + max96712_dphy3: max96712@29 { + compatible = "maxim,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dphy3_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy3_power>, <&max96712_dphy3_errb>, <&max96712_dphy3_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + auto-init-deskew-mask = <0x03>; + frame-sync-period = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_dphy3_out: endpoint { + remote-endpoint = <&mipi_dphy3_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi4_in: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96712-dphy3 { + max96712_dphy3_power: max96712-dphy3-power { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy3_errb: max96712-dphy3-errb { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy3_lock: max96712-dphy3-lock { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96722-dphy0.dtsi b/rk3588-vehicle-evb-maxim-max96722-dphy0.dtsi new file mode 100644 index 0000000..d2eedac --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96722-dphy0.dtsi @@ -0,0 +1,746 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96722_dphy0_osc0: max96722-dphy0-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96722-dphy0-osc0"; + }; + + max96722_dphy0_vcc1v2: max96722-dphy0-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96722_dphy0_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96722_dphy0_vcc1v8: max96722-dphy0-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96722_dphy0_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96722_dphy0_poc: max96722-dphy0-poc { + compatible = "regulator-fixed"; + regulator-name = "max96722_dphy0_poc"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1050>; + off-on-delay-us = <515000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96722: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96722_dphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + + max96722_dphy0: max96722@29 { + compatible = "maxim4c,max96722"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96722_dphy0_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96722_dphy0_pwdn>, <&max96722_dphy0_errb>, <&max96722_dphy0_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + vcc1v2-supply = <&max96722_dphy0_vcc1v2>; + vcc1v8-supply = <&max96722_dphy0_vcc1v8>; + poc-supply = <&max96722_dphy0_poc>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96722"; + rockchip,camera-module-lens-name = "max96722"; + + port { + max96722_dphy0_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96722>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1280>; + sensor-height = <800>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy0_link0_in: endpoint { + remote-endpoint = <&max96722_dphy0_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + 0B 06 ef 00 00 // HIM on + 0B 07 84 00 00 // Enable HVEN and DBL + 0B 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy0_link1_in: endpoint { + remote-endpoint = <&max96722_dphy0_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + 0C 06 ef 00 00 // HIM on + 0C 07 84 00 00 // Enable HVEN and DBL + 0C 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy0_link2_in: endpoint { + remote-endpoint = <&max96722_dphy0_remote2_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + 0D 06 ef 00 00 // HIM on + 0D 07 84 00 00 // Enable HVEN and DBL + 0D 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy0_link3_in: endpoint { + remote-endpoint = <&max96722_dphy0_remote3_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + 0E 06 ef 00 00 // HIM on + 0E 07 84 00 00 // Enable HVEN and DBL + 0E 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <1>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max96715"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96722_dphy0_remote0_out: endpoint { + remote-endpoint = <&max96722_dphy0_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max96715"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96722_dphy0_remote1_out: endpoint { + remote-endpoint = <&max96722_dphy0_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-2 { + compatible = "maxim4c,link2,max96715"; + status = "okay"; + + remote-id = <2>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x43>; // 0: disable remap + + port { + max96722_dphy0_remote2_out: endpoint { + remote-endpoint = <&max96722_dphy0_link2_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-3 { + compatible = "maxim4c,link3,max96715"; + status = "okay"; + + remote-id = <3>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x44>; // 0: disable remap + + port { + max96722_dphy0_remote3_out: endpoint { + remote-endpoint = <&max96722_dphy0_link3_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96722-dphy0 { + max96722_dphy0_pwdn: max96722-dphy0-pwdn { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96722_dphy0_errb: max96722-dphy0-errb { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96722_dphy0_lock: max96722-dphy0-lock { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96722-dphy3.dtsi b/rk3588-vehicle-evb-maxim-max96722-dphy3.dtsi new file mode 100644 index 0000000..53dfac5 --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96722-dphy3.dtsi @@ -0,0 +1,516 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96722_dphy3_osc0: max96722-dphy3-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96722-dphy3-osc0"; + }; + + max96722_dphy3_vcc1v2: max96722-dphy3-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96722_dphy3_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96722_dphy3_vcc1v8: max96722-dphy3-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96722_dphy3_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; + + max96722_dphy3_poc: max96722-dphy3-poc { + compatible = "regulator-fixed"; + regulator-name = "max96722_dphy3_poc"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <1050>; + off-on-delay-us = <515000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy3_in_max96722: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96722_dphy3_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + max96722_dphy3: max96722@29 { + compatible = "maxim4c,max96722"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96722_dphy3_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96722_dphy3_pwdn>, <&max96722_dphy3_errb>, <&max96722_dphy3_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + vcc1v2-supply = <&max96722_dphy3_vcc1v2>; + vcc1v8-supply = <&max96722_dphy3_vcc1v8>; + poc-supply = <&max96722_dphy3_poc>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96722"; + rockchip,camera-module-lens-name = "max96722"; + + port { + max96722_dphy3_out: endpoint { + remote-endpoint = <&mipi_dphy3_in_max96722>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1600>; + sensor-height = <1300>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy3_link0_in: endpoint { + remote-endpoint = <&max96722_dphy3_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy3_link1_in: endpoint { + remote-endpoint = <&max96722_dphy3_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + // pipe Cross + 01 D9 59 00 00 // pipe 0: Inverts Cross VS + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + // pipe Cross + 01 F9 59 00 00 // pipe 1: Inverts Cross VS + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <1>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max9295"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96722_dphy3_remote0_out: endpoint { + remote-endpoint = <&max96722_dphy3_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max9295"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96722_dphy3_remote1_out: endpoint { + remote-endpoint = <&max96722_dphy3_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi4_in: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96722-dphy3 { + max96722_dphy3_pwdn: max96722-dphy3-pwdn { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96722_dphy3_errb: max96722-dphy3-errb { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96722_dphy3_lock: max96722-dphy3-lock { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96722.dtsi b/rk3588-vehicle-evb-maxim-max96722.dtsi new file mode 100644 index 0000000..c464e0a --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96722.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + max96722_dphy0_osc0: max96722-dphy0-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96722-dphy0-osc0"; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96722: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96722_dphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + + max96722_dphy0: max96722@29 { + compatible = "maxim,max96722"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96722_dphy0_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96722_dphy0_power>, <&max96722_dphy0_errb>, <&max96722_dphy0_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pocen-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + link-mask = <0x0F>; + auto-init-deskew-mask = <0x03>; + frame-sync-period = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96722"; + rockchip,camera-module-lens-name = "max96722"; + + port { + max96722_dphy0_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96722>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96722-dphy0 { + max96722_dphy0_power: max96722-dphy0-power { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96722_dphy0_errb: max96722-dphy0-errb { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96722_dphy0_lock: max96722-dphy0-lock { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi b/rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi new file mode 100644 index 0000000..888e426 --- /dev/null +++ b/rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + max96756_dphy0_osc: max96712-dphy0-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96756-dphy0-osc"; + }; + + max96756_dphy0_vcc1v2: max96756-dphy0-vcc1v2 { + compatible = "regulator-fixed"; + regulator-name = "max96756_dphy0_vcc1v2"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + startup-delay-us = <850>; + vin-supply = <&vcc5v0_sys>; + }; + + max96756_dphy0_vcc1v8: max96756-dphy0-vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "max96756_dphy0_vcc1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <200>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +/** + * ============================================================================ + * Info DPHY0 + * ============================================================================ + */ +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96756: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96756_dphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + + max96756: max96756@48 { + compatible = "maxim,max96756"; + status = "okay"; + reg = <0x48>; + + clock-names = "xvclk"; + clocks = <&max96756_dphy0_osc 0>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + + pinctrl-names = "default"; + pinctrl-0 = <&max96756_dphy0_pwdn>, <&max96756_dphy0_errb>, <&max96756_dphy0_lock>; + + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + + vcc1v2-supply = <&max96756_dphy0_vcc1v2>; + vcc1v8-supply = <&max96756_dphy0_vcc1v8>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96756"; + rockchip,camera-module-lens-name = "max96756"; + + port { + max96756_dphy0_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96756>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +/** + * ============================================================================= + * Common + * ============================================================================= + */ +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&pinctrl { + max96756-dphy0 { + max96756_dphy0_pwdn: max96756-dphy0-pwdn { + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96756_dphy0_errb: max96756-dphy0-errb { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96756_dphy0_lock: max96756-dphy0-lock { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-evb-mipi-nvp6188.dtsi b/rk3588-vehicle-evb-mipi-nvp6188.dtsi new file mode 100644 index 0000000..39104b4 --- /dev/null +++ b/rk3588-vehicle-evb-mipi-nvp6188.dtsi @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_nvp6188: endpoint@1 { + reg = <1>; + remote-endpoint = <&nvp6188_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + + + nvp6188: nvp6188@31 { + compatible = "nvp6188"; + status = "okay"; + reg = <0x31>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + rockchip,grf = <&sys_grf>; + /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ + reset-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "nvp6188"; + rockchip,camera-module-lens-name = "nvp6188"; + + port { + nvp6188_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_nvp6188>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; + // memory-region = <&cif_reserved>; +}; + +&rkcif_mmu { + status = "okay"; +}; + diff --git a/rk3588-vehicle-evb-thine_thcv244.dtsi b/rk3588-vehicle-evb-thine_thcv244.dtsi new file mode 100644 index 0000000..a41675d --- /dev/null +++ b/rk3588-vehicle-evb-thine_thcv244.dtsi @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dcphy0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&thcv244_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + thcv244: thcv244@b { + compatible = "thine,thcv244"; + status = "okay"; + reg = <0xb>; + // clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + // clock-names = "xvclk"; + // power-domains = <&power RK3588_PD_VI>; + // pinctrl-names = "default"; + // pinctrl-0 = <&mipim0_camera1_clk>; + // rockchip,grf = <&sys_grf>; + /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ + // reset-gpios = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "thcv244"; + rockchip,camera-module-lens-name = "thcv244"; + + port { + thcv244_out: endpoint { + remote-endpoint = <&mipi_dcphy0_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi0_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi0_in: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; diff --git a/rk3588-vehicle-evb-v10.dts b/rk3588-vehicle-evb-v10.dts new file mode 100644 index 0000000..e4c9ef6 --- /dev/null +++ b/rk3588-vehicle-evb-v10.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-evb.dtsi" +#include "rk3588-vehicle-evb-mipi-nvp6188.dtsi" +#include "rk3588-vehicle-evb-thine_thcv244.dtsi" +#include "rk3588-vehicle-evb-image-reverse.dtsi" +#include "rk3588-vehicle-serdes-display.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE EVB V10 Board"; + compatible = "rockchip,rk3588-vehicle-evb-v10", "rockchip,rk3588"; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; +}; + +&i2s2_2ch{ + pinctrl-0 = <&i2s2m0_lrck + &i2s2m0_sclk + &i2s2m0_sdi + &i2s2m0_sdo>; + status = "okay"; +}; diff --git a/rk3588-vehicle-evb-v20.dts b/rk3588-vehicle-evb-v20.dts new file mode 100644 index 0000000..2dd0381 --- /dev/null +++ b/rk3588-vehicle-evb-v20.dts @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-evb-v20.dtsi" +#include "rk3588-vehicle-evb-mipi-nvp6188.dtsi" +#include "rk3588-vehicle-evb-image-reverse.dtsi" +#include "rk3588-vehicle-serdes-display-v20.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE EVB V20 Board"; + compatible = "rockchip,rk3588-vehicle-evb-v20", "rockchip,rk3588"; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; + + nvp6188_osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <27000000>; + clock-output-names = "nvp6188-osc"; + }; +}; + +&cif_sensor { + nvp6188 { + powerdown-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c7 { + status = "okay"; + /delete-node/ nvp6188@33; + nvp6188: nvp6188@31 { + compatible = "nvp6188"; + status = "okay"; + reg = <0x31>; + clocks = <&nvp6188_osc 0>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + /*power-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;*/ + reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "nvp6188"; + rockchip,camera-module-lens-name = "nvp6188"; + + port { + nvp6188_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_nvp6188>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + status = "okay"; +}; + +&pinctrl { + + bl { + bl0_enable_pin: bl0-enable-pin { + rockchip,pins = + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + + bl1_enable_pin: bl1-enable-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl2_enable_pin: bl2-enable-pin { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl3_enable_pin: bl3-enable-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl4_enable_pin: bl4-enable-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl5_enable_pin: bl5-enable-pin { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + //dsi0 + ser0_rst_pin: ser0-rst-pin { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + //dsi1 + ser1_rst_pin: ser1-rst-pin { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + //dsi0-i2c2 + touch_gpio_dsi0: touch-gpio-dsi0 { + rockchip,pins = + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //rst + }; + //dsi1-i2c6 + touch_gpio_dsi1: touch-gpio-dsi1 { + rockchip,pins = + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, //rst + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; //int + }; + //dp0-i2c4 + touch_gpio_dp0: touch-gpio-dp0 { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>, //rst + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; //int + }; + //edp0-i2c5 + touch_gpio_edp0: touch-gpio-edp0 { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>, //rst + <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; //int + }; + }; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; diff --git a/rk3588-vehicle-evb-v20.dtsi b/rk3588-vehicle-evb-v20.dtsi new file mode 100644 index 0000000..d562124 --- /dev/null +++ b/rk3588-vehicle-evb-v20.dtsi @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588m.dtsi" +#include "rk3588-vehicle-v20.dtsi" +#include "rk3588-rk806-dual.dtsi" +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <10>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + status = "okay"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm8 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + car_rk3308_sound: car-rk3308-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,car-rk3308-sound"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&spi_codec>; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &phydisb>; + tx_delay = <0x43>; + //rx_delay = <0x3f>; + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m2_xfer>; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + +}; + +&i2s0_8ch { + status = "okay"; + rockchip,tdm-fsync-half-frame; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pinctrl { + gmac0 { + phydisb: phydisb { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rk3308 { + rk3308_reset: rk3308-reset { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m2_pins>; + status = "okay"; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m1_pins>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + status = "okay"; +}; + +&sdmmc { + status = "disabled"; +}; + +&spi4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + + spi_codec: spi-codec@1 { + compatible ="rockchip,spi-codec"; + reg = <1>; + spi-lsb-first; + spi-max-frequency = <5000000>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rk3308_reset>; + status = "okay"; + }; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer &uart9m1_ctsn>; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; diff --git a/rk3588-vehicle-evb-v21.dts b/rk3588-vehicle-evb-v21.dts new file mode 100644 index 0000000..258ec54 --- /dev/null +++ b/rk3588-vehicle-evb-v21.dts @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-evb-v21.dtsi" +#include "rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi" +#include "rk3588-vehicle-serdes-mfd-display-rohm.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE EVB V21 Board"; + compatible = "rockchip,rk3588-vehicle-evb-v21", "rockchip,rk3588"; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + reverse { + label = "GPIO Key Reverse"; + linux,code = ; + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + + park { + label = "GPIO Key Park"; + linux,code = ; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + }; +}; + +&i2c2 { + himax@48 { + himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c4 { + himax@48 { + himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c5 { + ilitek@41 { + interrupt-parent = <&gpio0>; + interrupts = ; + reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c6 { + himax@48 { + himax,irq-gpio = <&gpio1 RK_PB7 IRQ_TYPE_EDGE_FALLING>; //use rst as int + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + status = "okay"; +}; + + +&pinctrl { + + bl { + bl0_enable_pin: bl0-enable-pin { + rockchip,pins = + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + + bl1_enable_pin: bl1-enable-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl2_enable_pin: bl2-enable-pin { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl3_enable_pin: bl3-enable-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl4_enable_pin: bl4-enable-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl5_enable_pin: bl5-enable-pin { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + //dsi0 + ser0_rst_pin: ser0-rst-pin { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + //dsi1 + ser1_rst_pin: ser1-rst-pin { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + //dsi0-i2c2 + touch_gpio_dsi0: touch-gpio-dsi0 { + rockchip,pins = + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //rst + }; + //dsi1-i2c6 + touch_gpio_dsi1: touch-gpio-dsi1 { + rockchip,pins = + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, //rst + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; //int + }; + //dp0-i2c4 + touch_gpio_dp0: touch-gpio-dp0 { + rockchip,pins = + <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>, //rst + <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; //int + }; + //edp0-i2c5 + touch_gpio_edp0: touch-gpio-edp0 { + rockchip,pins = + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>, //rst + <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>; //int + }; + }; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vdd_1v8_pll_s0 { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; +}; diff --git a/rk3588-vehicle-evb-v21.dtsi b/rk3588-vehicle-evb-v21.dtsi new file mode 100644 index 0000000..3624b81 --- /dev/null +++ b/rk3588-vehicle-evb-v21.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588m.dtsi" +#include "rk3588-vehicle-v20.dtsi" +#include "rk3588-rk806-dual.dtsi" +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_wifi"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <10>; + reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm8 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + car_rk3308_sound: car-rk3308-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,car-rk3308-sound"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&spi_codec>; + }; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &phydisb>; + tx_delay = <0x43>; + //rx_delay = <0x3f>; + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m2_xfer>; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + +}; + +&i2s0_8ch { + status = "okay"; + rockchip,tdm-fsync-half-frame; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + rockchip,perst-inactive-ms = <500>; + rockchip,skip-scan-in-resume; + vpcie3v3-supply = <&vcc3v3_pcie_wifi>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pinctrl { + gmac0 { + phydisb: phydisb { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + }; + + rk3308 { + rk3308_reset: rk3308-reset { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m2_pins>; + status = "okay"; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m1_pins>; + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&spi4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs1 &spi4m0_pins>; + + spi_codec: spi-codec@1 { + compatible ="rockchip,spi-codec"; + reg = <1>; + spi-lsb-first; + spi-max-frequency = <5000000>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rk3308_reset>; + status = "okay"; + }; +}; + +&uart7 { + /delete-property/ dmas; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer &uart9m1_ctsn>; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; diff --git a/rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi b/rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi new file mode 100644 index 0000000..bfb50d3 --- /dev/null +++ b/rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + nca9539_vdd: nca9539-vdd3v3 { + compatible = "regulator-fixed"; + regulator-name = "nca9539_vdd"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <20>; // NCA9539 POR + vin-supply = <&vcc_3v3_s0>; + }; + +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + nca9539_gpio: gpio@74 { + status = "okay"; + compatible = "novo,nca9539-gpio"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + interrupt-controller; + #interrupt-cells = <2>; + vdd-supply = <&nca9539_vdd>; + }; +}; diff --git a/rk3588-vehicle-evb-v22.dts b/rk3588-vehicle-evb-v22.dts new file mode 100644 index 0000000..c36f02f --- /dev/null +++ b/rk3588-vehicle-evb-v22.dts @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-evb-v21.dtsi" +#include "rk3588-vehicle-evb-v22-nca9539-io-expander.dtsi" +#include "rk3588-vehicle-evb-maxim-max96712-dphy3.dtsi" +#include "rk3588-vehicle-evb-maxim-max96756-dphy0.dtsi" +#include "rk3588-vehicle-serdes-mfd-display-rohm.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE EVB V22 Board"; + compatible = "rockchip,rk3588-vehicle-evb-v22", "rockchip,rk3588"; + + vcc5v0_buck: vcc5v0-buck { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_buck"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_buck_en>; + startup-delay-us = <2500>; + off-on-delay-us = <1500>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <5000000>; + }; + }; + + vcc4v0_sys_mode: vcc4v0-sys-mode { + compatible = "regulator-fixed"; + regulator-name = "vcc4v0_sys_mode"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + enable-active-high; + gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; + vin-supply = <&vcc12v_dcin>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc4v0_sys_mode_en>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <4000000>; + }; + }; + + lcd1_vcc12v_buck: lcd1_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd1_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd2_vcc12v_buck: lcd2_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd2_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd3_vcc12v_buck: lcd3_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd3_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd4_vcc12v_buck: lcd4_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd4_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd5_vcc12v_buck: lcd5_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd5_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + lcd6_vcc12v_buck: lcd6_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "lcd6_vcc12v_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dcphy0_vcc12v_buck: dcphy0_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dcphy0_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dcphy1_vcc12v_buck: dcphy1_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dcphy1_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dphy0_vcc12v_buck: dphy0_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dphy0_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 8 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + dphy3_vcc12v_buck: dphy3_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "dphy3_vcc12v_buck"; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + vcc5v0_host_usb20: vcc5v0-host-usb20 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host_usb20"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&nca9539_gpio 10 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_host_usb30: vcc5v0-host-usb30 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host_usb30"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&nca9539_gpio 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <2000>; + off-on-delay-us = <16000>; + vin-supply = <&vcc5v0_usb>; + }; + + adsp_vcc12v_buck: adsp_vcc12v-buck { + compatible = "regulator-fixed"; + regulator-name = "adsp_vcc12v_buck"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + enable-active-high; + gpio = <&nca9539_gpio 12 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc12v_dcin>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <12000000>; + }; + }; + + minipcie_power_buck: minipcie_power-buck { + compatible = "regulator-fixed"; + regulator-name = "minipcie_power_buck"; + regulator-boot-on; + //regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&nca9539_gpio 13 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_buck>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + reverse { + label = "GPIO Key Reverse"; + linux,code = ; + gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + + park { + label = "GPIO Key Park"; + linux,code = ; + gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; + debounce-interval = <100>; + }; + }; + + vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_wifi"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s3>; + }; + + wireless_bluetooth: wireless-bluetooth { + BT,reset_gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + WIFI,poweren_gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&max96712_dphy3_vcc1v2 { + vin-supply = <&vcc5v0_buck>; +}; + +&max96712_dphy3_poc { + vin-supply = <&dphy3_vcc12v_buck>; +}; + +&max96756_dphy0_vcc1v2 { + vin-supply = <&vcc5v0_buck>; +}; + +&avdd1v8_ddr_pll_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck + &i2s2m1_sclk + &i2s2m1_sdi + &i2s2m1_sdo>; + status = "okay"; +}; + +&i2c2 { + himax@48 { + himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c2_bu18tl82 { + route-enable; + //use-delay-work; +}; + +&i2c2_bu18rl82 { + //use-delay-work; + vpower-supply = <&lcd1_vcc12v_buck>; +}; + +&i2c4 { + himax@48 { + himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c4_bu18tl82 { + //use-delay-work; +}; + +&i2c4_bu18rl82 { + //use-delay-work; + vpower-supply = <&lcd5_vcc12v_buck>; +}; + +&i2c5 { + ilitek@41 { + interrupt-parent = <&gpio1>; + interrupts = ; + }; +}; + +&i2c5_bu18tl82 { + //use-delay-work; +}; + +&i2c5_bu18rl82 { + //use-delay-work; + vpower-supply = <&lcd3_vcc12v_buck>; +}; + +&i2c6 { + himax@48 { + himax,irq-gpio = <&gpio1 RK_PB7 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&i2c6_bu18tl82 { + route-enable; + //use-delay-work; +}; + +&i2c6_bu18rl82 { + use-delay-work; + vpower-supply = <&lcd2_vcc12v_buck>; +}; + +&pinctrl { + pinctrl-names = "init"; + pinctrl-0 = <&max96712_dphy3_pwdn + &max96712_dphy3_errb + &max96712_dphy3_lock>; + + bl { + bl0_enable_pin: bl0-enable-pin { + rockchip,pins = + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + + bl1_enable_pin: bl1-enable-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl2_enable_pin: bl2-enable-pin { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl3_enable_pin: bl3-enable-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl4_enable_pin: bl4-enable-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl5_enable_pin: bl5-enable-pin { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + max96712-dphy3 { + max96712_dphy3_pwdn: max96712-dphy3-pwdn { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy3_errb: max96712-dphy3-errb { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy3_lock: max96712-dphy3-lock { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; + + touch { + //dsi0-i2c2 + touch_gpio_dsi0: touch-gpio-dsi0 { + rockchip,pins = + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //RST->V22 INT + }; + //dsi1-i2c6 + touch_gpio_dsi1: touch-gpio-dsi1 { + rockchip,pins = + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; //RST->V22 INT + }; + //dp0-i2c4 + touch_gpio_dp0: touch-gpio-dp0 { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + //edp0-i2c5 + touch_gpio_edp0: touch-gpio-edp0 { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; //RST->V22 INT + }; + }; + + vcc5v0-buck { + vcc5v0_buck_en: vcc5v0-buck-en { + rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + vcc4v0-mode { + vcc4v0_sys_mode_en: vcc4v0-sys-mode-en { + rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_CPU0_WKUP_EN + | RKPM_GPIO_WKUP_EN + ) + >; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host_usb20>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host_usb20>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host_usb30>; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vdd_1v8_pll_s0 { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; +}; + +&vcc5v0_host { + status = "disabled"; +}; + diff --git a/rk3588-vehicle-evb.dtsi b/rk3588-vehicle-evb.dtsi new file mode 100644 index 0000000..15ccc0f --- /dev/null +++ b/rk3588-vehicle-evb.dtsi @@ -0,0 +1,675 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588m.dtsi" +#include "rk3588-vehicle.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + es8388_sound: es8388-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm3 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + rk_headset: rk-headset { + status = "disabled"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + io-channels = <&saradc 3>; + }; + + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc5v0_otg: vcc5v0-otg { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_otg"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_otg_en>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + dummy_codec: dummy-codec { + status = "okay"; + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&rk3308_reset>; + }; + + car_rk3308_sound: car-rk3308-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,car-rk3308-sound"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,bitclock-master = <&codec_master>; + simple-audio-card,frame-master = <&codec_master>; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + }; + codec_master: simple-audio-card,codec { + sound-dai = <&dummy_codec>; + }; + }; +}; + +&backlight { + pwms = <&pwm1 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac1 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus>; + + tx_delay = <0x43>; + /* rx_delay = <0x3f>; */ + + phy-handle = <&rgmii_phy>; + status = "disabled"; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi1_in_vp0 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&hdptxphy_hdmi1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m2_xfer>; + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + +}; + +&i2c5 { + status = "okay"; + +}; + +&i2c6 { + status = "okay"; + +}; + +&i2c7 { + status = "okay"; + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,tdm-fsync-half-frame; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdo0 + &i2s0_sdo1 + &i2s0_sdo2 + &i2s0_sdo3>; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&i2s7_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "disabled"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pinctrl { + cam { + mipicsi0_pwr: mipicsi0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipicsi1_pwr: mipicsi1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_otg_en: vcc5v0-otg-en { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + rk3308 { + rk3308_reset: rk3308-reset { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3m1_pins>; + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&route_hdmi0 { + status = "okay"; +}; + +&route_hdmi1 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom0_pins>; + sd-uhs-sdr104; + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_otg>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_otg>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; diff --git a/rk3588-vehicle-maxim-cameras-s66.dtsi b/rk3588-vehicle-maxim-cameras-s66.dtsi new file mode 100644 index 0000000..c9a6c4e --- /dev/null +++ b/rk3588-vehicle-maxim-cameras-s66.dtsi @@ -0,0 +1,1177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ +#include + +/ { + max96712_dphy0_osc0: max96712-dphy0-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96712-dphy0-osc0"; + }; + + max96722_dphy3_osc0: max96722-dphy3-oscillator@0 { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + clock-output-names = "max96722-dphy3-osc0"; + }; +}; + +/** + * ============================================================================ + * Inno DPHY0: full mode + * ============================================================================ + */ +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy0_in_max96712: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96712_dphy0_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi2_in: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +/** + * ============================================================================ + * Inno DPHY1: full mode + * ============================================================================ + */ +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_dphy3_in_max96722: endpoint@1 { + reg = <1>; + remote-endpoint = <&max96722_dphy3_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy3_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy3_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi4_in>; + }; + }; + }; +}; + +&rkcif_mipi_lvds4 { + status = "okay"; + /* parameters for do cif reset detecting: + * index0: monitor mode, + 0 for idle, + 1 for continue, + 2 for trigger, + 3 for hotplug (for nextchip) + * index1: the frame id to start timer, + min is 2 + * index2: frame num of monitoring cycle + * index3: err time for keep monitoring + after finding out err (ms) + * index4: csi2 err reference val for resetting + */ + rockchip,cif-monitor = <3 2 1 1000 5>; + + port { + cif_mipi4_in: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +/** + * ============================================================================= + * Common + * ============================================================================= + */ +&rkcif { + status = "okay"; + rockchip,android-usb-camerahal-enable; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + // AVM Camera x4 + max96712_dphy0: max96712@29 { + compatible = "maxim4c,max96712"; + status = "okay"; + reg = <0x29>; + clock-names = "xvclk"; + clocks = <&max96712_dphy0_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96712_dphy0_pwdn>, <&max96712_dphy0_errb>, <&max96712_dphy0_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96712"; + rockchip,camera-module-lens-name = "max96712"; + + port { + max96712_dphy0_out: endpoint { + remote-endpoint = <&mipi_dphy0_in_max96712>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1280>; + sensor-height = <800>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link0_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + 0B 06 ef 00 00 // HIM on + 0B 07 84 00 00 // Enable HVEN and DBL + 0B 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link1_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + 0C 06 ef 00 00 // HIM on + 0C 07 84 00 00 // Enable HVEN and DBL + 0C 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link C: link-id = 2 + gmsl-link-config-2 { + status = "okay"; + link-id = <2>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link2_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote2_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 16 D1 03 00 00 // VGAHiGain + 16 45 00 00 00 // Disable SSC + 0D 06 ef 00 00 // HIM on + 0D 07 84 00 00 // Enable HVEN and DBL + 0D 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + + // Link D: link-id = 3 + gmsl-link-config-3 { + status = "okay"; + link-id = <3>; // Link ID: 0/1/2/3 + + link-type = <0>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96712_dphy0_link3_in: endpoint { + remote-endpoint = <&max96712_dphy0_remote3_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 17 D1 03 00 00 // VGAHiGain + 17 45 00 00 00 // Disable SSC + 0E 06 ef 00 00 // HIM on + 0E 07 84 00 00 // Enable HVEN and DBL + 0E 0F 01 00 00 // Disable processing DE signals + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + ]; + }; + }; + + // Video Pipe 2 + video-pipe-config-2 { + status = "okay"; + pipe-id = <2>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <2>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 2 to Controller 1 + 09 8B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 AD 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 8D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 8E 9e 00 00 // DST0 VC = 2, DT = YUV422 8bit + 09 8F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 90 80 00 00 // DST1 VC = 2, DT = Frame Start + 09 91 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 92 81 00 00 // DST2 VC = 2, DT = Frame End + ]; + }; + }; + + // Video Pipe 3 + video-pipe-config-3 { + status = "okay"; + pipe-id = <3>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <3>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 3 to Controller 1 + 09 CB 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 ED 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 CD 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 CE de 00 00 // DST0 VC = 3, DT = YUV422 8bit + 09 CF 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 D0 c0 00 00 // DST1 VC = 3, DT = Frame Start + 09 D1 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 D2 c1 00 00 // DST2 VC = 3, DT = Frame End + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <0>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max96715"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x41>; // 0: disable remap + + port { + max96712_dphy0_remote0_out: endpoint { + remote-endpoint = <&max96712_dphy0_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max96715"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x42>; // 0: disable remap + + port { + max96712_dphy0_remote1_out: endpoint { + remote-endpoint = <&max96712_dphy0_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-2 { + compatible = "maxim4c,link2,max96715"; + status = "okay"; + + remote-id = <2>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x43>; // 0: disable remap + + port { + max96712_dphy0_remote2_out: endpoint { + remote-endpoint = <&max96712_dphy0_link2_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + + serdes-remote-device-3 { + compatible = "maxim4c,link3,max96715"; + status = "okay"; + + remote-id = <3>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x44>; // 0: disable remap + + port { + max96712_dphy0_remote3_out: endpoint { + remote-endpoint = <&max96712_dphy0_link3_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <4>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <1>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 07 84 00 00 + 67 c4 00 00 + 0F bf 00 00 + 3F 08 00 00 + 40 2d 00 00 + 20 10 00 00 + 21 11 00 00 + 22 12 00 00 + 23 13 00 00 + 24 14 00 00 + 25 15 00 00 + 26 16 00 00 + 27 17 00 00 + 30 00 00 00 + 31 01 00 00 + 32 02 00 00 + 33 03 00 00 + 34 04 00 00 + 35 05 00 00 + 36 06 00 00 + 37 07 00 00 + ]; + }; + }; + /* serdes remote device end */ + }; + + // DMS Camera x1 + OMS Camera x3 + max96722_dphy3: max96722@6b { + compatible = "maxim4c,max96722"; + status = "okay"; + reg = <0x6b>; + clock-names = "xvclk"; + clocks = <&max96722_dphy3_osc0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&max96722_dphy3_pwdn>, <&max96722_dphy3_errb>, <&max96722_dphy3_lock>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + lock-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "max96722"; + rockchip,camera-module-lens-name = "max96722"; + + port { + max96722_dphy3_out: endpoint { + remote-endpoint = <&mipi_dphy3_in_max96722>; + data-lanes = <1 2 3 4>; + }; + }; + + /* support mode config start */ + support-mode-config { + status = "okay"; + + bus-format = ; + sensor-width = <1600>; + sensor-height = <1300>; + max-fps-numerator = <10000>; + max-fps-denominator = <300000>; + bpp = <16>; + link-freq-idx = <20>; + vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7 + }; + /* support mode config end */ + + /* serdes local device start */ + serdes-local-device { + status = "okay"; + + /* GMSL LINK config start */ + gmsl-links { + status = "okay"; + + link-vdd-ldo1-en = <1>; + link-vdd-ldo2-en = <1>; + + // Link A: link-id = 0 + gmsl-link-config-0 { + status = "okay"; + link-id = <0>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy3_link0_in: endpoint { + remote-endpoint = <&max96722_dphy3_remote0_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 14 D1 03 00 00 // VGAHiGain + 14 45 00 00 00 // Disable SSC + ]; + }; + }; + + // Link B: link-id = 1 + gmsl-link-config-1 { + status = "okay"; + link-id = <1>; // Link ID: 0/1/2/3 + + link-type = <1>; + link-rx-rate = <0>; + link-tx-rate = <0>; + + port { + max96722_dphy3_link1_in: endpoint { + remote-endpoint = <&max96722_dphy3_remote1_out>; + }; + }; + + link-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 15 D1 03 00 00 // VGAHiGain + 15 45 00 00 00 // Disable SSC + ]; + }; + }; + }; + /* GMSL LINK config end */ + + /* VIDEO PIPE config start */ + video-pipes { + status = "okay"; + + // Video Pipe 0 + video-pipe-config-0 { + status = "okay"; + pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <0>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 0 to Controller 1 + 09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 2D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit + 09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 10 00 00 00 // DST1 VC = 0, DT = Frame Start + 09 11 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 12 01 00 00 // DST2 VC = 0, DT = Frame End + // pipe Cross + 01 D9 59 00 00 // pipe 0: Inverts Cross VS + ]; + }; + }; + + // Video Pipe 1 + video-pipe-config-1 { + status = "okay"; + pipe-id = <1>; // Video Pipe 1: pipe-id = 1 + + pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3 + link-idx = <1>; // Link A/B/C/D: 0/1/2/3 + + pipe-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Send YUV422, FS, and FE from Video Pipe 1 to Controller 1 + 09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings + 09 6D 15 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 1; + // For the following MSB 2 bits = VC, LSB 6 bits = DT + 09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit + 09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit + 09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start + 09 50 40 00 00 // DST1 VC = 1, DT = Frame Start + 09 51 01 00 00 // SRC2 VC = 0, DT = Frame End + 09 52 41 00 00 // DST2 VC = 1, DT = Frame End + // pipe Cross + 01 F9 59 00 00 // pipe 1: Inverts Cross VS + ]; + }; + }; + + // Software override for parallel mode + parallel-mode-config { + status = "okay"; + + parallel-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8) + 04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode + 04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00 + 04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00 + 04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit + 04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit + 04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit + 04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37 + 04 15 c0 c0 00 // pipe 0/1 enable software overide + 04 18 c0 c0 00 // pipe 2/3 enable software overide + ]; + }; + }; + }; + /* VIDEO PIPE config end */ + + /* MIPI TXPHY config start */ + mipi-txphys { + status = "okay"; + + phy-mode = <0>; + phy-force-clock-out = <1>; + phy-force-clk0-en = <0>; + phy-force-clk3-en = <0>; + + // MIPI TXPHY A: phy-id = 0 + mipi-txphy-config-0 { + status = "okay"; + phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0x4>; + vc-ext-en = <0>; + }; + + // MIPI TXPHY B: phy-id = 1 + mipi-txphy-config-1 { + status = "okay"; + phy-id = <1>; // MIPI TXPHY ID: 0/1/2/3 + + phy-type = <0>; + auto-deskew = <0x80>; + data-lane-num = <4>; + data-lane-map = <0xe>; + vc-ext-en = <0>; + }; + }; + /* MIPI TXPHY config end */ + + /* local device extra init sequence */ + extra-init-sequence { + status = "disabled"; + + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + // common init sequence such as fsync / gpio and so on + ]; + }; + }; + /* serdes local device end */ + + /* serdes remote device start */ + serdes-remote-device-0 { + compatible = "maxim4c,link0,max9295"; + status = "okay"; + + remote-id = <0>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x45>; // 0: disable remap + + port { + max96722_dphy3_remote0_out: endpoint { + remote-endpoint = <&max96722_dphy3_link0_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + + serdes-remote-device-1 { + compatible = "maxim4c,link1,max9295"; + status = "okay"; + + remote-id = <1>; // Same as Link ID: 0/1/2/3 + + // Serializer i2c 7bit address remap + ser-i2c-addr-def = <0x40>; + ser-i2c-addr-map = <0x46>; // 0: disable remap + + port { + max96722_dphy3_remote1_out: endpoint { + remote-endpoint = <&max96722_dphy3_link1_in>; + }; + }; + + remote-init-sequence { + seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1 + reg-addr-len = <2>; // 1: 8bits, 2: 16bits + reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits + + // reg_addr reg_val val_mask delay + init-sequence = [ + 00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps + 00 11 03 00 00 // Coax Drive + 02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1 + 03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL + 00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL + 00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected + 02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0 + 02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup + 00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable + 00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled + 00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE + 01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high + 01 01 50 00 00 // Video X, BPP = 0x10 + 00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel + 00 02 13 00 00 // Video transmit enable for Port X + ]; + }; + }; + /* serdes remote device end */ + }; +}; + +&pinctrl { + maxim-cameras { + max96712_dphy0_pwdn: max96712-dphy0-pwdn { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96712_dphy0_errb: max96712-dphy0-errb { + rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96712_dphy0_lock: max96712-dphy0-lock { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96722_dphy3_pwdn: max96722-dphy3-pwdn { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_output_low>; + }; + + max96722_dphy3_errb: max96722-dphy3-errb { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + + max96722_dphy3_lock: max96722-dphy3-lock { + rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none_smt>; + }; + }; +}; diff --git a/rk3588-vehicle-maxim-serdes-display-s66.dtsi b/rk3588-vehicle-maxim-serdes-display-s66.dtsi new file mode 100644 index 0000000..588e569 --- /dev/null +++ b/rk3588-vehicle-maxim-serdes-display-s66.dtsi @@ -0,0 +1,564 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + aliases { + pinctrl0 = &pinctrl; + }; + + backlight { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + i2c8_max96755f_backlight: backlight@0 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm0 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c8_max96745_1_backlight: backlight@1 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm1 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c8_max96745_2_backlight: backlight@2 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm7 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + }; +}; + +&dp0 { + //split-mode; + force-hpd; + status = "disabled"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&route_dp0 { + connect = <&vp0_out_dp0>; + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "disabled"; +}; + +&usbdp_phy1 { + //rockchip,dp-lane-mux = <0 1 2 3>; + status = "disabled"; +}; + +&usbdp_phy1_dp { + status = "disabled"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&i2c8_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&route_dsi0 { + connect = <&vp2_out_dsi0>; + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out: endpoint { + //remote-endpoint = <&i2c6_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&route_dsi1 { + connect = <&vp3_out_dsi1>; + status = "disabled"; +}; + +&edp0 { + split-mode; + force-hpd; + status = "disabled"; +}; + +&edp0_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96745_1_in>; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&route_edp0 { + connect = <&vp1_out_edp0>; + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "disabled"; +}; + +&edp1_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96745_2_in>; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m4_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96755f@62 { + compatible = "maxim,max96755f"; + reg = <0x62>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_ser1_lock_pins>, <&i2c8_ser1_pwdnb_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96755f-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96755f_pinctrl_hog>; + + i2c8_max96755f_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96755f_panel_pins: panel-pins { + bl-pwm { + pins = "MFP7"; + function = "GPIO_TX_0"; + }; + + tp-int { + pins = "MFP8"; + function = "GPIO_RX_2"; + }; + }; + }; + + bridge { + compatible = "maxim,max96755f-bridge"; + lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + bridge_dual_link; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96755f_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96755f_out: endpoint { + remote-endpoint = <&i2c8_max96755f_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + ts@30 { + compatible = "gac,gac_ts"; + reg = <0x30>; + pinctrl-names = "pmx_ts_active","pmx_ts_suspend"; + pinctrl-0 = <&touch_pin>; + pinctrl-1 = <&touch_pin>; + interrupt-parent = <&gpio1>; + interrupts = ; + gac,max_x = <2560>; + gac,max_y = <1440>; + }; + + panel@48 { + compatible = "boe,ae146m1t-l10"; + reg = <0x48>; + backlight = <&i2c8_max96755f_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96755f_panel_pins>; + panel_dual_link; + + panel-timing { + clock-frequency = <303000000>; + hactive = <2560>; + vactive = <1440>; + hfront-porch = <122>; + hsync-len = <60>; + hback-porch = <60>; + vfront-porch = <340>; + vsync-len = <2>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96755f_panel_in: endpoint { + remote-endpoint = <&i2c8_max96755f_out>; + }; + }; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_ser2_lock_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_1_pinctrl_hog>; + + i2c8_max96745_1_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96745_1_panel_pins: panel-pins { + bl-pwm { + pins = "MFP11"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96745_1_in: endpoint { + remote-endpoint = <&edp0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96745_1_out: endpoint { + remote-endpoint = <&i2c8_max96745_1_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c8_max96745_1_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_1_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96745_1_panel_in: endpoint { + remote-endpoint = <&i2c8_max96745_1_out>; + }; + }; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + + max96745@60 { + compatible = "maxim,max96745"; + reg = <0x60>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_ser3_lock_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_2_pinctrl_hog>; + + i2c8_max96745_2_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96745_2_panel_pins: panel-pins { + bl-pwm { + pins = "MFP11"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96745_2_in: endpoint { + remote-endpoint = <&edp1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96745_2_out: endpoint { + remote-endpoint = <&i2c8_max96745_2_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c8_max96745_2_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_2_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96745_2_panel_in: endpoint { + remote-endpoint = <&i2c8_max96745_2_out>; + }; + }; + }; + }; + }; +}; + +&pinctrl { + serdes { + i2c8_ser1_lock_pins: i2c8-ser1-lock-pins { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser2_lock_pins: i2c8-ser2-lock-pins { + rockchip,pins = + <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser3_lock_pins: i2c8-ser3-lock-pins { + rockchip,pins = + <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser1_errb_pins: i2c8-ser1-errb-pins { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser2_errb_pins: i2c8-ser2-errb-pins { + rockchip,pins = + <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser3_errb_pins: i2c8-ser3-errb-pins { + rockchip,pins = + <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_ser1_pwdnb_pins: i2c8-ser1-pwdnb-pins { + rockchip,pins = + <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_pin: touch-pin { + rockchip,pins = + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1m1_pins>; + status = "okay"; +}; + +&pwm7 { + pinctrl-0 = <&pwm7m3_pins>; + status = "okay"; +}; diff --git a/rk3588-vehicle-maxim-serdes.dtsi b/rk3588-vehicle-maxim-serdes.dtsi new file mode 100644 index 0000000..8b05614 --- /dev/null +++ b/rk3588-vehicle-maxim-serdes.dtsi @@ -0,0 +1,864 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + aliases { + pinctrl0 = &pinctrl; + }; + + backlight { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + i2c2_max96755f_backlight: backlight@0 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm6 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c3_max96745_backlight: backlight@1 { + compatible = "pwm-backlight"; + reg = <1>; + pwms = <&pwm10 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c5_max96745_backlight: backlight@2 { + compatible = "pwm-backlight"; + reg = <2>; + pwms = <&pwm12 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c6_max96755f_backlight: backlight@3 { + compatible = "pwm-backlight"; + reg = <3>; + pwms = <&pwm13 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c7_max96745_backlight: backlight@4 { + compatible = "pwm-backlight"; + reg = <4>; + pwms = <&pwm11 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c8_max96745_backlight: backlight@5 { + compatible = "pwm-backlight"; + reg = <5>; + pwms = <&pwm14 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + }; +}; + +&dp0 { + split-mode; + force-hpd; + status = "okay"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c3_max96745_in>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&route_dp0 { + connect = <&vp0_out_dp0>; + status = "okay"; +}; + +&dp1 { + force-hpd; + status = "okay"; +}; + +&dp1_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96745_in>; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&i2c2_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&route_dsi0 { + connect = <&vp2_out_dsi0>; + status = "okay"; +}; + +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out: endpoint { + remote-endpoint = <&i2c6_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&route_dsi1 { + connect = <&vp3_out_dsi1>; + status = "okay"; +}; + +&edp0 { + split-mode; + force-hpd; + status = "okay"; +}; + +&edp0_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c5_max96745_in>; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&route_edp0 { + connect = <&vp1_out_edp0>; + status = "okay"; +}; + +&edp1 { + force-hpd; + status = "okay"; +}; + +&edp1_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c7_max96745_in>; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96755f@40 { + compatible = "maxim,max96755f"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96755f-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_max96755f_pinctrl_hog>; + + i2c2_max96755f_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c2_max96755f_panel_pins: panel-pins { + bl-pwm { + pins = "MFP18"; + function = "GPIO_TX_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96755f-bridge"; + lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_max96755f_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_max96755f_out: endpoint { + remote-endpoint = <&i2c2_max96755f_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c2_max96755f_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_max96755f_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c2_max96755f_panel_in: endpoint { + remote-endpoint = <&i2c2_max96755f_out>; + }; + }; + }; + }; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_max96745_pinctrl_hog>; + + i2c3_max96745_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c3_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MFP0"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c3_max96745_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c3_max96745_out: endpoint { + remote-endpoint = <&i2c3_max96745_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c3_max96745_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_max96745_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c3_max96745_panel_in: endpoint { + remote-endpoint = <&i2c3_max96745_out>; + }; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_max96745_pinctrl_hog>; + + i2c5_max96745_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c5_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MFP0"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_max96745_in: endpoint { + remote-endpoint = <&edp0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_max96745_out: endpoint { + remote-endpoint = <&i2c5_max96745_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c5_max96745_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_max96745_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c5_max96745_panel_in: endpoint { + remote-endpoint = <&i2c5_max96745_out>; + }; + }; + }; + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96755f@40 { + compatible = "maxim,max96755f"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96755f-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_max96755f_pinctrl_hog>; + + i2c6_max96755f_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + + i2c6_max96755f_panel_pins: panel-pins { + bl-pwm { + pins = "MFP18"; + function = "GPIO_TX_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96755f-bridge"; + lock-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_max96755f_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_max96755f_out: endpoint { + remote-endpoint = <&i2c6_max96755f_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c6_max96755f_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_max96755f_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c6_max96755f_panel_in: endpoint { + remote-endpoint = <&i2c6_max96755f_out>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m3_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_max96745_pinctrl_hog>; + + i2c7_max96745_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c7_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MFP0"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_max96745_in: endpoint { + remote-endpoint = <&edp1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_max96745_out: endpoint { + remote-endpoint = <&i2c7_max96745_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c7_max96745_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_max96745_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c7_max96745_panel_in: endpoint { + remote-endpoint = <&i2c7_max96745_out>; + }; + }; + }; + }; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_pinctrl_hog>; + + i2c8_max96745_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MFP0"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96745_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96745_out: endpoint { + remote-endpoint = <&i2c8_max96745_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c8_max96745_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96745_panel_in: endpoint { + remote-endpoint = <&i2c8_max96745_out>; + }; + }; + }; + }; + }; +}; + +&pinctrl { + serdes { + i2c2_serdes_pins: i2c2-serdes-pins { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c3_serdes_pins: i2c3-serdes-pins { + rockchip,pins = + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c5_serdes_pins: i2c5-serdes-pins { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c6_serdes_pins: i2c6-serdes-pins { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c7_serdes_pins: i2c7-serdes-pins { + rockchip,pins = + <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_serdes_pins: i2c8-serdes-pins { + rockchip,pins = + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm6 { + pinctrl-0 = <&pwm6m1_pins>; + status = "okay"; +}; + +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; + status = "okay"; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; diff --git a/rk3588-vehicle-s66-v10.dts b/rk3588-vehicle-s66-v10.dts new file mode 100644 index 0000000..59abe8d --- /dev/null +++ b/rk3588-vehicle-s66-v10.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588-vehicle-s66-v10.dtsi" +#include "rk3588-vehicle-adsp-audio-s66.dtsi" +#include "rk3588-vehicle-maxim-serdes-display-s66.dtsi" +#include "rk3588-vehicle-maxim-cameras-s66.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588 VEHICLE S66 Board V10"; + compatible = "rockchip,rk3588-vehicle-s66-v10", "rockchip,rk3588"; +}; + +&rockchip_suspend { + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_DDRPD + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + status = "okay"; +}; + +&vdd_log_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; +}; + +&vcc_3v3_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; +}; + +&vcc_1v8_s0 { + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; +}; + +&vccio_sd_s0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&vdd_0v75_hdmi_edp_s0 { + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; +}; + +&vdd_cpu_big1_mem_s0 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +&vdd_cpu_big0_mem_s0 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; +}; + +&vdd_cpu_lit_mem_s0 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; +}; + +&vdd_gpu_mem_s0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + }; +}; + +&pinctrl { + pinctrl-names = "init"; + pinctrl-0 = <&max96712_dphy0_pwdn + &max96712_dphy0_errb + &max96712_dphy0_lock + &max96722_dphy3_pwdn + &max96722_dphy3_errb + &max96722_dphy3_lock>; +}; diff --git a/rk3588-vehicle-s66-v10.dtsi b/rk3588-vehicle-s66-v10.dtsi new file mode 100644 index 0000000..6cd0f02 --- /dev/null +++ b/rk3588-vehicle-s66-v10.dtsi @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588m.dtsi" +#include "rk3588-vehicle-s66.dtsi" +#include "rk3588-rk806-dual.dtsi" +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie_wifi: vcc3v3-pcie-wifi { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie_wifi"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + //gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + //pinctrl-names = "default"; + //pinctrl-0 = <&vcc5v0_host_en>; + //TODO: should powered by MCU + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + BT,reset_gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + WIFI,poweren_gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy1_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&gmac0 { + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + tx_delay = <0x43>; + //rx_delay = <0x3f>; + phy-handle = <&rgmii_phy>; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + iam20680_acc: acc@69 { + compatible = "iam20680_acc"; + reg = <0x69>; + irq-gpio = <&gpio1 RK_PC2 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <1>; + poll_delay_ms = <30>; + type = ; + layout = <1>; + }; + + iam20680_gyro: gyro@69 { + compatible = "iam20680_gyro"; + reg = <0x69>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <1>; + }; + + //todo, add mfi +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4m0_xfer>; + //todo, add LT9211 +}; + +&mdio0 { + rgmii_phy: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pcie2x1l0 { + status = "disabled"; +}; + +&pcie2x1l1 { + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + rockchip,perst-inactive-ms = <500>; + vpcie3v3-supply = <&vcc3v3_pcie_wifi>; + status = "okay"; +}; + +&pcie30phy { + rockchip,pcie30-phymode = ; + status = "disabled"; +}; + +&pcie3x4 { + num-lanes = <1>; + status = "disabled"; +}; + +&sata0 { + status = "disabled"; +}; + +&sdmmc { + status = "disabled"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn &uart1m1_rtsn>; +}; + +&u2phy1_otg { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <3 2 1 0>; + status = "disabled"; +}; + +&usbdp_phy1_dp { + status = "disabled"; +}; + +&usbdp_phy1_u3 { + maximum-speed = "high-speed"; + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; diff --git a/rk3588-vehicle-s66.dtsi b/rk3588-vehicle-s66.dtsi new file mode 100644 index 0000000..33e9186 --- /dev/null +++ b/rk3588-vehicle-s66.dtsi @@ -0,0 +1,434 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +/ { + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + rockchip,sel-pipe-phystatus; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "disabled"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon=<&u2phy0>; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; + maximum-speed = "high-speed"; + phys = <&u2phy1_otg>; + phy-names = "usb2-phy"; + snps,dis_u2_susphy_quirk; + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588-vehicle-serdes-display-v20.dtsi b/rk3588-vehicle-serdes-display-v20.dtsi new file mode 100644 index 0000000..c51d5eb --- /dev/null +++ b/rk3588-vehicle-serdes-display-v20.dtsi @@ -0,0 +1,2578 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dsi2lvds_panel0: dsi2lvds-panel0 { + compatible = "simple-panel"; + backlight = <&backlight>; + + display-timings { + native-mode = <&dsi2lvds0>; + dsi2lvds0: timing0 { + clock-frequency = <87381333>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <32>; + hsync-len = <10>; + hback-porch = <22>; + vfront-porch = <10>; + vsync-len = <4>; + vback-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel0_in_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_out_panel0>; + }; + }; + }; + }; + + dsi2lvds_panel1: dsi2lvds-panel1 { + compatible = "simple-panel"; + backlight = <&dsi2lvds_backlight1>; + + display-timings { + native-mode = <&dsi2lvds1>; + dsi2lvds1: timing0 { + clock-frequency = <87381333>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <32>; + hsync-len = <10>; + hback-porch = <22>; + vfront-porch = <10>; + vsync-len = <4>; + vback-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel1_in_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_out_panel1>; + }; + }; + }; + }; + + dp2lvds_panel0: dp2lvds-panel0 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight0>; + status = "okay"; + + dp2lvds0_panel_timing: panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c4_bu18rl82: endpoint { + remote-endpoint = <&i2c4_bu18rl82_out_panel0>; + }; + }; + }; + + dp2lvds_panel1: dp2lvds-panel1 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight1>; + status = "okay"; + + dp2lvds1_panel_timing: panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_out_panel1>; + }; + }; + }; + + edp2lvds_panel0: edp2lvds-panel0 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight0>; + status = "okay"; + + edp2lvds0_panel_timing: panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_out_panel0>; + }; + }; + }; + + edp2lvds_panel1: edp2lvds-panel1 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight1>; + status = "okay"; + + edp2lvds1_panel_timing: panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_out_panel1>; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm0 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl0_enable_pin>; + enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm13 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl1_enable_pin>; + enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0 { + split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c4_bu18tl82: endpoint { + remote-endpoint = <&i2c4_bu18tl82_in_dp0>; + }; + }; + }; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_in_dp1>; + }; + }; + }; +}; + +&dp1_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dp2lvds_backlight0 { + pwms = <&pwm10 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl2_enable_pin>; + enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp2lvds_backlight1 { + pwms = <&pwm14 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl3_enable_pin>; + enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&edp0 { + split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp0 { + status = "disabled"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_in_edp1>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm7 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl4_enable_pin>; + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl5_enable_pin>; + enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + i2c2_bu18tl82: i2c2-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + sel-mipi; + status = "okay"; + + serdes-init-sequence = [ + 0021 0008 + 0022 0008 + 0023 0009 + 0024 000a + 0013 0010 + 0014 0010 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 + 0047 0080 + 0048 0007 + 004b 00d0 + 004c 0002 + 004d 00d0 + 004e 0002 + 0051 0080 + 0052 0007 + 0053 0000 + 0054 00c0 + 022b 0076 + 022c 0062 + 022d 0037 + 024d 0061 + 0252 0005 + 0253 0000 + 0258 0000 + 025c 0000 + 025f 0000 + 0274 0030 + 0275 0020 + 032b 002f + 032c 00a1 + 032d 001d + 034d 0060 + 0353 0000 + 0358 0000 + 035c 0000 + 035f 0000 + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0013 0019 + 0014 0001 + 022e 0080 + 0296 0004 + 0297 000d + 032e 0080 + 038e 0000 + 0396 0004 + 0397 000a + 0060 0001 + 0061 0001 + 0018 0000 + 0019 0000 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c2_bu18tl82_pinctrl: i2c2-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c2_bu18tl82_panel_pins>; + status = "okay"; + + i2c2_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + i2c2_bu18tl82_gpio: i2c2-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_bu18tl82_pinctrl 0 160 8>; + }; + }; + + i2c2_bu18tl82_bridge: i2c2-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18tl82_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; + }; + }; + }; + }; + + i2c2_bu18rl82: i2c2-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0002 + 0013 0001 + 001d 0008 + 001f 0006 + 0020 0006 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0001 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0075 0080 + 0076 0007 + 0079 0009 + 007b 00d0 + 007c 0002 + 007d 00d0 + 007e 0002 + 0081 0003 + 0082 000a + 0084 001e + 0086 0001 + 0087 0003 + 0088 0005 + 0089 0014 + 008b 0028 + 008d 0002 + 008e 0004 + 008f 000f + 0090 0001 + 0091 0003 + 0423 00ab + 0424 00aa + 0425 001a + 0429 000a + 045d 0001 + 0523 0097 + 0524 00d0 + 0525 000e + 0529 000a + 055d 0001 + 0426 0080 + 0526 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c2_bu18rl82_pinctrl: i2c2-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c2_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c2_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c2_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c2_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c2_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c2_bu18rl82_gpio: i2c2-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_bu18rl82_pinctrl 0 169 8>; + }; + }; + + i2c2_bu18rl82_bridge: i2c2-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c2_bu18rl82>; + }; + }; + }; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c4_bu18tl82: i2c4-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c4_bu18tl82_pinctrl: i2c4-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c4_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c4_bu18tl82_panel_pins>; + status = "okay"; + + i2c4_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + + }; + + i2c4_bu18tl82_gpio: i2c4-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_bu18tl82_pinctrl 0 178 8>; + }; + }; + + i2c4_bu18tl82_bridge: i2c4-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_bu18tl82_in_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c4_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { + remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; + }; + }; + }; + }; + + i2c4_bu18rl82: i2c4-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c4_bu18rl82_pinctrl: i2c4-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c4_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c4_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c4_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c4_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c4_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c4_bu18rl82_gpio: i2c4-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_bu18rl82_pinctrl 0 187 8>; + }; + }; + + i2c4_bu18rl82_bridge: i2c4-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { + remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c4_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + i2c5_bu18tl82: i2c5-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002e 0004 + 002d 0018 + 0030 0000 + 0033 0018 + 027c 0041 + 027d 0041 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c5_bu18tl82_pinctrl: i2c5-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c5_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c5_bu18tl82_panel_pins>; + status = "okay"; + + i2c5_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO3_TO_SER"; + }; + }; + + + i2c5_bu18tl82_gpio: i2c5-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_bu18tl82_pinctrl 0 196 8>; + }; + }; + + i2c5_bu18tl82_bridge: i2c5-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18tl82_in_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; + }; + }; + }; + }; + + i2c5_bu18rl82: i2c5-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0031 0041 + 0032 0041 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0008 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + 042d 0004 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c5_bu18rl82_pinctrl: i2c5-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c5_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c5_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c5_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c5_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c5_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO4"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c5_bu18rl82_gpio: i2c5-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_bu18rl82_pinctrl 0 205 8>; + }; + }; + + i2c5_bu18rl82_bridge: i2c5-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c5_bu18rl82>; + }; + }; + }; + }; + + + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + clock-frequency = <400000>; + + i2c6_bu18tl82: i2c6-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + sel-mipi; + status = "okay"; + serdes-init-sequence = [ + 0021 0008 + 0022 0008 + 0023 0009 + 0024 000a + 0013 0010 + 0014 0010 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 027c 0070 + 027d 0070 + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 + 0047 0080 + 0048 0007 + 004b 00d0 + 004c 0002 + 004d 00d0 + 004e 0002 + 0051 0080 + 0052 0007 + 0053 0000 + 0054 00c0 + 022b 0076 + 022c 0062 + 022d 0037 + 024d 0061 + 0252 0005 + 0253 0000 + 0258 0000 + 025c 0000 + 025f 0000 + 0274 0030 + 0275 0020 + 032b 002f + 032c 00a1 + 032d 001d + 034d 0060 + 0353 0000 + 0358 0000 + 035c 0000 + 035f 0000 + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0013 0019 + 0014 0001 + 022e 0080 + 0296 0004 + 0297 000d + 032e 0080 + 038e 0000 + 0396 0004 + 0397 000a + 0060 0001 + 0061 0001 + 0018 0000 + 0019 0000 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c6_bu18tl82_pinctrl: i2c6-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c6_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c6_bu18tl82_panel_pins>; + status = "okay"; + + i2c6_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + + i2c6_bu18tl82_gpio: i2c6-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c6_bu18tl82_pinctrl 0 214 8>; + }; + }; + + i2c6_bu18tl82_bridge: i2c6-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18tl82_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; + }; + }; + }; + }; + + i2c6_bu18rl82: i2c6-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0002 + 0013 0001 + 001d 0008 + 001f 0006 + 0020 0006 + 0031 0070 + 0032 0038 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0001 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0075 0080 + 0076 0007 + 0079 0009 + 007b 00d0 + 007c 0002 + 007d 00d0 + 007e 0002 + 0081 0003 + 0082 000a + 0084 001e + 0086 0001 + 0087 0003 + 0088 0005 + 0089 0014 + 008b 0028 + 008d 0002 + 008e 0004 + 008f 000f + 0090 0001 + 0091 0003 + 0423 00ab + 0424 00aa + 0425 001a + 0429 000a + 045d 0001 + 0523 0097 + 0524 00d0 + 0525 000e + 0529 000a + 055d 0001 + 0426 0080 + 0526 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c6_bu18rl82_pinctrl: i2c6-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c6_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c6_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c6_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c6_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c6_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c6_bu18rl82_gpio: i2c6-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c6_bu18rl82_pinctrl 0 223 8>; + }; + }; + + i2c6_bu18rl82_bridge: i2c6-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c6_bu18rl82>; + }; + }; + }; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c7_bu18tl82: i2c7-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c7_bu18tl82_pinctrl: i2c7-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bu18tl82_panel_pins>; + status = "okay"; + + i2c7_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + + i2c7_bu18tl82_gpio: i2c7-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c7_bu18tl82_pinctrl 0 232 8>; + }; + }; + + i2c7_bu18tl82_bridge: i2c7-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18tl82_in_edp1: endpoint { + remote-endpoint = <&edp1_out_i2c7_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; + }; + }; + }; + }; + + i2c7_bu18rl82: i2c7-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c7_bu18rl82_pinctrl: i2c7-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bu18rl82_panel_pins>; + status = "okay"; + + i2c7_bu18rl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "SER_GPIO1_TO_DES"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + }; + + i2c7_bu18rl82_gpio: i2c7-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c7_bu18rl82_pinctrl 0 241 8>; + }; + }; + + i2c7_bu18rl82_bridge: i2c7-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c7_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c8_bu18tl82: i2c8-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c8_bu18tl82_pinctrl: i2c8-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_bu18tl82_panel_pins>; + status = "okay"; + + i2c8_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + + i2c8_bu18tl82_gpio: i2c8-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c8_bu18tl82_pinctrl 0 250 8>; + }; + }; + + i2c8_bu18tl82_bridge: i2c8-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18tl82_in_dp1: endpoint { + remote-endpoint = <&dp1_out_i2c8_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; + }; + }; + }; + }; + + i2c8_bu18rl82: i2c8-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c8_bu18rl82_pinctrl: i2c8-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_bu18rl82_panel_pins>; + status = "okay"; + + i2c8_bu18rl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "SER_GPIO1_TO_DES"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + }; + + i2c8_bu18rl82_gpio: i2c8-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c8_bu18rl82_pinctrl 0 259 8>; + }; + }; + + i2c8_bu18rl82_bridge: i2c8-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c8_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +/* dsi0->serdes->lvds_panel */ +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; +}; + +/* dp0->serdes->lvds_panel */ +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +/* edp1->serdes->lvds_panel */ +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +/* edp0->serdes->lvds_panel */ +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "okay"; +}; + +/* dsi1->serdes->lvds_panel */ +&pwm13 { + status = "okay"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +/* dp1->serdes->lvds_panel */ +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp0_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&vop { + //assigned-clocks = <&cru PLL_V0PLL>; + //assigned-clock-rates = <1152000000>; +}; +//dp01 +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; +//edp01 +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; +//dsi0 +&vp2 { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; +//dsi1 +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; diff --git a/rk3588-vehicle-serdes-display-v21.dtsi b/rk3588-vehicle-serdes-display-v21.dtsi new file mode 100644 index 0000000..425cfee --- /dev/null +++ b/rk3588-vehicle-serdes-display-v21.dtsi @@ -0,0 +1,2095 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dsi2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&backlight>; + + display-timings { + native-mode = <&dsi2lvds0>; + dsi2lvds0: timing0 { + clock-frequency = <115200000>;//115200000/105573600 + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel0_in_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_out_panel0>; + }; + }; + }; + }; + + dsi2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&dsi2lvds_backlight1>; + + display-timings { + native-mode = <&dsi2lvds1>; + dsi2lvds1: timing0 { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel1_in_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_out_panel1>; + }; + }; + }; + }; + + dp2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight0>; + status = "okay"; + + panel-timing { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c4_bu18rl82: endpoint { + remote-endpoint = <&i2c4_bu18rl82_out_panel0>; + }; + }; + }; + + dp2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight1>; + status = "disabled"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_out_panel1>; + }; + }; + }; + + edp2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight0>; + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_out_panel0>; + }; + }; + }; + + edp2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight1>; + status = "disabled"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_out_panel1>; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm0 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl0_enable_pin>; + enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm13 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl1_enable_pin>; + enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0 { + //split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c4_bu18tl82: endpoint { + remote-endpoint = <&i2c4_bu18tl82_in_dp0>; + }; + }; + }; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_in_dp1>; + }; + }; + }; +}; + +&dp1_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dp2lvds_backlight0 { + pwms = <&pwm10 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl2_enable_pin>; + enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp2lvds_backlight1 { + pwms = <&pwm14 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl3_enable_pin>; + enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&edp0 { + //split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp0 { + status = "disabled"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + edp1_out_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_in_edp1>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm7 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl4_enable_pin>; + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl5_enable_pin>; + enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + bu18tl82: bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ser0_rst_pin>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + sel-mipi; + status = "okay"; + + serdes-init-sequence = [ + 0013 0019 + 0014 0008 //014h[3]-lane1 enable + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 297h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0018 //gpio3 input tp_rst + 0034 0005 //bypass des gpio3 + 0036 0000 //gpio4 output tp_int + 0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes + 0054 0080 + 024d 0061 + 0252 0005 + 0274 0030 //I2C slave address of BU18RL82 for accessing via BU18TL82 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 + 0446 00d2 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18tl82_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; + }; + }; + }; + }; + + bu18rl82: bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 + 0058 0002 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0003 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0000 //rl gpio3 output tp-rst + 0061 0005 //bypass ser gpio3 + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0001 //set gpio5 high + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c2_bu18rl82>; + }; + }; + }; + }; + + himax@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi0>; + pinctrl-1 = <&touch_gpio_dsi0>; + himax,location = "himax-touch-dsi0"; + //himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A + 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0018 //gpio3 input tp_rst + 0034 0005 //bypass des gpio3 + 0036 0000 //gpio4 output tp_int + 0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes + 024d 0061 + 0252 0005 + 0274 0030 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 //h_blank=144 + 0446 00d2 //v_blank=210 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_bu18tl82_in_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c4_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { + remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 + 0058 0002 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0003 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0000 //rl gpio3 output tp-rst + 0061 0005 //bypass ser gpio3 + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0001 //set gpio5 high + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { + remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c4_bu18rl82>; + }; + }; + }; + }; + + himax@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dp0>; + pinctrl-1 = <&touch_gpio_dp0>; + himax,location = "himax-touch-dp0"; + himax,irq-gpio = <&gpio0 RK_PC0 IRQ_TYPE_EDGE_FALLING>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0000 //gpio3 output tp_int + 0034 0005 //bypass des gpio3 + 0036 0018 //gpio4 input tp_rst + 0037 0006 //bypass des gpio4 + 027c 0041 + 027d 0041 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18tl82_in_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0031 0041 //i2c addr 0x41 + 0032 0041 //i2c addr 0x41 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0001 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0018 //rl gpio3 input tp-int + 042e 0005 //bypass ser gpio3 + 0061 0005 //bypass ser gpio3 + 0063 0000 //rl gpio4 output tp-rst + 042f 0006 //bypass ser gpio4 + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0007 //bypass ser gpio5 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + 042d 0004 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c5_bu18rl82>; + }; + }; + }; + }; + + ilitek@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio_edp0>; + reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + ilitek,name = "ilitek_i2c"; + status = "okay"; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + clock-frequency = <400000>; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ser1_rst_pin>; + reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + sel-mipi; + status = "okay"; + serdes-init-sequence = [ + 0013 0019 + 0014 0008 //014h[3]-lane1 enable + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0018 //gpio3 input tp_rst + 0034 0005 //bypass des gpio3 + 0036 0000 //gpio4 output tp_int + 0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes + 0054 0080 + 024d 0061 + 0252 0005 + 0274 0030 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 //h_blank=144 + 0446 00d2 //v_blank=210 + + + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18tl82_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 + 0058 0002 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0003 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0000 //rl gpio3 output tp-rst + 0061 0005 //bypass ser gpio3 + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0001 //set gpio5 high + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c6_bu18rl82>; + }; + }; + }; + }; + + himax@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi1>; + pinctrl-1 = <&touch_gpio_dsi1>; + himax,location = "himax-touch-dsi1"; + himax,irq-gpio = <&gpio1 RK_PB1 IRQ_TYPE_EDGE_FALLING>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + clock-frequency = <400000>; + status = "disabled"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0000 //gpio3 output tp_int + 0034 0005 //bypass des gpio3 + 0036 0018 //gpio4 input tp_rst + 0037 0006 //bypass des gpio4 + 027c 0041 + 027d 0041 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18tl82_in_edp1: endpoint { + remote-endpoint = <&edp1_out_i2c7_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0031 0041 //i2c addr 0x41 + 0032 0041 //i2c addr 0x41 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0001 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0018 //rl gpio3 input tp-int + 042e 0005 //bypass ser gpio3 + 0061 0005 //bypass ser gpio3 + 0063 0000 //rl gpio4 output tp-rst + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0007 //bypass ser gpio5 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + 042d 0004 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c7_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "disabled"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A + 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0018 //gpio3 input tp_rst + 0034 0005 //bypass des gpio3 + 0036 0000 //gpio4 output tp_int + 0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes + 024d 0061 + 0252 0005 + 0274 0030 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 //h_blank=144 + 0446 00d2 //v_blank=210 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18tl82_in_dp1: endpoint { + remote-endpoint = <&dp1_out_i2c8_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 + 0058 0002 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0003 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0000 //rl gpio3 output tp-rst + 0061 0005 //bypass ser gpio3 + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0001 //set gpio5 high + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c8_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + + +&pinctrl { + + bl { + bl0_enable_pin: bl0-enable-pin { + rockchip,pins = + <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + + }; + + bl1_enable_pin: bl1-enable-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl2_enable_pin: bl2-enable-pin { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl3_enable_pin: bl3-enable-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl4_enable_pin: bl4-enable-pin { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl5_enable_pin: bl5-enable-pin { + rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + //dsi0 + ser0_rst_pin: ser0-rst-pin { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + //dsi1 + ser1_rst_pin: ser1-rst-pin { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + //dsi0-i2c2 + touch_gpio_dsi0: touch-gpio-dsi0 { + rockchip,pins = + //<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, //INT + <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; //RST + }; + //dsi1-i2c6 + touch_gpio_dsi1: touch-gpio-dsi1 { + rockchip,pins = + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, //INT + <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; //RST + }; + //dp0-i2c4 + touch_gpio_dp0: touch-gpio-dp0 { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + //edp0-i2c5 + touch_gpio_edp0: touch-gpio-edp0 { + rockchip,pins = + <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>, //INT + <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; //RST + }; + }; +}; + +/* dsi0->serdes->lvds_panel */ +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; +}; + +/* dp0->serdes->lvds_panel */ +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +/* edp1->serdes->lvds_panel */ +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +/* edp0->serdes->lvds_panel */ +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "okay"; +}; + +/* dsi1->serdes->lvds_panel */ +&pwm13 { + status = "okay"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +/* dp1->serdes->lvds_panel */ +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp0_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru PLL_V0PLL>; + assigned-clock-rates = <1152000000>; +}; + +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&vp2 { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; diff --git a/rk3588-vehicle-serdes-display.dtsi b/rk3588-vehicle-serdes-display.dtsi new file mode 100644 index 0000000..7ee1d48 --- /dev/null +++ b/rk3588-vehicle-serdes-display.dtsi @@ -0,0 +1,1943 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + lt7911d { + compatible = "lontium,lt7911d-fb-notifier"; + reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>, + <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>, + <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>, + <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + }; + + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dsi2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&backlight>; + + display-timings { + native-mode = <&dsi2lvds0>; + dsi2lvds0: timing0 { + clock-frequency = <88208000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <32>; + hsync-len = <10>; + hback-porch = <22>; + vfront-porch = <10>; + vsync-len = <4>; + vback-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel0_in_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_out_panel0>; + }; + }; + }; + }; + + dsi2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&dsi2lvds_backlight1>; + + display-timings { + native-mode = <&dsi2lvds1>; + dsi2lvds1: timing0 { + clock-frequency = <88208000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <32>; + hsync-len = <10>; + hback-porch = <22>; + vfront-porch = <10>; + vsync-len = <4>; + vback-porch = <7>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel1_in_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_out_panel1>; + }; + }; + }; + }; + + dp2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight0>; + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c3_bu18rl82: endpoint { + remote-endpoint = <&i2c3_bu18rl82_out_panel0>; + }; + }; + }; + + dp2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight1>; + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_out_panel1>; + }; + }; + }; + + edp2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight0>; + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_out_panel0>; + }; + }; + }; + + edp2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight1>; + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_out_panel1>; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm6 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl0_enable_pin>; + enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm13 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl1_enable_pin>; + enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0 { + split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c3_bu18tl82: endpoint { + remote-endpoint = <&i2c3_bu18tl82_in_dp0>; + }; + }; + }; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_in_dp1>; + }; + }; + }; +}; + +&dp1_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dp2lvds_backlight0 { + pwms = <&pwm10 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl2_enable_pin>; + enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp2lvds_backlight1 { + pwms = <&pwm14 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl3_enable_pin>; + enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&edp0 { + split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp0 { + status = "disabled"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_in_edp1>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm12 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl4_enable_pin>; + enable-gpios = <&gpio4 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl5_enable_pin>; + enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + bu18tl82: bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ser0_rst_pin>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + sel-mipi; + status = "okay"; + + serdes-init-sequence = [ + 0021 0008 + 0022 0008 + 0023 0009 + 0024 000a + 0013 0010 + 0014 0010 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 + 0047 0080 + 0048 0007 + 004b 00d0 + 004c 0002 + 004d 00d0 + 004e 0002 + 0051 0080 + 0052 0007 + 0053 0000 + 0054 00c0 + 022b 0076 + 022c 0062 + 022d 0037 + 024d 0061 + 0252 0005 + 0253 0000 + 0258 0000 + 025c 0000 + 025f 0000 + 0274 0030 + 0275 0020 + 032b 002f + 032c 00a1 + 032d 001d + 034d 0060 + 0353 0000 + 0358 0000 + 035c 0000 + 035f 0000 + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0013 0019 + 0014 0001 + 022e 0080 + 0296 0004 + 0297 000d + 032e 0080 + 038e 0000 + 0396 0004 + 0397 000a + 0060 0001 + 0061 0001 + 0018 0000 + 0019 0000 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18tl82_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; + }; + }; + }; + }; + + bu18rl82: bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0002 + 0013 0001 + 001d 0008 + 001f 0006 + 0020 0006 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0001 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0075 0080 + 0076 0007 + 0079 0009 + 007b 00d0 + 007c 0002 + 007d 00d0 + 007e 0002 + 0081 0003 + 0082 000a + 0084 001e + 0086 0001 + 0087 0003 + 0088 0005 + 0089 0014 + 008b 0028 + 008d 0002 + 008e 0004 + 008f 000f + 0090 0001 + 0091 0003 + 0423 00ab + 0424 00aa + 0425 001a + 0429 000a + 045d 0001 + 0523 0097 + 0524 00d0 + 0525 000e + 0529 000a + 055d 0001 + 0426 0080 + 0526 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c2_bu18rl82>; + }; + }; + }; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c3_bu18tl82_in_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c3_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c3_bu18tl82_out_i2c3_bu18rl82: endpoint { + remote-endpoint = <&i2c3_bu18rl82_in_i2c3_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c3_bu18rl82_in_i2c3_bu18tl82: endpoint { + remote-endpoint = <&i2c3_bu18tl82_out_i2c3_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c3_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c3_bu18rl82>; + }; + }; + }; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002e 0004 + 002d 0018 + 0030 0000 + 0033 0018 + 027c 0041 + 027d 0041 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18tl82_in_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0031 0041 + 0032 0041 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0008 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + 042d 0004 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c5_bu18rl82>; + }; + }; + }; + }; + + ilitek@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pin>; + reset-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + ilitek,name = "ilitek_i2c"; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + clock-frequency = <400000>; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&ser1_rst_pin>; + reset-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>; + sel-mipi; + status = "okay"; + serdes-init-sequence = [ + 0021 0008 + 0022 0008 + 0023 0009 + 0024 000a + 0013 0010 + 0014 0010 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 027c 0070 + 027d 0070 + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 + 0047 0080 + 0048 0007 + 004b 00d0 + 004c 0002 + 004d 00d0 + 004e 0002 + 0051 0080 + 0052 0007 + 0053 0000 + 0054 00c0 + 022b 0076 + 022c 0062 + 022d 0037 + 024d 0061 + 0252 0005 + 0253 0000 + 0258 0000 + 025c 0000 + 025f 0000 + 0274 0030 + 0275 0020 + 032b 002f + 032c 00a1 + 032d 001d + 034d 0060 + 0353 0000 + 0358 0000 + 035c 0000 + 035f 0000 + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0013 0019 + 0014 0001 + 022e 0080 + 0296 0004 + 0297 000d + 032e 0080 + 038e 0000 + 0396 0004 + 0397 000a + 0060 0001 + 0061 0001 + 0018 0000 + 0019 0000 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18tl82_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0002 + 0013 0001 + 001d 0008 + 001f 0006 + 0020 0006 + 0031 0070 + 0032 0038 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0001 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0075 0080 + 0076 0007 + 0079 0009 + 007b 00d0 + 007c 0002 + 007d 00d0 + 007e 0002 + 0081 0003 + 0082 000a + 0084 001e + 0086 0001 + 0087 0003 + 0088 0005 + 0089 0014 + 008b 0028 + 008d 0002 + 008e 0004 + 008f 000f + 0090 0001 + 0091 0003 + 0423 00ab + 0424 00aa + 0425 001a + 0429 000a + 045d 0001 + 0523 0097 + 0524 00d0 + 0525 000e + 0529 000a + 055d 0001 + 0426 0080 + 0526 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c6_bu18rl82>; + }; + }; + }; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + clock-frequency = <400000>; + status = "okay"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18tl82_in_edp1: endpoint { + remote-endpoint = <&edp1_out_i2c7_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c7_bu18rl82>; + }; + }; + }; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 + 002d 0018 + 0030 0018 + 0033 0018 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18tl82_in_dp1: endpoint { + remote-endpoint = <&dp1_out_i2c8_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; + }; + }; + }; + }; + + bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0057 0000 + 0058 0002 + 005a 0000 + 005b 0003 + 005d 0000 + 005e 0004 + 0060 0000 + 0061 0005 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c8_bu18rl82>; + }; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + + +&pinctrl { + + bl { + bl0_enable_pin: bl0-enable-pin { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl1_enable_pin: bl1-enable-pin { + rockchip,pins = <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl2_enable_pin: bl2-enable-pin { + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl3_enable_pin: bl3-enable-pin { + rockchip,pins = <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl4_enable_pin: bl4-enable-pin { + rockchip,pins = <4 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bl5_enable_pin: bl5-enable-pin { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + serdes { + //dsi0 + ser0_rst_pin: ser0-rst-pin { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + //dsi1 + ser1_rst_pin: ser1-rst-pin { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_pin: touch-pin { + rockchip,pins = + <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>, //INT + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; //RST + }; + }; +}; + +/* dsi0->serdes->lvds_panel */ +&pwm6 { + status = "okay"; + pinctrl-0 = <&pwm6m1_pins>; +}; + +/* dp0->serdes->lvds_panel */ +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +/* edp1->serdes->lvds_panel */ +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +/* edp0->serdes->lvds_panel */ +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +/* dsi1->serdes->lvds_panel */ +&pwm13 { + status = "okay"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +/* dp1->serdes->lvds_panel */ +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp0_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru PLL_V0PLL>; + assigned-clock-rates = <1152000000>; +}; + +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&vp2 { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; diff --git a/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi b/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi new file mode 100644 index 0000000..11754d8 --- /dev/null +++ b/rk3588-vehicle-serdes-mfd-display-maxim-split.dtsi @@ -0,0 +1,2438 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; +}; + +&backlight { + pwms = <&pwm0 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl0_enable_pin>; + //enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm13 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl1_enable_pin>; + //enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0 { + //split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c4_max96745: endpoint { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c4_max96745_from_dp0>; + }; + }; + }; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "disabled"; +#if 0 + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_from_dp1>; + }; + }; + }; +#endif +}; + +&dp1_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dp2lvds_backlight0 { + pwms = <&pwm10 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl2_enable_pin>; + //enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp2lvds_backlight1 { + pwms = <&pwm14 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl3_enable_pin>; + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_from_dsi0>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_from_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&edp0 { + //split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_max96745: endpoint { + remote-endpoint = <&i2c5_max96745_from_edp0>; + }; + }; + }; +}; + +&edp0_in_vp0 { + status = "disabled"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "disabled"; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm7 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl4_enable_pin>; + //enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + //pinctrl-names = "default"; + //pinctrl-0 = <&bl5_enable_pin>; + //enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + i2c2_max96789: i2c2-max96789@42 { + compatible = "maxim,max96789"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_serdes_pins>; + lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + sel-mipi; + id-serdes-bridge-split = <0x01>; + status = "okay"; + + serdes-init-sequence = [ + //Independent 11_07_17-56 Using MAX96789/91/F (GMSL-1/2) + //Disable Video pipe + 0002 0003 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set Stream for DSI Port A && assign pipeX + 0053 0010 + //Set Stream for DSI Port B && assign pipeY + 0057 0021 + //Clock Select, X for portA, Y/Z for PortB + 0308 0076 + //Start DSI Port + 0311 0061 + //Set Port A Lane Mapping + 0332 004E + //Set Port B Lane Mapping + 0333 00E4 + //Set GMSL type + 0004 00F2 + //Number of Lanes + 0331 0033 + //Set phy_config + 0330 0006 + //Set soft_dtx_en + 031C 0098 + //Set soft_dtx + 0321 0024 + //Set soft_dty_en + 031D 0098 + //Set soft_dty_ + 0322 0024 + //Init Default + 0326 00E4 + //HSYNC_WIDTH_L + 0385 0038 + //VSYNC_WIDTH_L + 0386 0008 + //HSYNC_WIDTH_H/VSYNC_WIDTH_H + 0387 0000 + //VFP_L + 03A5 00C8 + //VBP_H + 03A7 0000 + //VFP_H/VBP_L + 03A6 0020 + //VRES_L + 03A8 00D0 + //VRES_H + 03A9 0002 + //HFP_L + 03AA 0038 + //HBP_H + 03AC 0002 + //HFP_H/HBP_L + 03AB 0000 + //HRES_L + 03AD 0080 + //HRES_H + 03AE 0007 + //Disable FIFO/DESKEW_EN + 03A4 00C0 + //HSYNC_WIDTH_L + 0395 0038 + //VSYNC_WIDTH_L + 0396 0008 + //HSYNC_WIDTH_H/VSYNC_WIDTH_H + 0397 0000 + //VFP_L + 03B1 00C8 + //VBP_H + 03B3 0000 + //VFP_H/VBP_L + 03B2 0020 + //VRES_L + 03B4 00D0 + //VRES_H + 03B5 0002 + //HFP_L + 03B6 0038 + //HBP_H + 03B8 0002 + //HFP_H/HBP_L + 03B7 0000 + //HRES_L + 03B9 0080 + //HRES_H + 03BA 0007 + //Disable FIFO/DESKEW_EN + 03B0 00C0 + //Turn on video pipe + 0002 0033 + //Enable splitter mode reset one shot + 0010 0023 + ffff f000 //0xf000 ms delay + ]; + + i2c2_max96789_pinctrl: i2c2-max96789-pinctrl { + compatible = "maxim,max96789-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_max96789_pinctrl_pins>; + pinctrl-1 = <&i2c2_max96789_pinctrl_pins>; + status = "okay"; + i2c2_max96789_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96789_I2C"; + function = "MAX96789_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96789_MFP7"; + function = "SER_TXID4_TO_DES"; + }; + tp-int { + pins = "MAX96789_MFP8"; + function = "DES_RXID8_TO_SER"; + }; + lcd-bl-pwm-split { + pins = "MAX96789_MFP16"; + function = "SER_TXID4_TO_DES"; + }; + tp-int-split { + pins = "MAX96789_MFP14"; + function = "DES_RXID14_TO_SER"; + }; + }; + + i2c2_max96789_gpio: i2c2-max96789-gpio { + compatible = "maxim,max96789-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96789_pinctrl 0 160 20>; + }; + }; + + i2c2_max96789_bridge: i2c2-max96789-bridge { + compatible = "maxim,max96789-bridge"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96789_from_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_max96789>; + }; + }; + + port@1 { + reg = <1>; + i2c2_max96789_out_i2c2_max96752: endpoint { + remote-endpoint = <&i2c2_max96752_from_i2c2_max96789>; + }; + }; + }; + }; + + i2c2_max96789_bridge_split: i2c2-max96789-bridge-split { + compatible = "maxim,max96789-bridge-split"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96789_from_dsi1: endpoint { + remote-endpoint = <&dsi1_out_i2c2_max96789>; + }; + }; + + port@1 { + reg = <1>; + i2c2_max96789_out_i2c2_max96752_split: endpoint { + remote-endpoint = <&i2c2_max96752_split_from_i2c2_max96789>; + }; + }; + }; + }; + }; + + i2c2_max96752: i2c2-max96752@4a { + compatible = "maxim,max96752"; + reg = <0x4a>; + //reg-hw = <0x4a>; + id-serdes-panel-split = <0x01>; + link = <0x01>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0005 + ]; + + i2c2_max96752_pinctrl: i2c2-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c2_max96752_panel_pins>; + pinctrl-1 = <&i2c2_max96752_panel_pins>; + pinctrl-2 = <&i2c2_max96752_panel_sleep_pins>; + status = "okay"; + + i2c2_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + lcd-bias-en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd-vdd-en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID8_TO_SER"; + }; + 100ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_100MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + }; + + i2c2_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c2_max96752_gpio: i2c2-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96752_pinctrl 0 180 15>; + }; + }; + + i2c2_max96752_panel: i2c2-max96752-panel { + compatible = "maxim,max96752-panel"; + status = "okay"; + + backlight = <&backlight>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96752_from_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_out_i2c2_max96752>; + }; + }; + }; + }; + }; + + i2c2_max96752_split: i2c2-max96752-split@4b { + compatible = "maxim,max96752"; + reg = <0x4b>; + reg-hw = <0x4a>; + id-serdes-panel-split = <0x01>; + link = <0x02>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0032 + 007b 0032 + 007d 0038 + + //Address Value of I2C SRC_A + 0042 008c + //Address Value of I2C DST_A + 0043 0090 + //0140 0020 + 0050 0001 + 01ce 004e + 01ea 0005 + ]; + + i2c2_max96752_split_pinctrl: i2c2-max96752-split-pinctrl { + compatible = "maxim,max96752-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c2_max96752_split_panel_pins>; + pinctrl-1 = <&i2c2_max96752_split_panel_pins>; + pinctrl-2 = <&i2c2_max96752_split_panel_sleep_pins>; + status = "okay"; + + i2c2_max96752_split_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + lcd-bias-en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd-vdd-en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID14_TO_SER"; + }; + 100ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_100MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + }; + + i2c2_max96752_split_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c2_max96752_split_gpio: i2c2-max96752-split-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96752_split_pinctrl 0 200 15>; + }; + }; + + i2c2_max96752_split_panel: i2c2-max96752-split-panel { + compatible = "maxim,max96752-panel-split"; + status = "okay"; + + backlight = <&dsi2lvds_backlight1>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c2_max96752_split_from_i2c2_max96789: endpoint { + remote-endpoint = <&i2c2_max96789_out_i2c2_max96752_split>; + }; + }; + }; + }; + }; + + himax@45 { + compatible = "himax,hxcommon"; + reg = <0x45>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi0>; + pinctrl-1 = <&touch_gpio_dsi0>; + himax,location = "himax-touch-dsi0"; + himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c2_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; + + himax_split@46 { + compatible = "himax,hxcommon"; + reg = <0x46>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi1>; //hw change + pinctrl-1 = <&touch_gpio_dsi1>; + himax,location = "himax-touch-dsi1"; + himax,irq-gpio = <&gpio1 RK_PB6 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c2_max96752_split_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c4_max96745: i2c4-max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_serdes_pins>; + lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-bridge-split = <0x02>; + status = "okay"; + + serdes-init-sequence = [ + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + //ASYM_WR_B_MUX_Y of SER will be written 1 + 05CE 003F + //ASYM_WAIT_LINE_FOR_READ_X of SER will be written 1 + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y of SER will be written 1 + 05D1 00F8 + //ASYM_VID_EN_W_VS_X of SER will be written 1 + 04CF 00BF + //ASYM_VID_EN_W_VS_Y of SER will be written 1 + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X of SER will be written 1 + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y of SER will be written 1 + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 0020 + //X_M_m + 04C1 004A + //X_M_h + 04C2 001D + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0080 + //X_X_MAX_h + 04C9 0007 + //X_Y_MAX_l + 04CA 00D0 + //X_Y_MAX_h + 04CB 0002 + //Y_M + 05C0 0020 + //Y_M_h + 05C1 004A + //Y_M_h + 05C2 001D + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0080 + //Y_X_OFFSET_h + 05C7 0007 + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 000F + //Y_Y_MAX_l + 05CA 00D0 + //Y_Y_MAX_h + 05CB 0002 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //X_vs_dly_l + 04D8 0080 + //X_vs_dly_m + 04D9 00F9 + //X_vs_dly_h + 04DA 001C + //X_vs_high_l + 04DB 0080 + //X_vs_high_m + 04DC 0040 + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 0020 + //X_vs_low_m + 04DF 0010 + //X_vs_low_h + 04E0 0000 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0038 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 00D8 + //X_hs_low_h + 04E7 0007 + //X_hs_cnt_l + 04E8 00A2 + //X_hs_cnt_h + 04E9 0003 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 0058 + //X_de_dly_m + 04EE 0000 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0080 + //X_de_high_h + 04F1 0007 + //X_de_low_l + 04F2 0090 + //X_de_low_h + 04F3 0000 + //X_de_cnt_l + 04F4 00D0 + //X_de_cnt_h + 04F5 0002 + //X_de_llow_l + 04F6 00C8 + //X_de_llow_m + 04F7 009C + //X_de_llow_h + 04F8 0006 + //Y_vs_dly_l + 05D8 0080 + //Y_vs_dly_m + 05D9 00F9 + //Y_vs_dly_h + 05DA 001C + //Y_vs_high_l + 05DB 0080 + //Y_vs_high_m + 05DC 0040 + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 0020 + //Y_vs_low_m + 05DF 0010 + //Y_vs_low_h + 05E0 0000 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0038 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 00D8 + //Y_hs_low_h + 05E7 0007 + //Y_hs_cnt_l + 05E8 00A2 + //Y_hs_cnt_h + 05E9 0003 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 0058 + //Y_de_dly_m + 05EE 0000 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0080 + //Y_de_high_h + 05F1 0007 + //Y_de_low_l + 05F2 0090 + //Y_de_low_h + 05F3 0000 + //Y_de_cnt_l + 05F4 00D0 + //Y_de_cnt_h + 05F5 0002 + //Y_de_llow_l + 05F6 00C8 + //Y_de_llow_m + 05F7 009C + //Y_de_llow_h + 05F8 0006 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 + ]; + + + i2c4_max96745_pinctrl: i2c4-max96745-pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_max96745_pinctrl_pins>; + status = "okay"; + + i2c4_max96745_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96745_I2C"; + function = "MAX96745_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96745_MFP0"; + function = "SER_TXID0_TO_DES_LINKA"; + }; + tp-int { + pins = "MAX96745_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; + }; + lcd-bl-pwm-split { + pins = "MAX96745_MFP4"; + function = "SER_TXID4_TO_DES_LINKB"; + }; + tp-int-split { + pins = "MAX96745_MFP5"; + function = "DES_RXID5_TO_SER_LINKB"; + }; + }; + + i2c4_max96745_gpio: i2c4-max96745-gpio { + compatible = "maxim,max96745-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96745_pinctrl 0 220 25>; + }; + }; + + i2c4_max96745_bridge: i2c4-max96745-bridge { + compatible = "maxim,max96745-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + i2c4_max96745_from_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c4_max96745>; + }; + }; + port@1 { + reg = <1>; + i2c4_max96745_out_i2c4_max96752: endpoint { + remote-endpoint = <&i2c4_max96752_from_i2c4_max96745>; + }; + }; + port@2 { + reg = <2>; + i2c4_max96745_out_i2c4_max96752_split: endpoint { + remote-endpoint = <&i2c4_max96752_split_from_i2c4_max96745>; + }; + }; + }; + }; + + i2c4_max96752: i2c4-max96752@4a { + compatible = "maxim,max96752"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-panel-split = <0x02>; + link = <0x01>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0005 + ]; + + i2c4_max96752_pinctrl: i2c4-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "okay"; + + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c4_max96752_panel_pins>; + pinctrl-1 = <&i2c4_max96752_panel_pins>; + pinctrl-2 = <&i2c4_max96752_panel_sleep_pins>; + + i2c4_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID1_TO_SER"; + }; + 100ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_100MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c4_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c4_max96752_gpio: i2c4-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96752_pinctrl 0 250 15>; + }; + }; + + i2c4_max96752_panel: i2c4-max96752-panel { + compatible = "maxim,max96752-panel"; + status = "okay"; + + backlight = <&dp2lvds_backlight0>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <230400000>; //4128*930@60 + hactive = <3840>; + vactive = <720>; + hfront-porch = <112>; + hsync-len = <64>; + hback-porch = <112>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c4_max96752_from_i2c4_max96745: endpoint { + remote-endpoint = <&i2c4_max96745_out_i2c4_max96752>; + }; + }; + }; + + }; + + i2c4_max96752_split: i2c4-max96752-split@4b { + compatible = "maxim,max96752"; + reg = <0x4b>; + reg-hw = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-panel-split = <0x02>; + link = <0x02>; + status = "okay"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0032 + 007b 0032 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008c + //Address Value of I2C DST_A + 0043 0090 + + //0140 0020 + 0050 0001 + 01ce 004e + 01ea 0005 + ]; + + i2c4_max96752_split_pinctrl: i2c4-max96752-split-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "okay"; + + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c4_max96752_split_panel_pins>; + pinctrl-1 = <&i2c4_max96752_split_panel_pins>; + pinctrl-2 = <&i2c4_max96752_split_panel_sleep_pins>; + + i2c4_max96752_split_panel_pins: i2c4-max96752-split-panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID4_TO_SER"; + }; + 100ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_100MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c4_max96752_split_panel_sleep_pins: i2c4-max96752-split-panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c4_max96752_split_gpio: i2c4-max96752-split-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96752_split_pinctrl 0 265 15>; + }; + }; + + i2c4_max96752_split_panel: i2c4-max96752-split-panel { + compatible = "maxim,max96752-panel-split"; + status = "okay"; + + backlight = <&dp2lvds_backlight0>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c4_max96752_split_from_i2c4_max96745: endpoint { + remote-endpoint = <&i2c4_max96745_out_i2c4_max96752_split>; + }; + }; + }; + }; + + himax@45 { + compatible = "himax,hxcommon"; + reg = <0x45>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dp0>; + pinctrl-1 = <&touch_gpio_dp0>; + himax,location = "himax-touch-dp0"; + himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c4_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; + + himax_split@46 { + compatible = "himax,hxcommon"; + reg = <0x46>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_edp0>; + pinctrl-1 = <&touch_gpio_edp0>; + himax,location = "himax-touch-dp0-split"; + //himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c4_max96752_split_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + i2c5_max96745: i2c5-max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_serdes_pins>; + lock-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-bridge-split = <0x02>; + status = "disabled"; + + serdes-init-sequence = [ + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 008a + //Address Value of I2C SRC_B + 0044 008c + //Address Value of I2C DST_B + 0045 008c + //Set TX_STR_SEL_X to 0 + 00A3 0000 + //Set TX_STR_SEL_Y to 1 + 00A7 0001 + //Set TX_STR_SEL_Z to 2 + 00AB 0002 + //Set TX_STR_SEL_U to 3 + 00AF 0003 + + //INFOFR TX_SRC_ID0:1:2 + 00C2 0001 + //CC TX_SRC_ID0:1:2 + 00D2 0002 + //IIC X TX_SRC_ID0:1:2 + 00EA 0001 + //IIC Y TX_SRC_ID0:1:2 + 00F2 0002 + + 00B2 0003 + 00BA 0003 + 00CA 0003 + 00C2 0003 + 00D2 0003 + 00DA 0003 + 00E2 0003 + 00EA 0003 + 00F2 0003 + //Set X_VID_LINK_SEL to 0 + 0100 0061 + //Set Y_VID_LINK_SEL to 1 + 0110 0063 + //Set Z_VID_LINK_SEL to 0 + 0120 0061 + //Set U_VID_LINK_SEL to 1 + 0130 0063 + //ASYM_WR_B_MUX_Y of SER will be written 1 + 05CE 003F + //ASYM_WAIT_LINE_FOR_READ_X of SER will be written 1 + 04D1 00F8 + //ASYM_WAIT_LINE_FOR_READ_Y of SER will be written 1 + 05D1 00F8 + //ASYM_VID_EN_W_VS_X of SER will be written 1 + 04CF 00BF + //ASYM_VID_EN_W_VS_Y of SER will be written 1 + 05CF 00BF + //ASYM_FR2FR_CTRL_EN_X of SER will be written 1 + 04D1 00FC + //ASYM_FR2FR_CTRL_EN_Y of SER will be written 1 + 05D1 00FC + //ALT_VTG_EN_X + 04CE 002F + //AUTO_VTG_CFG_X + 04CE 000F + //ALT_VTG_EN_Y + 05CE 0027 + //AUTO_VTG_CFG_Y + 05CE 0007 + //X_M_l + 04C0 0020 + //X_M_m + 04C1 004A + //X_M_h + 04C2 001D + //X_N_l + 04C3 00C8 + //X_N_m + 04C4 0008 + //X_N_h + 04C5 0007 + //X_X_OFFSET_l + 04C6 0000 + //X_X_OFFSET_h + 04C7 0000 + //X_X_MAX_l + 04C8 0080 + //X_X_MAX_h + 04C9 0007 + //X_Y_MAX_l + 04CA 00D0 + //X_Y_MAX_h + 04CB 0002 + //Y_M + 05C0 0020 + //Y_M_h + 05C1 004A + //Y_M_h + 05C2 001D + //Y_N_l + 05C3 00C8 + //Y_N_m + 05C4 0008 + //Y_N_h + 05C5 0007 + //Y_X_OFFSET_l + 05C6 0080 + //Y_X_OFFSET_h + 05C7 0007 + //Y_X_MAX_l + 05C8 0000 + //Y_X_MAX_h + 05C9 000F + //Y_Y_MAX_l + 05CA 00D0 + //Y_Y_MAX_h + 05CB 0002 + //X_LUT_TEMPLATE_SEL + 04CD 0014 + //X_vs_dly_l + 04D8 0080 + //X_vs_dly_m + 04D9 00F9 + //X_vs_dly_h + 04DA 001C + //X_vs_high_l + 04DB 0080 + //X_vs_high_m + 04DC 0040 + //X_vs_high_h + 04DD 0000 + //X_vs_low_l + 04DE 0020 + //X_vs_low_m + 04DF 0010 + //X_vs_low_h + 04E0 0000 + //X_hs_dly_l + 04E1 0000 + //X_hs_dly_m + 04E2 0000 + //X_hs_dly_h + 04E3 0000 + //X_hs_high_l + 04E4 0038 + //X_hs_high_h + 04E5 0000 + //X_hs_low_l + 04E6 00D8 + //X_hs_low_h + 04E7 0007 + //X_hs_cnt_l + 04E8 00A2 + //X_hs_cnt_h + 04E9 0003 + //X_hs_llow_l + 04EA 0000 + //X_hs_llow_m + 04EB 0000 + //X_hs_llow_h + 04EC 0000 + //X_de_dly_l + 04ED 0058 + //X_de_dly_m + 04EE 0000 + //X_de_dly_h + 04EF 0000 + //X_de_high_l + 04F0 0080 + //X_de_high_h + 04F1 0007 + //X_de_low_l + 04F2 0090 + //X_de_low_h + 04F3 0000 + //X_de_cnt_l + 04F4 00D0 + //X_de_cnt_h + 04F5 0002 + //X_de_llow_l + 04F6 00C8 + //X_de_llow_m + 04F7 009C + //X_de_llow_h + 04F8 0006 + //Y_vs_dly_l + 05D8 0080 + //Y_vs_dly_m + 05D9 00F9 + //Y_vs_dly_h + 05DA 001C + //Y_vs_high_l + 05DB 0080 + //Y_vs_high_m + 05DC 0040 + //Y_vs_high_h + 05DD 0000 + //Y_vs_low_l + 05DE 0020 + //Y_vs_low_m + 05DF 0010 + //Y_vs_low_h + 05E0 0000 + //Y_hs_dly_l + 05E1 0000 + //Y_hs_dly_m + 05E2 0000 + //Y_hs_dly_h + 05E3 0000 + //Y_hs_high_l + 05E4 0038 + //Y_hs_high_h + 05E5 0000 + //Y_hs_low_l + 05E6 00D8 + //Y_hs_low_h + 05E7 0007 + //Y_hs_cnt_l + 05E8 00A2 + //Y_hs_cnt_h + 05E9 0003 + //Y_hs_llow_l + 05EA 0000 + //Y_hs_llow_m + 05EB 0000 + //Y_hs_llow_h + 05EC 0000 + //Y_de_dly_l + 05ED 0058 + //Y_de_dly_m + 05EE 0000 + //Y_de_dly_h + 05EF 0000 + //Y_de_high_l + 05F0 0080 + //Y_de_high_h + 05F1 0007 + //Y_de_low_l + 05F2 0090 + //Y_de_low_h + 05F3 0000 + //Y_de_cnt_l + 05F4 00D0 + //Y_de_cnt_h + 05F5 0002 + //Y_de_llow_l + 05F6 00C8 + //Y_de_llow_m + 05F7 009C + //Y_de_llow_h + 05F8 0006 + //Y_LUT_TEMPLATE_SEL + 05CD 0014 + //Turn off video + 6420 0010 + //Disable MST mode + 7019 0000 + //7019 0001 //Set MST_FUNCTION_ENABLE to 1 + //7904 0001 // Set MST_PAYLOAD_ID_0 to 01 + //7908 0002 // Set MST_PAYLOAD_ID_1 to 01 + //Disable MST_VS0_DTG_ENABLE + 7A14 0000 + //Disable LINK_ENABLE + 7000 0000 + //Reset DPRX core (VIDEO_INPUT_RESET) + 7054 0001 + ffff f000 //delay 0xf000 us + //Set MAX_LINK_RATE to 2.7Gb/s + 7074 000A + //Set MAX_LINK_COUNT to 4 + 7070 0004 + //Set ASYM_CTRL_PROP_GAIN to 000A + 04D0 000A + 05D0 000A + //Set AEQ time to 16ms + 6064 0000 + 6065 0000 + 6164 0000 + 6165 0000 + 6264 0000 + 6265 0000 + 6364 0000 + 6365 0000 + //Enable LINK_ENABLE + 7000 0001 + //delay 1000 + //Disable MSA reset + 7A18 0005 + //Adjust VS0_DMA_HSYNC + 7A28 00FF + 7A2A 00FF + //Adjust VS0_DMA_VSYNC + 7A24 00FF + 7A27 000F + //Enable MST_VS0_DTG_ENABLE + 7A14 0001 + //set EDP Video Control + 6421 0001 + //Turn on video + 6420 0013 + //delay 100 + //Turn off video + 6420 0010 + //delay 100 + //Turn on video + 6420 0013 + 6421 0003 + ]; + + i2c5_max96745_pinctrl: i2c5-max96745-pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c45_max96745_pinctrl_pins>; + status = "disabled"; + + i2c45_max96745_pinctrl_pins: pinctrl-pins { + i2c { + groups = "MAX96745_I2C"; + function = "MAX96745_I2C"; + }; + lcd-bl-pwm { + pins = "MAX96745_MFP0"; + function = "SER_TXID0_TO_DES_LINKA"; + }; + tp-int { + pins = "MAX96745_MFP1"; + function = "DES_RXID1_TO_SER_LINKA"; + }; + lcd-bl-pwm-split { + pins = "MAX96745_MFP4"; + function = "SER_TXID4_TO_DES_LINKB"; + }; + tp-int-split { + pins = "MAX96745_MFP5"; + function = "DES_RXID5_TO_SER_LINKB"; + }; + }; + + i2c5_max96745_gpio: i2c5-max96745-gpio { + compatible = "maxim,max96745-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96745_pinctrl 0 280 25>; + }; + }; + + i2c5_max96745_bridge: i2c5-max96745-bridge { + compatible = "maxim,max96745-bridge"; + status = "disabled"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_max96745_from_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_max96745>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_max96745_out_i2c5_max96752: endpoint { + remote-endpoint = <&i2c5_max96752_from_i2c5_max96745>; + }; + }; + + port@2 { + reg = <2>; + + i2c5_max96745_out_i2c5_max96752_split: endpoint { + remote-endpoint = <&i2c5_max96752_split_from_i2c5_max96745>; + }; + }; + }; + }; + + i2c5_max96752: i2c5-max96752@4a { + compatible = "maxim,max96752"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-panel-split = <0x02>; + link = <0x01>; + status = "disabled"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0031 + 007b 0031 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008a + //Address Value of I2C DST_A + 0043 0090 + + 0050 0000 + 01ce 004e + 01ea 0005 + ]; + + i2c5_max96752_pinctrl: i2c5-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "okay"; + + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c5_max96752_panel_pins>; + pinctrl-1 = <&i2c5_max96752_panel_pins>; + pinctrl-2 = <&i2c5_max96752_panel_sleep_pins>; + + i2c5_max96752_panel_pins: panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID1_TO_SER"; + }; + 100ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_100MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c5_max96752_panel_sleep_pins: panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c5_max96752_gpio: i2c5-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96752_pinctrl 0 305 15>; + }; + }; + + i2c5_max96752_panel: i2c5-max96752-panel { + compatible = "maxim,max96752-panel"; + status = "disabled"; + + backlight = <&edp2lvds_backlight0>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <230400000>; //4128*930@60 + hactive = <3840>; + vactive = <720>; + hfront-porch = <112>; + hsync-len = <64>; + hback-porch = <112>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c5_max96752_from_i2c5_max96745: endpoint { + remote-endpoint = <&i2c5_max96745_out_i2c5_max96752>; + }; + }; + }; + }; + + i2c5_max96752_split: i2c5-max96752-split@4b { + compatible = "maxim,max96752"; + reg = <0x4b>; + reg-hw = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + id-serdes-panel-split = <0x02>; + link = <0x02>; + status = "disabled"; + + serdes-init-sequence = [ + /*max96752 dual oLDI output*/ + 0002 0043 + 0073 0032 + 007b 0032 + 007d 0038 + //Address Value of I2C SRC_A + 0042 008c + //Address Value of I2C DST_A + 0043 0090 + + //0140 0020 + 0050 0001 + 01ce 004e + 01ea 0005 + ]; + + i2c5_max96752_split_pinctrl: i2c5-max96752-split-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "disabled"; + + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c5_max96752_split_panel_pins>; + pinctrl-1 = <&i2c5_max96752_split_panel_pins>; + pinctrl-2 = <&i2c5_max96752_split_panel_sleep_pins>; + + i2c5_max96752_split_panel_pins: i2c5-max96752-split-panel-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_HIGH"; + }; + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_HIGH"; + }; + tp-int { + pins = "MAX96752_GPIO2"; + function = "DES_TXID4_TO_SER"; + }; + 100ms-delay { + pins = "MAX96752_GPIO15"; + function = "DELAY_100MS"; + }; + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_HIGH"; + }; + lcd-bl-pwm { + pins = "MAX96752_GPIO4"; + function = "SER_TO_DES_RXID4"; + }; + lcd_bias_en { + pins = "MAX96752_GPIO7"; + function = "DES_TXID7_OUTPUT_HIGH"; + }; + lcd_vdd_en { + pins = "MAX96752_GPIO6"; + function = "DES_TXID6_OUTPUT_HIGH"; + }; + }; + + i2c5_max96752_split_panel_sleep_pins: i2c5-max96752-split-panel-sleep-pins { + lcd-rst-pin { + pins = "MAX96752_GPIO10"; + function = "DES_TXID10_OUTPUT_LOW"; + }; + + tp-rst { + pins = "MAX96752_GPIO5"; + function = "DES_TXID5_OUTPUT_LOW"; + }; + + lcd-pwr-on { + pins = "MAX96752_GPIO3"; + function = "DES_TXID3_OUTPUT_LOW"; + }; + }; + + i2c5_max96752_split_gpio: i2c5-max96752-split-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96752_split_pinctrl 0 320 15>; + }; + }; + + i2c5_max96752_split_panel: i2c5-max96752-split-panel { + compatible = "maxim,max96752-panel-split"; + status = "disabled"; + + backlight = <&edp2lvds_backlight1>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c5_max96752_split_from_i2c5_max96745: endpoint { + remote-endpoint = <&i2c5_max96745_out_i2c5_max96752_split>; + }; + }; + }; + }; + + himax@45 { + compatible = "himax,hxcommon"; + reg = <0x45>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_edp0>; + pinctrl-1 = <&touch_gpio_edp0>; + himax,location = "himax-touch-edp0"; + himax,irq-gpio = <&gpio1 RK_PA5 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c5_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "disabled"; + }; + + himax_split@46 { + compatible = "himax,hxcommon"; + reg = <0x46>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_edp0>; + pinctrl-1 = <&touch_gpio_edp0>; + himax,location = "himax-touch-edp0-split"; + //himax,irq-gpio = <&gpio1 RK_PA5 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c5_max96752_gpio 5 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "disabled"; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&pinctrl { + serdes { + i2c2_serdes_pins: i2c2-serdes-pins { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c4_serdes_pins: i2c4-serdes-pins { + rockchip,pins = + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c5_serdes_pins: i2c5-serdes-pins { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c6_serdes_pins: i2c6-serdes-pins { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c7_serdes_pins: i2c7-serdes-pins { + rockchip,pins = + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_serdes_pins: i2c8-serdes-pins { + rockchip,pins = + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +/* dsi0->serdes->lvds_panel */ +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; +}; + +/* dp0->serdes->lvds_panel */ +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +/* edp1->serdes->lvds_panel */ +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +/* edp0->serdes->lvds_panel */ +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "okay"; +}; + +/* dsi1->serdes->lvds_panel */ +&pwm13 { + status = "okay"; + pinctrl-0 = <&pwm13m2_pins>; //hw change to PWM13_M2(GPIO1_B7) +}; + +/* dp1->serdes->lvds_panel */ +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp0_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp2_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru PLL_V0PLL>; + assigned-clock-rates = <2304000000>; +}; + +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&vp2 { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; diff --git a/rk3588-vehicle-serdes-mfd-display-maxim.dtsi b/rk3588-vehicle-serdes-mfd-display-maxim.dtsi new file mode 100644 index 0000000..cc8129a --- /dev/null +++ b/rk3588-vehicle-serdes-mfd-display-maxim.dtsi @@ -0,0 +1,1092 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include + +/ { + aliases { + pinctrl0 = &pinctrl; + }; + + backlight { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + i2c2_max96755f_backlight: backlight@0 { + compatible = "pwm-backlight"; + reg = <0>; + pwms = <&pwm0 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c4_max96745_backlight: backlight@1 { + compatible = "pwm-backlight"; + reg = <1>; + pwms = <&pwm10 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c5_max96745_backlight: backlight@2 { + compatible = "pwm-backlight"; + reg = <2>; + pwms = <&pwm7 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c6_max96755f_backlight: backlight@3 { + compatible = "pwm-backlight"; + reg = <3>; + pwms = <&pwm13 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c7_max96745_backlight: backlight@4 { + compatible = "pwm-backlight"; + reg = <4>; + pwms = <&pwm11 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + i2c8_max96745_backlight: backlight@5 { + compatible = "pwm-backlight"; + reg = <5>; + pwms = <&pwm14 0 1000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + }; +}; + +&dp0 { + //split-mode; + force-hpd; + status = "okay"; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c4_max96745_in>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&route_dp0 { + connect = <&vp0_out_dp0>; + status = "okay"; +}; + +&dp1 { + force-hpd; + status = "disabled"; +}; + +&dp1_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c8_max96745_in>; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&i2c2_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&route_dsi0 { + connect = <&vp2_out_dsi0>; + status = "disabled"; +}; + +&dsi1 { + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out: endpoint { + remote-endpoint = <&i2c6_max96755f_in>; + }; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&route_dsi1 { + connect = <&vp3_out_dsi1>; + status = "disabled"; +}; + +&edp0 { + //split-mode; + force-hpd; + status = "okay"; +}; + +&edp0_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c5_max96745_in>; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&route_edp0 { + connect = <&vp1_out_edp0>; + status = "okay"; +}; + +&edp1 { + force-hpd; + status = "disabled"; +}; + +&edp1_out { + link-frequencies = /bits/ 64 <2700000000>; + remote-endpoint = <&i2c7_max96745_in>; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96755@40 { + compatible = "maxim,max96755"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_serdes_pins>; + lock-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + sel-mipi; + status = "okay"; + + serdes-init-sequence = [ + 0001 0008 + 0002 0053 + 0003 0040 + 0010 0031 + 0013 00ca + 0010 0000 + 02be 001c + 02bf 0040 + 02c0 0020 + 0311 0057 + 0331 0033 + 0332 004e + 03a4 0000 + 0385 0000 + 0386 0000 + 0387 0000 + 005b 0012 + 0053 0010 + ]; + + i2c2_max96755f_pinctrl: i2c2-max96755f-pinctrl { + compatible = "maxim,max96755-pinctrl"; + status = "okay"; + + i2c2_max96755f_pinctrl_hog: hog { + i2c { + groups = "MAX96755_I2C"; + function = "MAX96755_I2C"; + }; + }; + + i2c2_max96755f_panel_pins: panel-pins { + bl-pwm { + pins = "MAX96755_MFP0"; + function = "DES_GPIO0_OUTPUT"; + }; + }; + + i2c2_max96755f_gpio: i2c2-max96755f-gpio { + compatible = "maxim,max96755-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96755f_pinctrl 0 160 24>; + }; + }; + + i2c2_max96755f_bridge: i2c2-max96755f-bridge { + compatible = "maxim,max96755-bridge"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_max96755f_pinctrl_hog>; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_max96755f_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_max96755f_out: endpoint { + remote-endpoint = <&i2c2_max96755f_panel_in>; + }; + }; + }; + }; + + + max96772@48 { + compatible = "maxim,max96772"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + 0001 0002 + 0010 0011 + 0050 0000 + 07f0 0001 + e791 0000 + e793 0000 + e794 0000 + e795 000a + e796 007a + e797 0000 + e798 003c + e799 0000 + e79a 003c + e79b 0000 + e79c 00a0 + e79d 0005 + e79e 0054 + e79f 0001 + e7a0 0002 + e7a1 0000 + e7a2 0014 + e7a3 0000 + e7a4 00fc + e7a5 000e + e7a6 0055 + e7a7 0055 + e7a8 0000 + e7a9 0080 + e7aa 0040 + e7ab 0000 + e7ac 0003 + e7ad 0000 + e7b0 0000 + e7b1 0000 + e7b2 0050 + e7b3 0000 + e7b4 0000 + e7b5 0040 + e7b6 006c + e7b7 0020 + e7b8 0007 + e7b9 0000 + e7ba 0001 + e7bb 0000 + e7bc 0000 + e7bd 0000 + e7be 0052 + e7bf 0000 + ]; + + i2c2_max96772_pinctrl: i2c2-max96772-pinctrl { + compatible = "maxim,max96772-pinctrl"; + status = "okay"; + + i2c2_max96772_gpio: i2c2-max96772-gpio { + compatible = "maxim,max96772-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_max96772_pinctrl 0 185 24>; + }; + }; + + i2c2_max96772_panel: i2c2-max96772-panel { + compatible = "maxim,max96772-panel"; + backlight = <&i2c2_max96755f_backlight>; + + panel-timing { + clock-frequency = <180000000>; + hactive = <2560>; + vactive = <1440>; + hfront-porch = <122>; + hsync-len = <60>; + hback-porch = <60>; + vfront-porch = <340>; + vsync-len = <2>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c2_max96755f_panel_in: endpoint { + remote-endpoint = <&i2c2_max96755f_out>; + }; + }; + + }; + + }; + + ts@30 { + compatible = "gac,gac_ts"; + reg = <0x30>; + gac,max_x = <2560>; + gac,max_y = <1440>; + }; +}; + +&i2c4 { + pinctrl-0 = <&i2c4m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + serdes-init-sequence = [ + 0070 0016 + 0005 00c0 + 0107 0042 + 0027 0022 + 0026 0022 + 002a 0007 + 641a 00f0 + ]; + + + i2c4_max96745_pinctrl: i2c4-max96745-pinctrl { + compatible = "maxim,max96745-pinctrl"; + status = "okay"; + + i2c4_max96745_gpio: i2c4-max96745-gpio { + compatible = "maxim,max96745-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96745_pinctrl 0 210 25>; + }; + }; + + i2c4_max96745_bridge: i2c4-max96745-bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_max96745_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_max96745_out: endpoint { + remote-endpoint = <&i2c4_max96745_panel_in>; + }; + }; + }; + + }; + + + max96752@48 { + compatible = "maxim,max96752"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + serdes-init-sequence = [ + 0001 0002 + 0002 0043 + 0140 0020 + 01ce 005e + 0200 0084 + 020e 0040 + 020c 0084 + 0207 00a1 + 0206 0083 + 0215 0090 + 0227 0090 + 020f 0090 + 0221 0090 + 0212 0090 + 0209 0090 + ]; + + i2c4_max96752_pinctrl: i2c4-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "okay"; + + i2c4_max96752_gpio: i2c4-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_max96752_pinctrl 0 236 25>; + }; + }; + + i2c4_max96752_panel: i2c4-max96752-panel { + compatible = "maxim,max96752-panel"; + reg = <0x48>; + backlight = <&i2c4_max96745_backlight>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c4_max96745_panel_in: endpoint { + remote-endpoint = <&i2c4_max96745_out>; + }; + }; + }; + + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_serdes_pins>; + lock-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + 0070 0016 + 0005 00c0 + 0107 0042 + 0027 0022 + 0026 0022 + 002a 0007 + 641a 00f0 + ]; + + + i2c5_max96745_pinctrl: i2c5-max96745-pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_max96745_pinctrl_hog>, <&i2c5_max96745_panel_pins>; + status = "okay"; + + i2c5_max96745_pinctrl_hog: hog { + i2c { + groups = "MAX96745_I2C"; + function = "MAX96745_I2C"; + }; + }; + + i2c5_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MAX96745_MFP0"; + function = "DES_GPIO0_OUTPUT_A"; + }; + }; + + i2c5_max96745_gpio: i2c5-max96745-gpio { + compatible = "maxim,max96745-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96745_pinctrl 0 262 25>; + }; + }; + + i2c5_max96745_bridge: i2c5-max96745-bridge { + compatible = "maxim,max96745-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_max96745_in: endpoint { + remote-endpoint = <&edp0_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_max96745_out: endpoint { + remote-endpoint = <&i2c5_max96745_panel_in>; + }; + }; + }; + + }; + + + max96752@48 { + compatible = "maxim,max96752"; + reg = <0x48>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + serdes-init-sequence = [ + 0001 0002 + 0002 0043 + 0140 0020 + 01ce 005e + 0200 0084 + 020e 0040 + 020c 0084 + 0207 00a1 + 0206 0083 + 0215 0090 + 0227 0090 + 020f 0090 + 0221 0090 + 0212 0090 + 0209 0090 + ]; + + i2c5_max96752_pinctrl: i2c5-max96752-pinctrl { + compatible = "maxim,max96752-pinctrl"; + status = "okay"; + + i2c5_max96752_gpio: i2c5-max96752-gpio { + compatible = "maxim,max96752-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_max96752_pinctrl 0 288 25>; + }; + }; + + i2c5_max96752_panel: i2c5-max96752-panel { + compatible = "maxim,max96752-panel"; + reg = <0x48>; + backlight = <&i2c5_max96745_backlight>; + panel-size= <346 194>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c5_max96745_panel_in: endpoint { + remote-endpoint = <&i2c5_max96745_out>; + }; + }; + + }; + }; +}; + +&i2c6 { + pinctrl-0 = <&i2c6m3_xfer>; + clock-frequency = <400000>; + status = "okay"; + + max96755f@40 { + compatible = "maxim,max96755f"; + reg = <0x40>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + + pinctrl { + compatible = "maxim,max96755f-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_max96755f_pinctrl_hog>; + + i2c6_max96755f_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + + i2c6_max96755f_panel_pins: panel-pins { + bl-pwm { + pins = "MFP18"; + function = "GPIO_TX_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96755f-bridge"; + lock-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_max96755f_in: endpoint { + remote-endpoint = <&dsi1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_max96755f_out: endpoint { + remote-endpoint = <&i2c6_max96755f_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c6_max96755f_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_max96755f_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c6_max96755f_panel_in: endpoint { + remote-endpoint = <&i2c6_max96755f_out>; + }; + }; + }; + }; + }; +}; + +&i2c7 { + pinctrl-0 = <&i2c7m3_xfer>; + clock-frequency = <400000>; + status = "disabled"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_max96745_pinctrl_hog>; + + i2c7_max96745_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c7_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MFP0"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_max96745_in: endpoint { + remote-endpoint = <&edp1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_max96745_out: endpoint { + remote-endpoint = <&i2c7_max96745_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c7_max96745_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_max96745_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c7_max96745_panel_in: endpoint { + remote-endpoint = <&i2c7_max96745_out>; + }; + }; + }; + }; + }; +}; + +&i2c8 { + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "disabled"; + + max96745@42 { + compatible = "maxim,max96745"; + reg = <0x42>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_serdes_pins>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + + pinctrl { + compatible = "maxim,max96745-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_pinctrl_hog>; + + i2c8_max96745_pinctrl_hog: hog { + i2c { + groups = "I2C"; + function = "I2C"; + }; + }; + + i2c8_max96745_panel_pins: panel-pins { + bl-pwm { + pins = "MFP0"; + function = "GPIO_TX_A_0"; + }; + }; + }; + + bridge { + compatible = "maxim,max96745-bridge"; + lock-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_max96745_in: endpoint { + remote-endpoint = <&dp1_out>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_max96745_out: endpoint { + remote-endpoint = <&i2c8_max96745_panel_in>; + }; + }; + }; + }; + + gmsl@0 { + reg = <0>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + + panel@48 { + compatible = "boe,av156fht-l83"; + reg = <0x48>; + backlight = <&i2c8_max96745_backlight>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_max96745_panel_pins>; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <20>; + hsync-len = <20>; + hback-porch = <20>; + vfront-porch = <250>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + i2c8_max96745_panel_in: endpoint { + remote-endpoint = <&i2c8_max96745_out>; + }; + }; + }; + }; + }; +}; + +&pinctrl { + serdes { + i2c2_serdes_pins: i2c2-serdes-pins { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c4_serdes_pins: i2c4-serdes-pins { + rockchip,pins = + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c5_serdes_pins: i2c5-serdes-pins { + rockchip,pins = + <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c6_serdes_pins: i2c6-serdes-pins { + rockchip,pins = + <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c7_serdes_pins: i2c7-serdes-pins { + rockchip,pins = + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + i2c8_serdes_pins: i2c8-serdes-pins { + rockchip,pins = + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm0 { + pinctrl-0 = <&pwm0m2_pins>; + status = "okay"; +}; + +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "okay"; +}; + +&pwm13 { + pinctrl-0 = <&pwm13m1_pins>; + status = "okay"; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; diff --git a/rk3588-vehicle-serdes-mfd-display-rohm.dtsi b/rk3588-vehicle-serdes-mfd-display-rohm.dtsi new file mode 100644 index 0000000..1df644b --- /dev/null +++ b/rk3588-vehicle-serdes-mfd-display-rohm.dtsi @@ -0,0 +1,2697 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +/ { + dsi2lvds_backlight1: dsi2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight0: dp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp2lvds_backlight1: dp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight0: edp2lvds_backlight0 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + edp2lvds_backlight1: edp2lvds_backlight1 { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dsi2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&backlight>; + + display-timings { + native-mode = <&dsi2lvds0>; + dsi2lvds0: timing0 { + clock-frequency = <115200000>;//115200000/105573600 + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel0_in_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_out_panel0>; + }; + }; + }; + }; + + dsi2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&dsi2lvds_backlight1>; + + display-timings { + native-mode = <&dsi2lvds1>; + dsi2lvds1: timing0 { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel1_in_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_out_panel1>; + }; + }; + }; + }; + + dp2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight0>; + status = "okay"; + + panel-timing { + clock-frequency = <115200000>; + hactive = <1920>; + vactive = <720>; + hfront-porch = <56>; + hsync-len = <32>; + hback-porch = <56>; + vfront-porch = <200>; + vsync-len = <2>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c4_bu18rl82: endpoint { + remote-endpoint = <&i2c4_bu18rl82_out_panel0>; + }; + }; + }; + + dp2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&dp2lvds_backlight1>; + status = "disabled"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_out_panel1>; + }; + }; + }; + + edp2lvds_panel0 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight0>; + status = "okay"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel0_in_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_out_panel0>; + }; + }; + }; + + edp2lvds_panel1 { + compatible = "simple-panel"; + backlight = <&edp2lvds_backlight1>; + status = "disabled"; + + panel-timing { + clock-frequency = <148500000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <140>; + hsync-len = <40>; + hback-porch = <100>; + vfront-porch = <15>; + vsync-len = <20>; + vback-porch = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel1_in_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_out_panel1>; + }; + }; + }; +}; + +&backlight { + pwms = <&pwm0 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl0_enable_pin>; + enable-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dsi2lvds_backlight1 { + pwms = <&pwm13 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl1_enable_pin>; + enable-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp0 { + //split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dp0_out_i2c4_bu18tl82: endpoint { + link-frequencies = /bits/ 64 <1620000000>; + remote-endpoint = <&i2c4_bu18tl82_in_dp0>; + }; + }; + }; +}; + +&dp0_in_vp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "disabled"; +}; + +&dp0_in_vp2 { + status = "disabled"; +}; + +&dp1 { + force-hpd; + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + dp1_out_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_in_dp1>; + }; + }; + }; +}; + +&dp1_in_vp0 { + status = "okay"; +}; + +&dp1_in_vp1 { + status = "disabled"; +}; + +&dp1_in_vp2 { + status = "disabled"; +}; + +&dp2lvds_backlight0 { + pwms = <&pwm10 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl2_enable_pin>; + enable-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&dp2lvds_backlight1 { + pwms = <&pwm14 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl3_enable_pin>; + enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi0_out_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_in_dsi0>; + }; + }; + }; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + + dsi1_out_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_in_dsi1>; + }; + }; + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&edp0 { + //split-mode; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_in_edp0>; + }; + }; + }; +}; + +&edp0_in_vp0 { + status = "disabled"; +}; + +&edp0_in_vp1 { + status = "okay"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&edp1 { + force-hpd; + status = "disabled"; + + ports { + port@1 { + reg = <1>; + + edp1_out_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_in_edp1>; + }; + }; + }; +}; + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&edp2lvds_backlight0 { + pwms = <&pwm7 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl4_enable_pin>; + enable-gpios = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&edp2lvds_backlight1 { + pwms = <&pwm11 0 25000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&bl5_enable_pin>; + enable-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0 { + status = "disabled"; +}; + +&hdmi1 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "disabled"; +}; + +&hdptxphy_hdmi1 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + clock-frequency = <400000>; + + i2c2_bu18tl82: i2c2-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + sel-mipi; + status = "okay"; + + serdes-init-sequence = [ + 0013 0019 + 0014 0008 //014h[3]-lane1 enable + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 297h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + //002a 0018 //gpio0 input lcd_bl_pwm + //002d 0018 //gpio1 input lcd_pwr_en + + //0030 0018 //gpio2 input lcd_rst + //0033 0018 //gpio3 input tp_rst + //0034 0005 //bypass des gpio3 + //0036 0000 //gpio4 output tp_int + //0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes + 0054 0080 + 024d 0061 + 0252 0005 + 0274 0030 //I2C slave address of BU18RL82 for accessing via BU18TL82 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 + 0446 00d2 + ]; + + i2c2_bu18tl82_pinctrl: i2c2-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c2_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c2_bu18tl82_panel_pins>; + status = "okay"; + + i2c2_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + i2c2_bu18tl82_gpio: i2c2-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_bu18tl82_pinctrl 0 160 8>; + }; + }; + + i2c2_bu18tl82_bridge: i2c2-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18tl82_in_dsi0: endpoint { + remote-endpoint = <&dsi0_out_i2c2_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18tl82_out_i2c2_bu18rl82: endpoint { + remote-endpoint = <&i2c2_bu18rl82_in_i2c2_bu18tl82>; + }; + }; + }; + }; + + i2c2_bu18rl82: i2c2-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0000 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0000 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0000 //bypass ser gpio2 + 0060 0000 //rl gpio3 output tp-rst + 0061 0000 //bypass ser gpio3 + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0000 //set gpio5 high + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + i2c2_bu18rl82_pinctrl: i2c2-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c2_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c2_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c2_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c2_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c2_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c2_bu18rl82_gpio: i2c2-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c2_bu18rl82_pinctrl 0 169 8>; + }; + }; + + i2c2_bu18rl82_bridge: i2c2-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c2_bu18rl82_in_i2c2_bu18tl82: endpoint { + remote-endpoint = <&i2c2_bu18tl82_out_i2c2_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c2_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c2_bu18rl82>; + }; + }; + }; + }; + + himax@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi0>; + pinctrl-1 = <&touch_gpio_dsi0>; + himax,location = "himax-touch-dsi0"; + //himax,irq-gpio = <&gpio1 RK_PB0 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c2_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m2_xfer>; + clock-frequency = <400000>; + status = "okay"; + + i2c4_bu18tl82: i2c4-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A + 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + ffff 1000 //delay 0x1000us + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.31 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.60 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + //002a 0018 //gpio0 input lcd_bl_pwm + //002d 0018 //gpio1 input lcd_pwr_en + + //0030 0018 //gpio2 input lcd_rst + //0033 0018 //gpio3 input tp_rst + //0034 0005 //bypass des gpio3 + //0036 0000 //gpio4 output tp_int + //0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes + 024d 0061 + 0252 0005 + 0274 0030 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 //h_blank=144 + 0446 00d2 //v_blank=210 + ]; + + i2c4_bu18tl82_pinctrl: i2c4-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c4_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c4_bu18tl82_panel_pins>; + status = "okay"; + + i2c4_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + + }; + + i2c4_bu18tl82_gpio: i2c4-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_bu18tl82_pinctrl 0 178 8>; + }; + }; + + i2c4_bu18tl82_bridge: i2c4-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_bu18tl82_in_dp0: endpoint { + remote-endpoint = <&dp0_out_i2c4_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_bu18tl82_out_i2c4_bu18rl82: endpoint { + remote-endpoint = <&i2c4_bu18rl82_in_i2c4_bu18tl82>; + }; + }; + }; + }; + + i2c4_bu18rl82: i2c4-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0000 //set gpio0 low + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0000 //set gpio1 low + 005d 0000 //rl gpio2 output lcd_rst + 005e 0000 //set gpio2 low + 0060 0000 //rl gpio3 output tp-rst + 0061 0000 //set gpio3 low + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0000 //set gpio5 low + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + i2c4_bu18rl82_pinctrl: i2c4-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c4_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c4_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c4_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c4_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c4_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c4_bu18rl82_gpio: i2c4-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c4_bu18rl82_pinctrl 0 187 8>; + }; + }; + + i2c4_bu18rl82_bridge: i2c4-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c4_bu18rl82_in_i2c4_bu18tl82: endpoint { + remote-endpoint = <&i2c4_bu18tl82_out_i2c4_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c4_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c4_bu18rl82>; + }; + }; + }; + }; + + himax@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dp0>; + pinctrl-1 = <&touch_gpio_dp0>; + himax,location = "himax-touch-dp0"; + himax,irq-gpio = <&gpio3 RK_PC5 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c4_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c5 { + clock-frequency = <400000>; + status = "okay"; + + i2c5_bu18tl82: i2c5-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + //002a 0018 //gpio0 input lcd_bl_pwm + //002d 0018 //gpio1 input lcd_pwr_en + + //0030 0018 //gpio2 input lcd_rst + //0033 0000 //gpio3 output tp_int + //0034 0005 //bypass des gpio3 + //0036 0018 //gpio4 input tp_rst + //0037 0006 //bypass des gpio4 + 027c 0041 + 027d 0041 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c5_bu18tl82_pinctrl: i2c5-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c5_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c5_bu18tl82_panel_pins>; + status = "okay"; + + i2c5_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO3_TO_SER"; + }; + }; + + + i2c5_bu18tl82_gpio: i2c5-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_bu18tl82_pinctrl 0 196 8>; + }; + }; + + i2c5_bu18tl82_bridge: i2c5-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18tl82_in_edp0: endpoint { + remote-endpoint = <&edp0_out_i2c5_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18tl82_out_i2c5_bu18rl82: endpoint { + remote-endpoint = <&i2c5_bu18rl82_in_i2c5_bu18tl82>; + }; + }; + }; + }; + + i2c5_bu18rl82: i2c5-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0031 0041 //i2c addr 0x41 + 0032 0041 //i2c addr 0x41 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0000 //set gpio0 low + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0000 //set gpio1 low + 005d 0000 //rl gpio2 output lcd_rst + 005e 0000 //set gpio2 low + 0060 0000 //rl gpio3 output tp-rst + 0061 0000 //set gpio3 low + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0000 //set gpio5 low + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + 042d 0004 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + + i2c5_bu18rl82_pinctrl: i2c5-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c5_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c5_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c5_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c5_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c5_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO4"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c5_bu18rl82_gpio: i2c5-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c5_bu18rl82_pinctrl 0 205 8>; + }; + }; + + i2c5_bu18rl82_bridge: i2c5-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c5_bu18rl82_in_i2c5_bu18tl82: endpoint { + remote-endpoint = <&i2c5_bu18tl82_out_i2c5_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c5_bu18rl82_out_panel0: endpoint { + remote-endpoint = <&panel0_in_i2c5_bu18rl82>; + }; + }; + }; + }; + + ilitek@41 { + compatible = "ilitek,ili251x"; + reg = <0x41>; + interrupt-parent = <&gpio1>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio_edp0>; + //reset-gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_LOW>; + ilitek,name = "ilitek_i2c"; + status = "okay"; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio0 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + clock-frequency = <400000>; + + i2c6_bu18tl82: i2c6-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + sel-mipi; + status = "okay"; + + serdes-init-sequence = [ + 0013 0019 + 0014 0008 //014h[3]-lane1 enable + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + //002a 0018 //gpio0 input lcd_bl_pwm + //002d 0018 //gpio1 input lcd_pwr_en + + //0030 0018 //gpio2 input lcd_rst + //0033 0018 //gpio3 input tp_rst + //0034 0005 //bypass des gpio3 + //0036 0000 //gpio4 output tp_int + //0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0024 //CLLCH2_EN 53h[5] 0:1 Clock Tx lane/1:2 Clock Tx lanes + 0054 0080 + 024d 0061 + 0252 0005 + 0274 0030 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 //h_blank=144 + 0446 00d2 //v_blank=210 + + + ]; + + i2c6_bu18tl82_pinctrl: i2c6-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&i2c6_bu18tl82_panel_pins>; + pinctrl-1 = <&i2c6_bu18tl82_panel_pins>; + status = "okay"; + + i2c6_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + + i2c6_bu18tl82_gpio: i2c6-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c6_bu18tl82_pinctrl 0 214 8>; + }; + }; + + i2c6_bu18tl82_bridge: i2c6-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18tl82_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_i2c6_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18tl82_out_i2c6_bu18rl82: endpoint { + remote-endpoint = <&i2c6_bu18rl82_in_i2c6_bu18tl82>; + }; + }; + }; + }; + + i2c6_bu18rl82: i2c6-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0000 //set gpio0 low + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0000 //set gpio1 low + 005d 0000 //rl gpio2 output lcd_rst + 005e 0000 //set gpio2 low + 0060 0000 //rl gpio3 output tp-rst + 0061 0000 //set gpio3 low + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0000 //set gpio5 low + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + + i2c6_bu18rl82_pinctrl: i2c6-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default","init","sleep"; + pinctrl-0 = <&i2c6_bu18rl82_panel_pins>; + pinctrl-1 = <&i2c6_bu18rl82_panel_pins>; + pinctrl-2 = <&i2c6_bu18rl82_panel_sleep_pins>; + status = "okay"; + + i2c6_bu18rl82_panel_pins: panel-pins { + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + 100ms-delay { + pins = "BU18RL82_GPIO1"; + function = "DELAY_100MS"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + }; + + i2c6_bu18rl82_panel_sleep_pins: panel-sleep-pins { + lcd-rst-sleep { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + tp-rst-sleep { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + + lcd-otp-pin-sleep { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_LOW"; + }; + }; + + i2c6_bu18rl82_gpio: i2c6-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c6_bu18rl82_pinctrl 0 223 8>; + }; + }; + + i2c6_bu18rl82_bridge: i2c6-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c6_bu18rl82_in_i2c6_bu18tl82: endpoint { + remote-endpoint = <&i2c6_bu18tl82_out_i2c6_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c6_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c6_bu18rl82>; + }; + }; + }; + }; + + himax@48 { + compatible = "himax,hxcommon"; + reg = <0x48>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touch_gpio_dsi1>; + pinctrl-1 = <&touch_gpio_dsi1>; + himax,location = "himax-touch-dsi1"; + himax,irq-gpio = <&gpio1 RK_PB7 IRQ_TYPE_EDGE_FALLING>; + himax,rst-gpio = <&i2c6_bu18rl82_gpio 3 GPIO_ACTIVE_LOW>; + himax,panel-coords = <0 1920 0 720>; + himax,display-coords = <0 1920 0 720>; + status = "okay"; + }; +}; + +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m3_xfer>; + clock-frequency = <400000>; + status = "disabled"; + + i2c7_bu18tl82: i2c7-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a + 0014 000a + 0021 0008 + 0023 0009 + 0024 0009 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0000 //gpio3 output tp_int + 0034 0005 //bypass des gpio3 + 0036 0018 //gpio4 input tp_rst + 0037 0006 //bypass des gpio4 + 027c 0041 + 027d 0041 + 0045 0080 + 0046 0007 + 004b 0038 + 004c 0004 + 0053 0064 + 022b 0062 + 022c 0027 + 022d 002e + 0274 0030 + 0275 0020 + 0296 0004 + 0297 000d + 02b2 00c8 + 02b4 0001 + 02b8 00ff + 02b9 000f + 02ba 00ff + 02bb 000f + 02be 00ff + 02bf 001f + 02c2 00ff + 02c3 001f + 0396 0004 + 0397 000d + 03b2 00c8 + 03b4 0001 + 03b8 00ff + 03b9 000f + 03ba 00ff + 03bb 000f + 03be 00ff + 03bf 001f + 03c2 00ff + 03c3 001f + 0060 0001 + 0061 0003 + 022e 0080 + 032e 0080 + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0019 + 0445 0020 + 0446 001f + ]; + + i2c7_bu18tl82_pinctrl: i2c7-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bu18tl82_panel_pins>; + status = "okay"; + + i2c7_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + + i2c7_bu18tl82_gpio: i2c7-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c7_bu18tl82_pinctrl 0 232 8>; + }; + }; + + i2c7_bu18tl82_bridge: i2c7-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18tl82_in_edp1: endpoint { + remote-endpoint = <&edp1_out_i2c7_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18tl82_out_i2c7_bu18rl82: endpoint { + remote-endpoint = <&i2c7_bu18rl82_in_i2c7_bu18tl82>; + }; + }; + }; + }; + + i2c7_bu18rl82: i2c7-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 000b + 0012 0003 + 0013 0001 + 001d 0008 + 001f 0002 + 0020 0002 + 0031 0041 //i2c addr 0x41 + 0032 0041 //i2c addr 0x41 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0001 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0018 //rl gpio3 input tp-int + 042e 0005 //bypass ser gpio3 + 0061 0005 //bypass ser gpio3 + 0063 0000 //rl gpio4 output tp-rst + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0007 //bypass ser gpio5 + 0073 0080 + 0074 0007 + 0079 000a + 007b 0038 + 007c 0004 + 0081 0003 + 0082 0010 + 0084 0020 + 0086 0002 + 0087 0002 + 0088 0010 + 0089 0010 + 008b 0020 + 008d 0002 + 008e 0002 + 008f 0010 + 00d0 0040 + 00d8 0042 + 00d9 0004 + 0423 0002 + 0424 00ec + 0425 0027 + 0429 000a + 045d 0001 + 0529 000a + 055d 0003 + 0090 0001 + 0091 0003 + 0426 0080 + 042d 0004 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0019 + 0645 0020 + 0646 001f + ]; + i2c7_bu18rl82_pinctrl: i2c7-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bu18rl82_panel_pins>; + status = "okay"; + + i2c7_bu18rl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "SER_GPIO1_TO_DES"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + }; + + i2c7_bu18rl82_gpio: i2c7-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c7_bu18rl82_pinctrl 0 241 8>; + }; + }; + + i2c7_bu18rl82_bridge: i2c7-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c7_bu18rl82_in_i2c7_bu18tl82: endpoint { + remote-endpoint = <&i2c7_bu18tl82_out_i2c7_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c7_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c7_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&i2c8 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + clock-frequency = <400000>; + status = "disabled"; + + i2c8_bu18tl82: i2c8-bu18tl82@10 { + compatible = "rohm,bu18tl82"; + reg = <0x10>; + status = "okay"; + + serdes-init-sequence = [ + 0013 001a //013h[3]1-lane1 enable 013h[3] 1-LVDS Receiver Port-A + 0014 000a //014h[3]1-lane1 enable 014h[3] 1-LVDS Receiver Port-B + 0021 0008 + 0023 0009 + 0024 0009 + 022b 0038 + 022c 0072 + 022d 0023 //VPLL=75MHZS + //022b 00d8 + //022c 0089 + //022d 003d //VPLL=99MHz (ref26MHz) 4032984*26/1024x1024=99M + 022e 0080 + 027c 0048 + 027d 0048 //i2c addr 0x48 + 0296 0004 + 0297 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0297 000d //CLLTX0_PLL_GAIN 297h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0018 00a5 + 0019 0069 + 0267 003d + 0268 002c + 0269 002c + 026a 002c + 026b 002c + 0367 003d + 0368 002c + 0369 002c + 036a 002c + 036b 002c + 0018 0000 + 0019 0000 + 002a 0018 //gpio0 input lcd_bl_pwm + 002d 0018 //gpio1 input lcd_pwr_en + + 0030 0018 //gpio2 input lcd_rst + 0033 0018 //gpio3 input tp_rst + 0034 0005 //bypass des gpio3 + 0036 0000 //gpio4 output tp_int + 0037 0006 //bypass des gpio4 + + 02a7 0002 + 02a8 0003 + 02a9 0004 + 02aa 0005 + 0045 0080 + 0046 0007 //1920 + 004b 00d0 + 004c 0002 //720 + 004d 00d0 + 004e 0002 //720 + 0051 0080 + 0052 0007 //1920 + 0053 0064 //0053h[6]1:2 Rx ports CLLCH2_EN 53h[5] 1:2 Clock Tx lanes + 024d 0061 + 0252 0005 + 0274 0030 + 0275 0020 + 0396 0004 + 0397 0009 //CLLTX0_PLL_GAIN 397h[3:2] 1001 2'b10: 1.2~2.3 Gbps/lane + //0397 000d //CLLTX0_PLL_GAIN 397h[3:2] 1101 2'b11: 2.2~3.6 Gbps/lane + 0061 0003 //CLLTX0 enable CLLTX1 enable + 0060 0003 //CLLTX0/1 RGB data output Enable + /* TL82 Pattern Gen Set 1 + * Horizontal Gray Scale 256 steps + */ + 040A 0010 + 040B 0080 + 040C 0080 + 040D 0080 + 0444 0090 //h_blank=144 + 0446 00d2 //v_blank=210 + ]; + i2c8_bu18tl82_pinctrl: i2c8-bu18tl82-pinctrl { + compatible = "rohm,bu18tl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_bu18tl82_panel_pins>; + status = "okay"; + + i2c8_bu18tl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18TL82_GPIO0"; + function = "SER_TO_DES_GPIO0"; + }; + + lcd-pwr-en { + pins = "BU18TL82_GPIO1"; + function = "SER_TO_DES_GPIO1"; + }; + + ser-irq { + pins = "BU18TL82_GPIO2"; + function = "DES_GPIO2_TO_SER"; + }; + + tp-int { + pins = "BU18TL82_GPIO3"; + function = "DES_GPIO4_TO_SER"; + }; + }; + + + i2c8_bu18tl82_gpio: i2c8-bu18tl82-gpio { + compatible = "rohm,bu18tl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c8_bu18tl82_pinctrl 0 250 8>; + }; + }; + + i2c8_bu18tl82_bridge: i2c8-bu18tl82-bridge { + compatible = "rohm,bu18tl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18tl82_in_dp1: endpoint { + remote-endpoint = <&dp1_out_i2c8_bu18tl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18tl82_out_i2c8_bu18rl82: endpoint { + remote-endpoint = <&i2c8_bu18rl82_in_i2c8_bu18tl82>; + }; + }; + }; + }; + + i2c8_bu18rl82: i2c8-bu18rl82@30 { + compatible = "rohm,bu18rl82"; + reg = <0x30>; + status = "okay"; + serdes-init-sequence = [ + 0011 0003 //Clockless Link Receiver Lane-0+ LVDS portA + 0012 0003 //Clockless Link Receiver Lane-1+ LVDS portB + 0013 0000 + 001d 0008 + 001f 0002 //LVDSTX0_REFSEL + 0020 0002 //LVDSTX1_REFSEL + 0031 0048 + 0032 0048 //i2c addr 0x48 + 0423 0000 + 0424 0000 + 0425 0020 + 0426 0080 + 0057 0000 + 0058 0002 + 0057 0000 //rl gpio0 output lcd_bl_pwm + 0058 0002 //bypass ser gpio0 + 005a 0000 //rl gpio1 output lcd_pwr_en + 005b 0003 //bypass ser gpio1 + 005d 0000 //rl gpio2 output lcd_rst + 005e 0004 //bypass ser gpio2 + 0060 0000 //rl gpio3 output tp-rst + 0061 0005 //bypass ser gpio3 + 0063 0018 //rl gpio4 input tp-int + 0064 0006 //bypass ser gpio4 + 0066 0000 //rl gpio5 output + 0067 0001 //set gpio5 high + + 0073 0080 + 0074 0007 //0x0780 = 1920 + 0075 0080 + 0076 0007 //0x0780 = 1920 + 0079 000a //h[3]: dual lvds mode h[1] single lane / dual lane + 007b 00d0 + 007c 0002 //0x02d0 = 720 + 007d 00d0 + 007e 0002 //0x02d0 = 720 + 0081 0003 //01---> Sync OFF + 0082 0010 //Hsync=16clk + 0084 001c //HBP=28clk + 0086 0002 //Vsync=2lines + 0087 0008 //VBP=8lines + 0088 0000 //VSYNC_CHG=0CLK + 0089 0010 //Hsync = 16? + 008b 001c //HFP=28clk? + 008d 0002 //Vsync=2lines? + 008e 0008 //VFP=8line? + 008f 0000 //VSYNC_CHG=0CLK? + 00d0 0040 //[3]FixHtotalEN + 00d8 00c0 + 00d9 0003 //DE=960 + 0429 000a //LVDSTX0_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 045d 0001 + 0529 000a //LVDSTX1_PLLGAIN 2'b10: 30 MHz ~ 80 MHz + 055d 0001 + 0091 0003 + 0090 0001 + /* RL82 Pattern Gen Set + * Vertical Gray Scale Color Bar + */ + 060A 00B0 + 060B 00FF + 060C 00FF + 060D 00FF + 0644 0090 + 0646 00d2 + ]; + i2c8_bu18rl82_pinctrl: i2c8-bu18rl82-pinctrl { + compatible = "rohm,bu18rl82-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8_bu18rl82_panel_pins>; + status = "okay"; + + i2c8_bu18rl82_panel_pins: panel-pins { + lcd-bl-pwm { + pins = "BU18RL82_GPIO0"; + function = "SER_GPIO0_TO_DES"; + }; + + lcd-pwr-en { + pins = "BU18RL82_GPIO1"; + function = "SER_GPIO1_TO_DES"; + }; + + lcd-rst { + pins = "BU18RL82_GPIO2"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-rst { + pins = "BU18RL82_GPIO3"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + + tp-int { + pins = "BU18RL82_GPIO4"; + function = "DES_TO_SER_GPIO3"; + }; + + lcd-otp-pin { + pins = "BU18RL82_GPIO5"; + function = "DES_GPIO_OUTPUT_HIGH"; + }; + }; + + i2c8_bu18rl82_gpio: i2c8-bu18rl82-gpio { + compatible = "rohm,bu18rl82-gpio"; + status = "okay"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&i2c8_bu18rl82_pinctrl 0 259 8>; + }; + }; + + i2c8_bu18rl82_bridge: i2c8-bu18rl82-bridge { + compatible = "rohm,bu18rl82-bridge"; + status = "okay"; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + i2c8_bu18rl82_in_i2c8_bu18tl82: endpoint { + remote-endpoint = <&i2c8_bu18tl82_out_i2c8_bu18rl82>; + }; + }; + + port@1 { + reg = <1>; + + i2c8_bu18rl82_out_panel1: endpoint { + remote-endpoint = <&panel1_in_i2c8_bu18rl82>; + }; + }; + }; + }; + + lt7911d@2b { + compatible = "lontium,lt7911d-fb-notifier"; + reg = <0x2b>; + reset-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_LOW>; + status = "okay"; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +/* dsi0->serdes->lvds_panel */ +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m2_pins>; +}; + +/* dp0->serdes->lvds_panel */ +&pwm10 { + pinctrl-0 = <&pwm10m2_pins>; + status = "okay"; +}; + +/* edp1->serdes->lvds_panel */ +&pwm11 { + pinctrl-0 = <&pwm11m3_pins>; + status = "okay"; +}; + +/* edp0->serdes->lvds_panel */ +&pwm7 { + pinctrl-0 = <&pwm7m0_pins>; + status = "okay"; +}; + +/* dsi1->serdes->lvds_panel */ +&pwm13 { + status = "okay"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +/* dp1->serdes->lvds_panel */ +&pwm14 { + pinctrl-0 = <&pwm14m0_pins>; + status = "okay"; +}; + +&route_dp0 { + status = "disabled"; + connect = <&vp0_out_dp0>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dp1 { + status = "disabled"; + connect = <&vp0_out_dp1>; + logo,uboot = "logo34.bmp"; + logo,kernel = "logo34.bmp"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp2_out_dsi0>; + logo,uboot = "logo1.bmp"; + logo,kernel = "logo1.bmp"; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; + logo,uboot = "logo2.bmp"; + logo,kernel = "logo2.bmp"; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp1_out_edp0>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; + logo,uboot = "logo56.bmp"; + logo,kernel = "logo56.bmp"; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&usbdp_phy1 { + rockchip,dp-lane-mux = <0 1 2 3>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru PLL_V0PLL>; + assigned-clock-rates = <1152000000>; +}; + +&vp0 { + assigned-clocks = <&cru DCLK_VOP0_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp1 { + assigned-clocks = <&cru DCLK_VOP1_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; +}; + +&vp2 { + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; + +&vp3 { + assigned-clocks = <&cru DCLK_VOP3>; + assigned-clock-parents = <&cru PLL_V0PLL>; +}; diff --git a/rk3588-vehicle-v20.dtsi b/rk3588-vehicle-v20.dtsi new file mode 100644 index 0000000..91d6ecb --- /dev/null +++ b/rk3588-vehicle-v20.dtsi @@ -0,0 +1,458 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17821>; //17000 + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <415384>;//417000 + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <728574>;//890000 + }; + + }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588-vehicle.dtsi b/rk3588-vehicle.dtsi new file mode 100644 index 0000000..f4498cd --- /dev/null +++ b/rk3588-vehicle.dtsi @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588.dtsi b/rk3588.dtsi new file mode 100644 index 0000000..eed99fd --- /dev/null +++ b/rk3588.dtsi @@ -0,0 +1,923 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3588s.dtsi" +#include "rk3588-vccio3-pinctrl.dtsi" + +/ { + aliases { + dp0 = &dp0; + dp1 = &dp1; + edp0 = &edp0; + edp1 = &edp1; + ethernet0 = &gmac0; + hdptx0 = &hdptxphy0; + hdptx1 = &hdptxphy1; + hdptxhdmi0 = &hdptxphy_hdmi0; + hdptxhdmi1 = &hdptxphy_hdmi1; + hdmi0 = &hdmi0; + hdmi1 = &hdmi1; + hdmirx0 = &hdmirx_ctrler; + rkcif_mipi_lvds4= &rkcif_mipi_lvds4; + rkcif_mipi_lvds5= &rkcif_mipi_lvds5; + usbdp0 = &usbdp_phy0; + usbdp1 = &usbdp_phy1; + }; + + rkcif_mipi_lvds4: rkcif-mipi-lvds4 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds5: rkcif-mipi-lvds5 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf: rkcif-mipi-lvds5-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf_vir1: rkcif-mipi-lvds5-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf_vir2: rkcif-mipi-lvds5-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf_vir3: rkcif-mipi-lvds5-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + usbdrd3_1: usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_1: usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = ; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG1>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 22>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; + assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; + clock-names = "mclk_tx", "hclk"; + assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S8_8CH_TX>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 8>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + assigned-clocks = <&cru CLK_SPDIF4_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S6_8CH_TX>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S7_8CH_RX>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S10_8CH_RX>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx1: spdif-rx@fde10000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde10000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru MCLK_SPDIFRX1>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac0 22>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_SPDIFRX1>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx2: spdif-rx@fde18000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde18000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru MCLK_SPDIFRX2>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac0 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_SPDIFRX2>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dp1: dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = ; + clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, + <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_SPDIF5_DP1>, + <&hclk_vo0>, <&cru CLK_DP1>; + clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp"; + assigned-clocks = <&cru CLK_AUX16M_1>; + assigned-clock-rates = <16000000>; + resets = <&cru SRST_DP1>; + phys = <&usbdp_phy1_dp>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dp1>; + status = "disabled"; + }; + + dp1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dp1>; + status = "disabled"; + }; + + dp1_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_dp1>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + dp1_out: endpoint { }; + }; + }; + }; + + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfdea0000 0x0 0x10000>, <0x0 0xfdeb0000 0x0 0x10000>; + interrupts = , + , + , + , + ; + clocks = <&cru PCLK_HDMITX1>, + <&cru CLK_HDMIHDP1>, + <&cru CLK_HDMITX1_EARC>, + <&cru CLK_HDMITX1_REF>, + <&cru MCLK_I2S6_8CH_TX>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&hclk_vo1>, + <&hdptxphy_hdmi_clk1>; + clock-names = "pclk", + "hpd", + "earc", + "hdmitx_ref", + "aud", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "hclk_vo1", + "link_clk"; + resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; + reset-names = "ref", "hdp"; + power-domains = <&power RK3588_PD_VO1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + reg-io-width = <4>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdptxphy_hdmi1>; + phy-names = "hdmi"; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi1>; + status = "disabled"; + }; + + hdmi1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi1>; + status = "disabled"; + }; + + hdmi1_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_hdmi1>; + status = "disabled"; + }; + }; + }; + }; + + edp1: edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfded0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, + <&cru CLK_EDP1_200M>, <&hclk_vo1>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; + reset-names = "dp", "apb"; + phys = <&hdptxphy1>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp1>; + status = "disabled"; + }; + + edp1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp1>; + status = "disabled"; + }; + + edp1_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_edp1>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + edp1_out: endpoint { }; + }; + }; + }; + + hdmirx_ctrler: hdmirx-controller@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + reg-names = "hdmirx_regs"; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + interrupts = , + , + ; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&hclk_vo1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu"; + pinctrl-0 = <&hdmim1_rx>; + pinctrl-names = "default"; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 + 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 + 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000 + 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe150000 0x0 0x10000>, + <0xa 0x40000000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, + <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, + <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000 + 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000 + 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000 + 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0x0 0xfe160000 0x0 0x10000>, + <0xa 0x40400000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x20 0x2f>; + clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, + <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, + <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 + 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 + 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000 + 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0x0 0xfe170000 0x0 0x10000>, + <0xa 0x40800000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac_uio0: uio@fe1b0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + rockchip,ethernet = <&gmac0>; + status = "disabled"; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&php_grf>; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, + <&cru CLK_GMAC0_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + resets = <&cru SRST_A_GMAC0>; + reset-names = "stmmaceth"; + power-domains = <&power RK3588_PD_GMAC>; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, + <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, + <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy1_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + resets = <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>, + <&cru SRST_HDPTX1_CMN>, <&cru SRST_HDPTX1_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdptxphy_hdmi1: hdmiphy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + + hdptxphy_hdmi_clk1: clk-port { + #clock-cells = <0>; + status = "okay"; + }; + }; + + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY1_IMMORTAL>, + <&cru PCLK_USBDPPHY1>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, + <&cru SRST_USBDP_COMBO_PHY1_CMN>, + <&cru SRST_USBDP_COMBO_PHY1_LANE>, + <&cru SRST_USBDP_COMBO_PHY1_PCS>, + <&cru SRST_P_USBDPPHY1>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1_u3: u3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; + clock-names = "pclk"; + resets = <&cru SRST_PCIE30_PHY>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + +}; + +&display_subsystem { + route { + route_dp1: route-dp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_dp1>; + }; + + route_hdmi1: route-hdmi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi1>; + }; + }; +}; + +&vp0 { + vp0_out_dp1: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp1_in_vp0>; + }; + + vp0_out_edp1: endpoint@4 { + reg = <4>; + remote-endpoint = <&edp1_in_vp0>; + }; + + vp0_out_hdmi1: endpoint@5 { + reg = <5>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dp1: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp1_in_vp1>; + }; + + vp1_out_edp1: endpoint@4 { + reg = <4>; + remote-endpoint = <&edp1_in_vp1>; + }; + + vp1_out_hdmi1: endpoint@5 { + reg = <5>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; + +&vp2 { + vp2_out_dp1: endpoint@5 { + reg = <5>; + remote-endpoint = <&dp1_in_vp2>; + }; + + vp2_out_edp1: endpoint@6 { + reg = <6>; + remote-endpoint = <&edp1_in_vp2>; + }; + + vp2_out_hdmi1: endpoint@7 { + reg = <7>; + remote-endpoint = <&hdmi1_in_vp2>; + }; +}; diff --git a/rk3588/.dr4-rk3588.dtb.cmd b/rk3588/.dr4-rk3588.dtb.cmd new file mode 100644 index 0000000..fc337e9 --- /dev/null +++ b/rk3588/.dr4-rk3588.dtb.cmd @@ -0,0 +1,59 @@ +cmd_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := gcc -E -Wp,-MMD,arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.d.pre.tmp -nostdinc -I./scripts/dtc/include-prefixes -undef -D__DTS__ -x assembler-with-cpp -o arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.dts.tmp arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts ; ./scripts/dtc/dtc -O dtb -o arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb -b 0 -iarch/arm64/boot/dts/rockchip/rk3588/ -i./scripts/dtc/include-prefixes -Wno-interrupt_provider -@ -Wno-unit_address_vs_reg -Wno-unit_address_format -Wno-avoid_unnecessary_addr_size -Wno-alias_paths -Wno-graph_child_address -Wno-simple_bus_reg -Wno-unique_unit_address -Wno-pci_device_reg -d arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.d.dtc.tmp arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.dts.tmp ; cat arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.d.pre.tmp arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.d.dtc.tmp > arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.d + +source_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts + +deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := \ + arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/usb/pd.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588j.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/phy/phy-snps-pcie3.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/clock/rk3588-cru.h \ + scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h \ + scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h \ + scripts/dtc/include-prefixes/dt-bindings/phy/phy.h \ + scripts/dtc/include-prefixes/dt-bindings/power/rk3588-power.h \ + scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h \ + scripts/dtc/include-prefixes/dt-bindings/soc/rockchip-system-status.h \ + scripts/dtc/include-prefixes/dt-bindings/suspend/rockchip-rk3588.h \ + scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinconf.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rockchip-pinconf.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h \ + scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h \ + scripts/dtc/include-prefixes/dt-bindings/input/rk-input.h \ + scripts/dtc/include-prefixes/dt-bindings/display/drm_mipi_dsi.h \ + scripts/dtc/include-prefixes/dt-bindings/display/rockchip_vop.h \ + scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rd-rk3588-lcd-gpio.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-eth-pcie2gmac-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-power-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-pcie3.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-5g.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-audio-rt5640.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-wifi-bt-ap6275p-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dcphy1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dphy0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dphy1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi \ + +arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb) + +$(deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb): diff --git a/rk3588/.dr4-rk3588.dtb.d.dtc.tmp b/rk3588/.dr4-rk3588.dtb.d.dtc.tmp new file mode 100644 index 0000000..9d597dd --- /dev/null +++ b/rk3588/.dr4-rk3588.dtb.d.dtc.tmp @@ -0,0 +1 @@ +arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb: arch/arm64/boot/dts/rockchip/rk3588/.dr4-rk3588.dtb.dts.tmp diff --git a/rk3588/.dr4-rk3588.dtb.d.pre.tmp b/rk3588/.dr4-rk3588.dtb.d.pre.tmp new file mode 100644 index 0000000..3918e91 --- /dev/null +++ b/rk3588/.dr4-rk3588.dtb.d.pre.tmp @@ -0,0 +1,51 @@ +dr4-rk3588.o: arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts \ + arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/usb/pd.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588j.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/phy/phy-snps-pcie3.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/clock/rk3588-cru.h \ + scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h \ + scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h \ + scripts/dtc/include-prefixes/dt-bindings/phy/phy.h \ + scripts/dtc/include-prefixes/dt-bindings/power/rk3588-power.h \ + scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h \ + scripts/dtc/include-prefixes/dt-bindings/soc/rockchip-system-status.h \ + scripts/dtc/include-prefixes/dt-bindings/suspend/rockchip-rk3588.h \ + scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinconf.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rockchip-pinconf.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi \ + scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h \ + scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h \ + scripts/dtc/include-prefixes/dt-bindings/input/rk-input.h \ + scripts/dtc/include-prefixes/dt-bindings/display/drm_mipi_dsi.h \ + scripts/dtc/include-prefixes/dt-bindings/display/rockchip_vop.h \ + scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rd-rk3588-lcd-gpio.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-eth-pcie2gmac-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-power-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-pcie3.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-5g.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-audio-rt5640.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-wifi-bt-ap6275p-rk3588.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dcphy1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dphy0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dphy1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi \ + arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi diff --git a/rk3588/.dr4-rk3588.dtb.dts.tmp b/rk3588/.dr4-rk3588.dtb.dts.tmp new file mode 100644 index 0000000..bafcdcc --- /dev/null +++ b/rk3588/.dr4-rk3588.dtb.dts.tmp @@ -0,0 +1,16256 @@ +# 0 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" +# 0 "" +# 0 "" +# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 1 + + + + + + +/dts-v1/; + + + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/usb/pd.h" 1 +# 12 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588j.dtsi" 1 + + + + + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 1 + + + + + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy-snps-pcie3.h" 1 +# 7 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 1 + + + + + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rk3588-cru.h" 1 +# 7 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1 +# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" +# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1 +# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2 +# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy.h" 1 +# 10 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3588-power.h" 1 +# 11 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h" 1 +# 12 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip-system-status.h" 1 +# 13 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/suspend/rockchip-rk3588.h" 1 +# 14 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1 +# 15 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi2dcphy0 = &csi2_dcphy0; + csi2dcphy1 = &csi2_dcphy1; + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; + csi2dphy3 = &csi2_dphy3; + csi2dphy4 = &csi2_dphy4; + csi2dphy5 = &csi2_dphy5; + dsi0 = &dsi0; + dsi1 = &dsi1; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + rkcif_mipi_lvds0= &rkcif_mipi_lvds; + rkcif_mipi_lvds1= &rkcif_mipi_lvds1; + rkcif_mipi_lvds2= &rkcif_mipi_lvds2; + rkcif_mipi_lvds3= &rkcif_mipi_lvds3; + rkvdec0 = &rkvdec0; + rkvdec1 = &rkvdec1; + rkvenc0 = &rkvenc0; + rkvenc1 = &rkvenc1; + jpege0 = &jpege0; + jpege1 = &jpege1; + jpege2 = &jpege2; + jpege3 = &jpege3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &sfc; + hdcp0 = &hdcp0; + hdcp1 = &hdcp1; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spll: spll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <702000000>; + clock-output-names = "spll"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + hclk_vo1: hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08ec 0 0x10>; + clock-names = "link"; + clocks = <&cru 612>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08b0 0 0x10>; + clock-names = "link"; + clocks = <&cru 444>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_vo0: hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08dc 0 0x10>; + clock-names = "link"; + clocks = <&cru 621>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_usb: hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a8 0 0x10>; + clock-names = "link"; + clocks = <&cru 612>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_nvm: hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c087c 0 0x10>; + clock-names = "link"; + clocks = <&cru 321>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_usb: aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a8 0 0x10>; + clock-names = "link"; + clocks = <&cru 611>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_isp1_pre: hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0868 0 0x10>; + clock-names = "link"; + clocks = <&cru 481>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_isp1_pre: aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0868 0 0x10>; + clock-names = "link"; + clocks = <&cru 480>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a0 0 0x10>; + clock-names = "link"; + clocks = <&cru 444>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a0 0 0x10>; + clock-names = "link"; + clocks = <&cru 446>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a4 0 0x10>; + clock-names = "link"; + clocks = <&cru 444>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a4 0 0x10>; + clock-names = "link"; + clocks = <&cru 446>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08b0 0 0x10>; + clock-names = "link"; + clocks = <&cru 444>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08c0 0 0x10>; + clock-names = "link"; + clocks = <&cru 453>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08c0 0 0x10>; + clock-names = "link"; + clocks = <&cru 452>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08dc 0 0x10>; + clock-names = "link"; + clocks = <&cru 620>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08ec 0 0x10>; + clock-names = "link"; + clocks = <&cru 611>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + pclk_av1_pre: pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0910 0 0x10>; + clock-names = "link"; + clocks = <&cru 446>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_av1_pre: aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0910 0 0x10>; + clock-names = "link"; + clocks = <&cru 444>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_sdio_pre: hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c092c 0 0x10>; + clock-names = "link"; + clocks = <&hclk_nvm>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + pclk_vo0_grf: pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x4>; + clocks = <&hclk_vo0>; + clock-names = "link"; + #clock-cells = <0>; + }; + + pclk_vo1_grf: pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x4>; + clocks = <&hclk_vo1>; + clock-names = "link"; + #clock-cells = <0>; + }; + + mclkin_i2s0: mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin_i2s1: mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkin_i2s2: mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s2_mclkin"; + }; + + mclkin_i2s3: mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s3_mclkin"; + }; + + mclkout_i2s0: mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru 57>; + assigned-clocks = <&cru 57>; + assigned-clock-rates = <22288000>; + #clock-cells = <0>; + clock-output-names = "i2s0_mclkout_to_io"; + rockchip,bit-shift = <0>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + }; + + mclkout_i2s1: mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru 657>; + #clock-cells = <0>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <1>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + }; + + mclkout_i2s1m1: mclkout-i2s1@fd58a000 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58a000 0 0x4>; + clocks = <&cru 657>; + #clock-cells = <0>; + clock-output-names = "i2s1m1_mclkout_to_io"; + rockchip,bit-shift = <6>; + rockchip,clk-ignore-unused; + }; + + mclkout_i2s2: mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru 40>; + #clock-cells = <0>; + clock-output-names = "i2s2_mclkout_to_io"; + rockchip,bit-shift = <2>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + }; + + mclkout_i2s3: mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru 46>; + #clock-cells = <0>; + clock-output-names = "i2s3_mclkout_to_io"; + rockchip,bit-shift = <7>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <100>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk 0>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk 2>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <300>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk 2>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b1>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk 3>; + operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b2>; + #cooling-cells = <2>; + dynamic-power-coefficient = <300>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk 3>; + operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b3>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + }; + }; + + cluster0_opp_table: cluster0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + rockchip,opp-shared-dsu; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1365 0 + 1366 1387 1 + 1388 1409 2 + 1410 1431 3 + 1432 1453 4 + 1454 1475 5 + 1476 9999 6 + >; + rockchip,pvtm-voltage-sel = < + 0 1410 0 + 1411 1434 1 + 1435 1458 2 + 1459 1482 3 + 1483 1506 4 + 1507 1530 5 + 1531 9999 6 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x64>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1416000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <244 244>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + + rockchip,grf = <&litcore_grf>; + rockchip,dsu-grf = <&dsu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <1008000>; + rockchip,reboot-freq = <1416000>; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <1608000>; + + + opp-408000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L3 = <687500 687500 950000>, + <687500 687500 950000>; + opp-microvolt-L4 = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L5 = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L6 = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L1 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L2 = <737500 737500 950000>, + <737500 737500 950000>; + opp-microvolt-L3 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L4 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L5 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L6 = <712500 712500 950000>, + <712500 712500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L1 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L2 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L3 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L4 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L5 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L6 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L2 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L3 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L4 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L5 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L6 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-1296000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L1 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L1 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L2 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L1 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L2 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L3 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L4 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L5 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L6 = <812500 812500 950000>, + <812500 812500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1704000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L1 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L2 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L3 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L4 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L5 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L6 = <862500 862500 950000>, + <862500 862500 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: cluster1-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1539 0 + 1540 1564 1 + 1565 1589 2 + 1590 1614 3 + 1615 1644 4 + 1645 1674 5 + 1675 1704 6 + 1705 9999 7 + >; + rockchip,pvtm-voltage-sel = < + 0 1595 0 + 1596 1615 1 + 1616 1640 2 + 1641 1675 3 + 1676 1710 4 + 1711 1743 5 + 1744 1776 6 + 1777 9999 7 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <270 270>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <3>; + + rockchip,grf = <&bigcore0_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <1008000>; + rockchip,idle-threshold-freq = <2208000>; + rockchip,reboot-freq = <1800000>; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <2208000>; + + + opp-408000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L2 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L3 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L4 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L5 = <687500 687500 1000000>, + <687500 687500 1000000>; + opp-microvolt-L6 = <675000 675000 1000000>, + <675000 675000 1000000>; + opp-microvolt-L7 = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L2 = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L3 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L4 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L5 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L6 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L7 = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L1 = <837500 837500 1000000>, + <837500 837500 1000000>; + opp-microvolt-L2 = <825000 825000 1000000>, + <825000 825000 1000000>; + opp-microvolt-L3 = <812500 812500 1000000>, + <812500 812500 1000000>; + opp-microvolt-L4 = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L5 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L6 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L7 = <762500 762500 1000000>, + <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L1 = <912500 912500 1000000>, + <912500 912500 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>, + <900000 900000 1000000>; + opp-microvolt-L3 = <887500 887500 1000000>, + <887500 887500 1000000>; + opp-microvolt-L4 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L5 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L6 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L7 = <837500 837500 1000000>, + <837500 837500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>, + <987500 987500 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>, + <975000 975000 1000000>; + opp-microvolt-L2 = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L3 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L4 = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L5 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L6 = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L7 = <912500 912500 1000000>, + <912500 912500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L6 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L7 = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L1 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L2 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L3 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L4 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L5 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L6 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L7 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: cluster2-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1539 0 + 1540 1564 1 + 1565 1589 2 + 1590 1614 3 + 1615 1644 4 + 1645 1674 5 + 1675 1704 6 + 1705 9999 7 + >; + rockchip,pvtm-voltage-sel = < + 0 1595 0 + 1596 1615 1 + 1616 1640 2 + 1641 1675 3 + 1676 1710 4 + 1711 1743 5 + 1744 1776 6 + 1777 9999 7 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <270 270>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <3>; + + rockchip,grf = <&bigcore1_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <1008000>; + rockchip,idle-threshold-freq = <2208000>; + rockchip,reboot-freq = <1800000>; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <2208000>; + + + opp-408000000 { + opp-supported-hw = <0xf9 0x0ffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L2 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L3 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L4 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L5 = <687500 687500 1000000>, + <687500 687500 1000000>; + opp-microvolt-L6 = <675000 675000 1000000>, + <675000 675000 1000000>; + opp-microvolt-L7 = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L2 = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L3 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L4 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L5 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L6 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L7 = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L1 = <837500 837500 1000000>, + <837500 837500 1000000>; + opp-microvolt-L2 = <825000 825000 1000000>, + <825000 825000 1000000>; + opp-microvolt-L3 = <812500 812500 1000000>, + <812500 812500 1000000>; + opp-microvolt-L4 = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L5 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L6 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L7 = <762500 762500 1000000>, + <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L1 = <912500 912500 1000000>, + <912500 912500 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>, + <900000 900000 1000000>; + opp-microvolt-L3 = <887500 887500 1000000>, + <887500 887500 1000000>; + opp-microvolt-L4 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L5 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L6 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L7 = <837500 837500 1000000>, + <837500 837500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>, + <987500 987500 1000000>; + opp-microvolt-L3 = <975000 975000 1000000>, + <975000 975000 1000000>; + opp-microvolt-L4 = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L5 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L6 = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L7 = <912500 912500 1000000>, + <912500 912500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + + + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L6 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L7 = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L1 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L2 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L3 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L4 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L5 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L6 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L7 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <1 7 8>; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, + <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + csi2_dcphy0: csi2-dcphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dcphy1: csi2-dcphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy3: csi2-dphy3 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy4: csi2-dphy4 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy5: csi2-dphy5 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + + route { + route_dp0: route-dp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_dp0>; + }; + + route_dsi0: route-dsi0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp3_out_dsi0>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp3_out_dsi1>; + }; + + route_edp0: route-edp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp2_out_edp0>; + }; + + route_edp1: route-edp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + }; + + route_hdmi0: route-hdmi0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp3_out_rgb>; + }; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3588-dmc"; + interrupts = <0 73 4>; + interrupt-names = "complete"; + devfreq-events = <&dfi>; + clocks = <&scmi_clk 4>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + upthreshold = <40>; + downdifferential = <20>; + system-status-level = < + + (1 << 0) (0x1 << 2) + (1 << 3) (0x1 << 3) + (1 << 1) (0x1 << 0) + (1 << 4) (0x1 << 2) + (1 << 16) (0x1 << 2) + (1 << 19) (0x1 << 2) + (1 << 12) (0x1 << 3) + (1 << 14) (0x1 << 3) + (1 << 13) (0x1 << 3) + ((1 << 10) | (1 << 11)) (0x1 << 3) + (1 << 18) (0x1 << 3) + (1 << 21) (0x1 << 3) + >; + auto-freq-en = <1>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,leakage-voltage-sel = < + 1 31 0 + 32 44 1 + 45 57 2 + 58 254 3 + >; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + + + opp-528000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <675000 675000 875000>, + <725000 725000 750000>; + opp-microvolt-L1 = <675000 675000 875000>, + <700000 700000 750000>; + opp-microvolt-L2 = <675000 675000 875000>, + <687500 687500 750000>; + opp-microvolt-L3 = <675000 675000 875000>, + <675000 675000 750000>; + }; + opp-1068000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <725000 725000 875000>, + <737500 737500 750000>; + opp-microvolt-L1 = <700000 700000 875000>, + <712500 712500 750000>; + opp-microvolt-L2 = <675000 675000 875000>, + <700000 700000 750000>; + opp-microvolt-L3 = <675000 675000 875000>, + <687500 687500 750000>; + }; + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <800000 800000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <775000 775000 875000>, + <725000 725000 750000>; + opp-microvolt-L2 = <750000 750000 875000>, + <712500 712500 750000>; + opp-microvolt-L3 = <725000 725000 875000>, + <700000 700000 750000>; + }; + opp-2750000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2750000000>; + opp-microvolt = <875000 875000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <850000 850000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <837500 837500 875000>, + <725000 725000 750000>; + opp-microvolt-L3 = <825000 820000 875000>, + <700000 700000 750000>; + }; + + + opp-j-m-528000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-1068000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <800000 800000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <775000 775000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <750000 750000 875000>, + <750000 750000 750000>; + opp-microvolt-L3 = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-2750000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2750000000>; + opp-microvolt = <875000 875000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <850000 850000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <837500 837500 875000>, + <750000 750000 750000>; + opp-microvolt-L3 = <825000 820000 875000>, + <750000 750000 750000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + + assigned-clocks = <&scmi_clk 0>, + <&scmi_clk 2>, + <&scmi_clk 3>; + assigned-clock-rates = <816000000>, + <816000000>, + <816000000>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + sdei: sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + jpege_ccu: jpege-ccu { + compatible = "rockchip,vpu-jpege-ccu"; + status = "disabled"; + }; + + /omit-if-no-ref/ + mipi_dcphy1: mipi_dcphy0: mipi-dcphy-dummy { + }; + + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi4_csi2: mipi4-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi5_csi2: mipi5-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <12>; + rockchip,resetgroup-count = <1>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif_dvp: rkcif-dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_dvp_sditf: rkcif-dvp-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_dvp>; + status = "disabled"; + }; + + rkcif_mipi_lvds: rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds1: rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds2: rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds3: rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkisp0_vir0: rkisp0-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + + + + + + status = "disabled"; + }; + + rkisp0_vir1: rkisp0-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + status = "disabled"; + }; + + rkisp0_vir2: rkisp0-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + status = "disabled"; + }; + + rkisp0_vir3: rkisp0-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + status = "disabled"; + }; + + rkisp1_vir0: rkisp1-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkisp1_vir1: rkisp1-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkisp1_vir2: rkisp1-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkisp1_vir3: rkisp1-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkispp0_vir0: rkispp0-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <&rkispp0>; + status = "disabled"; + }; + + rkispp1_vir0: rkispp1-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <&rkispp1>; + status = "disabled"; + }; + + rkvenc_ccu: rkvenc-ccu { + compatible = "rockchip,rkv-encoder-v2-ccu"; + status = "disabled"; + }; + + rkvtunnel: rkvtunnel { + compatible = "rockchip,video-tunnel"; + status = "disabled"; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3588"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | (1 << (3)) + | (1 << (9)) + | (1 << (10)) + | (1 << (24)) + ) + >; + rockchip,wakeup-config = < + (0 + | (1 << (8)) + ) + >; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + sustainable-power = <2100>; + + thermal-sensors = <&tsadc 0>; + trips { + threshold: trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + + temperature = <115000>; + + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu_l0 (~0) (~0)>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&cpu_b0 (~0) (~0)>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = <&cpu_b2 (~0) (~0)>; + contribution = <1024>; + }; + map3 { + trip = <&target>; + cooling-device = <&gpu (~0) (~0)>; + contribution = <1024>; + }; + }; + }; + + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 1>; + }; + + bigcore1_thermal: bigcore1-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 2>; + }; + + little_core_thermal: littlecore-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 3>; + }; + + center_thermal: center-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 4>; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 5>; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <20>; + polling-delay = <1000>; + thermal-sensors = <&tsadc 6>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 ((((1 << (4)) - 1) << 8) | 4)>, + <1 14 ((((1 << (4)) - 1) << 8) | 4)>, + <1 11 ((((1 << (4)) - 1) << 8) | 4)>, + <1 10 ((((1 << (4)) - 1) << 8) | 4)>; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gpu: gpu@fb000000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xfb000000 0x0 0x200000>; + interrupts = <0 94 4>, + <0 93 4>, + <0 92 4>; + interrupt-names = "GPU", "MMU", "JOB"; + + clocks = <&scmi_clk 5>, <&cru 277>, + <&cru 278>, <&cru 276>; + clock-names = "clk_mali", "clk_gpu_coregroup", + "clk_gpu_stacks", "clk_gpu"; + assigned-clocks = <&scmi_clk 5>; + assigned-clock-rates = <200000000>; + power-domains = <&power 12>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <2982>; + + upthreshold = <30>; + downdifferential = <10>; + + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x04>; + rockchip,pvtm-voltage-sel-hw = < + 0 799 0 + 800 819 1 + 820 844 2 + 845 869 3 + 870 894 4 + 895 9999 5 + >; + rockchip,pvtm-voltage-sel = < + 0 815 0 + 816 835 1 + 836 860 2 + 861 885 3 + 886 910 4 + 911 9999 5 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x1c>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <800000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <(-135) (-135)>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + + rockchip,opp-clocks = <&cru 276>; + rockchip,grf = <&gpu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <400000>; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <800000>; + + + opp-300000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-400000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-500000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-700000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L2 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L1 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L2 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L3 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L4 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L5 = <700000 700000 850000>, + <700000 700000 850000>; + }; + opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <737500 737500 850000>, + <737500 737500 850000>; + }; + opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + + + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + + opp-j-850000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L3 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <750000 750000 850000>, + <750000 750000 850000>; + }; + + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-m-1000000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + }; + + usbdrd3_0: usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru 419>, <&cru 418>, + <&cru 417>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = <0 220 4>; + power-domains = <&power 31>; + resets = <&cru 676>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "disabled"; + }; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = <0 215 4>; + clocks = <&cru 413>, <&cru 414>, <&u2phy2>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + companion = <&usb_host0_ohci>; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + power-domains = <&power 31>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = <0 216 4>; + clocks = <&cru 413>, <&cru 414>, <&u2phy2>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + power-domains = <&power 31>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = <0 218 4>; + clocks = <&cru 415>, <&cru 416>, <&u2phy3>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + companion = <&usb_host1_ohci>; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + power-domains = <&power 31>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = <0 219 4>; + clocks = <&cru 415>, <&cru 416>, <&u2phy3>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + power-domains = <&power 31>; + status = "disabled"; + }; + + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = <0 369 4>, + <0 371 4>, + <0 374 4>, + <0 367 4>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = <0 381 4>, + <0 383 4>, + <0 386 4>, + <0 379 4>; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + usbhost3_0: usbhost3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru 377>, <&cru 376>, + <&cru 375>, <&cru 378>, + <&cru 358>, <&cru 385>; + clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbhost_dwc3_0: usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = <0 222 4>; + resets = <&cru 567>; + reset-names = "usb3-host"; + dr_mode = "host"; + phys = <&combphy2_psu 4>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + pmu0_grf: syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd588000 0x0 0x2000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = <(0x5242C300 + 1)>; + mode-charge = <(0x5242C300 + 11)>; + mode-fastboot = <(0x5242C300 + 9)>; + mode-loader = <(0x5242C300 + 1)>; + mode-normal = <(0x5242C300 + 0)>; + mode-recovery = <(0x5242C300 + 3)>; + mode-ums = <(0x5242C300 + 12)>; + mode-panic = <(0x5242C300 + 7)>; + mode-watchdog = <(0x5242C300 + 8)>; + mode-quiescent = <(0x5242C300 + 14)>; + + mode-winusb = <(0x5242C300 + 15)>; + }; + }; + + pmu1_grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf", "syscon"; + reg = <0x0 0xfd58a000 0x0 0x2000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + + rgb: rgb { + compatible = "rockchip,rk3588-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&bt1120_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp3: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp3_out_rgb>; + status = "disabled"; + }; + }; + }; + }; + }; + + bigcore0_grf: syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; + }; + + bigcore1_grf: syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + }; + + litcore_grf: syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf", "syscon"; + reg = <0x0 0xfd594000 0x0 0x100>; + }; + + dsu_grf: syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf", "syscon"; + reg = <0x0 0xfd598000 0x0 0x100>; + }; + + gpu_grf: syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf", "syscon"; + reg = <0x0 0xfd5a0000 0x0 0x100>; + }; + + npu_grf: syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf", "syscon"; + reg = <0x0 0xfd5a2000 0x0 0x100>; + }; + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&pclk_vo0_grf>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&pclk_vo1_grf>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + mipidphy0_grf: syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf", "syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + }; + + mipidphy1_grf: syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf", "syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = <0 393 4>; + resets = <&cru 786503>, <&cru 1160>; + reset-names = "phy", "apb"; + clocks = <&cru 693>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = <0 391 4>; + resets = <&cru 786505>, <&cru 1162>; + reset-names = "phy", "apb"; + clocks = <&cru 693>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = <0 392 4>; + resets = <&cru 786506>, <&cru 1163>; + reset-names = "phy", "apb"; + clocks = <&cru 693>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + + mipidcphy0_grf: syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf", "syscon"; + reg = <0x0 0xfd5e8000 0x0 0x4000>; + }; + + mipidcphy1_grf: syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf", "syscon"; + reg = <0x0 0xfd5ec000 0x0 0x4000>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <&php_grf>; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru 9>, <&cru 5>, + <&cru 8>, <&cru 7>, + <&cru 216>, + <&cru 218>, <&cru 217>, + <&cru 270>, <&cru 271>, + <&cru 272>, <&cru 665>, + <&cru 666>, + <&cru 123>, <&cru 236>, + <&cru 276>, <&cru 520>, + <&cru 526>, <&cru 543>, + <&cru 119>; + assigned-clock-rates = + <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <750000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, + <375000000>, <150000000>, + <200000000>, <12000000>, + <12000000>, <99000000>, + <20000000>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + clocks = <&cru 647>, <&cru 646>; + clock-names = "i2c", "pclk"; + interrupts = <0 317 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + resets = <&cru 786466>, <&cru 786465>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = <0 331 4>; + clocks = <&cru 686>, <&cru 687>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m1_xfer>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + interrupts = <0 344 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru 677>, <&cru 676>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + interrupts = <0 344 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru 677>, <&cru 676>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + interrupts = <0 344 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru 677>, <&cru 676>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + interrupts = <0 344 4>, + <0 345 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru 677>, <&cru 676>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + + power-domain@8 { + reg = <8>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@9 { + reg = <9>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 303>, + <&cru 305>, + <&cru 304>, + <&cru 294>; + pm_qos = <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + + power-domain@10 { + reg = <10>; + clocks = <&cru 303>, + <&cru 305>, + <&cru 304>; + pm_qos = <&qos_npu1>; + }; + power-domain@11 { + reg = <11>; + clocks = <&cru 303>, + <&cru 305>, + <&cru 304>; + pm_qos = <&qos_npu2>; + }; + }; + }; + + power-domain@12 { + reg = <12>; + clocks = <&cru 276>, + <&cru 277>, + <&cru 278>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + }; + + power-domain@13 { + reg = <13>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@14 { + reg = <14>; + clocks = <&cru 399>, + <&cru 446>, + <&cru 444>, + <&cru 400>, + <&cru 398>; + pm_qos = <&qos_rkvdec0>; + }; + power-domain@15 { + reg = <15>; + clocks = <&cru 404>, + <&cru 446>, + <&cru 444>, + <&cru 405>; + pm_qos = <&qos_rkvdec1>; + }; + power-domain@16 { + reg = <16>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 452>, + <&cru 453>; + pm_qos = <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + + power-domain@17 { + reg = <17>; + clocks = <&cru 457>, + <&cru 452>, + <&cru 453>, + <&cru 458>; + pm_qos = <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + }; + }; + }; + + power-domain@21 { + reg = <21>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 446>, + <&cru 445>, + <&cru 444>, + <&cru 447>, + <&cru 426>, + <&cru 425>, + <&cru 428>, + <&cru 429>, + <&cru 430>, + <&cru 431>, + <&cru 432>, + <&cru 433>, + <&cru 434>, + <&cru 435>, + <&cru 436>, + <&cru 437>, + <&cru 439>, + <&cru 438>; + pm_qos = <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + + power-domain@23 { + reg = <23>; + clocks = <&cru 75>, + <&cru 73>, + <&cru 446>; + pm_qos = <&qos_av1>; + }; + power-domain@14 { + reg = <14>; + clocks = <&cru 399>, + <&cru 446>, + <&cru 444>, + <&cru 400>; + pm_qos = <&qos_rkvdec0>; + }; + power-domain@15 { + reg = <15>; + clocks = <&cru 404>, + <&cru 446>, + <&cru 444>; + pm_qos = <&qos_rkvdec1>; + }; + power-domain@22 { + reg = <22>; + clocks = <&cru 442>, + <&cru 441>; + pm_qos = <&qos_rga3_0>; + }; + }; + power-domain@24 { + reg = <24>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 622>, + <&cru 621>, + <&cru 624>; + pm_qos = <&qos_vop_m0>, + <&qos_vop_m1>; + + power-domain@25 { + reg = <25>; + clocks = <&cru 502>, + <&cru 503>, + <&cru 501>, + <&cru 499>, + <&cru 494>, + <&cru 493>, + <&cru 621>; + pm_qos = <&qos_hdcp0>; + }; + }; + power-domain@26 { + reg = <26>; + clocks = <&cru 558>, + <&cru 559>, + <&cru 557>, + <&cru 536>, + <&cru 535>, + <&cru 555>, + <&cru 612>; + pm_qos = <&qos_hdcp1>, + <&qos_hdmirx>; + }; + power-domain@27 { + reg = <27>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 481>, + <&cru 482>, + <&cru 479>, + <&cru 478>, + <&cru 485>, + <&cru 484>; + pm_qos = <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + + power-domain@28 { + reg = <28>; + clocks = <&cru 289>, + <&cru 288>, + <&cru 481>, + <&cru 482>; + pm_qos = <&qos_isp1_mwo>, + <&qos_isp1_mro>; + }; + power-domain@29 { + reg = <29>; + clocks = <&cru 470>, + <&cru 469>, + <&cru 473>, + <&cru 472>, + <&cru 482>; + pm_qos = <&qos_fisheye0>, + <&qos_fisheye1>; + }; + }; + power-domain@30 { + reg = <30>; + clocks = <&cru 393>, + <&cru 394>; + pm_qos = <&qos_rga3_1>; + }; + power-domain@31 { + reg = <31>; + clocks = <&cru 358>, + <&cru 417>, + <&cru 420>, + <&cru 413>, + <&cru 414>, + <&cru 415>, + <&cru 416>; + pm_qos = <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + }; + power-domain@33 { + reg = <33>; + clocks = <&cru 358>, + <&cru 361>, + <&cru 362>; + }; + power-domain@34 { + reg = <34>; + clocks = <&cru 358>, + <&cru 361>, + <&cru 362>; + }; + power-domain@37 { + reg = <37>; + clocks = <&cru 409>, + <&cru 320>; + pm_qos = <&qos_sdio>; + }; + power-domain@38 { + reg = <38>; + clocks = <&cru 60>, + <&cru 61>; + }; + power-domain@40 { + reg = <40>; + pm_qos = <&qos_sdmmc>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x0 0xfda40000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@0 { + reg = <0>; + clocks = <&cru 710>, <&cru 21>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x0 0xfda50000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@1 { + reg = <1>; + clocks = <&cru 712>, <&cru 23>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x0 0xfda60000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@2 { + reg = <2>; + clocks = <&cru 714>, <&cru 27>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x0 0xfdaf0000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@3 { + reg = <3>; + clocks = <&cru 299>, <&cru 297>; + clock-names = "clk", "pclk"; + resets = <&cru 478>, <&cru 476>; + reset-names = "rts", "rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x0 0xfdb30000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@4 { + reg = <4>; + clocks = <&cru 280>; + clock-names = "clk"; + resets = <&cru 1072>, <&cru 1071>; + reset-names = "rts", "rst-p"; + }; + }; + + rknpu: npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x0 0xfdab0000 0x0 0x10000>, + <0x0 0xfdac0000 0x0 0x10000>, + <0x0 0xfdad0000 0x0 0x10000>; + interrupts = <0 110 4>, + <0 111 4>, + <0 112 4>; + interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; + clocks = <&scmi_clk 6>, <&cru 301>, + <&cru 290>, <&cru 292>, + <&cru 302>, <&cru 291>, + <&cru 293>, <&cru 305>; + clock-names = "clk_npu", "aclk0", + "aclk1", "aclk2", + "hclk0", "hclk1", + "hclk2", "pclk"; + assigned-clocks = <&scmi_clk 6>; + assigned-clock-rates = <200000000>; + resets = <&cru 486>, <&cru 432>, <&cru 448>, + <&cru 488>, <&cru 434>, <&cru 450>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2"; + power-domains = <&power 9>, + <&power 10>, + <&power 11>; + power-domain-names = "npu0", "npu1", "npu2"; + operating-points-v2 = <&npu_opp_table>; + iommus = <&rknpu_mmu>; + status = "disabled"; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 799 0 + 800 819 1 + 820 844 2 + 845 869 3 + 870 894 4 + 895 9999 5 + >; + rockchip,pvtm-voltage-sel = < + 0 815 0 + 816 835 1 + 836 860 2 + 861 885 3 + 886 910 4 + 911 9999 5 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x50>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <800000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <(-113) (-113)>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + + rockchip,opp-clocks = <&cru 298>, <&cru 303>; + rockchip,grf = <&npu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <500000>; + rockchip,init-freq = <1000000>; + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <800000>; + + + opp-300000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-400000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-500000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-700000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L3 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L2 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L3 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L4 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L5 = <700000 700000 850000>, + <700000 700000 850000>; + }; + opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <737500 737500 850000>, + <737500 737500 850000>; + }; + opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + + + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-950000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L1 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L2 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L3 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L4 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L5 = <775000 775000 850000>, + <775000 775000 850000>; + }; + }; + + rknpu_mmu: iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdab9000 0x0 0x100>, + <0x0 0xfdaba000 0x0 0x100>, + <0x0 0xfdaca000 0x0 0x100>, + <0x0 0xfdada000 0x0 0x100>; + interrupts = <0 110 4>, + <0 111 4>, + <0 112 4>; + interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu"; + clocks = <&cru 301>, <&cru 290>, <&cru 292>, + <&cru 302>, <&cru 291>, <&cru 293>; + clock-names = "aclk0", "aclk1", "aclk2", + "iface0", "iface1", "iface2"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu: vepu@fdb50000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xfdb50000 0x0 0x400>; + interrupts = <0 120 4>; + interrupt-names = "irq_vepu"; + clocks = <&cru 448>, <&cru 449>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 448>; + assigned-clock-rates = <594000000>; + resets = <&cru 712>, <&cru 713>; + reset-names = "shared_video_a", "shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&vdpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + power-domains = <&power 21>; + status = "disabled"; + }; + + vdpu: vdpu@fdb50400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xfdb50400 0x0 0x400>; + interrupts = <0 119 4>; + interrupt-names = "irq_vdpu"; + clocks = <&cru 448>, <&cru 449>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 448>; + assigned-clock-rates = <594000000>; + resets = <&cru 712>, <&cru 713>; + reset-names = "shared_video_a", "shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&vdpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + power-domains = <&power 21>; + status = "disabled"; + }; + + vdpu_mmu: iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb50800 0x0 0x40>; + interrupts = <0 118 4>; + interrupt-names = "irq_vdpu_mmu"; + clocks = <&cru 448>, <&cru 449>; + clock-names = "aclk", "iface"; + power-domains = <&power 21>; + #iommu-cells = <0>; + status = "disabled"; + }; + + avsd: avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xfdb51000 0x0 0x200>; + interrupts = <0 119 4>; + interrupt-names = "irq_avsd"; + clocks = <&cru 448>, <&cru 449>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 448>; + assigned-clock-rates = <594000000>; + resets = <&cru 712>, <&cru 713>; + reset-names = "shared_video_a", "shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&vdpu_mmu>; + power-domains = <&power 21>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rga3_core0"; + reg = <0x0 0xfdb60000 0x0 0x1000>; + interrupts = <0 114 4>; + interrupt-names = "rga3_core0_irq"; + clocks = <&cru 442>, <&cru 441>, <&cru 443>; + clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0"; + power-domains = <&power 22>; + iommus = <&rga3_0_mmu>; + status = "disabled"; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = <0 114 4>; + interrupt-names = "rga3_0_mmu"; + clocks = <&cru 442>, <&cru 441>; + clock-names = "aclk", "iface"; + power-domains = <&power 22>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rga3_core1"; + reg = <0x0 0xfdb70000 0x0 0x1000>; + interrupts = <0 115 4>; + interrupt-names = "rga3_core1_irq"; + clocks = <&cru 394>, <&cru 393>, <&cru 395>; + clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1"; + power-domains = <&power 30>; + iommus = <&rga3_1_mmu>; + status = "disabled"; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = <0 115 4>; + interrupt-names = "rga3_1_mmu"; + clocks = <&cru 394>, <&cru 393>; + clock-names = "aclk", "iface"; + power-domains = <&power 30>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga2: rga@fdb80000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xfdb80000 0x0 0x1000>; + interrupts = <0 116 4>; + interrupt-names = "rga2_irq"; + clocks = <&cru 439>, <&cru 438>, <&cru 440>; + clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; + power-domains = <&power 21>; + status = "disabled"; + }; + + jpegd: jpegd@fdb90000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xfdb90000 0x0 0x400>; + interrupts = <0 129 4>; + interrupt-names = "irq_jpegd"; + clocks = <&cru 436>, <&cru 437>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <600000000>, <0>; + assigned-clocks = <&cru 436>; + assigned-clock-rates = <600000000>; + resets = <&cru 722>, <&cru 723>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + power-domains = <&power 21>; + status = "disabled"; + }; + + jpegd_mmu: iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb90480 0x0 0x40>; + interrupts = <0 130 4>; + interrupt-names = "irq_jpegd_mmu"; + clocks = <&cru 436>, <&cru 437>; + clock-names = "aclk", "iface"; + power-domains = <&power 21>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege0: jpege-core@fdba0000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba0000 0x0 0x400>; + interrupts = <0 122 4>; + interrupt-names = "irq_jpege0"; + clocks = <&cru 428>, <&cru 429>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 428>; + assigned-clock-rates = <594000000>; + resets = <&cru 714>, <&cru 715>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege0_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power 21>; + status = "disabled"; + }; + + jpege0_mmu: iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = <0 121 4>; + interrupt-names = "irq_jpege0_mmu"; + clocks = <&cru 428>, <&cru 429>; + clock-names = "aclk", "iface"; + power-domains = <&power 21>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege1: jpege-core@fdba4000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba4000 0x0 0x400>; + interrupts = <0 124 4>; + interrupt-names = "irq_jpege1"; + clocks = <&cru 430>, <&cru 431>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 430>; + assigned-clock-rates = <594000000>; + resets = <&cru 716>, <&cru 717>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege1_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power 21>; + status = "disabled"; + }; + + jpege1_mmu: iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = <0 123 4>; + interrupt-names = "irq_jpege1_mmu"; + clocks = <&cru 430>, <&cru 431>; + clock-names = "aclk", "iface"; + power-domains = <&power 21>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege2: jpege-core@fdba8000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba8000 0x0 0x400>; + interrupts = <0 126 4>; + interrupt-names = "irq_jpege2"; + clocks = <&cru 432>, <&cru 433>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 432>; + assigned-clock-rates = <594000000>; + resets = <&cru 718>, <&cru 719>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege2_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power 21>; + status = "disabled"; + }; + + jpege2_mmu: iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = <0 125 4>; + interrupt-names = "irq_jpege2_mmu"; + clocks = <&cru 432>, <&cru 433>; + clock-names = "aclk", "iface"; + power-domains = <&power 21>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege3: jpege-core@fdbac000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdbac000 0x0 0x400>; + interrupts = <0 128 4>; + interrupt-names = "irq_jpege3"; + clocks = <&cru 434>, <&cru 435>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 434>; + assigned-clock-rates = <594000000>; + resets = <&cru 720>, <&cru 721>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege3_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power 21>; + status = "disabled"; + }; + + jpege3_mmu: iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = <0 127 4>; + interrupt-names = "irq_jpege3_mmu"; + clocks = <&cru 434>, <&cru 435>; + clock-names = "aclk", "iface"; + power-domains = <&power 21>; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep: iep@fdbb0000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xfdbb0000 0x0 0x500>; + interrupts = <0 117 4>; + interrupt-names = "irq_iep"; + clocks = <&cru 426>, <&cru 425>, <&cru 427>; + clock-names = "aclk", "hclk", "sclk"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru 426>; + assigned-clock-rates = <594000000>; + resets = <&cru 725>, <&cru 724>, <&cru 726>; + reset-names = "rst_a", "rst_h", "rst_s"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + power-domains = <&power 21>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <6>; + iommus = <&iep_mmu>; + status = "disabled"; + }; + + iep_mmu: iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbb0800 0x0 0x100>; + interrupts = <0 117 4>; + interrupt-names = "irq_iep_mmu"; + clocks = <&cru 426>, <&cru 425>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power 21>; + status = "disabled"; + }; + + rkvenc0: rkvenc-core@fdbd0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbd0000 0x0 0x6000>; + interrupts = <0 101 4>; + interrupt-names = "irq_rkvenc0"; + clocks = <&cru 453>, <&cru 452>, <&cru 454>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <500000000>, <0>, <800000000>; + assigned-clocks = <&cru 453>, <&cru 454>; + assigned-clock-rates = <500000000>, <800000000>; + resets = <&cru 757>, <&cru 756>, <&cru 758>; + reset-names = "video_a", "video_h", "video_core"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvenc0_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvenc_ccu>; + rockchip,taskqueue-node = <7>; + rockchip,task-capacity = <8>; + power-domains = <&power 16>; + operating-points-v2 = <&venc_opp_table>; + status = "disabled"; + }; + + rkvenc0_mmu: iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; + interrupts = <0 99 4>, + <0 100 4>; + interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; + clocks = <&cru 453>, <&cru 452>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0>; + power-domains = <&power 16>; + status = "disabled"; + }; + + rkvenc1: rkvenc-core@fdbe0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbe0000 0x0 0x6000>; + interrupts = <0 104 4>; + interrupt-names = "irq_rkvenc1"; + clocks = <&cru 458>, <&cru 457>, <&cru 459>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <500000000>, <0>, <800000000>; + assigned-clocks = <&cru 458>, <&cru 459>; + assigned-clock-rates = <500000000>, <800000000>; + resets = <&cru 773>, <&cru 772>, <&cru 774>; + reset-names = "video_a", "video_h", "video_core"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvenc1_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvenc_ccu>; + rockchip,taskqueue-node = <7>; + rockchip,task-capacity = <8>; + power-domains = <&power 17>; + operating-points-v2 = <&venc_opp_table>; + status = "disabled"; + }; + + rkvenc1_mmu: iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; + interrupts = <0 102 4>, + <0 103 4>; + interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; + clocks = <&cru 458>, <&cru 457>; + lock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0>; + power-domains = <&power 17>; + status = "disabled"; + }; + + venc_opp_table: venc-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&codec_leakage>, <&venc_opp_info>; + nvmem-cell-names = "leakage", "opp-info"; + rockchip,leakage-voltage-sel = < + 1 15 0 + 16 25 1 + 26 254 2 + >; + + rockchip,grf = <&sys_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L0 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <750000 750000 850000>, + <750000 750000 850000>; + }; + }; + + rkvdec_ccu: rkvdec-ccu@fdc30000 { + compatible = "rockchip,rkv-decoder-v2-ccu"; + reg = <0x0 0xfdc30000 0x0 0x100>; + reg-names = "ccu"; + clocks = <&cru 398>; + clock-names = "aclk_ccu"; + assigned-clocks = <&cru 398>; + assigned-clock-rates = <600000000>; + resets = <&cru 642>; + reset-names = "video_ccu"; + rockchip,skip-pmu-idle-request; + + rockchip,ccu-mode = <1>; + power-domains = <&power 14>; + status = "disabled"; + }; + + rkvdec0: rkvdec-core@fdc38000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = <0 95 4>; + interrupt-names = "irq_rkvdec0"; + clocks = <&cru 400>, <&cru 399>, <&cru 403>, + <&cru 401>, <&cru 402>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", + "clk_cabac", "clk_hevc_cabac"; + rockchip,normal-rates = <800000000>, <0>, <600000000>, + <600000000>, <1000000000>; + assigned-clocks = <&cru 400>, <&cru 403>, + <&cru 401>, <&cru 402>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + resets = <&cru 644>, <&cru 643>, <&cru 649>, + <&cru 647>, <&cru 648>; + reset-names = "video_a", "video_h", "video_core", + "video_cabac", "video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvdec0_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvdec_ccu>; + rockchip,core-mask = <0x00010001>; + rockchip,task-capacity = <16>; + rockchip,taskqueue-node = <9>; + rockchip,sram = <&rkvdec0_sram>; + + rockchip,rcb-iova = <0xFFF00000 0x100000>; + rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>, + <139 180224>, <133 49152>, <134 8192>, <135 4352>, + <138 13056>, <142 291584>; + rockchip,rcb-min-width = <512>; + power-domains = <&power 14>; + status = "disabled"; + }; + + rkvdec0_mmu: iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts = <0 96 4>; + interrupt-names = "irq_rkvdec0_mmu"; + clocks = <&cru 400>, <&cru 399>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0>; + power-domains = <&power 14>; + status = "disabled"; + }; + + rkvdec1: rkvdec-core@fdc48000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = <0 97 4>; + interrupt-names = "irq_rkvdec1"; + clocks = <&cru 405>, <&cru 404>, <&cru 408>, + <&cru 406>, <&cru 407>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", + "clk_cabac", "clk_hevc_cabac"; + rockchip,normal-rates = <800000000>, <0>, <600000000>, + <600000000>, <1000000000>; + assigned-clocks = <&cru 405>, <&cru 408>, + <&cru 406>, <&cru 407>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + resets = <&cru 659>, <&cru 658>, <&cru 664>, + <&cru 662>, <&cru 663>; + reset-names = "video_a", "video_h", "video_core", + "video_cabac", "video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvdec1_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvdec_ccu>; + rockchip,core-mask = <0x00020002>; + rockchip,task-capacity = <16>; + rockchip,taskqueue-node = <9>; + rockchip,sram = <&rkvdec1_sram>; + + rockchip,rcb-iova = <0xFFE00000 0x100000>; + rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>, + <139 180224>, <133 49152>, <134 8192>, <135 4352>, + <138 13056>, <142 291584>; + rockchip,rcb-min-width = <512>; + power-domains = <&power 15>; + status = "disabled"; + }; + + rkvdec1_mmu: iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; + interrupts = <0 98 4>; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <&cru 405>, <&cru 404>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0>; + power-domains = <&power 15>; + status = "disabled"; + }; + + av1d: av1d@fdc70000 { + compatible = "rockchip,av1-decoder"; + reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>, + <0x0 0xfdc90000 0x0 0x400>; + reg-names = "vcd", "cache", "afbc"; + interrupts = <0 108 4>, <0 107 4>, + <0 106 4>; + interrupt-names = "irq_av1d", "irq_cache", "irq_afbc"; + clocks = <&cru 73>, <&cru 75>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <400000000>, <400000000>; + assigned-clocks = <&cru 73>, <&cru 75>; + assigned-clock-rates = <400000000>, <400000000>; + resets = <&cru 1090>, <&cru 1093>; + reset-names = "video_a", "video_h"; + iommus = <&av1d_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <11>; + power-domains = <&power 23>; + status = "disabled"; + }; + + av1d_mmu: iommu@fdca0000 { + compatible = "rockchip,iommu-av1"; + reg = <0x0 0xfdca0000 0x0 0x600>; + interrupts = <0 109 4>; + interrupt-names = "irq_av1d_mmu"; + clocks = <&cru 73>, <&cru 75>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power 23>; + status = "disabled"; + }; + + rkisp_unite: rkisp-unite@fdcb0000 { + compatible = "rockchip,rk3588-rkisp-unite"; + reg = <0x0 0xfdcb0000 0x0 0x10000>, + <0x0 0xfdcc0000 0x0 0x10000>; + interrupts = <0 135 4>, + <0 137 4>, + <0 138 4>; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru 478>, <&cru 479>, + <&cru 475>, <&cru 476>, + <&cru 477>, <&cru 288>, + <&cru 289>, <&cru 285>, + <&cru 286>, <&cru 287>; + clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0", + "clk_isp_core_marvin0", "clk_isp_core_vicap0", + "aclk_isp1", "hclk_isp1", "clk_isp_core1", + "clk_isp_core_marvin1", "clk_isp_core_vicap1"; + power-domains = <&power 28>; + iommus = <&rkisp_unite_mmu>; + status = "disabled"; + }; + + rkisp0: rkisp@fdcb0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x0 0xfdcb0000 0x0 0x7f00>; + interrupts = <0 131 4>, + <0 133 4>, + <0 134 4>; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru 478>, <&cru 479>, + <&cru 475>, <&cru 476>, + <&cru 477>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", + "clk_isp_core_marvin", "clk_isp_core_vicap"; + power-domains = <&power 27>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + + rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>; + interrupts = <0 132 4>, + <0 136 4>; + interrupt-names = "isp0_mmu", "isp1_mmu"; + clocks = <&cru 478>, <&cru 479>, + <&cru 288>, <&cru 289>; + clock-names = "aclk0", "iface0", "aclk1", "iface1"; + power-domains = <&power 28>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + isp0_mmu: iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>; + interrupts = <0 132 4>; + interrupt-names = "isp0_mmu"; + clocks = <&cru 478>, <&cru 479>; + clock-names = "aclk", "iface"; + power-domains = <&power 27>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkisp1: rkisp@fdcc0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x0 0xfdcc0000 0x0 0x7f00>; + interrupts = <0 135 4>, + <0 137 4>, + <0 138 4>; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru 288>, <&cru 289>, + <&cru 285>, <&cru 286>, + <&cru 287>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", + "clk_isp_core_marvin", "clk_isp_core_vicap"; + power-domains = <&power 28>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + + isp1_mmu: iommu@fdcc7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcc7f00 0x0 0x100>; + interrupts = <0 136 4>; + interrupt-names = "isp1_mmu"; + clocks = <&cru 288>, <&cru 289>; + clock-names = "aclk", "iface"; + power-domains = <&power 28>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkispp0: rkispp@fdcd0000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x0 0xfdcd0000 0x0 0x0f00>; + interrupts = <0 139 4>; + interrupt-names = "fec_irq"; + clocks = <&cru 469>, <&cru 470>, + <&cru 471>; + clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; + assigned-clocks = <&cru 470>; + assigned-clock-rates = <100000000>; + power-domains = <&power 29>; + iommus = <&fec0_mmu>; + status = "disabled"; + }; + + fec0_mmu: iommu@fdcd0f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcd0f00 0x0 0x100>; + interrupts = <0 140 4>; + interrupt-names = "fec0_mmu"; + clocks = <&cru 469>, <&cru 470>, <&cru 471>; + clock-names = "aclk", "iface", "pclk"; + power-domains = <&power 29>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkispp1: rkispp@fdcd8000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x0 0xfdcd8000 0x0 0x0f00>; + interrupts = <0 141 4>; + interrupt-names = "fec_irq"; + clocks = <&cru 472>, <&cru 473>, + <&cru 474>; + clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; + assigned-clocks = <&cru 473>; + assigned-clock-rates = <100000000>; + power-domains = <&power 29>; + iommus = <&fec1_mmu>; + status = "disabled"; + }; + + fec1_mmu: iommu@fdcd8f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcd8f00 0x0 0x100>; + interrupts = <0 142 4>; + interrupt-names = "fec1_mmu"; + clocks = <&cru 472>, <&cru 473>, <&cru 474>; + clock-names = "aclk", "iface", "pclk"; + power-domains = <&power 29>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkcif: rkcif@fdce0000 { + compatible = "rockchip,rk3588-cif"; + reg = <0x0 0xfdce0000 0x0 0x800>; + reg-names = "cif_regs"; + interrupts = <0 155 4>; + interrupt-names = "cif-intr"; + clocks = <&cru 484>, <&cru 485>, <&cru 483>, + <&cru 461>, <&cru 462>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif", + "iclk_host0", "iclk_host1"; + resets = <&cru 791>, <&cru 792>, <&cru 790>, + <&cru 820>, <&cru 821>, + <&cru 822>, <&cru 823>, + <&cru 824>, <&cru 825>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", + "rst_cif_host0", "rst_cif_host1", "rst_cif_host2", + "rst_cif_host3", "rst_cif_host4", "rst_cif_host5"; + assigned-clocks = <&cru 483>; + assigned-clock-rates = <600000000>; + power-domains = <&power 27>; + rockchip,grf = <&sys_grf>; + iommus = <&rkcif_mmu>; + nvmem-cells = <&specification_serial_number>, + <&package_serial_number_low>, + <&package_serial_number_high>; + nvmem-cell-names = "specification", + "package_low", + "package_high"; + status = "disabled"; + }; + + rkcif_mmu: iommu@fdce0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdce0800 0x0 0x100>, + <0x0 0xfdce0900 0x0 0x100>; + interrupts = <0 113 4>; + interrupt-names = "cif_mmu"; + clocks = <&cru 484>, <&cru 485>; + clock-names = "aclk", "iface"; + power-domains = <&power 27>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi0_csi2_hw: mipi0-csi2-hw@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd10000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0 143 4>, + <0 144 4>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru 463>; + clock-names = "pclk_csi2host"; + resets = <&cru 804>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi1_csi2_hw: mipi1-csi2-hw@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd20000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0 145 4>, + <0 146 4>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru 464>; + clock-names = "pclk_csi2host"; + resets = <&cru 805>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi2_csi2_hw: mipi2-csi2-hw@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd30000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0 147 4>, + <0 148 4>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru 465>; + clock-names = "pclk_csi2host"; + resets = <&cru 806>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi3_csi2_hw: mipi3-csi2-hw@fdd40000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd40000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0 149 4>, + <0 150 4>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru 466>; + clock-names = "pclk_csi2host"; + resets = <&cru 807>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi4_csi2_hw: mipi4-csi2-hw@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd50000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0 151 4>, + <0 152 4>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru 467>; + clock-names = "pclk_csi2host"; + resets = <&cru 808>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi5_csi2_hw: mipi5-csi2-hw@fdd60000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd60000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = <0 153 4>, + <0 154 4>; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru 468>; + clock-names = "pclk_csi2host"; + resets = <&cru 809>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "regs", "gamma_lut"; + interrupts = <0 156 4>; + clocks = <&cru 624>, + <&cru 623>, + <&cru 628>, + <&cru 629>, + <&cru 630>, + <&cru 631>, + <&cru 622>, + <&cru 625>, + <&cru 626>, + <&cru 627>; + clock-names = "aclk_vop", + "hclk_vop", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "dclk_src_vp0", + "dclk_src_vp1", + "dclk_src_vp2"; + assigned-clocks = <&cru 624>; + assigned-clock-rates = <750000000>; + resets = <&cru 841>, + <&cru 840>, + <&cru 845>, + <&cru 848>, + <&cru 849>, + <&cru 850>; + reset-names = "axi", + "ahb", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3"; + iommus = <&vop_mmu>; + power-domains = <&power 24>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_dp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dp0_in_vp0>; + }; + + vp0_out_edp0: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp0_in_vp0>; + }; + + vp0_out_hdmi0: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_dp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dp0_in_vp1>; + }; + + vp1_out_edp0: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp0_in_vp1>; + }; + + vp1_out_hdmi0: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi0_in_vp1>; + }; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + assigned-clocks = <&cru 627>; + assigned-clock-parents = <&cru 4>; + + vp2_out_dp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dp0_in_vp2>; + }; + + vp2_out_edp0: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp0_in_vp2>; + }; + + vp2_out_hdmi0: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi0_in_vp2>; + }; + + vp2_out_dsi0: endpoint@3 { + reg = <3>; + remote-endpoint = <&dsi0_in_vp2>; + }; + + vp2_out_dsi1: endpoint@4 { + reg = <4>; + remote-endpoint = <&dsi1_in_vp2>; + }; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + vp3_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp3>; + }; + + vp3_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp3>; + }; + + vp3_out_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&rgb_in_vp3>; + }; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = <0 156 4>; + interrupt-names = "vop_mmu"; + clocks = <&cru 624>, <&cru 623>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "disabled"; + }; + + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + interrupts = <0 195 4>; + dmas = <&dmac1 6>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru 521>, <&cru 516>; + assigned-clocks = <&cru 517>; + assigned-clock-parents = <&cru 5>; + power-domains = <&power 25>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = <0 184 4>; + clocks = <&cru 507>, <&cru 507>, <&cru 496>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 505>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power 25>; + resets = <&cru 909>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + interrupts = <0 196 4>; + dmas = <&dmac1 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru 599>, <&cru 595>; + assigned-clocks = <&cru 596>; + assigned-clock-parents = <&cru 5>; + power-domains = <&power 26>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = <0 185 4>; + clocks = <&cru 582>, <&cru 582>, <&cru 584>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 579>; + assigned-clock-parents = <&cru 7>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power 26>; + resets = <&cru 1000>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = <0 189 4>; + clocks = <&cru 578>, <&cru 578>, <&cru 574>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 575>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power 26>; + resets = <&cru 1043>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx0: spdif-rx@fde08000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde08000 0x0 0x1000>; + interrupts = <0 199 4>; + clocks = <&cru 606>, <&cru 605>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru 606>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac0 21>; + dma-names = "rx"; + power-domains = <&power 26>; + resets = <&cru 1021>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dsi0: dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = <0 167 4>; + clocks = <&cru 632>, <&cru 634>; + clock-names = "pclk", "sys_clk"; + resets = <&cru 852>; + reset-names = "apb"; + power-domains = <&power 24>; + phys = <&mipidcphy0>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in_vp2: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp2_out_dsi0>; + status = "disabled"; + }; + + dsi0_in_vp3: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp3_out_dsi0>; + status = "disabled"; + }; + }; + }; + }; + + dsi1: dsi@fde30000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde30000 0x0 0x10000>; + interrupts = <0 168 4>; + clocks = <&cru 633>, <&cru 635>; + clock-names = "pclk", "sys_clk"; + resets = <&cru 853>; + reset-names = "apb"; + power-domains = <&power 24>; + phys = <&mipidcphy1>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in_vp2: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp2_out_dsi1>; + status = "disabled"; + }; + + dsi1_in_vp3: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp3_out_dsi1>; + status = "disabled"; + }; + }; + }; + }; + + hdcp0: hdcp@fde40000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x0 0xfde40000 0x0 0x80>; + interrupts = <0 159 4>; + clocks = <&cru 493>, <&cru 495>, + <&cru 494>, <&cru 492>, + <&cru 497>, <&cru 498>; + clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng"; + resets = <&cru 895>, <&cru 893>, + <&cru 892>, <&cru 891>, + <&cru 897>; + reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng"; + power-domains = <&power 25>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + dp0: dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = <0 161 4>; + clocks = <&cru 486>, <&cru 716>, + <&cru 507>, <&cru 519>, + <&hclk_vo0>, <&cru 490>; + clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp"; + assigned-clocks = <&cru 716>; + assigned-clock-rates = <16000000>; + resets = <&cru 904>; + phys = <&usbdp_phy0_dp>; + power-domains = <&power 25>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dp0>; + status = "disabled"; + }; + + dp0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dp0>; + status = "disabled"; + }; + + dp0_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_dp0>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + dp0_out: endpoint { }; + }; + }; + }; + + hdcp1: hdcp@fde70000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x0 0xfde70000 0x0 0x80>; + interrupts = <0 160 4>; + clocks = <&cru 535>, <&cru 537>, + <&cru 536>, <&cru 534>, + <&cru 552>, <&cru 553>; + clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng"; + resets = <&cru 968>, <&cru 966>, + <&cru 965>, <&cru 964>, + <&cru 970>; + reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng"; + power-domains = <&power 26>; + rockchip,vo-grf = <&vo1_grf>; + status = "disabled"; + }; + + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfde80000 0x0 0x10000>, <0x0 0xfde90000 0x0 0x10000>; + interrupts = <0 169 4>, + <0 170 4>, + <0 171 4>, + <0 172 4>, + <0 360 4>; + clocks = <&cru 545>, + <&cru 613>, + <&cru 546>, + <&cru 547>, + <&cru 582>, + <&cru 628>, + <&cru 629>, + <&cru 630>, + <&cru 631>, + <&hclk_vo1>, + <&hdptxphy_hdmi_clk0>; + clock-names = "pclk", + "hpd", + "earc", + "hdmitx_ref", + "aud", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "hclk_vo1", + "link_clk"; + resets = <&cru 976>, <&cru 1180>; + reset-names = "ref", "hdp"; + power-domains = <&power 26>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; + reg-io-width = <4>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdptxphy_hdmi0>; + phy-names = "hdmi"; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi0>; + status = "disabled"; + }; + + hdmi0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi0>; + status = "disabled"; + }; + + hdmi0_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_hdmi0>; + status = "disabled"; + }; + }; + }; + }; + + edp0: edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfdec0000 0x0 0x1000>; + interrupts = <0 163 4>; + clocks = <&cru 529>, <&cru 528>, + <&cru 530>, <&hclk_vo1>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru 993>, <&cru 992>; + reset-names = "dp", "apb"; + phys = <&hdptxphy0>; + phy-names = "dp"; + power-domains = <&power 26>; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp0>; + status = "disabled"; + }; + + edp0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp0>; + status = "disabled"; + }; + + edp0_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_edp0>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + edp0_out: endpoint { }; + }; + }; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible = "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible = "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible = "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible = "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible = "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible = "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible = "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible = "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible = "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible = "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible = "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible = "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible = "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible = "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible = "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible = "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible = "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible = "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible = "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible = "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible = "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible = "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible = "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible = "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible = "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible = "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible = "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible = "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible = "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible = "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible = "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible = "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible = "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible = "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible = "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible = "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible = "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible = "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible = "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible = "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible = "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible = "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible = "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible = "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible = "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible = "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible = "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible = "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + + dfi: dfi@fe060000 { + compatible = "rockchip,rk3588-dfi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + rockchip,pmu_grf = <&pmu1_grf>; + status = "disabled"; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x3f>; + clocks = <&cru 337>, <&cru 342>, + <&cru 332>, <&cru 348>, + <&cru 353>, <&cru 709>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <0 248 4>, + <0 247 4>, + <0 246 4>, + <0 245 4>, + <0 244 4>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu 2>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 + 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 + 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 + 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0x0 0xfe180000 0x0 0x10000>, + <0xa 0x40c00000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru 528>, <&cru 543>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 245 1>; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru 338>, <&cru 343>, + <&cru 333>, <&cru 349>, + <&cru 354>, <&cru 386>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <0 253 4>, + <0 252 4>, + <0 251 4>, + <0 250 4>, + <0 249 4>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps 2>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 + 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 + 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 + 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe190000 0x0 0x10000>, + <0xa 0x41000000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru 529>, <&cru 544>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 250 1>; + }; + }; + + gmac_uio1: uio@fe1c0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + rockchip,ethernet = <&gmac1>; + status = "disabled"; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = <0 234 4>, + <0 233 4>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&php_grf>; + clocks = <&cru 324>, <&cru 325>, + <&cru 360>, <&cru 365>, + <&cru 323>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + resets = <&cru 523>; + reset-names = "stmmaceth"; + power-domains = <&power 33>; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + clocks = <&cru 369>, <&cru 366>, + <&cru 372>, <&cru 355>, + <&cru 382>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = <0 273 4>; + interrupt-names = "hostc"; + phys = <&combphy0_ps 1>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + clocks = <&cru 371>, <&cru 368>, + <&cru 374>, <&cru 357>, + <&cru 384>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = <0 275 4>; + interrupt-names = "hostc"; + phys = <&combphy2_psu 1>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = <0 206 4>; + clocks = <&cru 317>, <&cru 318>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru 317>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = <0 203 4>; + clocks = <&scmi_clk 23>, <&scmi_clk 9>, + <&cru 706>, <&cru 707>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power 40>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2d0000 0x0 0x4000>; + interrupts = <0 204 4>; + clocks = <&cru 409>, <&cru 410>, + <&cru 704>, <&cru 705>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power 37>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = <0 205 4>; + assigned-clocks = <&cru 315>, <&cru 316>, <&cru 314>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru 314>, <&cru 312>, + <&cru 313>, <&cru 315>, + <&cru 316>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru 502>, <&cru 500>, + <&cru 501>, <&cru 503>, + <&cru 504>; + reset-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + crypto: crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x0 0xfe370000 0x0 0x2000>; + interrupts = <0 209 4>; + clocks = <&scmi_clk 11>, <&scmi_clk 12>, + <&scmi_clk 20>, <&scmi_clk 21>; + clock-names = "aclk", "hclk", "sclk", "pka"; + resets = <&scmi_reset 15>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = <0 400 4>; + clocks = <&scmi_clk 12>; + clock-names = "hclk_trng"; + resets = <&scmi_reset 48>; + reset-names = "reset"; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = <0 180 4>; + clocks = <&cru 51>, <&cru 55>, <&cru 48>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 49>, <&cru 53>; + assigned-clock-parents = <&cru 5>, <&cru 5>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power 38>; + resets = <&cru 119>, <&cru 122>; + reset-names = "tx-m", "rx-m"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1>; + pinctrl-1 = <&i2s0_idle>; + pinctrl-2 = <&i2s0_lrck + &i2s0_sclk>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = <0 181 4>; + clocks = <&cru 652>, <&cru 656>, <&cru 648>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru 786474>, <&cru 786477>; + reset-names = "tx-m", "rx-m"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = <0 182 4>; + clocks = <&cru 39>, <&cru 34>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru 36>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power 38>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s2m1_sdi + &i2s2m1_sdo>; + pinctrl-1 = <&i2s2m1_idle>; + pinctrl-2 = <&i2s2m1_lrck + &i2s2m1_sclk>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = <0 183 4>; + clocks = <&cru 45>, <&cru 35>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru 42>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power 38>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s3_sdi + &i2s3_sdo>; + pinctrl-1 = <&i2s3_idle>; + pinctrl-2 = <&i2s3_lrck + &i2s3_sclk>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm0: pdm@fe4b0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4b0000 0x0 0x1000>; + clocks = <&cru 671>, <&cru 670>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac0 4>; + dma-names = "rx"; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdm0m0_sdi0 + &pdm0m0_sdi1 + &pdm0m0_sdi2 + &pdm0m0_sdi3>; + pinctrl-1 = <&pdm0m0_idle>; + pinctrl-2 = <&pdm0m0_clk + &pdm0m0_clk1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm1: pdm@fe4c0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4c0000 0x0 0x1000>; + clocks = <&cru 59>, <&cru 58>; + clock-names = "pdm_clk", "pdm_hclk"; + assigned-clocks = <&cru 59>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac1 4>; + dma-names = "rx"; + power-domains = <&power 38>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdm1m0_sdi0 + &pdm1m0_sdi1 + &pdm1m0_sdi2 + &pdm1m0_sdi3>; + pinctrl-1 = <&pdm1m0_idle>; + pinctrl-2 = <&pdm1m0_clk + &pdm1m0_clk1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + vad: vad@fe4d0000 { + compatible = "rockchip,rk3588-vad"; + reg = <0x0 0xfe4d0000 0x0 0x1000>; + reg-names = "vad"; + clocks = <&cru 672>; + clock-names = "hclk"; + interrupts = <0 202 4>; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + interrupts = <0 193 4>; + dmas = <&dmac0 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru 65>, <&cru 62>; + assigned-clocks = <&cru 63>; + assigned-clock-parents = <&cru 5>; + power-domains = <&power 38>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + interrupts = <0 194 4>; + dmas = <&dmac1 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru 71>, <&cru 68>; + assigned-clocks = <&cru 69>; + assigned-clock-parents = <&cru 5>; + power-domains = <&power 38>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + acdcdig_dsm: codec-digital@fe500000 { + compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; + reg = <0x0 0xfe500000 0x0 0x1000>; + clocks = <&cru 41>, <&cru 47>; + clock-names = "dac", "pclk"; + power-domains = <&power 38>; + resets = <&cru 132>; + reset-names = "reset" ; + rockchip,grf = <&sys_grf>; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&auddsm_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hwlock: hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0 0xfe5a0000 0 0x100>; + #hwlock-cells = <1>; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfe600000 0 0x10000>, + <0x0 0xfe680000 0 0x100000>; + interrupts = <1 9 4>; + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfe640000 0x0 0x20000>; + }; + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfe660000 0x0 0x20000>; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = <0 86 4>, + <0 87 4>; + clocks = <&cru 120>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = <0 88 4>, + <0 89 4>; + clocks = <&cru 121>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + can0: can@fea50000 { + compatible = "rockchip,can-2.0"; + reg = <0x0 0xfea50000 0x0 0x1000>; + interrupts = <0 341 4>; + clocks = <&cru 112>, <&cru 111>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru 185>, <&cru 184>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can1: can@fea60000 { + compatible = "rockchip,can-2.0"; + reg = <0x0 0xfea60000 0x0 0x1000>; + interrupts = <0 342 4>; + clocks = <&cru 114>, <&cru 113>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru 187>, <&cru 186>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can2: can@fea70000 { + compatible = "rockchip,can-2.0"; + reg = <0x0 0xfea70000 0x0 0x1000>; + interrupts = <0 343 4>; + clocks = <&cru 116>, <&cru 115>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru 189>, <&cru 188>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + hw_decompress: decompress@fea80000 { + compatible = "rockchip,hw-decompress"; + reg = <0x0 0xfea80000 0x0 0x1000>; + interrupts = <0 85 4>; + clocks = <&cru 117>, <&cru 119>, <&cru 118>; + clock-names = "aclk", "dclk", "pclk"; + resets = <&cru 280>; + reset-names = "dresetn"; + status = "disabled"; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru 141>, <&cru 133>; + clock-names = "i2c", "pclk"; + interrupts = <0 318 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + resets = <&cru 176>, <&cru 168>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru 142>, <&cru 134>; + clock-names = "i2c", "pclk"; + interrupts = <0 319 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + resets = <&cru 177>, <&cru 169>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru 143>, <&cru 135>; + clock-names = "i2c", "pclk"; + interrupts = <0 320 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + resets = <&cru 178>, <&cru 170>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru 144>, <&cru 136>; + clock-names = "i2c", "pclk"; + interrupts = <0 321 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + resets = <&cru 179>, <&cru 171>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru 145>, <&cru 137>; + clock-names = "i2c", "pclk"; + interrupts = <0 322 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + resets = <&cru 180>, <&cru 172>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rktimer: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = <0 289 4>; + clocks = <&cru 92>, <&cru 95>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru 108>, <&cru 107>; + clock-names = "tclk", "pclk"; + interrupts = <0 315 4>; + status = "disabled"; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = <0 326 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 163>, <&cru 158>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = <0 327 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 164>, <&cru 159>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = <0 328 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 165>, <&cru 160>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = <0 329 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 166>, <&cru 161>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + num-cs = <2>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = <0 332 4>; + clocks = <&cru 183>, <&cru 171>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = <0 333 4>; + clocks = <&cru 187>, <&cru 172>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = <0 334 4>; + clocks = <&cru 191>, <&cru 173>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = <0 335 4>; + clocks = <&cru 195>, <&cru 174>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 9>, <&dmac1 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = <0 336 4>; + clocks = <&cru 199>, <&cru 175>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 11>, <&dmac1 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = <0 337 4>; + clocks = <&cru 203>, <&cru 176>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 13>, <&dmac1 14>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = <0 338 4>; + clocks = <&cru 207>, <&cru 177>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 7>, <&dmac2 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = <0 339 4>; + clocks = <&cru 211>, <&cru 178>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 9>, <&dmac2 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = <0 340 4>; + clocks = <&cru 215>, <&cru 179>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 11>, <&dmac2 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + interrupts = <0 346 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru 84>, <&cru 83>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + interrupts = <0 346 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru 84>, <&cru 83>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + interrupts = <0 346 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru 84>, <&cru 83>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + interrupts = <0 346 4>, + <0 347 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru 84>, <&cru 83>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + interrupts = <0 348 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru 87>, <&cru 86>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + interrupts = <0 348 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru 87>, <&cru 86>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + interrupts = <0 348 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru 87>, <&cru 86>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + interrupts = <0 348 4>, + <0 349 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru 87>, <&cru 86>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + interrupts = <0 350 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru 90>, <&cru 89>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + interrupts = <0 350 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru 90>, <&cru 89>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + interrupts = <0 350 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru 90>, <&cru 89>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + interrupts = <0 350 4>, + <0 351 4>; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru 90>, <&cru 89>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = <0 397 4>; + clocks = <&cru 170>, <&cru 169>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru 170>; + assigned-clock-rates = <2000000>; + resets = <&cru 193>, <&cru 192>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + status = "disabled"; + }; + + saradc: saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = <0 398 4>; + #io-channel-cells = <1>; + clocks = <&cru 157>, <&cru 156>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru 190>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + mailbox0: mailbox@fec60000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfec60000 0x0 0x200>; + interrupts = <0 61 4>, + <0 62 4>, + <0 63 4>, + <0 64 4>; + clocks = <&cru 76>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox1: mailbox@fec70000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfec70000 0x0 0x200>; + interrupts = <0 69 4>, + <0 70 4>, + <0 71 4>, + <0 72 4>; + clocks = <&cru 77>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru 146>, <&cru 138>; + clock-names = "i2c", "pclk"; + interrupts = <0 323 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + resets = <&cru 181>, <&cru 173>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru 147>, <&cru 139>; + clock-names = "i2c", "pclk"; + interrupts = <0 324 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + resets = <&cru 182>, <&cru 174>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru 148>, <&cru 140>; + clock-names = "i2c", "pclk"; + interrupts = <0 325 4>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m0_xfer>; + resets = <&cru 183>, <&cru 175>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = <0 330 4>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru 167>, <&cru 162>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + otp: otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru 150>, <&cru 149>, + <&cru 151>, <&cru 153>; + clock-names = "otpc", "apb", "arb", "phy"; + resets = <&cru 298>, <&cru 297>, + <&cru 299>; + reset-names = "otpc", "apb", "arb"; + + + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + package_serial_number_high: package-serial-number-high@5 { + reg = <0x05 0x1>; + bits = <0 1>; + }; + package_serial_number_low: package-serial-number-low@6 { + reg = <0x06 0x1>; + bits = <5 3>; + }; + specification_serial_number: specification-serial-number@6 { + reg = <0x06 0x1>; + bits = <0 5>; + }; + otp_id: id@7 { + reg = <0x07 0x10>; + }; + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + cpub0_leakage: cpub0-leakage@17 { + reg = <0x17 0x1>; + }; + cpub1_leakage: cpub1-leakage@18 { + reg = <0x18 0x1>; + }; + cpul_leakage: cpul-leakage@19 { + reg = <0x19 0x1>; + }; + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + cpul_opp_info: cpul-opp-info@3d { + reg = <0x3d 0x6>; + }; + cpub01_opp_info: cpub01-opp-info@43 { + reg = <0x43 0x6>; + }; + cpub23_opp_info: cpub23-opp-info@49 { + reg = <0x49 0x6>; + }; + gpu_opp_info: gpu-opp-info@4f { + reg = <0x4f 0x6>; + }; + npu_opp_info: npu-opp-info@55 { + reg = <0x55 0x6>; + }; + dmc_opp_info: dmc-opp-info@5b { + reg = <0x5b 0x6>; + }; + vop_opp_info: vop-opp-info@61 { + reg = <0x61 0x6>; + }; + venc_opp_info: venc-opp-info@67 { + reg = <0x67 0x6>; + }; + }; + + mailbox2: mailbox@fece0000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfece0000 0x0 0x200>; + interrupts = <0 77 4>, + <0 78 4>, + <0 79 4>, + <0 80 4>; + clocks = <&cru 78>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = <0 90 4>, + <0 91 4>; + clocks = <&cru 122>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru 693>, <&cru 615>; + clock-names = "ref", "apb"; + resets = <&cru 1157>, <&cru 786491>, + <&cru 786492>, <&cru 786493>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy0_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdptxphy_hdmi0: hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru 693>, <&cru 615>; + clock-names = "ref", "apb"; + resets = <&cru 1166>, <&cru 1157>, + <&cru 786491>, <&cru 786492>, + <&cru 786493>, <&cru 1164>, + <&cru 1165>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + #phy-cells = <0>; + status = "disabled"; + + hdptxphy_hdmi_clk0: clk-port { + #clock-cells = <0>; + status = "okay"; + }; + }; + + hdptxphy_hdmi1: hdmiphy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru 693>, <&cru 616>; + clock-names = "ref", "apb"; + resets = <&cru 1169>, <&cru 1158>, + <&cru 786495>, <&cru 786496>, + <&cru 786497>, <&cru 1167>, + <&cru 1168>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + + hdptxphy_hdmi_clk1: clk-port { + #clock-cells = <0>; + status = "okay"; + }; + }; + + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru 694>, + <&cru 639>, + <&cru 617>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru 40>, + <&cru 41>, + <&cru 42>, + <&cru 43>, + <&cru 1154>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0_u3: u3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + mipidcphy0: phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy0_grf>; + clocks = <&cru 264>, + <&cru 694>; + clock-names = "pclk", "ref"; + resets = <&cru 786499>, + <&cru 62>, + <&cru 63>, + <&cru 786500>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <0>; + status = "okay"; + }; + + mipidcphy1: phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfedb0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy1_grf>; + clocks = <&cru 265>, + <&cru 694>; + clock-names = "pclk", "ref"; + resets = <&cru 786501>, + <&cru 67>, + <&cru 68>, + <&cru 786502>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <0>; + status = "okay"; + }; + + csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <&cru 268>; + clock-names = "pclk"; + resets = <&cru 23>, <&cru 22>; + reset-names = "srst_csiphy0", "srst_p_csiphy0"; + rockchip,grf = <&mipidphy0_grf>; + rockchip,sys_grf = <&sys_grf>; + status = "okay"; + }; + + csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc8000 0x0 0x8000>; + clocks = <&cru 269>; + clock-names = "pclk"; + resets = <&cru 25>, <&cru 24>; + reset-names = "srst_csiphy1", "srst_p_csiphy1"; + rockchip,grf = <&mipidphy1_grf>; + rockchip,sys_grf = <&sys_grf>; + status = "okay"; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru 701>, <&cru 389>, + <&cru 358>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru 701>; + assigned-clock-rates = <100000000>; + resets = <&cru 131077>, <&cru 1238>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru 703>, <&cru 391>, + <&cru 358>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru 703>; + assigned-clock-rates = <100000000>; + resets = <&cru 131079>, <&cru 1240>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; + status = "disabled"; + }; + + syssram: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff001000 0xef000>; + + rkvdec0_sram: rkvdec-sram@0 { + reg = <0x0 0x78000>; + }; + rkvdec1_sram: rkvdec-sram@78000 { + reg = <0x78000 0x77000>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = <0 277 4>; + clocks = <&cru 644>, <&cru 645>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = <0 278 4>; + clocks = <&cru 125>, <&cru 126>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = <0 279 4>; + clocks = <&cru 127>, <&cru 128>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = <0 280 4>; + clocks = <&cru 129>, <&cru 130>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = <0 281 4>; + clocks = <&cru 131>, <&cru 132>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi" 1 + + + + + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1 +# 7 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinconf.dtsi" 1 + + + + + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <1>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <2>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <3>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <4>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <5>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6_smt: pcfg-pull-none-drv-level-6-smt { + bias-disable; + drive-strength = <6>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_up: pcfg-output-high-pull-up { + output-high; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_down: pcfg-output-high-pull-down { + output-high; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_none: pcfg-output-high-pull-none { + output-high; + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_up: pcfg-output-low-pull-up { + output-low; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_down: pcfg-output-low-pull-down { + output-low; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_none: pcfg-output-low-pull-none { + output-low; + bias-disable; + }; +}; +# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi" 2 + + + + + +&pinctrl { + auddsm { + /omit-if-no-ref/ + auddsm_pins: auddsm-pins { + rockchip,pins = + + <3 1 4 &pcfg_pull_none>, + + <3 2 4 &pcfg_pull_none>, + + <3 3 4 &pcfg_pull_none>, + + <3 4 4 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + + <4 8 2 &pcfg_pull_none>, + + <4 0 2 &pcfg_pull_none>, + + <4 1 2 &pcfg_pull_none>, + + <4 2 2 &pcfg_pull_none>, + + <4 3 2 &pcfg_pull_none>, + + <4 4 2 &pcfg_pull_none>, + + <4 5 2 &pcfg_pull_none>, + + <4 6 2 &pcfg_pull_none>, + + <4 7 2 &pcfg_pull_none>, + + <4 10 2 &pcfg_pull_none>, + + <4 11 2 &pcfg_pull_none>, + + <4 12 2 &pcfg_pull_none>, + + <4 13 2 &pcfg_pull_none>, + + <4 14 2 &pcfg_pull_none>, + + <4 15 2 &pcfg_pull_none>, + + <4 16 2 &pcfg_pull_none>, + + <4 17 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + + <0 16 11 &pcfg_pull_none>, + + <0 15 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + + <4 29 9 &pcfg_pull_none>, + + <4 28 9 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + + <3 13 9 &pcfg_pull_none>, + + <3 14 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + + <4 10 12 &pcfg_pull_none>, + + <4 11 12 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + + <3 20 9 &pcfg_pull_none>, + + <3 21 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + + <0 28 10 &pcfg_pull_none>, + + <0 29 10 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + + <4 12 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + + <4 8 1 &pcfg_pull_none>, + + <4 10 1 &pcfg_pull_none>, + + <4 11 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + + <3 20 1 &pcfg_pull_none>, + + <3 21 1 &pcfg_pull_none>, + + <3 22 1 &pcfg_pull_none>, + + <3 23 1 &pcfg_pull_none>, + + <3 24 1 &pcfg_pull_none>, + + <3 25 1 &pcfg_pull_none>, + + <3 26 1 &pcfg_pull_none>, + + <3 27 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + + <4 0 1 &pcfg_pull_none>, + + <4 1 1 &pcfg_pull_none>, + + <4 2 1 &pcfg_pull_none>, + + <4 3 1 &pcfg_pull_none>, + + <4 4 1 &pcfg_pull_none>, + + <4 5 1 &pcfg_pull_none>, + + <4 6 1 &pcfg_pull_none>, + + <4 7 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + + <0 10 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + + <0 10 2 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + + <0 25 2 &pcfg_pull_none>, + + <0 29 2 &pcfg_pull_none>; + }; + }; + + ddrphych0 { + /omit-if-no-ref/ + ddrphych0_pins: ddrphych0-pins { + rockchip,pins = + + <4 0 7 &pcfg_pull_none>, + + <4 1 7 &pcfg_pull_none>, + + <4 2 7 &pcfg_pull_none>, + + <4 3 7 &pcfg_pull_none>; + }; + }; + + ddrphych1 { + /omit-if-no-ref/ + ddrphych1_pins: ddrphych1-pins { + rockchip,pins = + + <4 4 7 &pcfg_pull_none>, + + <4 5 7 &pcfg_pull_none>, + + <4 6 7 &pcfg_pull_none>, + + <4 7 7 &pcfg_pull_none>; + }; + }; + + ddrphych2 { + /omit-if-no-ref/ + ddrphych2_pins: ddrphych2-pins { + rockchip,pins = + + <4 8 7 &pcfg_pull_none>, + + <4 9 7 &pcfg_pull_none>, + + <4 10 7 &pcfg_pull_none>, + + <4 11 7 &pcfg_pull_none>; + }; + }; + + ddrphych3 { + /omit-if-no-ref/ + ddrphych3_pins: ddrphych3-pins { + rockchip,pins = + + <4 12 7 &pcfg_pull_none>, + + <4 13 7 &pcfg_pull_none>, + + <4 14 7 &pcfg_pull_none>, + + <4 15 7 &pcfg_pull_none>; + }; + }; + + dp0 { + /omit-if-no-ref/ + dp0m0_pins: dp0m0-pins { + rockchip,pins = + + <4 12 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m1_pins: dp0m1-pins { + rockchip,pins = + + <0 20 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m2_pins: dp0m2-pins { + rockchip,pins = + + <1 0 5 &pcfg_pull_none>; + }; + }; + + dp1 { + /omit-if-no-ref/ + dp1m0_pins: dp1m0-pins { + rockchip,pins = + + <3 29 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m1_pins: dp1m1-pins { + rockchip,pins = + + <0 21 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m2_pins: dp1m2-pins { + rockchip,pins = + + <1 1 5 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + + <2 3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + + <2 24 1 &pcfg_pull_up_drv_level_2>, + + <2 25 1 &pcfg_pull_up_drv_level_2>, + + <2 26 1 &pcfg_pull_up_drv_level_2>, + + <2 27 1 &pcfg_pull_up_drv_level_2>, + + <2 28 1 &pcfg_pull_up_drv_level_2>, + + <2 29 1 &pcfg_pull_up_drv_level_2>, + + <2 30 1 &pcfg_pull_up_drv_level_2>, + + <2 31 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + + <2 1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + + <2 0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = + + <2 2 1 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1_pins: eth1-pins { + rockchip,pins = + + <3 6 1 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspim0_pins: fspim0-pins { + rockchip,pins = + + <2 0 2 &pcfg_pull_up_drv_level_2>, + + <2 30 2 &pcfg_pull_up_drv_level_2>, + + <2 24 2 &pcfg_pull_up_drv_level_2>, + + <2 25 2 &pcfg_pull_up_drv_level_2>, + + <2 26 2 &pcfg_pull_up_drv_level_2>, + + <2 27 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim0_cs1: fspim0-cs1 { + rockchip,pins = + + <2 31 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_pins: fspim2-pins { + rockchip,pins = + + <3 5 5 &pcfg_pull_up_drv_level_2>, + + <3 20 2 &pcfg_pull_up_drv_level_2>, + + <3 0 5 &pcfg_pull_up_drv_level_2>, + + <3 1 5 &pcfg_pull_up_drv_level_2>, + + <3 2 5 &pcfg_pull_up_drv_level_2>, + + <3 3 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_cs1: fspim2-cs1 { + rockchip,pins = + + <3 21 2 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1_miim: gmac1-miim { + rockchip,pins = + + <3 18 1 &pcfg_pull_none>, + + <3 19 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_clkinout: gmac1-clkinout { + rockchip,pins = + + <3 14 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rx_bus2: gmac1-rx-bus2 { + rockchip,pins = + + <3 7 1 &pcfg_pull_none>, + + <3 8 1 &pcfg_pull_none>, + + <3 9 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_tx_bus2: gmac1-tx-bus2 { + rockchip,pins = + + <3 11 1 &pcfg_pull_none>, + + <3 12 1 &pcfg_pull_none>, + + <3 13 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_clk: gmac1-rgmii-clk { + rockchip,pins = + + <3 5 1 &pcfg_pull_none>, + + <3 4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_bus: gmac1-rgmii-bus { + rockchip,pins = + + <3 2 1 &pcfg_pull_none>, + + <3 3 1 &pcfg_pull_none>, + + <3 0 1 &pcfg_pull_none>, + + <3 1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppsclk: gmac1-ppsclk { + rockchip,pins = + + <3 17 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppstrig: gmac1-ppstrig { + rockchip,pins = + + <3 16 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { + rockchip,pins = + + <3 15 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_txer: gmac1-txer { + rockchip,pins = + + <3 10 1 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + + <0 21 2 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_rx_cec: hdmim0-rx-cec { + rockchip,pins = + + <4 13 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_hpdin: hdmim0-rx-hpdin { + rockchip,pins = + + <4 14 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_scl: hdmim0-rx-scl { + rockchip,pins = + + <0 26 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_sda: hdmim0-rx-sda { + rockchip,pins = + + <0 25 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins = + + <4 17 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins = + + <1 5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins = + + <4 15 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins = + + <4 16 5 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_hpd: hdmim0-tx1-hpd { + rockchip,pins = + + <1 6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx: hdmim1-rx { + rockchip,pins = + + <3 25 5 &pcfg_pull_none>, + + <3 26 5 &pcfg_pull_none_smt>, + + <3 27 5 &pcfg_pull_none_smt>, + + <3 28 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_cec: hdmim1-rx-cec { + rockchip,pins = + + <3 25 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_hpdin: hdmim1-rx-hpdin { + rockchip,pins = + + <3 28 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_scl: hdmim1-rx-scl { + rockchip,pins = + + <3 26 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + hdmim1_rx_sda: hdmim1-rx-sda { + rockchip,pins = + + <3 27 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_cec: hdmim1-tx0-cec { + rockchip,pins = + + <0 25 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_hpd: hdmim1-tx0-hpd { + rockchip,pins = + + <3 28 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_scl: hdmim1-tx0-scl { + rockchip,pins = + + <0 29 11 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_sda: hdmim1-tx0-sda { + rockchip,pins = + + <0 28 11 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_cec: hdmim1-tx1-cec { + rockchip,pins = + + <0 26 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_hpd: hdmim1-tx1-hpd { + rockchip,pins = + + <3 15 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_scl: hdmim1-tx1-scl { + rockchip,pins = + + <3 22 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_sda: hdmim1-tx1-sda { + rockchip,pins = + + <3 21 5 &pcfg_pull_none_drv_level_1_smt>; + }; + /omit-if-no-ref/ + hdmim2_rx_cec: hdmim2-rx-cec { + rockchip,pins = + + <1 15 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_hpdin: hdmim2-rx-hpdin { + rockchip,pins = + + <1 14 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_scl: hdmim2-rx-scl { + rockchip,pins = + + <1 30 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_sda: hdmim2-rx-sda { + rockchip,pins = + + <1 31 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_scl: hdmim2-tx0-scl { + rockchip,pins = + + <3 23 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_sda: hdmim2-tx0-sda { + rockchip,pins = + + <3 24 5 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_cec: hdmim2-tx1-cec { + rockchip,pins = + + <3 20 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_scl: hdmim2-tx1-scl { + rockchip,pins = + + <1 4 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_sda: hdmim2-tx1-sda { + rockchip,pins = + + <1 3 5 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmi_debug0: hdmi-debug0 { + rockchip,pins = + + <1 7 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug1: hdmi-debug1 { + rockchip,pins = + + <1 8 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug2: hdmi-debug2 { + rockchip,pins = + + <1 9 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug3: hdmi-debug3 { + rockchip,pins = + + <1 10 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug4: hdmi-debug4 { + rockchip,pins = + + <1 11 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug5: hdmi-debug5 { + rockchip,pins = + + <1 12 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug6: hdmi-debug6 { + rockchip,pins = + + <1 0 7 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + + <0 11 2 &pcfg_pull_none_smt>, + + <0 6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + + <0 25 3 &pcfg_pull_none_smt>, + + <0 26 3 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + + <0 13 9 &pcfg_pull_none_smt>, + + <0 14 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + + <0 8 2 &pcfg_pull_none_smt>, + + <0 9 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m2_xfer: i2c1m2-xfer { + rockchip,pins = + + <0 28 9 &pcfg_pull_none_smt>, + + <0 29 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m3_xfer: i2c1m3-xfer { + rockchip,pins = + + <2 28 9 &pcfg_pull_none_smt>, + + <2 29 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m4_xfer: i2c1m4-xfer { + rockchip,pins = + + <1 26 9 &pcfg_pull_none_smt>, + + <1 27 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + + <0 15 9 &pcfg_pull_none_smt>, + + <0 16 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m2_xfer: i2c2m2-xfer { + rockchip,pins = + + <2 3 9 &pcfg_pull_none_smt>, + + <2 2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m3_xfer: i2c2m3-xfer { + rockchip,pins = + + <1 21 9 &pcfg_pull_none_smt>, + + <1 20 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m4_xfer: i2c2m4-xfer { + rockchip,pins = + + <1 1 9 &pcfg_pull_none_smt>, + + <1 0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + + <1 17 9 &pcfg_pull_none_smt>, + + <1 16 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + + <3 15 9 &pcfg_pull_none_smt>, + + <3 16 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + + <4 4 9 &pcfg_pull_none_smt>, + + <4 5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m4_xfer: i2c3m4-xfer { + rockchip,pins = + + <4 24 9 &pcfg_pull_none_smt>, + + <4 25 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + + <3 6 9 &pcfg_pull_none_smt>, + + <3 5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m2_xfer: i2c4m2-xfer { + rockchip,pins = + + <0 21 9 &pcfg_pull_none_smt>, + + <0 20 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m3_xfer: i2c4m3-xfer { + rockchip,pins = + + <1 3 9 &pcfg_pull_none_smt>, + + <1 2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m4_xfer: i2c4m4-xfer { + rockchip,pins = + + <1 23 9 &pcfg_pull_none_smt>, + + <1 22 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + + <3 23 9 &pcfg_pull_none_smt>, + + <3 24 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + + <4 14 9 &pcfg_pull_none_smt>, + + <4 15 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins = + + <4 6 9 &pcfg_pull_none_smt>, + + <4 7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m3_xfer: i2c5m3-xfer { + rockchip,pins = + + <1 14 9 &pcfg_pull_none_smt>, + + <1 15 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + + <0 24 9 &pcfg_pull_none_smt>, + + <0 23 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + + <1 19 9 &pcfg_pull_none_smt>, + + <1 18 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m3_xfer: i2c6m3-xfer { + rockchip,pins = + + <4 9 9 &pcfg_pull_none_smt>, + + <4 8 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m4_xfer: i2c6m4-xfer { + rockchip,pins = + + <3 1 9 &pcfg_pull_none_smt>, + + <3 0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m0_xfer: i2c7m0-xfer { + rockchip,pins = + + <1 24 9 &pcfg_pull_none_smt>, + + <1 25 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m2_xfer: i2c7m2-xfer { + rockchip,pins = + + <3 26 9 &pcfg_pull_none_smt>, + + <3 27 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m3_xfer: i2c7m3-xfer { + rockchip,pins = + + <4 10 9 &pcfg_pull_none_smt>, + + <4 11 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m0_xfer: i2c8m0-xfer { + rockchip,pins = + + <4 26 9 &pcfg_pull_none_smt>, + + <4 27 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m2_xfer: i2c8m2-xfer { + rockchip,pins = + + <1 30 9 &pcfg_pull_none_smt>, + + <1 31 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m3_xfer: i2c8m3-xfer { + rockchip,pins = + + <4 16 9 &pcfg_pull_none_smt>, + + <4 17 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m4_xfer: i2c8m4-xfer { + rockchip,pins = + + <3 18 9 &pcfg_pull_none_smt>, + + <3 19 9 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0_idle: i2s0-idle { + rockchip,pins = + + <1 21 0 &pcfg_pull_none>, + + <1 19 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_lrck: i2s0-lrck { + rockchip,pins = + + <1 21 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0_mclk: i2s0-mclk { + rockchip,pins = + + <1 18 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0_sclk: i2s0-sclk { + rockchip,pins = + + <1 19 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0_sdi0: i2s0-sdi0 { + rockchip,pins = + + <1 28 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi1: i2s0-sdi1 { + rockchip,pins = + + <1 27 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi2: i2s0-sdi2 { + rockchip,pins = + + <1 26 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi3: i2s0-sdi3 { + rockchip,pins = + + <1 25 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo0: i2s0-sdo0 { + rockchip,pins = + + <1 23 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo1: i2s0-sdo1 { + rockchip,pins = + + <1 24 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo2: i2s0-sdo2 { + rockchip,pins = + + <1 25 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo3: i2s0-sdo3 { + rockchip,pins = + + <1 26 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + + <4 2 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + + <4 0 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + + <4 1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + + <4 5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + + <4 6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + + <4 7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + + <4 8 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + + <4 9 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + + <4 10 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + + <4 11 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + + <4 12 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + + <0 15 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + + <0 13 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + + <0 14 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + + <0 21 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + + <0 22 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + + <0 23 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + + <0 24 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + + <0 25 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + + <0 26 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + + <0 28 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + + <0 29 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m1_idle: i2s2m1-idle { + rockchip,pins = + + <3 14 0 &pcfg_pull_none>, + + <3 13 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + + <3 14 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + + <3 12 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + + <3 13 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + + <3 10 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + + <3 11 3 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3_idle: i2s3-idle { + rockchip,pins = + + <3 2 0 &pcfg_pull_none>, + + <3 1 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_lrck: i2s3-lrck { + rockchip,pins = + + <3 2 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3_mclk: i2s3-mclk { + rockchip,pins = + + <3 0 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3_sclk: i2s3-sclk { + rockchip,pins = + + <3 1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3_sdi: i2s3-sdi { + rockchip,pins = + + <3 4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdo: i2s3-sdo { + rockchip,pins = + + <3 3 3 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + + <4 26 5 &pcfg_pull_none>, + + <4 27 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + + <4 24 5 &pcfg_pull_none>, + + <4 25 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2_pins: jtagm2-pins { + rockchip,pins = + + <0 13 2 &pcfg_pull_none>, + + <0 14 2 &pcfg_pull_none>; + }; + }; + + litcpu { + /omit-if-no-ref/ + litcpu_pins: litcpu-pins { + rockchip,pins = + + <0 27 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcum0_pins: mcum0-pins { + rockchip,pins = + + <4 28 5 &pcfg_pull_none>, + + <4 29 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mcum1_pins: mcum1-pins { + rockchip,pins = + + <3 28 6 &pcfg_pull_none>, + + <3 29 6 &pcfg_pull_none>; + }; + }; + + mipi { + /omit-if-no-ref/ + mipim0_camera0_clk: mipim0-camera0-clk { + rockchip,pins = + + <4 9 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera1_clk: mipim0-camera1-clk { + rockchip,pins = + + <1 14 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera2_clk: mipim0-camera2-clk { + rockchip,pins = + + <1 15 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera3_clk: mipim0-camera3-clk { + rockchip,pins = + + <1 30 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera4_clk: mipim0-camera4-clk { + rockchip,pins = + + <1 31 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera0_clk: mipim1-camera0-clk { + rockchip,pins = + + <3 5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera1_clk: mipim1-camera1-clk { + rockchip,pins = + + <3 6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera2_clk: mipim1-camera2-clk { + rockchip,pins = + + <3 7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera3_clk: mipim1-camera3-clk { + rockchip,pins = + + <3 8 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera4_clk: mipim1-camera4-clk { + rockchip,pins = + + <3 9 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te0: mipi-te0 { + rockchip,pins = + + <3 18 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te1: mipi-te1 { + rockchip,pins = + + <3 19 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + + <0 22 2 &pcfg_pull_none>; + }; + }; + + pcie20x1 { + /omit-if-no-ref/ + pcie20x1m0_pins: pcie20x1m0-pins { + rockchip,pins = + + <3 23 4 &pcfg_pull_none>, + + <3 25 4 &pcfg_pull_none>, + + <3 24 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_pins: pcie20x1m1-pins { + rockchip,pins = + + <4 15 4 &pcfg_pull_none>, + + <4 17 4 &pcfg_pull_none>, + + <4 16 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { + rockchip,pins = + + <4 11 4 &pcfg_pull_none>; + }; + }; + + pcie30phy { + /omit-if-no-ref/ + pcie30phy_pins: pcie30phy-pins { + rockchip,pins = + + <1 20 4 &pcfg_pull_none>, + + <1 25 4 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + + <0 16 12 &pcfg_pull_none>, + + <0 21 12 &pcfg_pull_none>, + + <0 20 12 &pcfg_pull_none>, + + <0 13 12 &pcfg_pull_none>, + + <0 15 12 &pcfg_pull_none>, + + <0 14 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + + <4 3 4 &pcfg_pull_none>, + + <4 5 4 &pcfg_pull_none>, + + <4 4 4 &pcfg_pull_none>, + + <4 0 4 &pcfg_pull_none>, + + <4 2 4 &pcfg_pull_none>, + + <4 1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + + <1 13 4 &pcfg_pull_none>, + + <1 12 4 &pcfg_pull_none>, + + <1 11 4 &pcfg_pull_none>, + + <1 0 4 &pcfg_pull_none>, + + <1 7 4 &pcfg_pull_none>, + + <1 1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { + rockchip,pins = + + <4 9 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { + rockchip,pins = + + <4 10 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + + <0 25 12 &pcfg_pull_none>, + + <0 28 12 &pcfg_pull_none>, + + <0 26 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + + <4 6 4 &pcfg_pull_none>, + + <4 8 4 &pcfg_pull_none>, + + <4 7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + + <3 26 4 &pcfg_pull_none>, + + <3 28 4 &pcfg_pull_none>, + + <3 27 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_pins: pcie30x2m3-pins { + rockchip,pins = + + <1 31 4 &pcfg_pull_none>, + + <1 15 4 &pcfg_pull_none>, + + <1 14 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_button_rstn: pcie30x2-button-rstn { + rockchip,pins = + + <3 17 4 &pcfg_pull_none>; + }; + }; + + pcie30x4 { + /omit-if-no-ref/ + pcie30x4m0_pins: pcie30x4m0-pins { + rockchip,pins = + + <0 22 12 &pcfg_pull_none>, + + <0 24 12 &pcfg_pull_none>, + + <0 23 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_pins: pcie30x4m1-pins { + rockchip,pins = + + <4 12 4 &pcfg_pull_none>, + + <4 14 4 &pcfg_pull_none>, + + <4 13 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_pins: pcie30x4m2-pins { + rockchip,pins = + + <3 20 4 &pcfg_pull_none>, + + <3 22 4 &pcfg_pull_none>, + + <3 21 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_pins: pcie30x4m3-pins { + rockchip,pins = + + <1 8 4 &pcfg_pull_none>, + + <1 10 4 &pcfg_pull_none>, + + <1 9 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4_button_rstn: pcie30x4-button-rstn { + rockchip,pins = + + <3 29 4 &pcfg_pull_none>; + }; + }; + + pdm0 { + /omit-if-no-ref/ + pdm0m0_clk: pdm0m0-clk { + rockchip,pins = + + <1 22 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_clk1: pdm0m0-clk1 { + rockchip,pins = + + <1 20 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_idle: pdm0m0-idle { + rockchip,pins = + + <1 22 0 &pcfg_pull_none>, + + <1 20 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi0: pdm0m0-sdi0 { + rockchip,pins = + + <1 29 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi1: pdm0m0-sdi1 { + rockchip,pins = + + <1 25 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi2: pdm0m0-sdi2 { + rockchip,pins = + + <1 26 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi3: pdm0m0-sdi3 { + rockchip,pins = + + <1 27 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm0m1_clk: pdm0m1-clk { + rockchip,pins = + + <0 16 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_clk1: pdm0m1-clk1 { + rockchip,pins = + + <0 20 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_idle: pdm0m1-idle { + rockchip,pins = + + <0 16 0 &pcfg_pull_none>, + + <0 20 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi0: pdm0m1-sdi0 { + rockchip,pins = + + <0 23 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi1: pdm0m1-sdi1 { + rockchip,pins = + + <0 24 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi2: pdm0m1-sdi2 { + rockchip,pins = + + <0 28 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi3: pdm0m1-sdi3 { + rockchip,pins = + + <0 30 2 &pcfg_pull_none>; + }; + }; + + pdm1 { + /omit-if-no-ref/ + pdm1m0_clk: pdm1m0-clk { + rockchip,pins = + + <4 29 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_clk1: pdm1m0-clk1 { + rockchip,pins = + + <4 28 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_idle: pdm1m0-idle { + rockchip,pins = + + <4 29 0 &pcfg_pull_none>, + + <4 28 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi0: pdm1m0-sdi0 { + rockchip,pins = + + <4 27 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi1: pdm1m0-sdi1 { + rockchip,pins = + + <4 26 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi2: pdm1m0-sdi2 { + rockchip,pins = + + <4 25 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi3: pdm1m0-sdi3 { + rockchip,pins = + + <4 24 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk: pdm1m1-clk { + rockchip,pins = + + <1 12 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk1: pdm1m1-clk1 { + rockchip,pins = + + <1 11 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_idle: pdm1m1-idle { + rockchip,pins = + + <1 12 0 &pcfg_pull_none>, + + <1 11 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi0: pdm1m1-sdi0 { + rockchip,pins = + + <1 7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi1: pdm1m1-sdi1 { + rockchip,pins = + + <1 8 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi2: pdm1m1-sdi2 { + rockchip,pins = + + <1 9 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi3: pdm1m1-sdi3 { + rockchip,pins = + + <1 10 2 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + + <0 7 0 &pcfg_pull_up>, + + <0 2 1 &pcfg_pull_none>, + + <0 3 1 &pcfg_pull_none>, + + <0 17 1 &pcfg_pull_none>, + + <0 18 1 &pcfg_pull_none>, + + <0 19 1 &pcfg_pull_none>, + + <0 30 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + + <0 5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + + <0 15 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + + <1 26 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m2_pins: pwm0m2-pins { + rockchip,pins = + + <1 2 11 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + + <0 16 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + + <1 27 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m2_pins: pwm1m2-pins { + rockchip,pins = + + <1 3 11 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + + <0 20 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + + <3 9 11 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + + <0 28 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + + <3 10 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m2_pins: pwm3m2-pins { + rockchip,pins = + + <1 18 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m3_pins: pwm3m3-pins { + rockchip,pins = + + <1 7 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + + <0 21 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + + <0 9 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + + <0 22 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + + <0 23 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + + <4 17 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + + <0 24 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + + <4 28 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m2_pins: pwm7m2-pins { + rockchip,pins = + + <1 19 11 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + + <3 7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + + <4 24 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m2_pins: pwm8m2-pins { + rockchip,pins = + + <3 24 11 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + + <3 8 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + + <4 25 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m2_pins: pwm9m2-pins { + rockchip,pins = + + <3 25 11 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + + <3 0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + + <4 27 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m2_pins: pwm10m2-pins { + rockchip,pins = + + <3 27 11 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + + <3 1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + + <4 12 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m2_pins: pwm11m2-pins { + rockchip,pins = + + <1 20 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m3_pins: pwm11m3-pins { + rockchip,pins = + + <3 29 11 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + + <3 13 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + + <4 13 11 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + + <3 14 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + + <4 14 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m2_pins: pwm13m2-pins { + rockchip,pins = + + <1 15 11 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + + <3 18 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + + <4 10 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m2_pins: pwm14m2-pins { + rockchip,pins = + + <1 30 11 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + + <3 19 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + + <4 11 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m2_pins: pwm15m2-pins { + rockchip,pins = + + <1 22 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m3_pins: pwm15m3-pins { + rockchip,pins = + + <1 31 11 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + + <0 0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + + <0 22 13 &pcfg_pull_none>, + + <0 28 13 &pcfg_pull_none>, + + <0 29 13 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0m0_pins: sata0m0-pins { + rockchip,pins = + + <4 14 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata0m1_pins: sata0m1-pins { + rockchip,pins = + + <1 11 6 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1m0_pins: sata1m0-pins { + rockchip,pins = + + <4 13 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata1m1_pins: sata1m1-pins { + rockchip,pins = + + <1 1 6 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2m0_pins: sata2m0-pins { + rockchip,pins = + + <4 9 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata2m1_pins: sata2m1-pins { + rockchip,pins = + + <1 15 6 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom1_pins: sdiom1-pins { + rockchip,pins = + + <3 5 2 &pcfg_pull_none>, + + <3 4 2 &pcfg_pull_up>, + + <3 0 2 &pcfg_pull_up>, + + <3 1 2 &pcfg_pull_up>, + + <3 2 2 &pcfg_pull_up>, + + <3 3 2 &pcfg_pull_up>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + + <4 24 1 &pcfg_pull_up_drv_level_2>, + + <4 25 1 &pcfg_pull_up_drv_level_2>, + + <4 26 1 &pcfg_pull_up_drv_level_2>, + + <4 27 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + + <4 29 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + + <4 28 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + + <0 4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + + <0 5 2 &pcfg_pull_none>; + }; + }; + + spdif0 { + /omit-if-no-ref/ + spdif0m0_tx: spdif0m0-tx { + rockchip,pins = + + <1 14 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif0m1_tx: spdif0m1-tx { + rockchip,pins = + + <4 12 6 &pcfg_pull_none>; + }; + }; + + spdif1 { + /omit-if-no-ref/ + spdif1m0_tx: spdif1m0-tx { + rockchip,pins = + + <1 15 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m1_tx: spdif1m1-tx { + rockchip,pins = + + <4 9 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m2_tx: spdif1m2-tx { + rockchip,pins = + + <4 17 3 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + + <0 22 8 &pcfg_pull_up_drv_level_6>, + + <0 23 8 &pcfg_pull_up_drv_level_6>, + + <0 16 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + + <0 25 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + + <0 15 8 &pcfg_pull_up_drv_level_6>; + }; + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + + <4 2 8 &pcfg_pull_up_drv_level_6>, + + <4 0 8 &pcfg_pull_up_drv_level_6>, + + <4 1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + + <4 10 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + + <4 9 8 &pcfg_pull_up_drv_level_6>; + }; + /omit-if-no-ref/ + spi0m2_pins: spi0m2-pins { + rockchip,pins = + + <1 11 8 &pcfg_pull_up_drv_level_6>, + + <1 9 8 &pcfg_pull_up_drv_level_6>, + + <1 10 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + + <1 12 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m2_cs1: spi0m2-cs1 { + rockchip,pins = + + <1 13 8 &pcfg_pull_up_drv_level_6>; + }; + /omit-if-no-ref/ + spi0m3_pins: spi0m3-pins { + rockchip,pins = + + <3 27 8 &pcfg_pull_up_drv_level_6>, + + <3 25 8 &pcfg_pull_up_drv_level_6>, + + <3 26 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m3_cs0: spi0m3-cs0 { + rockchip,pins = + + <3 28 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m3_cs1: spi0m3-cs1 { + rockchip,pins = + + <3 29 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + + <3 17 8 &pcfg_pull_up_drv_level_6>, + + <3 16 8 &pcfg_pull_up_drv_level_6>, + + <3 15 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + + <3 18 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m1_cs1: spi1m1-cs1 { + rockchip,pins = + + <3 19 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m2_pins: spi1m2-pins { + rockchip,pins = + + <1 26 8 &pcfg_pull_up_drv_level_6>, + + <1 24 8 &pcfg_pull_up_drv_level_6>, + + <1 25 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m2_cs0: spi1m2-cs0 { + rockchip,pins = + + <1 27 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m2_cs1: spi1m2-cs1 { + rockchip,pins = + + <1 29 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + + <1 6 8 &pcfg_pull_up_drv_level_6>, + + <1 4 8 &pcfg_pull_up_drv_level_6>, + + <1 5 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + + <1 7 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + + <1 8 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + + <4 6 8 &pcfg_pull_up_drv_level_6>, + + <4 4 8 &pcfg_pull_up_drv_level_6>, + + <4 5 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + + <4 7 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + + <4 8 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m2_pins: spi2m2-pins { + rockchip,pins = + + <0 5 1 &pcfg_pull_up_drv_level_1>, + + <0 11 1 &pcfg_pull_up_drv_level_1>, + + <0 6 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs0: spi2m2-cs0 { + rockchip,pins = + + <0 9 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs1: spi2m2-cs1 { + rockchip,pins = + + <0 8 1 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + + <4 15 8 &pcfg_pull_up_drv_level_6>, + + <4 13 8 &pcfg_pull_up_drv_level_6>, + + <4 14 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + + <4 16 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + + <4 17 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m2_pins: spi3m2-pins { + rockchip,pins = + + <0 27 8 &pcfg_pull_up_drv_level_6>, + + <0 24 8 &pcfg_pull_up_drv_level_6>, + + <0 26 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m2_cs0: spi3m2-cs0 { + rockchip,pins = + + <0 28 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m2_cs1: spi3m2-cs1 { + rockchip,pins = + + <0 29 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m3_pins: spi3m3-pins { + rockchip,pins = + + <3 24 8 &pcfg_pull_up_drv_level_6>, + + <3 22 8 &pcfg_pull_up_drv_level_6>, + + <3 23 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m3_cs0: spi3m3-cs0 { + rockchip,pins = + + <3 20 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m3_cs1: spi3m3-cs1 { + rockchip,pins = + + <3 21 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + spi4 { + /omit-if-no-ref/ + spi4m0_pins: spi4m0-pins { + rockchip,pins = + + <1 18 8 &pcfg_pull_up_drv_level_6>, + + <1 16 8 &pcfg_pull_up_drv_level_6>, + + <1 17 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m0_cs0: spi4m0-cs0 { + rockchip,pins = + + <1 19 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m0_cs1: spi4m0-cs1 { + rockchip,pins = + + <1 20 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m1_pins: spi4m1-pins { + rockchip,pins = + + <3 2 8 &pcfg_pull_up_drv_level_6>, + + <3 0 8 &pcfg_pull_up_drv_level_6>, + + <3 1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m1_cs0: spi4m1-cs0 { + rockchip,pins = + + <3 3 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m1_cs1: spi4m1-cs1 { + rockchip,pins = + + <3 4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m2_pins: spi4m2-pins { + rockchip,pins = + + <1 2 8 &pcfg_pull_up_drv_level_6>, + + <1 0 8 &pcfg_pull_up_drv_level_6>, + + <1 1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m2_cs0: spi4m2-cs0 { + rockchip,pins = + + <1 3 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + + <0 2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut: tsadc-shut { + rockchip,pins = + + <0 1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + + <0 1 1 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + + <0 20 4 &pcfg_pull_up>, + + <0 21 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + + <0 8 4 &pcfg_pull_up>, + + <0 9 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + + <4 4 10 &pcfg_pull_up>, + + <4 3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + + <0 25 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + + <0 22 4 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + + <1 15 10 &pcfg_pull_up>, + + <1 14 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + + <1 31 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + + <1 30 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + + <0 26 10 &pcfg_pull_up>, + + <0 25 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + + <0 24 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + + <0 23 10 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + + <0 14 10 &pcfg_pull_up>, + + <0 13 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + + <4 25 10 &pcfg_pull_up>, + + <4 24 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + + <3 10 10 &pcfg_pull_up>, + + <3 9 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2_ctsn: uart2-ctsn { + rockchip,pins = + + <3 12 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2_rtsn: uart2-rtsn { + rockchip,pins = + + <3 11 10 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + + <1 16 10 &pcfg_pull_up>, + + <1 17 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + + <3 14 10 &pcfg_pull_up>, + + <3 13 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + + <4 6 10 &pcfg_pull_up>, + + <4 5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + + <1 19 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + + <1 18 10 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + + <1 27 10 &pcfg_pull_up>, + + <1 26 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + + <3 24 10 &pcfg_pull_up>, + + <3 25 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + + <1 10 10 &pcfg_pull_up>, + + <1 11 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + + <1 23 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + + <1 21 10 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + + <4 28 10 &pcfg_pull_up>, + + <4 29 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + + <4 26 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + + <4 27 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + + <3 21 10 &pcfg_pull_up>, + + <3 20 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + + <2 2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + + <2 3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + + <2 28 10 &pcfg_pull_up>, + + <2 29 10 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + + <1 0 10 &pcfg_pull_up>, + + <1 1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + + <1 3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + + <1 2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m2_xfer: uart6m2-xfer { + rockchip,pins = + + <1 25 10 &pcfg_pull_up>, + + <1 24 10 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + + <3 17 10 &pcfg_pull_up>, + + <3 16 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + + <3 19 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + + <3 18 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + + <1 12 10 &pcfg_pull_up>, + + <1 13 10 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + + <4 9 10 &pcfg_pull_up>, + + <4 8 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + + <4 11 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + + <4 10 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + + <3 3 10 &pcfg_pull_up>, + + <3 2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + + <3 5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + + <3 4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8_xfer: uart8-xfer { + rockchip,pins = + + <4 9 10 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + + <4 13 10 &pcfg_pull_up>, + + <4 12 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m1_ctsn: uart9m1-ctsn { + rockchip,pins = + + <4 1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_rtsn: uart9m1-rtsn { + rockchip,pins = + + <4 0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + + <3 28 10 &pcfg_pull_up>, + + <3 29 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_ctsn: uart9m2-ctsn { + rockchip,pins = + + <3 27 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_rtsn: uart9m2-rtsn { + rockchip,pins = + + <3 26 10 &pcfg_pull_none>; + }; + }; + + vop { + /omit-if-no-ref/ + vop_pins: vop-pins { + rockchip,pins = + + <1 2 1 &pcfg_pull_none>; + }; + }; +}; + + + + +&pinctrl { + bt656 { + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + + <4 8 2 &pcfg_pull_none_drv_level_2>, + + <4 0 2 &pcfg_pull_none_drv_level_2>, + + <4 1 2 &pcfg_pull_none_drv_level_2>, + + <4 2 2 &pcfg_pull_none_drv_level_2>, + + <4 3 2 &pcfg_pull_none_drv_level_2>, + + <4 4 2 &pcfg_pull_none_drv_level_2>, + + <4 5 2 &pcfg_pull_none_drv_level_2>, + + <4 6 2 &pcfg_pull_none_drv_level_2>, + + <4 7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 1 0 &pcfg_pull_none>; + }; + }; +}; +# 6888 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2 +# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 1 + + + + + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rockchip-pinconf.dtsi" 1 + + + + + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <1>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <2>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <3>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <4>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <5>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_up: pcfg-output-high-pull-up { + output-high; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_down: pcfg-output-high-pull-down { + output-high; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_none: pcfg-output-high-pull-none { + output-high; + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_up: pcfg-output-low-pull-up { + output-low; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_down: pcfg-output-low-pull-down { + output-low; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_none: pcfg-output-low-pull-none { + output-low; + bias-disable; + }; +}; +# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 2 + + + + + +&pinctrl { + clk32k { + /omit-if-no-ref/ + clk32k_out1: clk32k-out1 { + rockchip,pins = + + <2 21 1 &pcfg_pull_none>; + }; + + }; + + eth0 { + /omit-if-no-ref/ + eth0_pins: eth0-pins { + rockchip,pins = + + <2 19 1 &pcfg_pull_none>; + }; + + }; + + fspi { + /omit-if-no-ref/ + fspim1_pins: fspim1-pins { + rockchip,pins = + + <2 11 3 &pcfg_pull_up_drv_level_2>, + + <2 12 3 &pcfg_pull_up_drv_level_2>, + + <2 6 3 &pcfg_pull_up_drv_level_2>, + + <2 7 3 &pcfg_pull_up_drv_level_2>, + + <2 8 3 &pcfg_pull_up_drv_level_2>, + + <2 9 3 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim1_cs1: fspim1-cs1 { + rockchip,pins = + + <2 13 3 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac0 { + /omit-if-no-ref/ + gmac0_miim: gmac0-miim { + rockchip,pins = + + <4 20 1 &pcfg_pull_none>, + + <4 21 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_clkinout: gmac0-clkinout { + rockchip,pins = + + <4 19 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rx_bus2: gmac0-rx-bus2 { + rockchip,pins = + + <2 17 1 &pcfg_pull_none>, + + <2 18 1 &pcfg_pull_none>, + + <4 18 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_tx_bus2: gmac0-tx-bus2 { + rockchip,pins = + + <2 14 1 &pcfg_pull_none>, + + <2 15 1 &pcfg_pull_none>, + + <2 16 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_clk: gmac0-rgmii-clk { + rockchip,pins = + + <2 8 1 &pcfg_pull_none>, + + <2 11 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_rgmii_bus: gmac0-rgmii-bus { + rockchip,pins = + + <2 6 1 &pcfg_pull_none>, + + <2 7 1 &pcfg_pull_none>, + + <2 9 1 &pcfg_pull_none>, + + <2 10 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppsclk: gmac0-ppsclk { + rockchip,pins = + + <2 20 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ppstring: gmac0-ppstring { + rockchip,pins = + + <2 13 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_ptp_refclk: gmac0-ptp-refclk { + rockchip,pins = + + <2 12 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac0_txer: gmac0-txer { + rockchip,pins = + + <4 22 1 &pcfg_pull_none>; + }; + + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_tx1_cec: hdmim0-tx1-cec { + rockchip,pins = + + <2 20 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_scl: hdmim0-tx1-scl { + rockchip,pins = + + <2 13 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_sda: hdmim0-tx1-sda { + rockchip,pins = + + <2 12 4 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + + <4 21 9 &pcfg_pull_none_smt>, + + <4 22 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + + <2 17 9 &pcfg_pull_none_smt>, + + <2 16 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m3_xfer: i2c3m3-xfer { + rockchip,pins = + + <2 10 9 &pcfg_pull_none_smt>, + + <2 11 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m1_xfer: i2c4m1-xfer { + rockchip,pins = + + <2 13 9 &pcfg_pull_none_smt>, + + <2 12 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m4_xfer: i2c5m4-xfer { + rockchip,pins = + + <2 14 9 &pcfg_pull_none_smt>, + + <2 15 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m2_xfer: i2c6m2-xfer { + rockchip,pins = + + <2 19 9 &pcfg_pull_none_smt>, + + <2 18 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m1_xfer: i2c7m1-xfer { + rockchip,pins = + + <4 19 9 &pcfg_pull_none_smt>, + + <4 20 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m1_xfer: i2c8m1-xfer { + rockchip,pins = + + <2 8 9 &pcfg_pull_none_smt>, + + <2 9 9 &pcfg_pull_none_smt>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m0_idle: i2s2m0-idle { + rockchip,pins = + + <2 16 0 &pcfg_pull_none>, + + <2 15 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_lrck: i2s2m0-lrck { + rockchip,pins = + + <2 16 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_mclk: i2s2m0-mclk { + rockchip,pins = + + <2 14 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sclk: i2s2m0-sclk { + rockchip,pins = + + <2 15 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m0_sdi: i2s2m0-sdi { + rockchip,pins = + + <2 19 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m0_sdo: i2s2m0-sdo { + rockchip,pins = + + <4 19 2 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m2_pins: pwm2m2-pins { + rockchip,pins = + + <4 18 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + + <4 19 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m2_pins: pwm5m2-pins { + rockchip,pins = + + <4 20 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + + <4 21 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m3_pins: pwm7m3-pins { + rockchip,pins = + + <4 22 11 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom0_pins: sdiom0-pins { + rockchip,pins = + + <2 11 2 &pcfg_pull_none>, + + <2 10 2 &pcfg_pull_up>, + + <2 6 2 &pcfg_pull_up>, + + <2 7 2 &pcfg_pull_up>, + + <2 8 2 &pcfg_pull_up>, + + <2 9 2 &pcfg_pull_up>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m0_pins: spi1m0-pins { + rockchip,pins = + + <2 16 8 &pcfg_pull_up_drv_level_1>, + + <2 17 8 &pcfg_pull_up_drv_level_1>, + + <2 18 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs0: spi1m0-cs0 { + rockchip,pins = + + <2 19 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi1m0_cs1: spi1m0-cs1 { + rockchip,pins = + + <2 20 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m0_pins: spi3m0-pins { + rockchip,pins = + + <4 22 8 &pcfg_pull_up_drv_level_1>, + + <4 20 8 &pcfg_pull_up_drv_level_1>, + + <4 21 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs0: spi3m0-cs0 { + rockchip,pins = + + <4 18 8 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi3m0_cs1: spi3m0-cs1 { + rockchip,pins = + + <4 19 8 &pcfg_pull_up_drv_level_1>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + + <2 14 10 &pcfg_pull_up>, + + <2 15 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m0_ctsn: uart1m0-ctsn { + rockchip,pins = + + <2 17 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m0_rtsn: uart1m0-rtsn { + rockchip,pins = + + <2 16 10 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + + <2 6 10 &pcfg_pull_up>, + + <2 7 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m0_ctsn: uart6m0-ctsn { + rockchip,pins = + + <2 9 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m0_rtsn: uart6m0-rtsn { + rockchip,pins = + + <2 8 10 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + + <2 12 10 &pcfg_pull_up>, + + <2 13 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + + <4 22 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + + <4 18 10 &pcfg_pull_none>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m0_xfer: uart9m0-xfer { + rockchip,pins = + + <2 20 10 &pcfg_pull_up>, + + <2 18 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m0_ctsn: uart9m0-ctsn { + rockchip,pins = + + <4 21 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m0_rtsn: uart9m0-rtsn { + rockchip,pins = + + <4 20 10 &pcfg_pull_none>; + }; + }; +}; +# 9 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2 + +/ { + aliases { + dp0 = &dp0; + dp1 = &dp1; + edp0 = &edp0; + edp1 = &edp1; + ethernet0 = &gmac0; + hdptx0 = &hdptxphy0; + hdptx1 = &hdptxphy1; + hdptxhdmi0 = &hdptxphy_hdmi0; + hdptxhdmi1 = &hdptxphy_hdmi1; + hdmi0 = &hdmi0; + hdmi1 = &hdmi1; + hdmirx0 = &hdmirx_ctrler; + rkcif_mipi_lvds4= &rkcif_mipi_lvds4; + rkcif_mipi_lvds5= &rkcif_mipi_lvds5; + usbdp0 = &usbdp_phy0; + usbdp1 = &usbdp_phy1; + }; + + rkcif_mipi_lvds4: rkcif-mipi-lvds4 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds4>; + status = "disabled"; + }; + + rkcif_mipi_lvds5: rkcif-mipi-lvds5 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf: rkcif-mipi-lvds5-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf_vir1: rkcif-mipi-lvds5-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf_vir2: rkcif-mipi-lvds5-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + rkcif_mipi_lvds5_sditf_vir3: rkcif-mipi-lvds5-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds5>; + status = "disabled"; + }; + + usbdrd3_1: usbdrd3_1 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru 422>, <&cru 421>, + <&cru 420>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_1: usb@fc400000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc400000 0x0 0x400000>; + interrupts = <0 221 4>; + power-domains = <&power 31>; + resets = <&cru 679>; + reset-names = "usb3-otg"; + dr_mode = "host"; + phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + pcie30_phy_grf: syscon@fd5b8000 { + compatible = "rockchip,pcie30-phy-grf", "syscon"; + reg = <0x0 0xfd5b8000 0x0 0x10000>; + }; + + pipe_phy1_grf: syscon@fd5c0000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c0000 0x0 0x100>; + }; + + usbdpphy1_grf: syscon@fd5cc000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5cc000 0x0 0x4000>; + }; + + usb2phy1_grf: syscon@fd5d4000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d4000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy1: usb2-phy@4000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x4000 0x10>; + interrupts = <0 394 4>; + resets = <&cru 786504>, <&cru 1161>; + reset-names = "phy", "apb"; + clocks = <&cru 693>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy1"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy1_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + interrupts = <0 198 4>; + dmas = <&dmac1 22>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru 527>, <&cru 522>; + assigned-clocks = <&cru 523>; + assigned-clock-parents = <&cru 5>; + power-domains = <&power 25>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s8_8ch: i2s@fddc8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc8000 0x0 0x1000>; + interrupts = <0 188 4>; + clocks = <&cru 513>, <&cru 510>; + clock-names = "mclk_tx", "hclk"; + assigned-clocks = <&cru 511>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac2 22>; + dma-names = "tx"; + power-domains = <&power 25>; + resets = <&cru 913>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + interrupts = <0 197 4>; + dmas = <&dmac1 8>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru 604>, <&cru 600>; + assigned-clocks = <&cru 601>; + assigned-clock-parents = <&cru 5>; + power-domains = <&power 26>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s6_8ch: i2s@fddf4000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf4000 0x0 0x1000>; + interrupts = <0 186 4>; + clocks = <&cru 588>, <&cru 588>, <&cru 594>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 585>; + assigned-clock-parents = <&cru 7>; + dmas = <&dmac2 4>; + dma-names = "tx"; + power-domains = <&power 26>; + resets = <&cru 1007>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s7_8ch: i2s@fddf8000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf8000 0x0 0x1000>; + interrupts = <0 187 4>; + clocks = <&cru 572>, <&cru 572>, <&cru 568>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 569>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac2 21>; + dma-names = "rx"; + power-domains = <&power 26>; + resets = <&cru 963>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s10_8ch: i2s@fde00000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfde00000 0x0 0x1000>; + interrupts = <0 190 4>; + clocks = <&cru 567>, <&cru 567>, <&cru 563>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru 564>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac2 24>; + dma-names = "rx"; + power-domains = <&power 26>; + resets = <&cru 1047>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx1: spdif-rx@fde10000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde10000 0x0 0x1000>; + interrupts = <0 200 4>; + clocks = <&cru 608>, <&cru 607>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru 608>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac0 22>; + dma-names = "rx"; + power-domains = <&power 26>; + resets = <&cru 1023>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx2: spdif-rx@fde18000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde18000 0x0 0x1000>; + interrupts = <0 201 4>; + clocks = <&cru 610>, <&cru 609>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru 610>; + assigned-clock-parents = <&cru 5>; + dmas = <&dmac0 23>; + dma-names = "rx"; + power-domains = <&power 26>; + resets = <&cru 1025>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dp1: dp@fde60000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde60000 0x0 0x4000>; + interrupts = <0 162 4>; + clocks = <&cru 487>, <&cru 717>, + <&cru 513>, <&cru 525>, + <&hclk_vo0>, <&cru 491>; + clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp"; + assigned-clocks = <&cru 717>; + assigned-clock-rates = <16000000>; + resets = <&cru 905>; + phys = <&usbdp_phy1_dp>; + power-domains = <&power 25>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dp1>; + status = "disabled"; + }; + + dp1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dp1>; + status = "disabled"; + }; + + dp1_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_dp1>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + dp1_out: endpoint { }; + }; + }; + }; + + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfdea0000 0x0 0x10000>, <0x0 0xfdeb0000 0x0 0x10000>; + interrupts = <0 173 4>, + <0 174 4>, + <0 175 4>, + <0 176 4>, + <0 361 4>; + clocks = <&cru 548>, + <&cru 614>, + <&cru 549>, + <&cru 550>, + <&cru 588>, + <&cru 628>, + <&cru 629>, + <&cru 630>, + <&cru 631>, + <&hclk_vo1>, + <&hdptxphy_hdmi_clk1>; + clock-names = "pclk", + "hpd", + "earc", + "hdmitx_ref", + "aud", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "hclk_vo1", + "link_clk"; + resets = <&cru 983>, <&cru 1181>; + reset-names = "ref", "hdp"; + power-domains = <&power 26>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; + reg-io-width = <4>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdptxphy_hdmi1>; + phy-names = "hdmi"; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi1>; + status = "disabled"; + }; + + hdmi1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi1>; + status = "disabled"; + }; + + hdmi1_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_hdmi1>; + status = "disabled"; + }; + }; + }; + }; + + edp1: edp@fded0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfded0000 0x0 0x1000>; + interrupts = <0 164 4>; + clocks = <&cru 532>, <&cru 531>, + <&cru 533>, <&hclk_vo1>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru 996>, <&cru 995>; + reset-names = "dp", "apb"; + phys = <&hdptxphy1>; + phy-names = "dp"; + power-domains = <&power 26>; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp1_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp1>; + status = "disabled"; + }; + + edp1_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp1>; + status = "disabled"; + }; + + edp1_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_edp1>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + edp1_out: endpoint { }; + }; + }; + }; + + hdmirx_ctrler: hdmirx-controller@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + reg-names = "hdmirx_regs"; + power-domains = <&power 26>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + interrupts = <0 177 4>, + <0 436 4>, + <0 179 4>; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru 538>, + <&cru 543>, + <&cru 690>, + <&cru 539>, + <&cru 540>, + <&cru 562>, + <&hclk_vo1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + resets = <&cru 985>, <&cru 986>, + <&cru 987>, <&cru 951>; + reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu"; + pinctrl-0 = <&hdmim1_rx>; + pinctrl-names = "default"; + status = "disabled"; + }; + + pcie3x4: pcie@fe150000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0x0f>; + clocks = <&cru 334>, <&cru 339>, + <&cru 329>, <&cru 344>, + <&cru 350>, <&cru 387>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <0 263 4>, + <0 262 4>, + <0 261 4>, + <0 260 4>, + <0 259 4>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, + <0 0 0 2 &pcie3x4_intc 1>, + <0 0 0 3 &pcie3x4_intc 2>, + <0 0 0 4 &pcie3x4_intc 3>; + linux,pci-domain = <0>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x0000 &its1 0x0000 0x1000>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power 34>; + ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 + 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 + 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000 + 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe150000 0x0 0x10000>, + <0xa 0x40000000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru 525>, <&cru 540>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie3x4_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 260 1>; + }; + }; + + pcie3x2: pcie@fe160000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x10 0x1f>; + clocks = <&cru 335>, <&cru 340>, + <&cru 330>, <&cru 345>, + <&cru 351>, <&cru 388>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <0 258 4>, + <0 257 4>, + <0 256 4>, + <0 255 4>, + <0 254 4>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, + <0 0 0 2 &pcie3x2_intc 1>, + <0 0 0 3 &pcie3x2_intc 2>, + <0 0 0 4 &pcie3x2_intc 3>; + linux,pci-domain = <1>; + num-ib-windows = <16>; + num-ob-windows = <16>; + num-viewport = <8>; + max-link-speed = <3>; + msi-map = <0x1000 &its1 0x1000 0x1000>; + num-lanes = <2>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power 34>; + ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000 + 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000 + 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000 + 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; + reg = <0x0 0xfe160000 0x0 0x10000>, + <0xa 0x40400000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru 526>, <&cru 541>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie3x2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 255 1>; + }; + }; + + pcie2x1l0: pcie@fe170000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x20 0x2f>; + clocks = <&cru 336>, <&cru 341>, + <&cru 331>, <&cru 347>, + <&cru 352>, <&cru 708>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = <0 243 4>, + <0 242 4>, + <0 241 4>, + <0 240 4>, + <0 239 4>; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, + <0 0 0 2 &pcie2x1l0_intc 1>, + <0 0 0 3 &pcie2x1l0_intc 2>, + <0 0 0 4 &pcie2x1l0_intc 3>; + linux,pci-domain = <2>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x2000 &its0 0x2000 0x1000>; + num-lanes = <1>; + phys = <&combphy1_ps 2>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 + 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 + 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000 + 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + reg = <0x0 0xfe170000 0x0 0x10000>, + <0xa 0x40800000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru 527>, <&cru 542>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l0_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <0 240 1>; + }; + }; + + gmac_uio0: uio@fe1b0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + rockchip,ethernet = <&gmac0>; + status = "disabled"; + }; + + gmac0: ethernet@fe1b0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1b0000 0x0 0x10000>; + interrupts = <0 227 4>, + <0 226 4>; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&php_grf>; + clocks = <&cru 324>, <&cru 325>, + <&cru 359>, <&cru 364>, + <&cru 322>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + resets = <&cru 522>; + reset-names = "stmmaceth"; + power-domains = <&power 33>; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac0_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + status = "disabled"; + + mdio0: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sata1: sata@fe220000 { + compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; + reg = <0 0xfe220000 0 0x1000>; + clocks = <&cru 370>, <&cru 367>, + <&cru 373>, <&cru 356>, + <&cru 383>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = <0 274 4>; + interrupt-names = "hostc"; + phys = <&combphy1_ps 1>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru 693>, <&cru 616>; + clock-names = "ref", "apb"; + resets = <&cru 1158>, <&cru 786495>, + <&cru 786496>, <&cru 786497>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdptxphy_hdmi1: hdmiphy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru 693>, <&cru 616>; + clock-names = "ref", "apb"; + resets = <&cru 1169>, <&cru 1158>, + <&cru 786495>, <&cru 786496>, + <&cru 786497>, <&cru 1167>, + <&cru 1168>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + + hdptxphy_hdmi_clk1: clk-port { + #clock-cells = <0>; + status = "okay"; + }; + }; + + + usbdp_phy1: phy@fed90000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed90000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy1_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy1_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru 694>, + <&cru 640>, + <&cru 618>, + <&u2phy1>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru 47>, + <&cru 48>, + <&cru 49>, + <&cru 50>, + <&cru 1156>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy1_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy1_u3: u3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + combphy1_ps: phy@fee10000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee10000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru 702>, <&cru 390>, + <&cru 358>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru 702>; + assigned-clock-rates = <100000000>; + resets = <&cru 131078>, <&cru 1239>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy1_grf>; + rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; + status = "disabled"; + }; + + pcie30phy: phy@fee80000 { + compatible = "rockchip,rk3588-pcie3-phy"; + reg = <0x0 0xfee80000 0x0 0x20000>; + #phy-cells = <0>; + clocks = <&cru 392>; + clock-names = "pclk"; + resets = <&cru 131082>; + reset-names = "phy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,phy-grf = <&pcie30_phy_grf>; + status = "disabled"; + }; + +}; + +&display_subsystem { + route { + route_dp1: route-dp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_dp1>; + }; + + route_hdmi1: route-hdmi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_hdmi1>; + }; + }; +}; + +&vp0 { + vp0_out_dp1: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp1_in_vp0>; + }; + + vp0_out_edp1: endpoint@4 { + reg = <4>; + remote-endpoint = <&edp1_in_vp0>; + }; + + vp0_out_hdmi1: endpoint@5 { + reg = <5>; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; + +&vp1 { + vp1_out_dp1: endpoint@3 { + reg = <3>; + remote-endpoint = <&dp1_in_vp1>; + }; + + vp1_out_edp1: endpoint@4 { + reg = <4>; + remote-endpoint = <&edp1_in_vp1>; + }; + + vp1_out_hdmi1: endpoint@5 { + reg = <5>; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; + +&vp2 { + vp2_out_dp1: endpoint@5 { + reg = <5>; + remote-endpoint = <&dp1_in_vp2>; + }; + + vp2_out_edp1: endpoint@6 { + reg = <6>; + remote-endpoint = <&edp1_in_vp2>; + }; + + vp2_out_hdmi1: endpoint@7 { + reg = <7>; + remote-endpoint = <&hdmi1_in_vp2>; + }; +}; +# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588j.dtsi" 2 + +&cluster0_opp_table { + + + + + + + + /delete-node/ opp-j-m-1416000000; + /delete-node/ opp-j-m-1608000000; + /delete-node/ opp-j-m-1704000000; +}; + +&cluster1_opp_table { + + + + + + + + /delete-node/ opp-j-m-1800000000; + /delete-node/ opp-j-m-2016000000; +}; + +&cluster2_opp_table { + + + + + + + + /delete-node/ opp-j-m-1800000000; + /delete-node/ opp-j-m-2016000000; +}; + +&gpu_opp_table { + + + + + + + + /delete-node/ opp-j-850000000; +}; + +&npu_opp_table { + + + + + + + + /delete-node/ opp-j-m-950000000; +}; +# 13 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 1 + + + + + + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1 +# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h" 1 +# 9 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2 + +# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/rk-input.h" 1 +# 11 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/display/drm_mipi_dsi.h" 1 +# 12 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/display/rockchip_vop.h" 1 +# 13 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2 +# 1 "./scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h" 1 +# 14 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2 + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = <115>; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = <114>; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = <139>; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = <158>; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + hdmi1_sound: hdmi1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi1"; + rockchip,cpu = <&i2s6_8ch>; + rockchip,codec = <&hdmi1>; + rockchip,jack-det; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + dp1_sound: dp1-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp1"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx5>; + rockchip,codec = <&dp1 1>; + rockchip,jack-det; + }; + + leds: leds { + compatible = "gpio-leds"; + work_led: work { + gpios = <&gpio3 15 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + spdif_tx0_dc: spdif-tx0-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx0_sound: spdif-tx0-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx0"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx0>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx0_dc>; + }; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avsd { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dsi0 { + status = "disabled"; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <60>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <((1 << 0) | (1 << 1) | + (1 << 11) | (1 << 9))>; + dsi,format = <0>; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <10>; + enable-delay-ms = <10>; + prepare-delay-ms = <10>; + unprepare-delay-ms = <10>; + disable-delay-ms = <10>; + width-mm = <68>; + height-mm = <121>; + dsi,flags = <((1 << 0) | (1 << 1) | + (1 << 11) | (1 << 9))>; + dsi,format = <0>; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 00 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rkvtunnel { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usbdp_phy1_dp { + status = "okay"; +}; + +&usbdp_phy1_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&usbdrd3_1 { + status = "okay"; +}; + +&usbdrd_dwc3_1 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + + +&vp0 { + rockchip,plane-mask = <(1 << 0 | 1 << 2)>; + rockchip,primary-plane = <2>; +}; + +&vp1 { + rockchip,plane-mask = <(1 << 1 | 1 << 3)>; + rockchip,primary-plane = <3>; +}; + +&vp2 { + rockchip,plane-mask = <(1 << 6 | 1 << 8)>; + rockchip,primary-plane = <8>; +}; + +&vp3 { + rockchip,plane-mask = <(1 << 7 | 1 << 9)>; + rockchip,primary-plane = <9>; +}; +# 14 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi" 1 +# 10 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi" +&spi2 { + status = "okay"; + assigned-clocks = <&cru 165>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; + + rk806single: rk806single@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 8>; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + + low_voltage_threshold = <3000>; + + shutdown_voltage_threshold = <2700>; + + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; +# 45 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi" + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-init-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: NLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; +# 15 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi" 1 + + + + + + +/ { + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + mmc2 = &sdio; + }; + + chosen: chosen { + bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait rcupdate.rcu_expedited=1 rcu_nocbs=all"; + }; + + cspmu: cspmu@fd10c000 { + compatible = "rockchip,cspmu"; + reg = <0x0 0xfd10c000 0x0 0x1000>, + <0x0 0xfd10d000 0x0 0x1000>, + <0x0 0xfd10e000 0x0 0x1000>, + <0x0 0xfd10f000 0x0 0x1000>, + <0x0 0xfd12c000 0x0 0x1000>, + <0x0 0xfd12d000 0x0 0x1000>, + <0x0 0xfd12e000 0x0 0x1000>, + <0x0 0xfd12f000 0x0 0x1000>; + }; + + debug: debug@fd104000 { + compatible = "rockchip,debug"; + reg = <0x0 0xfd104000 0x0 0x1000>, + <0x0 0xfd105000 0x0 0x1000>, + <0x0 0xfd106000 0x0 0x1000>, + <0x0 0xfd107000 0x0 0x1000>, + <0x0 0xfd124000 0x0 0x1000>, + <0x0 0xfd125000 0x0 0x1000>, + <0x0 0xfd126000 0x0 0x1000>, + <0x0 0xfd127000 0x0 0x1000>; + }; + + fiq_debugger: fiq-debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <1500000>; + interrupts = <0 423 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + + }; + }; + + minidump: minidump { + compatible = "rockchip,minidump"; + smem-region = <&minidump_smem>; + minidump-region = <&minidump_mem>; + status = "disabled"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 (8 * 0x100000)>; + linux,cma-default; + }; + + drm_logo: drm-logo@00000000 { + compatible = "rockchip,drm-logo"; + reg = <0x0 0x0 0x0 0x0>; + }; + + drm_cubic_lut: drm-cubic-lut@00000000 { + compatible = "rockchip,drm-cubic-lut"; + reg = <0x0 0x0 0x0 0x0>; + }; + + ramoops: ramoops@110000 { + compatible = "ramoops"; + + reg = <0x0 0x110000 0x0 0xe0000>; + boot-log-size = <0x8000>; + boot-log-count = <0x1>; + console-size = <0x80000>; + pmsg-size = <0x30000>; + ftrace-size = <0x00000>; + record-size = <0x14000>; + }; + + minidump_smem: minidump-smem@1f0000 { + reg = <0x0 0x1f0000 0x0 0x100>; + no-map; + status = "disabled"; + }; + + minidump_mem: minidump-mem@c000000 { + reg = <0x0 0x0c000000 0x0 0x2000000>; + no-map; + status = "disabled"; + }; + + }; +}; + +&display_subsystem { + memory-region = <&drm_logo>; + memory-region-names = "drm-logo"; +}; + +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + center-supply = <&vdd_ddr_s0>; + mem-supply = <&vdd_log_s0>; +}; + +&rng { + status = "okay"; +}; +# 16 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2 + +/ { + model = "Rockchip RK3588 EVB4 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + /delete-node/ panel@0; + ports { + /delete-node/ port@1; + }; +}; + +&dsi1 { + status = "disabled"; + /delete-node/ panel@0; + ports { + /delete-node/ port@1; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 3 0>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 30 0>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 17 0>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + + +&fiq_debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; + interrupts = <0 423 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + + +/delete-node/ &backlight; +# 4 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi" 1 + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + goodix_ts:goodix_ts@5d { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + }; +}; +# 6 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rd-rk3588-lcd-gpio.dtsi" 1 + + +/ { + vcc3v3_lcd_n: vcc3v3-lcd0-n { + gpio = <&gpio4 18 0>; + }; + + backlight_mipi: backlight { + pwms = <&pwm1 0 25000 0>; + }; + + backlight_edp: backlight-edp { + pwms = <&pwm0 0 25000 0>; + }; + + backlight_lvds: backlight-lvds { + pwms = <&pwm0 0 25000 0>; + }; + +}; + + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + +&dsi0 { + status = "disabled"; + dsi0_panel: panel@0 { + status = "disabled"; + reset-gpios = <&gpio4 22 1>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + +&dsi1 { + status = "disabled"; + dsi1_panel: panel@0 { + status = "disabled"; + enable-gpios = <&gpio3 22 1>; + reset-gpios = <&gpio4 22 1>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 22 0 &pcfg_pull_none>; + }; + }; + + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 24 0 &pcfg_pull_up>; + }; + }; +}; + +&goodix_ts { + goodix_rst_gpio = <&gpio0 22 0>; + goodix_irq_gpio = <&gpio3 24 8>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; +}; +# 7 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi" 1 + +/ { + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + + lcd_device0 = "DSI-1"; + lcd_rotate0 = "0"; + + lcd_device1 = "HDMI-1"; + lcd_rotate1 = "0"; + + lcd_device2 = "HDMI-2"; + lcd_rotate2 = "0"; + + lcd_device3 = "DP-1"; + lcd_rotate3 = "0"; + + status = "okay"; + }; +}; +# 9 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi" 1 + +/ { + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 2 0>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + + + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = <27 8>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + <(((0) << 30) | ((1 << 26)) | ((((5000) / 50) & 0x3ff) << 10) | ((((1000) / 10) & 0x3ff) << 0))>; + source-pdos = + <(((0) << 30) | ((1 << 26)) | ((((5000) / 50) & 0x3ff) << 10) | ((((3000) / 10) & 0x3ff) << 0))>; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio3 28 0>; + sbu2-dc-gpios = <&gpio3 29 0>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&pinctrl { + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 27 0 &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 2 0 &pcfg_pull_none>; + }; + + }; +}; +# 12 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi" 1 + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + + + + + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + + + + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; +# 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-pcie2gmac-rk3588.dtsi" 1 +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + phys = <&combphy0_ps 2>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + reset-gpios = <&gpio4 2 0>; + status = "okay"; +}; +# 16 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi" 1 + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru 262>; + }; +}; + +&gmac1 { + + phy-mode = "rgmii-rxid"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio3 15 1>; + snps,reset-active-low; + + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout + ð1_pins>; + + tx_delay = <0x44>; + + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; +# 17 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-power-rk3588.dtsi" 1 + +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 5 0>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + +}; +# 20 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-pcie3.dtsi" 1 +/ { + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 14 0>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; +# 21 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-pcie-5g.dtsi" 1 +/{ + vdd_5G: vdd-5G{ + compatible = "regulator-fixed"; + regulator-name = "vdd_5G"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio4 4 0>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + phys = <&combphy2_psu 2>; + reset-gpios = <&gpio2 21 0>; + + modem-en-gpios = <&gpio2 14 0>; + pcie-waken-gpios = <&gpio3 21 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&modem_wakup>,<&modem_rst>,<&modem_pwr>,<&modem_en>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + + +&pinctrl { + modem { + modem_pwr: modem-pwr { + rockchip,pins = <4 4 0 &pcfg_pull_up>; + }; + modem_en: modem-en { + rockchip,pins = <2 14 0 &pcfg_pull_up>; + }; + modem_rst: modem-rst { + rockchip,pins = <2 21 0 &pcfg_pull_up>; + }; + modem_wakup: modem-wakup { + rockchip,pins = <3 21 0 &pcfg_pull_up>; + }; + }; +}; +# 22 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-audio-rt5640.dtsi" 1 + +/ { + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + rk_headset: rk-headset { + status = "okay"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 20 0>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + io-channels = <&saradc 4>; + hp-det-adc-value = <500>; + + spk-play-volume = <7>; + hp-play-volume = <15>; + capture-volume = <127>; + + + + }; +}; + + +&pinctrl { + rt5640_pinctrl { + hp_det:hp_det { + rockchip,pins = <1 20 0 &pcfg_pull_none>; + }; + }; +}; +# 25 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-wifi-bt-ap6275p-rk3588.dtsi" 1 + +/ { + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 20 1>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 0 0>; + BT,wake_gpio = <&gpio2 11 0>; + BT,wake_host_irq = <&gpio2 8 0>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 8 0>; + WIFI,poweren_gpio = <&gpio0 10 0>; + status = "okay"; + }; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie2x1l0 { + phys = <&combphy1_ps 2>; + reset-gpios = <&gpio1 12 0>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + + +&pinctrl { + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 20 0 &pcfg_pull_none>; + }; + bt_gpio: bt-gpio { + rockchip,pins = + <0 0 0 &pcfg_pull_none>, + <2 11 0 &pcfg_pull_up>, + <2 8 0 &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 8 0 &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 10 0 &pcfg_pull_up>; + }; + }; +}; +# 28 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi" 1 + +/ { + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + +}; + +&i2s7_8ch { + status = "okay"; +}; + + +&hdmirx_ctrler { + status = "okay"; + + + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 29 1>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim2_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda>; + pinctrl-names = "default"; +}; +# 31 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + + + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dcphy1.dtsi" 1 + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + dw9763_1: dw9763_1@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855_1@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru 257>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 8 0>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_1>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_ov13855_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru 257>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 8 1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_gc8034_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_1: imx415_1@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&cru 257>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 8 0>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out1: endpoint { + remote-endpoint = <&mipi_in_imx415_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov13855_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_1: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; +# 37 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dphy0.dtsi" 1 + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9763_2: dw9763_2@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_2: ov13855_2@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru 258>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 9 0>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_2>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ov13855_2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_2: gc8034_2@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru 258>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 9 1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out2: endpoint { + remote-endpoint = <&mipi_in_gc8034_2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_2: imx415_2@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru 258>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 9 1>; + + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out2: endpoint { + remote-endpoint = <&mipi_in_imx415_2>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ov13855_2: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out2>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_2: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; +# 38 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-camera-dphy1.dtsi" 1 + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9763_3: dw9763_3@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_3: ov13855_3@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru 259>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 10 0>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_3>; + port { + ov13855_out3: endpoint { + remote-endpoint = <&mipi_in_ov13855_3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_3: gc8034_3@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru 259>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 10 1>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out3: endpoint { + remote-endpoint = <&mipi_in_gc8034_3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_3: imx415_3@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&cru 259>; + clock-names = "xvclk"; + power-domains = <&power 27>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 10 0>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out3: endpoint { + remote-endpoint = <&mipi_in_imx415_3>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ov13855_3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out3>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_3: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out3>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_3: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out3>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds4 { + status = "okay"; + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; +# 39 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 65 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 1 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi" 1 +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; +# 2 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi" 1 +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + + +&hdptxphy_hdmi1 { + status = "okay"; +}; + + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; +}; +# 3 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2 +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi" 1 +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; +# 4 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2 +# 66 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 + + +# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" 1 + +&backlight_mipi { + compatible = "pwm-backlight"; + + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + + + + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <((1 << 0) | (1 << 1) | + (1 << 11) | (1 << 9))>; + dsi,format = <0>; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 + + 05 32 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 4D D0 02 00 05 05 35 00 01 08 32 + 08 5A 3C 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 29 0A 55 57 B5 + 06 00 00 00 41 22 10 00 01 00 0F + 00 2A 00 00 19 50 32 3C 78 94 D5 + 02 08 00 00 04 A2 40 00 8F 4A 00 + 80 55 00 73 61 00 67 70 00 67 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 + 06 08 0A 0F 10 12 FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF 8D 01 + ]; + }; +# 69 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 +# 89 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" +/ { + model = "dr4-rk3588"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 7 0>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; + running-time = <10000>; + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; +# 136 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" + led { + gpio_num = <&gpio4 6 0>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 17 0>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 10 0>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3c7 { + gpio_num = <&gpio3 23 0>; + gpio_function = <0>; + }; + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&can0 { + assigned-clocks = <&cru 112>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&can1 { + assigned-clocks = <&cru 114>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + + + + + + }; + +}; + + +&sdmmc { + status = "okay"; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/dr4-rk3588.dtb b/rk3588/dr4-rk3588.dtb new file mode 100644 index 0000000..73b0b0b Binary files /dev/null and b/rk3588/dr4-rk3588.dtb differ diff --git a/rk3588/dr4-rk3588.dts b/rk3588/dr4-rk3588.dts new file mode 100755 index 0000000..a9c01d8 --- /dev/null +++ b/rk3588/dr4-rk3588.dts @@ -0,0 +1,244 @@ +/* board base */ +//#include "../rk3588-evb4-lp4-v10-linux.dts" +#include "rp-rk3588-board.dtsi" + +#include "rp-tp-i2c6-gt911.dtsi" +#include "rd-rk3588-lcd-gpio.dtsi" + +#include "rpdzkj_config.dtsi" + +/* usb */ +#include "rp-usb-typec-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588.dtsi" +#include "rp-eth-gmac1.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588.dtsi" +#include "rp-pcie3.dtsi" //need comment when use board of make it youself,and remove the pcie function +#include "rp-pcie-5g.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rk3588.dtsi" + +/* hdmi rx */ +#include "rp-hdmirx.dtsi" + +/* camera */ +/***********all camera config********/ + +//#include "rp-camera-dcphy0.dtsi" +#include "rp-camera-dcphy1.dtsi" +#include "rp-camera-dphy0.dtsi" +#include "rp-camera-dphy1.dtsi" + +//#include "rp-camera-dcphy0-ov13855.dtsi" +//#include "rp-camera-dcphy1-ov13855.dtsi" +//#include "rp-camera-dphy0-ov13855.dtsi" +//#include "rp-camera-dphy1-ov13855.dtsi" + +//#include "rp-camera-dcphy0-gc8034.dtsi" +//#include "rp-camera-dcphy1-gc8034.dtsi" +//#include "rp-camera-dphy0-gc8034.dtsi" +//#include "rp-camera-dphy1-gc8034.dtsi" + +//#include "rp-camera-dcphy0-imx415.dtsi" +//#include "rp-camera-dcphy1-imx415.dtsi" +//#include "rp-camera-dphy0-imx415.dtsi" +//#include "rp-camera-dphy1-imx415.dtsi" + +/**********4 channel must be disabled hdmi in*********/ +//#include "rp-camera-dcphy1-gc8034.dtsi" +//#include "rp-camera-dphy1-gc8034.dtsi" +//#include "rp-camera-dcphy0-imx415.dtsi" +//#include "rp-camera-dphy0-imx415.dtsi" +/******************************************/ + +//#include "rp-lcd-hdmi0.dtsi" //batch ignore +//#include "rp-lcd-hdmi1.dtsi" //batch ignore +//#include "rp-lcd-typec-dp0.dtsi" //usb edp0, must be enable rp-usb-typec.dtsi, batch ignore +#include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" + +/* lcd */ +#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" +//#include "rp-lcd-edp0-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-edp1-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" + +/* mulit lcd */ +//#include "rp-multi-lcd-edp0-13.3-edp1-13.3-dp0.dtsi" +//#include "rp-multi-lcd-edp0-13.3-edp1-15.6-dp0.dtsi" + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-edp1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi" +/ { + model = "dr4-rk3588"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + //fan { + // gpio_num = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3c7 { + gpio_num = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + + +&sdmmc { + status = "okay"; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/nano-rk3588.dts b/rk3588/nano-rk3588.dts new file mode 100755 index 0000000..962798d --- /dev/null +++ b/rk3588/nano-rk3588.dts @@ -0,0 +1,295 @@ +/* board base */ +//#include "../rk3588-evb4-lp4-v10-linux.dts" +#include "rp-rk3588-board.dtsi" + +#include "rp-tp-i2c6-gt911.dtsi" +#include "rd-rk3588-lcd-gpio.dtsi" +#include "rpdzkj_config.dtsi" + +/* usb */ +#include "rp-usb-typea-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588.dtsi" +#include "rp-eth-gmac1.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588.dtsi" +#include "rp-pcie-m2.dtsi" + +/* audio */ +#include "rp-audio-es8311.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rk3588.dtsi" + +/* hdmi rx */ +#include "rp-hdmirx.dtsi" + +/* camera */ +//#include "rp-camera-dual-ov13855.dtsi" + + +//#include "rp-lcd-hdmi0.dtsi" //batch ignore +//#include "rp-lcd-hdmi1.dtsi" //batch ignore +#include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" + +/* lcd */ +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi" + +/ { + model = "nano-rk3588"; + compatible = "rpdzkj,nano-rk3588", "rockchip,rk3588"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + + vdd_3v3_5v_control: vdd_3v3_5v_control { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_5v_control"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; //In the uboot phase fixed.c resolves gpio + gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_control>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + //fan { + // gpio_num = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg-power { + gpio_num = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd-4g { //4g enable + gpio_num = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + VDD_USB2_0 { + gpio_num = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + VDD_USB2_1 { + gpio_num = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + spk_en { //spk enable + gpio_num = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + spk_mute { //spk mute + gpio_num = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio4b2 { + gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4b3 { + gpio_num = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + vdd5v_uart { + gpio_num = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + vdd3v3_uart { + gpio_num = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + }; + +}; + +&pinctrl { + power_control{ + vdd_control: vdd_control { + rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&vcc3v3_pcie30 { + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + + + +/*uart6 > RS485*/ +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; +}; + +&sdmmc { + status = "okay"; + //vmmc-supply = <&vccio_sd_s0>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/rd-box-rk3588.dts b/rk3588/rd-box-rk3588.dts new file mode 100755 index 0000000..7c3637d --- /dev/null +++ b/rk3588/rd-box-rk3588.dts @@ -0,0 +1,295 @@ +/* board base */ +//#include "../rk3588-evb4-lp4-v10-linux.dts" +#include "rp-rk3588-board.dtsi" + +#include "rp-tp-i2c6-gt911.dtsi" +#include "rd-rk3588-lcd-gpio.dtsi" +#include "rpdzkj_config.dtsi" + +/* usb */ +#include "rp-usb-typea-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588.dtsi" +#include "rp-eth-gmac1.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588.dtsi" +#include "rp-pcie-5g.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rk3588.dtsi" + + +/* camera */ +//#include "rp-camera-dual-ov13855.dtsi" + + +#include "rp-lcd-hdmi0.dtsi" + +/* lcd */ +#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-box-edp1-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" + + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi" + + +/ { + model = "rd-box-rk3588"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + //fan { + // gpio_num = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + otg-power { + gpio_num = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio3c7 { + gpio_num = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0d3 { + gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3c4 { + gpio_num = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3c5 { + gpio_num = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3d5 { + gpio_num = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4b2 { + gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4b3 { + gpio_num = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; +/*** already use for spi0 + gpio3d1 { + gpio_num = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3d3 { + gpio_num = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3d2 { + gpio_num = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3d4 { + gpio_num = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; +***/ + }; + + rp-keys { + compatible = "rp-keys"; + status = "disabled"; + label = "rp_gpiokeys"; + + gpio4b3 { + gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + }; + gpio0d3 { + label = "gpio0d3_key"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + wakeup; + debounce_interval = <10>; + press_type = <0>; + code = ; + }; + }; + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + + +&i2c3{ + status="okay"; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0m3_cs0 &spi0m3_pins>; + num-cs = <1>; + spidev@0 { + status = "okay"; + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +&sdmmc { + status = "okay"; + // vmmc-supply = <&vccio_sd_s0>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/rd-rk3588-ahd.dts b/rk3588/rd-rk3588-ahd.dts new file mode 100755 index 0000000..085981b --- /dev/null +++ b/rk3588/rd-rk3588-ahd.dts @@ -0,0 +1,330 @@ +/* board base */ +//#include "../rk3588-evb4-lp4-v10-linux.dts" +#include "rp-rk3588-board.dtsi" + +#include "rp-tp-i2c6-gt911.dtsi" +#include "rd-rk3588-lcd-gpio.dtsi" +#include "rpdzkj_config.dtsi" + +/* usb */ +#include "rp-usb-typea-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588.dtsi" +#include "rp-eth-gmac1.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rk3588.dtsi" + +/* camera */ +#include "rp-camera-dcphy0-mipi-xs9922b.dtsi" +#include "rp-camera-dcphy1-mipi-xs9922b.dtsi" + +#include "rp-lcd-hdmi0.dtsi" + +/* lcd */ +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-7-1024-600.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" +//#include "rp-lcd-box-edp1-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi" +/ { + model = "rd-rk3588-ahd"; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_m2: vcc3v3-m2 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_m2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + stm706 { + status = "okay"; + compatible = "stm706"; + reset_gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + wdt_gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + //fan { + // gpio_num = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vbus5v0_typec { + gpio_num = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + gps { + gpio_num = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + 4G { + gpio_num = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb_to_serial { + gpio_num = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + serial_5v { + gpio_num = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + + }; + + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio0d3 { + gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3c4 { + gpio_num = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio3c5 { + gpio_num = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3c7 { + gpio_num = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3d5 { + gpio_num = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4b2 { + gpio_num = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4b3 { + gpio_num = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4b6 { + gpio_num = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio2b2 { + gpio_num = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4c3 { + gpio_num = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio2b7 { + gpio_num = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio2c3 { + gpio_num = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + }; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "gpio3c4", "gpio3c5", "", "gpio3c7", + "", "", "", "", "", "gpio3d5", "", ""; +}; + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +// 485 +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0m3_pins &spi0m3_cs0>; + + spi0_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + +// M2.0 +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + phys = <&combphy2_psu PHY_TYPE_PCIE>; + status = "okay"; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + + +&i2c3{ + status="okay"; +}; + +&sdmmc { + status = "okay"; + // vmmc-supply = <&vccio_sd_s0>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/rd-rk3588-lcd-gpio.dtsi b/rk3588/rd-rk3588-lcd-gpio.dtsi new file mode 100755 index 0000000..aaf5350 --- /dev/null +++ b/rk3588/rd-rk3588-lcd-gpio.dtsi @@ -0,0 +1,74 @@ + + +/ { + vcc3v3_lcd_n: vcc3v3-lcd0-n { + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + }; + + backlight_mipi: backlight { + pwms = <&pwm1 0 25000 0>; + }; + + backlight_edp: backlight-edp { + pwms = <&pwm0 0 25000 0>; + }; + + backlight_lvds: backlight-lvds { + pwms = <&pwm0 0 25000 0>; + }; + +}; + + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0m1_pins>; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + +&dsi0 { + status = "disabled"; + dsi0_panel: panel@0 { + status = "disabled"; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + +&dsi1 { + status = "disabled"; + dsi1_panel: panel@0 { + status = "disabled"; + enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&goodix_ts { + goodix_rst_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PD0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; +}; diff --git a/rk3588/rd-rk3588.dts b/rk3588/rd-rk3588.dts new file mode 100755 index 0000000..7cc39ad --- /dev/null +++ b/rk3588/rd-rk3588.dts @@ -0,0 +1,265 @@ +/* board base */ +//#include "../rk3588-evb4-lp4-v10-linux.dts" +#include "rp-rk3588-board.dtsi" + +#include "rp-tp-i2c6-gt911.dtsi" +#include "rd-rk3588-lcd-gpio.dtsi" +#include "rpdzkj_config.dtsi" + +/* usb */ +#include "rp-usb-typec-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588.dtsi" +#include "rp-eth-gmac1.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588.dtsi" +#include "rp-pcie3.dtsi" //need comment when use board of make it youself,and remove the pcie function +#include "rp-pcie-5g.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rk3588.dtsi" + +/* hdmi rx */ +#include "rp-hdmirx.dtsi" + +/* mipi camera */ +/* use dcphy0 camera , need to disabled rp-hdmirx.dtsi*/ +/***********all camera config********/ + + +//#include "rp-camera-dcphy0.dtsi" +#include "rp-camera-dcphy1.dtsi" +#include "rp-camera-dphy0.dtsi" +#include "rp-camera-dphy1.dtsi" + +//#include "rp-camera-dcphy0-ov13855.dtsi" +//#include "rp-camera-dcphy1-ov13855.dtsi" +//#include "rp-camera-dphy0-ov13855.dtsi" +//#include "rp-camera-dphy1-ov13855.dtsi" + +//#include "rp-camera-dcphy0-gc8034.dtsi" +//#include "rp-camera-dcphy1-gc8034.dtsi" +//#include "rp-camera-dphy0-gc8034.dtsi" +//#include "rp-camera-dphy1-gc8034.dtsi" + +//#include "rp-camera-dcphy0-imx415.dtsi" +//#include "rp-camera-dcphy1-imx415.dtsi" +//#include "rp-camera-dphy0-imx415.dtsi" +//#include "rp-camera-dphy1-imx415.dtsi" + +/**********4 channel must be disabled hdmi in*********/ +//#include "rp-camera-dcphy1-gc8034.dtsi" +//#include "rp-camera-dphy1-gc8034.dtsi" +//#include "rp-camera-dcphy0-imx415.dtsi" +//#include "rp-camera-dphy0-imx415.dtsi" +/******************************************/ + +//#include "rp-lcd-hdmi0.dtsi" //batch ignore +//#include "rp-lcd-hdmi1.dtsi" //batch ignore +//#include "rp-lcd-typec-dp0.dtsi" //usb edp0,must be enable rp-usb-typec.dtsi, batch ignore +#include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" + +/* lcd */ +#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" +//#include "rp-lcd-edp0-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-edp1-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" + +/* edp */ +//#include "rp-multi-lcd-edp0-13.3-edp1-13.3-dp0.dtsi" +//#include "rp-multi-lcd-edp0-13.3-edp1-15.6-dp0.dtsi" + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-edp1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi" + +/ { + model = "rd-rk3588"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + //fan { + // gpio_num = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + +/* gpio4a4 { + gpio_num = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a5 { + gpio_num = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio4a6 { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; +*/ + gpio3c6 { + gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + + + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + + +&sdmmc { + status = "okay"; + //vmmc-supply = <&vccio_sd_s0>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; + diff --git a/rk3588/rd-rk3588s-ahd-lcd-gpio.dtsi b/rk3588/rd-rk3588s-ahd-lcd-gpio.dtsi new file mode 100644 index 0000000..23a6c3a --- /dev/null +++ b/rk3588/rd-rk3588s-ahd-lcd-gpio.dtsi @@ -0,0 +1,75 @@ + +/ { + vcc3v3_lcd_n: vcc3v3_lcd0_n { + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_lcd: vcc3v3_lcd { + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + backlight_mipi: backlight_mipi { + pwms = <&pwm12 0 25000 0>; + }; + + backlight_edp: backlight_edp { + pwms = <&pwm12 0 25000 0>; + }; + + backlight_lvds: backlight_lvds { + pwms = <&pwm1 0 25000 0>; + }; +}; + + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + + +&dsi0 { + status = "disabled"; + dsi0_panel: panel@0 { + status = "disabled"; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + +&dsi1 { + status = "disabled"; + dsi1_panel: panel@0 { + status = "disabled"; + reset-gpios = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&goodix_ts { + goodix_rst_gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio1 RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; +}; diff --git a/rk3588/rd-rk3588s-ahd.dts b/rk3588/rd-rk3588s-ahd.dts new file mode 100755 index 0000000..bd7a97c --- /dev/null +++ b/rk3588/rd-rk3588s-ahd.dts @@ -0,0 +1,337 @@ +/* board base */ +//#include "rk3588s-evb4-lp4x-v10.dts" +#include "rp-rk3588s-board.dtsi" + +#include "rp-tp-i2c4-gt911.dtsi" +#include "rd-rk3588s-ahd-lcd-gpio.dtsi" + +/* usb */ +#include "rp-usb-typea-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-gmac1.dtsi" +#include "rp-eth-pcie2gmac-rk3588s.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588s.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rd-rk3588s-ahd.dtsi" + +/* camera */ +#include "rp-camera-dcphy0-mipi-xs9922b-rk3588s.dtsi" +#include "rp-camera-dcphy1-mipi-xs9922b-rk3588s.dtsi" +//#include "rp-camera-dphy0-imx415-rk3588s.dtsi" + +#include "rp-lcd-hdmi0.dtsi" + +/* mipi lcd */ +//#include "rp-lcd-mipi0-5-720-1280-v2.dtsi" +//#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +#include "rp-lcd-mipi0-7-1024-600.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v2-JC101HD131.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" + +/* edp lcd */ +//#include "rp-lcd-rk3588s-edp0-13.3-15.6-1920-1080.dtsi" + +/* mipi_to_lvds lcd */ +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" + + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi" +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi" + + + +/ { + model = "rd-rk3588s-ahd"; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vdd_ADP5585: vdd_ADP5585 { //vdd_5v vdd_3v3 enable + compatible = "regulator-fixed"; + regulator-name = "vdd_ADP5585"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; //注æ„驱动解æžçš„是gpio还是gpios + gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_ADP5585_control>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 +/* + vdd_5v_3v3 { + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; +*/ + //fan { + // gpio_num = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + otg_vdd5v { + gpio_num = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + sd-pwren { + gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd_gps { //gpio_r0 + gpio_num = <&adp5585_gpio 0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + vdd_4g { //gpio_r1 + gpio_num = <&adp5585_gpio 1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio_r2 { + gpio_num = <&adp5585_gpio 2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_r3 { + gpio_num = <&adp5585_gpio 3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_r4 { + gpio_num = <&adp5585_gpio 4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_c0 { + gpio_num = <&adp5585_gpio 5 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_c1 { + gpio_num = <&adp5585_gpio 6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_c2 { + gpio_num = <&adp5585_gpio 7 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_c3 { + gpio_num = <&adp5585_gpio 8 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio_c4 { + gpio_num = <&adp5585_gpio 9 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; +}; + + +&uart5 { //485 + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; +}; + +&sdmmc { + status = "okay"; + /delete-property/ vmmc-supply; +}; + +&rk_headset { + headset_gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; +}; + + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + }; + + adp5585: mfd-gpio@34 { + compatible = "adi,adp5585"; + reg = <0x34>; + status = "okay"; + + adp5585_gpio: gpio-normal@34 { + compatible = "adp5585-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + // adp5585pwm: pwm@34 { + // compatible = "adp5585-pwm"; + // #pwm-cells = <3>; + // }; + }; +}; + +&dmc { + status = "disabled"; +}; + +&pinctrl { + vdd-ADP5585 { + vdd_ADP5585_control: vdd-ADP5585-control { + rockchip,pins = + /** power supply enable pin */ + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/rp-audio-es8311.dtsi b/rk3588/rp-audio-es8311.dtsi new file mode 100755 index 0000000..070d3b5 --- /dev/null +++ b/rk3588/rp-audio-es8311.dtsi @@ -0,0 +1,47 @@ + +/ { + i2s0_sound: i2s0-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8311"; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8311>; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + es8311: es8311@18 { + status = "okay"; + compatible = "everest,es8311"; + reg = <0x18>; + #sound-dai-cells = <0>; + adc-pga-gain = <6>; /* 18dB */ + adc-volume = <0xbf>; /* 0dB */ + dac-volume = <0xbf>; /* 0dB */ + aec-mode = "adc left, adc right"; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; +// assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + // assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; +}; + diff --git a/rk3588/rp-audio-rt5640.dtsi b/rk3588/rp-audio-rt5640.dtsi new file mode 100755 index 0000000..c0799ba --- /dev/null +++ b/rk3588/rp-audio-rt5640.dtsi @@ -0,0 +1,71 @@ + +/ { + rt5640-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,rt5640-codec"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Mic Jack", "MICBIAS1", + "IN1P", "Mic Jack", + "Headphone Jack", "HPOL", + "Headphone Jack", "HPOR"; + simple-audio-card,cpu { + sound-dai = <&i2s0_8ch>; + }; + simple-audio-card,codec { + sound-dai = <&rt5640>; + }; + }; + + rk_headset: rk-headset { + status = "okay"; + compatible = "rockchip_headset"; + headset_gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + }; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + rt5640: rt5640@1c { + #sound-dai-cells = <0>; + compatible = "realtek,rt5640"; + reg = <0x1c>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + realtek,in1-differential; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + io-channels = <&saradc 4>; + hp-det-adc-value = <500>; + + spk-play-volume = <7>; ////63-0 min-max + hp-play-volume = <15>; ////63-0 min-max + capture-volume = <127>; //0-127 min-max + + // assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; +// assigned-clock-rates = <12288000>; + }; +}; + + +&pinctrl { + rt5640_pinctrl { + hp_det:hp_det { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dcphy0-gc8034.dtsi b/rk3588/rp-camera-dcphy0-gc8034.dtsi new file mode 100755 index 0000000..3f54227 --- /dev/null +++ b/rk3588/rp-camera-dcphy0-gc8034.dtsi @@ -0,0 +1,152 @@ + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + +vm149c_0: vm149c_0@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <20>; // 马达的å¯åŠ¨ç”µæµ + rockchip,vcm-rated-current = <100>; // 马达的é¢å®šç”µæµ + rockchip,vcm-step-mode = <13>; // 马达驱动 ic 的电æµè¾“å‡ºæ¨¡å¼ + rockchip,camera-module-index = <0>; // æ¨¡ç»„ç¼–å· + rockchip,camera-module-facing = "back"; // 模组æœå‘，有"back"å’Œ"front" +}; + + gc8034_0: gc8034_0@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + lens-focus = <&vm149c_0>; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + + + diff --git a/rk3588/rp-camera-dcphy0-imx415.dtsi b/rk3588/rp-camera-dcphy0-imx415.dtsi new file mode 100644 index 0000000..e03d229 --- /dev/null +++ b/rk3588/rp-camera-dcphy0-imx415.dtsi @@ -0,0 +1,161 @@ +/ +{ + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + + imx415_0: imx415_0@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + // reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + + +&pinctrl { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PA7 3 &pcfg_pull_down>; + }; +}; diff --git a/rk3588/rp-camera-dcphy0-mipi-xs9922b-rk3588s.dtsi b/rk3588/rp-camera-dcphy0-mipi-xs9922b-rk3588s.dtsi new file mode 100755 index 0000000..0502ab8 --- /dev/null +++ b/rk3588/rp-camera-dcphy0-mipi-xs9922b-rk3588s.dtsi @@ -0,0 +1,261 @@ +/** + * mipi csi to xs9922b config + */ +#define RP_DOUBLE_XS9922B +#define RP_CAMERA_XS9922B + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + + xs9922_0: xs9922_0@31 { + compatible = "xs9922"; + status = "okay"; + reg = <0x31>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&xs9922_pwr_0>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,default_rect= <1920 1080>; + port { + xs9922_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pinctrl { + xs9922_0 { + xs9922_pwr_0: camera-pwr-0 { + rockchip,pins = + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + + + + +&mipi_dcphy0 { + status = "okay"; +}; + + + + + + + + + + +// CIF + + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&xs9922_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in0>; + }; + + }; + }; +}; + + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + + + +#if 0 + +// isp +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + + +#endif + + + + +#if 0 + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + + +&rkisp_unite { + status = "okay"; +}; + +&rkisp_unite_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + */ + rockchip,hw = <&rkisp_unite>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; +/* + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + */ + }; +}; + + +#endif diff --git a/rk3588/rp-camera-dcphy0-mipi-xs9922b.dtsi b/rk3588/rp-camera-dcphy0-mipi-xs9922b.dtsi new file mode 100755 index 0000000..d85d9c6 --- /dev/null +++ b/rk3588/rp-camera-dcphy0-mipi-xs9922b.dtsi @@ -0,0 +1,239 @@ +/** + * mipi csi to xs9922b config + */ + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + + xs9922: xs9922@31 { + compatible = "xs9922"; + status = "okay"; + reg = <0x31>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&xs9922_pwr>; + reset-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,default_rect= <1280 720>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pinctrl { + xs9922 { + xs9922_pwr: camera-pwr { + rockchip,pins = + <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + + + +&mipi_dcphy0 { + status = "okay"; +}; + +// CIF +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + + }; + }; +}; + + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + + + +#if 0 + +// isp +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "disabled"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; +#endif + +#if 0 +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + + +&rkisp_unite { + status = "okay"; +}; + +&rkisp_unite_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + */ + rockchip,hw = <&rkisp_unite>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; +#endif diff --git a/rk3588/rp-camera-dcphy0-ov13855.dtsi b/rk3588/rp-camera-dcphy0-ov13855.dtsi new file mode 100644 index 0000000..17f2e0c --- /dev/null +++ b/rk3588/rp-camera-dcphy0-ov13855.dtsi @@ -0,0 +1,155 @@ + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + dw9763_0: dw9763_0@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_0: ov13855_0@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_0>; + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + + + diff --git a/rk3588/rp-camera-dcphy0.dtsi b/rk3588/rp-camera-dcphy0.dtsi new file mode 100755 index 0000000..f327e0b --- /dev/null +++ b/rk3588/rp-camera-dcphy0.dtsi @@ -0,0 +1,211 @@ + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + dw9763_0: dw9763_0@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_0: ov13855_0@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_0>; + port { + ov13855_out0: endpoint { + remote-endpoint = <&mipi_in_ov13855_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_0: gc8034_0@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out0: endpoint { + remote-endpoint = <&mipi_in_gc8034_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_0: imx415_0@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera1_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;//modify camera addr 0x1a + // reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out0: endpoint { + remote-endpoint = <&mipi_in_imx415_0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + + +&mipi_dcphy0 { + status = "okay"; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov13855_0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_0: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out0>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_0: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + + + diff --git a/rk3588/rp-camera-dcphy1-gc8034.dtsi b/rk3588/rp-camera-dcphy1-gc8034.dtsi new file mode 100755 index 0000000..6d4de86 --- /dev/null +++ b/rk3588/rp-camera-dcphy1-gc8034.dtsi @@ -0,0 +1,152 @@ + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + +vm149c_1: vm149c_1@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <20>; // 马达的å¯åŠ¨ç”µæµ + rockchip,vcm-rated-current = <100>; // 马达的é¢å®šç”µæµ + rockchip,vcm-step-mode = <13>; // 马达驱动 ic 的电æµè¾“å‡ºæ¨¡å¼ + rockchip,camera-module-index = <1>; // æ¨¡ç»„ç¼–å· + rockchip,camera-module-facing = "front"; // 模组æœå‘，有"back"å’Œ"front" +}; + + + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + lens-focus = <&vm149c_1>; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dcphy1-imx415.dtsi b/rk3588/rp-camera-dcphy1-imx415.dtsi new file mode 100644 index 0000000..eb6dd72 --- /dev/null +++ b/rk3588/rp-camera-dcphy1-imx415.dtsi @@ -0,0 +1,140 @@ + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + + imx415_1: imx415_1@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dcphy1-mipi-xs9922b-rk3588s.dtsi b/rk3588/rp-camera-dcphy1-mipi-xs9922b-rk3588s.dtsi new file mode 100755 index 0000000..99dc2a2 --- /dev/null +++ b/rk3588/rp-camera-dcphy1-mipi-xs9922b-rk3588s.dtsi @@ -0,0 +1,194 @@ +/** + * mipi csi to xs9922b config + */ +#define RP_CAMERA_XS9922B + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + + xs9922_1: xs9922_1@30 { + compatible = "xs9922"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&xs9922_pwr_1>; + reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; +// power-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,default_rect= <1280 720>; + port { + xs9922_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +#ifndef RP_DOUBLE_XS9922B //rd-rk3588s-ahd share the same power-gpio +&xs9922_1 { + power-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + +&pinctrl { + xs9922_1 { + xs9922_pwr_1: camera-pwr-1 { + rockchip,pins = + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; + +#else +&pinctrl { + xs9922_1 { + xs9922_pwr_1: camera-pwr-1 { + rockchip,pins = + <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + }; +#endif + + +&mipi_dcphy1 { + status = "okay"; +}; + + + + + + + + + + +// CIF + + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&xs9922_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + + }; + }; +}; + + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; diff --git a/rk3588/rp-camera-dcphy1-mipi-xs9922b.dtsi b/rk3588/rp-camera-dcphy1-mipi-xs9922b.dtsi new file mode 100755 index 0000000..aa5fc04 --- /dev/null +++ b/rk3588/rp-camera-dcphy1-mipi-xs9922b.dtsi @@ -0,0 +1,152 @@ + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + + xs9922_1: xs9922@30 { + compatible = "xs9922"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&xs9922_pwr_1>; + reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,default_rect= <1280 720>; + port { + ucam_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pinctrl { + xs9922 { + xs9922_pwr_1: camera-pwr_1 { + rockchip,pins = + <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dcphy1-ov13855.dtsi b/rk3588/rp-camera-dcphy1-ov13855.dtsi new file mode 100644 index 0000000..d49e501 --- /dev/null +++ b/rk3588/rp-camera-dcphy1-ov13855.dtsi @@ -0,0 +1,154 @@ + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + dw9763_1: dw9763_1@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855_1@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_1>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dcphy1.dtsi b/rk3588/rp-camera-dcphy1.dtsi new file mode 100755 index 0000000..d937760 --- /dev/null +++ b/rk3588/rp-camera-dcphy1.dtsi @@ -0,0 +1,208 @@ + + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + dw9763_1: dw9763_1@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_1: ov13855_1@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_1>; + port { + ov13855_out1: endpoint { + remote-endpoint = <&mipi_in_ov13855_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_1: gc8034_1@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out1: endpoint { + remote-endpoint = <&mipi_in_gc8034_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_1: imx415_1@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera2_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;//modify camera addr 0x37 + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out1: endpoint { + remote-endpoint = <&mipi_in_imx415_1>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&mipi_dcphy1 { + status = "okay"; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov13855_1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out1>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_1: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out1>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_1: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out1>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@0 { + reg = <0>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@1 { + reg = <1>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi_lvds1_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds1_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy0-gc8034.dtsi b/rk3588/rp-camera-dphy0-gc8034.dtsi new file mode 100755 index 0000000..379c9bf --- /dev/null +++ b/rk3588/rp-camera-dphy0-gc8034.dtsi @@ -0,0 +1,140 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + +vm149c_2: vm149c_2@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <20>; // 马达的å¯åŠ¨ç”µæµ + rockchip,vcm-rated-current = <100>; // 马达的é¢å®šç”µæµ + rockchip,vcm-step-mode = <13>; // 马达驱动 ic 的电æµè¾“å‡ºæ¨¡å¼ + rockchip,camera-module-index = <2>; // æ¨¡ç»„ç¼–å· + rockchip,camera-module-facing = "back"; // 模组æœå‘，有"back"å’Œ"front" +}; + + gc8034_2: gc8034_2@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + lens-focus = <&vm149c_2>; + port { + gc8034_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy0-imx415-rk3588s.dtsi b/rk3588/rp-camera-dphy0-imx415-rk3588s.dtsi new file mode 100755 index 0000000..e39e8a3 --- /dev/null +++ b/rk3588/rp-camera-dphy0-imx415-rk3588s.dtsi @@ -0,0 +1,162 @@ + +#ifndef RP_CAMERA_XS9922B +/{ + vcc_camera: vcc-camera-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera_pwr>; + regulator-name = "vcc_camera"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + + &pinctrl { + camera_pwr: camera-pwr { + rockchip,pins = + /* camera power en */ + <4 RK_PB0 3 &pcfg_pull_down>; + }; + }; +#endif + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + + imx415_2: imx415_2@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_CIFOUT_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "BACK"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy0-imx415.dtsi b/rk3588/rp-camera-dphy0-imx415.dtsi new file mode 100644 index 0000000..de7fecc --- /dev/null +++ b/rk3588/rp-camera-dphy0-imx415.dtsi @@ -0,0 +1,129 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + + imx415_2: imx415_2@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; +// pwdn-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy0-ov13855.dtsi b/rk3588/rp-camera-dphy0-ov13855.dtsi new file mode 100644 index 0000000..3779a4d --- /dev/null +++ b/rk3588/rp-camera-dphy0-ov13855.dtsi @@ -0,0 +1,143 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9763_2: dw9763_2@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_2: ov13855_2@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_2>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ucam2>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam2: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy0.dtsi b/rk3588/rp-camera-dphy0.dtsi new file mode 100755 index 0000000..a258508 --- /dev/null +++ b/rk3588/rp-camera-dphy0.dtsi @@ -0,0 +1,198 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9763_2: dw9763_2@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + }; + + ov13855_2: ov13855_2@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_2>; + port { + ov13855_out2: endpoint { + remote-endpoint = <&mipi_in_ov13855_2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_2: gc8034_2@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out2: endpoint { + remote-endpoint = <&mipi_in_gc8034_2>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_2: imx415_2@1a { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x1a>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera3_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>; //modify camera addr 0x1a + // reset-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <2>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out2: endpoint { + remote-endpoint = <&mipi_in_imx415_2>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&csi2_dphy0 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ov13855_2: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out2>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_2: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out2>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_2: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out2>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&mipi2_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi2_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir0>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir0 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy1-gc8034.dtsi b/rk3588/rp-camera-dphy1-gc8034.dtsi new file mode 100755 index 0000000..2e85003 --- /dev/null +++ b/rk3588/rp-camera-dphy1-gc8034.dtsi @@ -0,0 +1,142 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + +vm149c_3: vm149c_3@0c { + compatible = "silicon touch,vm149c"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <20>; // 马达的å¯åŠ¨ç”µæµ + rockchip,vcm-rated-current = <100>; // 马达的é¢å®šç”µæµ + rockchip,vcm-step-mode = <13>; // 马达驱动 ic 的电æµè¾“å‡ºæ¨¡å¼ + rockchip,camera-module-index = <3>; // æ¨¡ç»„ç¼–å· + rockchip,camera-module-facing = "back"; // 模组æœå‘，有"back"å’Œ"front" +}; + + + gc8034_3: gc8034_3@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + lens-focus = <&vm149c_3>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + + port { + gc8034_out3: endpoint { + remote-endpoint = <&mipi_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&gc8034_out3>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds4 { + status = "okay"; + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy1-imx415.dtsi b/rk3588/rp-camera-dphy1-imx415.dtsi new file mode 100644 index 0000000..c1f8b69 --- /dev/null +++ b/rk3588/rp-camera-dphy1-imx415.dtsi @@ -0,0 +1,147 @@ +/{ + vcc_camera_4: vcc-camera_4-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&camera4_pwr>; + regulator-name = "vcc_camera4"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; +}; + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + + imx415_3: imx415_3@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; +// pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out3: endpoint { + remote-endpoint = <&mipi_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&imx415_out3>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds4 { + status = "okay"; + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; +&pinctrl { + camera4_pwr: camera4_pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 3 &pcfg_pull_up>; + }; +}; diff --git a/rk3588/rp-camera-dphy1-ov13855.dtsi b/rk3588/rp-camera-dphy1-ov13855.dtsi new file mode 100644 index 0000000..b8979f0 --- /dev/null +++ b/rk3588/rp-camera-dphy1-ov13855.dtsi @@ -0,0 +1,143 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9763_3: dw9763_3@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_3: ov13855_3@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_3>; + port { + ov13855_out3: endpoint { + remote-endpoint = <&mipi_in_ucam3>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ucam3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out3>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds4 { + status = "okay"; + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir1>; + }; + }; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-dphy1.dtsi b/rk3588/rp-camera-dphy1.dtsi new file mode 100755 index 0000000..fc95816 --- /dev/null +++ b/rk3588/rp-camera-dphy1.dtsi @@ -0,0 +1,198 @@ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + dw9763_3: dw9763_3@c { + compatible = "dongwoon,dw9763"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-max-current = <120>; + rockchip,vcm-start-current = <20>; + rockchip,vcm-rated-current = <90>; + rockchip,vcm-step-mode = <3>; + rockchip,vcm-t-src = <0x20>; + rockchip,vcm-t-div = <1>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + }; + + ov13855_3: ov13855_3@36 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&dw9763_3>; + port { + ov13855_out3: endpoint { + remote-endpoint = <&mipi_in_ov13855_3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + gc8034_3: gc8034_3@37 { + compatible = "galaxycore,gc8034"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "RK-CMK-8M-2-v1"; + rockchip,camera-module-lens-name = "CK8401-4"; + port { + gc8034_out3: endpoint { + remote-endpoint = <&mipi_in_gc8034_3>; + data-lanes = <1 2 3 4>; + }; + }; + }; + imx415_3: imx415_3@37 { + compatible = "sony,imx415"; + status = "okay"; + reg = <0x37>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim0_camera4_clk>; + rockchip,grf = <&sys_grf>; + power-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;//modify camera addr 0x37 + rockchip,camera-module-index = <3>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "CMK-OT2022-PX1"; + rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; + port { + imx415_out3: endpoint { + remote-endpoint = <&mipi_in_imx415_3>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + + +&csi2_dphy1_hw { + status = "okay"; +}; + +&csi2_dphy3 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi_in_ov13855_3: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out3>; + data-lanes = <1 2 3 4>; + }; + mipi_in_gc8034_3: endpoint@2 { + reg = <2>; + remote-endpoint = <&gc8034_out3>; + data-lanes = <1 2 3 4>; + }; + mipi_in_imx415_3: endpoint@3 { + reg = <3>; + remote-endpoint = <&imx415_out3>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + csidphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_csi2_input>; + }; + }; + }; +}; + +&mipi4_csi2 { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy1_out>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + mipi4_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in4>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds4 { + status = "okay"; + port { + cif_mipi_in4: endpoint { + remote-endpoint = <&mipi4_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds4_sditf { + status = "okay"; + port { + mipi4_lvds_sditf: endpoint { + remote-endpoint = <&isp1_vir1>; + }; + }; +}; + +&rkisp1 { + status = "okay"; +}; + +&isp1_mmu { + status = "okay"; +}; + +&rkisp1_vir1 { + status = "okay"; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_vir1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi4_lvds_sditf>; + }; + }; +}; + diff --git a/rk3588/rp-camera-mipi-xs9922b.dtsi b/rk3588/rp-camera-mipi-xs9922b.dtsi new file mode 100755 index 0000000..92d72c3 --- /dev/null +++ b/rk3588/rp-camera-mipi-xs9922b.dtsi @@ -0,0 +1,260 @@ +/** + * mipi csi to xs9922b config + */ + + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + + + xs9922: xs9922@31 { + compatible = "xs9922"; + status = "okay"; + reg = <0x31>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&xs9922_pwr>; + reset-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + //avdd-supply = <&vcc_avdd>; + //dovdd-supply = <&vcc_dovdd>; + //dvdd-supply = <&vcc_dvdd>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,default_rect= <1280 720>; + port { + ucam_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&pinctrl { + xs9922 { + xs9922_pwr: camera-pwr { + rockchip,pins = + <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, + <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + + + + +&mipi_dcphy0 { + status = "okay"; +}; + + + + + + + + + + +// CIF + + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&ucam_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + + }; + }; +}; + + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + + + +#if 0 + +// isp +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in2>; + }; + }; + }; +}; + + +&rkcif_mipi_lvds2 { + status = "okay"; + port { + cif_mipi_in2: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + + +#endif + + + + +#if 0 + +&rkcif_mipi_lvds2_sditf { + status = "okay"; + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + + +&rkisp_unite { + status = "okay"; +}; + +&rkisp_unite_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + */ + rockchip,hw = <&rkisp_unite>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; +/* + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + */ + }; +}; + + +#endif diff --git a/rk3588/rp-eth-gmac0.dtsi b/rk3588/rp-eth-gmac0.dtsi new file mode 100755 index 0000000..3622350 --- /dev/null +++ b/rk3588/rp-eth-gmac0.dtsi @@ -0,0 +1,33 @@ + +&mdio0 { + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&gmac0 { + // Use rgmii-rxid mode to disable rx delay inside Soc + phy-mode = "rgmii-rxid"; + clock_in_out = "output"; + + snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus>; + + tx_delay = <0x44>; + // rx_delay = <0x4f>; + + phy-handle = <&rgmii_phy0>; + status = "okay"; +}; + + diff --git a/rk3588/rp-eth-gmac1.dtsi b/rk3588/rp-eth-gmac1.dtsi new file mode 100755 index 0000000..8c14a50 --- /dev/null +++ b/rk3588/rp-eth-gmac1.dtsi @@ -0,0 +1,34 @@ + +&mdio1 { + rgmii_phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_ETH1_OUT>; + }; +}; + +&gmac1 { + // Use rgmii-rxid mode to disable rx delay inside Soc + phy-mode = "rgmii-rxid"; + clock_in_out = "input"; + + snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + // Reset time is 20ms, 100ms for rtl8211f + snps,reset-delays-us = <0 20000 100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&gmac1_miim + &gmac1_tx_bus2 + &gmac1_rx_bus2 + &gmac1_rgmii_clk + &gmac1_rgmii_bus + &gmac1_clkinout + ð1_pins>; + + tx_delay = <0x44>; + // rx_delay = <0x4f>; + + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; diff --git a/rk3588/rp-eth-pcie2gmac-rk3588.dtsi b/rk3588/rp-eth-pcie2gmac-rk3588.dtsi new file mode 100755 index 0000000..8eb09e6 --- /dev/null +++ b/rk3588/rp-eth-pcie2gmac-rk3588.dtsi @@ -0,0 +1,10 @@ +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + phys = <&combphy0_ps PHY_TYPE_PCIE>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/rk3588/rp-eth-pcie2gmac-rk3588s.dtsi b/rk3588/rp-eth-pcie2gmac-rk3588s.dtsi new file mode 100755 index 0000000..2991a3a --- /dev/null +++ b/rk3588/rp-eth-pcie2gmac-rk3588s.dtsi @@ -0,0 +1,22 @@ +/* +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + phys = <&combphy0_ps PHY_TYPE_PCIE>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; +*/ + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + //vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; diff --git a/rk3588/rp-hdmirx.dtsi b/rk3588/rp-hdmirx.dtsi new file mode 100755 index 0000000..90c75bb --- /dev/null +++ b/rk3588/rp-hdmirx.dtsi @@ -0,0 +1,54 @@ + +/ { + /* If hdmirx node is disabled, delete the reserved-memory node here. */ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Reserve 256MB memory for hdmirx-controller@fdee0000 */ + cma { + compatible = "shared-dma-pool"; + reusable; + reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; + linux,cma-default; + }; + }; + + hdmiin-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,hdmiin"; + simple-audio-card,bitclock-master = <&dailink0_master>; + simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + simple-audio-card,cpu { + sound-dai = <&i2s7_8ch>; + }; + dailink0_master: simple-audio-card,codec { + sound-dai = <&hdmiin_dc>; + }; + }; + + hdmiin_dc: hdmiin-dc { + compatible = "rockchip,dummy-codec"; + #sound-dai-cells = <0>; + }; + +}; + +&i2s7_8ch { + status = "okay"; +}; + + +&hdmirx_ctrler { + status = "okay"; + + /* Effective level used to trigger HPD: 0-low, 1-high */ + hpd-trigger-level = <1>; + hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim2_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda>; + pinctrl-names = "default"; +}; + diff --git a/rk3588/rp-lcd-box-edp1-13.3-15.6-1920-1080.dtsi b/rk3588/rp-lcd-box-edp1-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..5eeea35 --- /dev/null +++ b/rk3588/rp-lcd-box-edp1-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,163 @@ +/ { + + + panel_edp1 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp1: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + +}; +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; +}; + + + +&backlight_edp { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp1>; + }; + }; + }; +}; + +&route_edp1 { + status = "okay"; + connect = <&vp1_out_edp1>; +}; + + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&hdptxphy1 { + status = "okay"; +}; + + +&goodix_ts { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; diff --git a/rk3588/rp-lcd-edp0-13.3-15.6-1920-1080.dtsi b/rk3588/rp-lcd-edp0-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..6edc954 --- /dev/null +++ b/rk3588/rp-lcd-edp0-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,165 @@ + +/ { + panel-edp0 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + +}; + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; +}; + + +&backlight_edp { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&route_edp0 { + status = "disabled"; + connect = <&vp0_out_edp0>; +}; + + +&edp0_in_vp0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "disabled"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + + + + +&goodix_ts { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; + diff --git a/rk3588/rp-lcd-edp1-13.3-15.6-1920-1080.dtsi b/rk3588/rp-lcd-edp1-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..075c66a --- /dev/null +++ b/rk3588/rp-lcd-edp1-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,126 @@ +/ { + panel-edp1 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp1: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + + +}; + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; +}; + +&backlight_edp { + compatible = "pwm-backlight"; + //pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; + +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp1>; + }; + }; + }; +}; + +&route_edp1 { + status = "disabled"; + connect = <&vp1_out_edp1>; +}; + + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&hdptxphy1 { + status = "okay"; +}; + + diff --git a/rk3588/rp-lcd-hdmi0-hdmi1-dp0.dtsi b/rk3588/rp-lcd-hdmi0-hdmi1-dp0.dtsi new file mode 100755 index 0000000..a15d9ee --- /dev/null +++ b/rk3588/rp-lcd-hdmi0-hdmi1-dp0.dtsi @@ -0,0 +1,3 @@ +#include "rp-lcd-hdmi0.dtsi" // batch ignore +#include "rp-lcd-hdmi1.dtsi" // batch ignore +#include "rp-lcd-typec-dp0.dtsi" // usb dp0, must be enable rp-usb-typec.dtsi, batch ignore diff --git a/rk3588/rp-lcd-hdmi0.dtsi b/rk3588/rp-lcd-hdmi0.dtsi new file mode 100755 index 0000000..9e46a82 --- /dev/null +++ b/rk3588/rp-lcd-hdmi0.dtsi @@ -0,0 +1,24 @@ +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; diff --git a/rk3588/rp-lcd-hdmi1.dtsi b/rk3588/rp-lcd-hdmi1.dtsi new file mode 100755 index 0000000..188cc71 --- /dev/null +++ b/rk3588/rp-lcd-hdmi1.dtsi @@ -0,0 +1,29 @@ +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + + +&hdptxphy_hdmi1 { + status = "okay"; +}; + + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; +}; + diff --git a/rk3588/rp-lcd-mipi0-10-1200-1920.dtsi b/rk3588/rp-lcd-mipi0-10-1200-1920.dtsi new file mode 100755 index 0000000..2225bac --- /dev/null +++ b/rk3588/rp-lcd-mipi0-10-1200-1920.dtsi @@ -0,0 +1,208 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1110000>; + + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <150000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <40>; + hfront-porch = <50>; + vback-porch = <10>; + vfront-porch = <10>; + hsync-len = <5>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 42 B0 04 80 07 0A 35 00 01 0F 28 0F + 5A 3C 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 33 35 D3 07 00 00 + 00 B9 03 10 00 00 00 00 00 00 00 00 + 00 00 00 32 46 94 C5 02 07 00 00 04 + 73 33 00 6E 37 00 69 3B 00 66 3F 00 + 62 43 00 62 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 3E 01 + ]; + /** for new tp sensor id 2 but cfg is the same as id 0 */ + goodix,cfg-group2 = [ + 42 B0 04 80 07 0A 35 00 01 0F 28 0F + 5A 3C 03 05 00 00 00 00 00 00 04 17 + 19 1D 14 90 30 AA 33 35 D3 07 00 00 + 00 B9 03 10 00 00 00 00 00 00 00 00 + 00 00 00 32 46 94 C5 02 07 00 00 04 + 73 33 00 6E 37 00 69 3B 00 66 3F 00 + 62 43 00 62 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 01 00 + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 07 08 0A 0C 0D 0E 0F 10 11 12 + 13 14 2A 29 28 27 26 25 24 23 22 21 + 20 1F 1E 1C 1B 19 FF FF FF FF FF FF + FF FF FF FF 3E 01 + ]; +}; diff --git a/rk3588/rp-lcd-mipi0-10-1920-1200-jc.dtsi b/rk3588/rp-lcd-mipi0-10-1920-1200-jc.dtsi new file mode 100755 index 0000000..eb90667 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-10-1920-1200-jc.dtsi @@ -0,0 +1,189 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <1100000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <120>; + prepare-delay-ms = <120>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1200>; + hback-porch = <32>; + hfront-porch = <110>; + vback-porch = <14>; + vfront-porch = <11>; + hsync-len = <2>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 7F 80 07 B0 04 0A 3D 00 01 06 23 + 08 37 2D 03 05 00 00 00 00 00 00 + 04 17 19 1D 14 90 30 AA 53 55 0C + 08 00 00 00 01 03 1D 00 00 00 00 + 00 00 00 00 00 00 00 3C 78 94 D0 + 42 00 08 00 04 8E 40 00 85 4A 00 + 7F 55 00 7B 61 00 7A 70 00 7B 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 0F + 0E 0D 0C 09 08 07 06 05 04 01 00 + 00 00 00 00 00 00 00 00 00 00 19 + 1B 1C 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 14 13 12 11 10 0F 0E + 0D 0C 0A 08 07 06 04 02 00 00 00 + 00 00 00 00 00 00 00 00 BE 01 + ]; +}; diff --git a/rk3588/rp-lcd-mipi0-10-800-1280-v2-JC101HD131.dtsi b/rk3588/rp-lcd-mipi0-10-800-1280-v2-JC101HD131.dtsi new file mode 100755 index 0000000..b87b355 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-10-800-1280-v2-JC101HD131.dtsi @@ -0,0 +1,191 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 70 20 03 00 05 0A 05 00 01 08 + 28 05 5A 46 03 05 00 00 00 00 + 00 00 00 17 19 1B 14 8E 2E 99 + 37 39 D3 07 00 00 00 80 02 2D + 00 00 00 00 00 00 00 00 00 00 + 00 28 78 94 C5 02 07 00 00 04 + 9A 2C 00 80 37 00 6B 45 00 5C + 56 00 50 6C 00 50 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 17 16 15 14 11 10 0F 0E + 0D 0C 09 08 07 06 05 04 01 00 + FF FF 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0D 0F 10 11 12 28 27 26 25 24 + 23 22 21 20 1F 1E 1C 1B 19 13 + FF FF FF FF 00 00 00 00 00 00 + 00 00 00 00 AA 01 + ]; +}; diff --git a/rk3588/rp-lcd-mipi0-10-800-1280-v2.dtsi b/rk3588/rp-lcd-mipi0-10-800-1280-v2.dtsi new file mode 100755 index 0000000..1eeda72 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-10-800-1280-v2.dtsi @@ -0,0 +1,450 @@ + +/ { + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; + }; + + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + +}; + + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + +&dsi0 { + status = "okay"; + rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + //=========_1===========// + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 53 + 39 00 02 04 13 + 39 00 02 05 00 + 39 00 02 06 04 + 39 00 02 07 00 + 39 00 02 08 00 + 39 00 02 09 22 + 39 00 02 0a 22 + 39 00 02 0b 00 + 39 00 02 0c 01 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 23 + 39 00 02 10 23 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 44 + 39 00 02 1f 80 + 39 00 02 20 02 + 39 00 02 21 03 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 03 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 04 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 3C + 39 00 02 39 00 + 39 00 02 3a 40 + 39 00 02 3b 40 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 + 39 00 02 44 00 + + + + //=========_2===========// + 39 00 02 50 01 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + //=========_3===========// + 39 00 02 5e 11 + + 39 00 02 5f 01 + 39 00 02 60 00 + 39 00 02 61 15 + 39 00 02 62 14 + 39 00 02 63 0C + 39 00 02 64 0D + 39 00 02 65 0E + 39 00 02 66 0F + 39 00 02 67 06 + 39 00 02 68 02 + 39 00 02 69 02 + 39 00 02 6a 02 + 39 00 02 6b 02 + 39 00 02 6c 02 + 39 00 02 6d 02 + 39 00 02 6e 08 + 39 00 02 6f 02 + 39 00 02 70 02 + 39 00 02 71 02 + 39 00 02 72 02 + 39 00 02 73 02 + 39 00 02 74 02 + + 39 00 02 75 01 + 39 00 02 76 00 + 39 00 02 77 15 + 39 00 02 78 14 + 39 00 02 79 0C + 39 00 02 7a 0D + 39 00 02 7b 0E + 39 00 02 7c 0F + 39 00 02 7D 08 + 39 00 02 7E 02 + 39 00 02 7F 02 + 39 00 02 80 02 + 39 00 02 81 02 + 39 00 02 82 02 + 39 00 02 83 02 + 39 00 02 84 06 + 39 00 02 85 02 + 39 00 02 86 02 + 39 00 02 87 02 + 39 00 02 88 02 + 39 00 02 89 02 + 39 00 02 8A 02 + + + //CMD_Page + 39 00 04 FF 98 81 04 + 39 00 02 6C 15 + 39 00 02 6E 3B + 39 00 02 6F 73 + 39 00 02 3A 24 + 39 00 02 8D 14 + 39 00 02 87 BA + 39 00 02 26 76 + 39 00 02 B2 D1 + 39 00 02 B5 27 + 39 00 02 31 75 + 39 00 02 30 03 + 39 00 02 3B 98 + 39 00 02 35 1f + 39 00 02 33 14 + 39 00 02 7A 0F + 39 00 02 38 02 + 39 00 02 39 00 + + + //CMD_Page + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 0A + 39 00 02 35 07 + 39 00 02 52 00 + 39 00 02 53 5A + 39 00 02 54 00 + 39 00 02 55 59 + 39 00 02 50 83 + 39 00 02 51 80 + 39 00 02 60 20 + 39 00 02 61 01 + 39 00 02 62 07 + 39 00 02 63 00 + + //GammaP + 39 00 02 A0 08 + 39 00 02 A1 0F + 39 00 02 A2 15 + 39 00 02 A3 0E + 39 00 02 A4 0D + 39 00 02 A5 1B + 39 00 02 A6 0F + 39 00 02 A7 14 + 39 00 02 A8 33 + 39 00 02 A9 17 + 39 00 02 AA 23 + 39 00 02 AB 3F + 39 00 02 AC 22 + 39 00 02 AD 24 + 39 00 02 AE 59 + 39 00 02 AF 2B + 39 00 02 B0 2E + 39 00 02 B1 4C + 39 00 02 B2 5C + 39 00 02 B3 33 + + //GammaN + 39 00 02 C0 08 + 39 00 02 C1 0F + 39 00 02 C2 15 + 39 00 02 C3 0E + 39 00 02 C4 0D + 39 00 02 C5 1B + 39 00 02 C6 0F + 39 00 02 C7 14 + 39 00 02 C8 33 + 39 00 02 C9 17 + 39 00 02 CA 23 + 39 00 02 CB 3F + 39 00 02 CC 22 + 39 00 02 CD 24 + 39 00 02 CE 59 + 39 00 02 CF 2B + 39 00 02 D0 2E + 39 00 02 D1 4C + 39 00 02 D2 5C + 39 00 02 D3 33 + + + //CMD_Page + 39 00 04 FF 98 81 00 + 05 78 01 11 //sleep out + + 05 00 01 29 //display on + 05 00 01 35 //TE on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + goodix_ts@5d { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + goodix_rst_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio3 RK_PD0 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; + + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group2 = [ + 41 20 03 00 05 0A 35 00 01 06 + 23 08 37 2D 03 05 00 00 00 00 + 00 00 04 17 19 1D 14 90 30 AA + 53 55 0C 08 00 00 00 01 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B + 61 00 7A 70 00 7B 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0D 0E 0F 10 11 12 13 14 2A 29 + 28 27 26 25 24 23 22 21 20 1F + 1E 1C 1B 19 00 00 00 00 00 00 + 00 00 00 00 17 01 + ]; + +}; +}; + + diff --git a/rk3588/rp-lcd-mipi0-10-800-1280-v3.dtsi b/rk3588/rp-lcd-mipi0-10-800-1280-v3.dtsi new file mode 100755 index 0000000..1b1cb90 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-10-800-1280-v3.dtsi @@ -0,0 +1,192 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <82000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <30>; + vfront-porch = <20>; + hsync-len = <30>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group2 = [ + 41 20 03 00 05 0A 35 00 01 06 + 23 08 37 2D 03 05 00 00 00 00 + 00 00 04 17 19 1D 14 90 30 AA + 53 55 0C 08 00 00 00 01 03 1D + 00 00 00 00 00 00 00 00 00 00 + 00 3C 78 94 D0 42 00 08 00 04 + 8E 40 00 85 4A 00 7F 55 00 7B + 61 00 7A 70 00 7B 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 19 18 17 16 15 14 11 10 + 0F 0E 0D 0C 09 08 07 06 05 04 + 01 00 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 07 08 0A 0C + 0D 0E 0F 10 11 12 13 14 2A 29 + 28 27 26 25 24 23 22 21 20 1F + 1E 1C 1B 19 00 00 00 00 00 00 + 00 00 00 00 17 01 + ]; + +}; diff --git a/rk3588/rp-lcd-mipi0-1280-720-test.dtsi b/rk3588/rp-lcd-mipi0-1280-720-test.dtsi new file mode 100755 index 0000000..de3d94b --- /dev/null +++ b/rk3588/rp-lcd-mipi0-1280-720-test.dtsi @@ -0,0 +1,223 @@ + +&backlight_lvds { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < +/* + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 +*/ + + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + + + + + +&dsi0 { + status = "okay"; +// rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <70000000>; + hactive = <1280>; + vactive = <720>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + + + diff --git a/rk3588/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi b/rk3588/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi new file mode 100755 index 0000000..9848cbc --- /dev/null +++ b/rk3588/rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi @@ -0,0 +1,223 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 4D D0 02 00 05 05 35 00 01 08 32 + 08 5A 3C 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 29 0A 55 57 B5 + 06 00 00 00 41 22 10 00 01 00 0F + 00 2A 00 00 19 50 32 3C 78 94 D5 + 02 08 00 00 04 A2 40 00 8F 4A 00 + 80 55 00 73 61 00 67 70 00 67 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 02 04 06 08 0A 0C 0E 10 12 + 14 FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 + 06 08 0A 0F 10 12 FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF 8D 01 + ]; + }; diff --git a/rk3588/rp-lcd-mipi0-5-720-1280-v2.dtsi b/rk3588/rp-lcd-mipi0-5-720-1280-v2.dtsi new file mode 100755 index 0000000..2dea5b2 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-5-720-1280-v2.dtsi @@ -0,0 +1,220 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <60000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 46 D0 02 00 05 05 35 01 01 08 1E 0F 5A 3C + 03 05 00 00 00 00 11 11 00 19 1B 1E 14 89 + 29 0A 41 43 D3 07 00 00 00 9A 02 11 00 01 + 05 00 00 00 00 09 11 00 00 36 4A 94 45 00 + 00 00 00 00 94 37 00 8B 3B 00 83 3F 00 7C + 43 00 76 47 00 76 10 30 48 00 F0 4A 3A FF + FF 27 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 08 0A 0C 0E 10 12 14 16 18 1A 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 0E 0C 0A 08 06 05 04 02 00 1D 1E 1F + 20 22 24 28 29 2A 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 84 01 + ]; + }; diff --git a/rk3588/rp-lcd-mipi0-7-1024-600.dtsi b/rk3588/rp-lcd-mipi0-7-1024-600.dtsi new file mode 100755 index 0000000..1d52212 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-7-1024-600.dtsi @@ -0,0 +1,219 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <55000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <160>; + hfront-porch = <136>; + vback-porch = <16>; + vfront-porch = <16>; + hsync-len = <4>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <1024>; + gtp_resolution_y = <600>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + + goodix,cfg-group0 = [ //odl touch sensor_id 0 + 41 00 04 58 02 05 7D 00 01 2F 28 + 0F 50 32 03 05 00 00 00 00 00 00 + 00 18 1A 1E 14 89 0D 0C 2C 2A 0C + 08 00 00 00 82 03 1D 0A 32 05 0A + 32 00 00 00 00 00 0B 1E 50 94 E5 + 02 08 00 00 04 A7 21 00 8B 28 00 + 73 31 00 62 3B 00 52 48 00 52 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 32 50 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 2A + 29 28 26 24 22 21 20 1F 1E 1D 18 + 16 14 13 12 10 0F 0C 0A 08 06 FF + FF FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 3B 01 + ]; + + goodix,cfg-group5 = [ //new touch sensor_id 5 + FF 00 04 58 02 05 0D 04 01 + 0A 28 0A 50 32 03 05 00 00 + 00 00 00 00 08 00 00 00 00 + 8B 2B 0E 30 32 0F 0A 00 00 + 00 83 02 1D 00 00 00 00 00 + 03 03 32 00 00 00 24 60 94 + C0 02 00 00 00 04 93 27 00 + 80 30 00 70 3B 00 65 47 00 + 5C 57 00 5C 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 + 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 26 24 + 22 21 20 1F 1E 1D 1C 18 16 + 13 12 10 0F 0C 0A 08 06 04 + 02 00 FF FF FF FF 00 00 00 + 00 00 00 00 00 00 00 00 00 + 00 00 00 00 6A 01 + ]; + + +}; + diff --git a/rk3588/rp-lcd-mipi0-7-720-1280.dtsi b/rk3588/rp-lcd-mipi0-7-720-1280.dtsi new file mode 100755 index 0000000..891460e --- /dev/null +++ b/rk3588/rp-lcd-mipi0-7-720-1280.dtsi @@ -0,0 +1,444 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 02 E0 00 + 39 00 02 E1 93 + 39 00 02 E2 65 + 39 00 02 E3 F8 + 39 00 02 80 03 + 39 00 02 E0 04 + 39 00 02 2D 03 + 39 00 02 E0 00 + 39 00 02 70 10 + 39 00 02 71 13 + 39 00 02 72 06 + 39 00 02 75 03 + + 39 00 02 E0 01 + // 39 00 02 4A 30 + 39 00 02 00 00 + 39 00 02 01 A0 + 39 00 02 03 00 + 39 00 02 04 A0 + 39 00 02 0A 07 + 39 00 02 0C 74 + 39 00 02 17 00 + 39 00 02 18 D7 + 39 00 02 19 01 + 39 00 02 1A 00 + 39 00 02 1B D7 + 39 00 02 1C 01 + 39 00 02 1F 74 + 39 00 02 20 19 + 39 00 02 21 19 + 39 00 02 22 0E + 39 00 02 27 43 + + 39 00 02 37 09 + 39 00 02 38 04 + 39 00 02 39 08 + 39 00 02 3A 18 + 39 00 02 3B 18 + 39 00 02 3C 72 + 39 00 02 3E FF + 39 00 02 3E FF + 39 00 02 3F FF + 39 00 02 40 04 + 39 00 02 41 A0 + 39 00 02 43 08 + 39 00 02 44 07 + 39 00 02 45 30 + 39 00 02 55 01 + 39 00 02 56 01 + 39 00 02 57 65 + 39 00 02 58 0A + 39 00 02 59 0A + 39 00 02 5A 28 + 39 00 02 5B 0F + + 39 00 02 5D 7C + 39 00 02 5E 5F + 39 00 02 5F 4D + 39 00 02 60 3F + 39 00 02 61 39 + 39 00 02 62 29 + 39 00 02 63 2B + 39 00 02 64 12 + 39 00 02 65 28 + 39 00 02 66 24 + 39 00 02 67 22 + 39 00 02 68 3E + 39 00 02 69 2C + 39 00 02 6A 33 + 39 00 02 6B 26 + 39 00 02 6C 23 + 39 00 02 6D 18 + 39 00 02 6E 09 + 39 00 02 6F 00 + 39 00 02 70 7C + 39 00 02 71 5F + 39 00 02 72 4D + 39 00 02 73 3F + 39 00 02 74 39 + 39 00 02 75 29 + 39 00 02 76 2B + 39 00 02 77 12 + 39 00 02 78 28 + 39 00 02 79 24 + 39 00 02 7A 22 + 39 00 02 7B 3E + 39 00 02 7C 2C + 39 00 02 7D 33 + 39 00 02 7E 26 + 39 00 02 7F 23 + 39 00 02 80 18 + 39 00 02 81 09 + 39 00 02 82 00 + + 39 00 02 E0 02 + 39 00 02 00 37 + 39 00 02 01 17 + 39 00 02 02 0A + 39 00 02 03 06 + 39 00 02 04 08 + 39 00 02 05 04 + 39 00 02 06 00 + 39 00 02 07 1F + 39 00 02 08 1F + 39 00 02 09 1F + 39 00 02 0A 1F + 39 00 02 0B 1F + 39 00 02 0C 1F + 39 00 02 0D 1F + 39 00 02 0E 1F + 39 00 02 0F 1F + 39 00 02 10 3F + 39 00 02 11 1F + 39 00 02 12 1F + 39 00 02 13 1E + 39 00 02 14 10 + 39 00 02 15 1F + + 39 00 02 16 37 + 39 00 02 17 17 + 39 00 02 18 0B + 39 00 02 19 07 + 39 00 02 1A 09 + 39 00 02 1B 05 + 39 00 02 1C 01 + 39 00 02 1D 1F + 39 00 02 1E 1F + 39 00 02 1F 1F + 39 00 02 20 1F + 39 00 02 21 1F + 39 00 02 22 1F + 39 00 02 23 1F + 39 00 02 24 1F + 39 00 02 25 1F + 39 00 02 26 1F + 39 00 02 27 1F + 39 00 02 28 1F + 39 00 02 29 1E + 39 00 02 2A 11 + 39 00 02 2B 1F + 39 00 02 2C 37 + 39 00 02 2D 17 + 39 00 02 2E 05 + 39 00 02 2F 09 + 39 00 02 30 07 + 39 00 02 31 0B + 39 00 02 32 11 + 39 00 02 33 1F + 39 00 02 34 1F + 39 00 02 35 1F + 39 00 02 36 1F + 39 00 02 37 1F + 39 00 02 38 1F + 39 00 02 39 1F + 39 00 02 3A 1F + 39 00 02 3B 1F + 39 00 02 3C 3F + 39 00 02 3D 1F + 39 00 02 3E 1E + 39 00 02 3F 1F + 39 00 02 40 01 + + 39 00 02 41 1F + 39 00 02 42 38 + 39 00 02 43 18 + 39 00 02 44 04 + 39 00 02 45 08 + 39 00 02 46 06 + 39 00 02 47 0A + 39 00 02 48 10 + 39 00 02 49 1F + 39 00 02 4A 1F + 39 00 02 4B 1F + 39 00 02 4C 1F + 39 00 02 4D 1F + 39 00 02 4E 1F + 39 00 02 4F 1F + 39 00 02 50 1F + 39 00 02 51 1F + 39 00 02 52 1F + 39 00 02 53 1F + 39 00 02 54 1E + 39 00 02 55 1F + 39 00 02 56 00 + 39 00 02 57 1F + 39 00 02 58 10 + 39 00 02 59 00 + 39 00 02 5A 00 + 39 00 02 5B 10 + 39 00 02 5C 01 + 39 00 02 5D 50 + 39 00 02 5E 01 + 39 00 02 5F 02 + 39 00 02 60 30 + 39 00 02 61 01 + 39 00 02 62 02 + 39 00 02 63 06 + 39 00 02 64 6A + 39 00 02 65 55 + 39 00 02 66 08 + 39 00 02 67 73 + 39 00 02 68 05 + 39 00 02 69 08 + 39 00 02 6A 6E + 39 00 02 6B 00 + 39 00 02 6C 00 + 39 00 02 6D 00 + 39 00 02 6E 00 + 39 00 02 6F 88 + 39 00 02 70 00 + 39 00 02 71 00 + 39 00 02 72 06 + 39 00 02 73 7B + 39 00 02 74 00 + 39 00 02 75 80 + 39 00 02 76 00 + 39 00 02 77 0D + 39 00 02 78 18 + 39 00 02 79 00 + 39 00 02 7A 00 + 39 00 02 7B 00 + 39 00 02 7C 00 + 39 00 02 7D 03 + 39 00 02 7E 7B + 39 00 02 E0 04 + 39 00 02 04 01 + 39 00 02 0E 38 + 39 00 02 2B 2B + 39 00 02 2E 44 + 39 00 02 E0 00 + 39 00 02 E6 02 + 39 00 02 E6 02 + //39 00 02 36 00 + 39 C8 02 11 00 + 39 C8 02 29 00 + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <70000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <34>; + hfront-porch = <34>; + vback-porch = <6>; + vfront-porch = <20>; + hsync-len = <24>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <720>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 57 58 02 00 04 05 35 00 01 08 32 0F + 5A 32 03 05 00 00 00 00 02 00 00 18 + 1A 1E 14 8A 2A 0C 55 57 B5 06 00 00 + 00 20 33 1C 14 01 00 0F 00 2B FF 7F + 19 46 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 61 00 + 6F 70 00 6F 00 00 00 00 F0 40 30 FF + FF 27 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 24 22 + 21 20 1F 1E 1D 1C 18 16 00 02 04 06 + 08 0A 0F 10 12 13 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 81 01 + ]; + + goodix,cfg-group2 = [ + 5A 58 02 00 04 05 35 00 01 08 + 32 0F 5A 32 03 05 00 00 00 00 + 02 00 00 18 1A 1E 14 8A 2A 0C + 55 57 B5 06 00 00 00 20 33 1C + 14 01 00 0F 00 2B FF 7F 19 46 + 32 3C 78 94 D5 02 08 00 00 04 + 98 40 00 8A 4A 00 80 55 00 77 + 61 00 6F 70 00 6F 00 00 00 00 + F0 40 30 FF FF 27 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 18 16 14 12 10 0E 0C 0A + 08 06 04 02 FF FF 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 02 04 06 08 0A 0F 10 + 12 13 24 22 21 20 1F 1E 1D 1C + 18 16 FF FF FF FF FF FF 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 5E 01 + ]; +}; + diff --git a/rk3588/rp-lcd-mipi0-8-1200-1920.dtsi b/rk3588/rp-lcd-mipi0-8-1200-1920.dtsi new file mode 100755 index 0000000..3c88300 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-8-1200-1920.dtsi @@ -0,0 +1,212 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <148000000>; + hactive = <1200>; + vactive = <1920>; + hback-porch = <60>; + hfront-porch = <80>; + vback-porch = <25>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <2>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <1200>; + gtp_resolution_y = <1920>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 5E B0 04 80 07 05 05 00 01 0F 28 05 + 50 32 03 05 00 00 00 00 00 00 00 00 + 00 00 00 8C 2C 0E 52 54 31 0D 00 00 + 01 80 04 1C 00 00 00 00 00 03 64 32 + 00 00 00 52 66 94 C5 02 07 00 00 04 + 83 53 00 82 57 00 80 5B 00 7F 5F 00 + 7E 63 00 7E 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 1C 1A 18 16 14 12 10 0E + 0C 0A 08 06 04 02 FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF 00 02 + 04 06 08 0A 0C 0F 10 12 13 14 28 26 + 24 22 21 20 1F 1E 1D 1C 18 16 FF FF + FF FF FF FF FF FF FF FF FF FF FF FF + FF FF FF FF 22 01 + ]; + + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + +}; + diff --git a/rk3588/rp-lcd-mipi0-8-800-1280-v3.dtsi b/rk3588/rp-lcd-mipi0-8-800-1280-v3.dtsi new file mode 100755 index 0000000..04af719 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-8-800-1280-v3.dtsi @@ -0,0 +1,412 @@ + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 FF 98 81 03 + + 39 00 02 01 00 + 39 00 02 02 00 + 39 00 02 03 57 //54 + 39 00 02 04 D3 //D4 + 39 00 02 05 00 + 39 00 02 06 11 + 39 00 02 07 08 //09 + 39 00 02 08 00 + 39 00 02 09 00 + 39 00 02 0a 3F //00 + 39 00 02 0b 00 + 39 00 02 0c 00 + 39 00 02 0d 00 + 39 00 02 0e 00 + 39 00 02 0f 3F //00 + 39 00 02 10 3F //00 + 39 00 02 11 00 + 39 00 02 12 00 + 39 00 02 13 00 + 39 00 02 14 00 + 39 00 02 15 00 + 39 00 02 16 00 + 39 00 02 17 00 + 39 00 02 18 00 + 39 00 02 19 00 + 39 00 02 1a 00 + 39 00 02 1b 00 + 39 00 02 1c 00 + 39 00 02 1d 00 + 39 00 02 1e 40 + 39 00 02 1f 80 + 39 00 02 20 06 + 39 00 02 21 01 + 39 00 02 22 00 + 39 00 02 23 00 + 39 00 02 24 00 + 39 00 02 25 00 + 39 00 02 26 00 + 39 00 02 27 00 + 39 00 02 28 33 + 39 00 02 29 33 + 39 00 02 2a 00 + 39 00 02 2b 00 + 39 00 02 2c 00 + 39 00 02 2d 00 + 39 00 02 2e 00 + 39 00 02 2f 00 + 39 00 02 30 00 + 39 00 02 31 00 + 39 00 02 32 00 + 39 00 02 33 00 + 39 00 02 34 00 + 39 00 02 35 00 + 39 00 02 36 00 + 39 00 02 37 00 + 39 00 02 38 78 + 39 00 02 39 00 + 39 00 02 3a 00 + 39 00 02 3b 00 + 39 00 02 3c 00 + 39 00 02 3d 00 + 39 00 02 3e 00 + 39 00 02 3f 00 + 39 00 02 40 00 + 39 00 02 41 00 + 39 00 02 42 00 + 39 00 02 43 00 //GCH/L + 39 00 02 44 00 + + + 39 00 02 50 00 + 39 00 02 51 23 + 39 00 02 52 45 + 39 00 02 53 67 + 39 00 02 54 89 + 39 00 02 55 ab + 39 00 02 56 01 + 39 00 02 57 23 + 39 00 02 58 45 + 39 00 02 59 67 + 39 00 02 5a 89 + 39 00 02 5b ab + 39 00 02 5c cd + 39 00 02 5d ef + + 39 00 02 5e 00 + 39 00 02 5f 0D //FW_CGOUT_L[1] + 39 00 02 60 0D //FW_CGOUT_L[2] + 39 00 02 61 0C //FW_CGOUT_L[3] + 39 00 02 62 0C //FW_CGOUT_L[4] + 39 00 02 63 0F //FW_CGOUT_L[5] + 39 00 02 64 0F //FW_CGOUT_L[6] + 39 00 02 65 0E //FW_CGOUT_L[7] + 39 00 02 66 0E //FW_CGOUT_L[8] + 39 00 02 67 08 //FW_CGOUT_L[9] + 39 00 02 68 02 //FW_CGOUT_L[10] + 39 00 02 69 02 //FW_CGOUT_L[11] + 39 00 02 6a 02 //FW_CGOUT_L[12] + 39 00 02 6b 02 //FW_CGOUT_L[13] + 39 00 02 6c 02 //FW_CGOUT_L[14] + 39 00 02 6d 02 //FW_CGOUT_L[15] + 39 00 02 6e 02 //FW_CGOUT_L[16] + 39 00 02 6f 02 //FW_CGOUT_L[17] + 39 00 02 70 14 //FW_CGOUT_L[18] + 39 00 02 71 15 //FW_CGOUT_L[19] + 39 00 02 72 06 //FW_CGOUT_L[20] + 39 00 02 73 02 //FW_CGOUT_L[21] + 39 00 02 74 02 //FW_CGOUT_L[22] + + 39 00 02 75 0D //BW_CGOUT_L[1] + 39 00 02 76 0D //BW_CGOUT_L[2] + 39 00 02 77 0C //BW_CGOUT_L[3] + 39 00 02 78 0C //BW_CGOUT_L[4] + 39 00 02 79 0F //BW_CGOUT_L[5] + 39 00 02 7a 0F //BW_CGOUT_L[6] + 39 00 02 7b 0E //BW_CGOUT_L[7] + 39 00 02 7c 0E //BW_CGOUT_L[8] + 39 00 02 7d 08 //BW_CGOUT_L[9] + 39 00 02 7e 02 //BW_CGOUT_L[10] + 39 00 02 7f 02 //BW_CGOUT_L[11] + 39 00 02 80 02 //BW_CGOUT_L[12] + 39 00 02 81 02 //BW_CGOUT_L[13] + 39 00 02 82 02 //BW_CGOUT_L[14] + 39 00 02 83 02 //BW_CGOUT_L[15] + 39 00 02 84 02 //BW_CGOUT_L[16] + 39 00 02 85 02 //BW_CGOUT_L[17] + 39 00 02 86 14 //BW_CGOUT_L[18] + 39 00 02 87 15 //BW_CGOUT_L[19] + 39 00 02 88 06 //BW_CGOUT_L[20] + 39 00 02 89 02 //BW_CGOUT_L[21] + 39 00 02 8A 02 //BW_CGOUT_L[22] + + 39 00 04 FF 98 81 04 + + 39 00 02 6E 3B + 39 00 02 6F 57 + 39 00 02 3A 24 + 39 00 02 8D 1F + 39 00 02 87 BA + 39 00 02 B2 D1 + 39 00 02 88 0B + 39 00 02 38 01 + 39 00 02 39 00 + 39 00 02 B5 07 + 39 00 02 31 75 + 39 00 02 3B 98 + + + 39 00 04 FF 98 81 01 + 39 00 02 22 0A + 39 00 02 31 09 + 39 00 02 35 07 + 39 00 02 53 87 + 39 00 02 55 84 + 39 00 02 50 86 + 39 00 02 51 82 + 39 00 02 60 10 + 39 00 02 62 00 + + 39 00 02 A0 00 + 39 00 02 A1 12 + 39 00 02 A2 1F + 39 00 02 A3 12 + 39 00 02 A4 16 + 39 00 02 A5 29 + 39 00 02 A6 1E + 39 00 02 A7 1F + 39 00 02 A8 7E + 39 00 02 A9 1B + 39 00 02 AA 28 + 39 00 02 AB 6D + 39 00 02 AC 19 + 39 00 02 AD 18 + 39 00 02 AE 4C + 39 00 02 AF 1E + 39 00 02 B0 23 + 39 00 02 B1 52 + 39 00 02 B2 6D + 39 00 02 B3 3F + + 39 00 02 C0 00 + 39 00 02 C1 12 + 39 00 02 C2 20 + 39 00 02 C3 10 + 39 00 02 C4 13 + 39 00 02 C5 27 + 39 00 02 C6 1B + 39 00 02 C7 1D + 39 00 02 C8 75 + 39 00 02 C9 1F + 39 00 02 CA 28 + 39 00 02 CB 68 + 39 00 02 CC 1A + 39 00 02 CD 18 + 39 00 02 CE 4D + 39 00 02 CF 25 + 39 00 02 D0 2E + 39 00 02 D1 53 + 39 00 02 D2 60 + 39 00 02 D3 3F + + 39 00 04 FF 98 81 00 + 39 00 02 35 00 + 05 80 01 11 + 05 20 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <76000000>; + hactive = <800>; + vactive = <1280>; + hback-porch = <70>; + hfront-porch = <70>; + vback-porch = <22>; + vfront-porch = <16>; + hsync-len = <20>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + +&goodix_ts { + gtp_resolution_x = <800>; + gtp_resolution_y = <1280>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_back = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32 + 03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C + 2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00 + 00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02 + 07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78 + 20 00 61 28 00 61 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C + 18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 CB 01 + ]; + +/** jc */ + goodix,cfg-group2 = [ + 00 20 03 00 05 0A 05 00 01 08 28 + 05 50 32 03 05 00 00 00 00 00 00 + 00 00 00 00 00 8C 2C 0E 17 15 31 + 0D 00 00 01 BA 03 1D 00 00 00 00 + 00 03 64 32 00 00 00 0F 41 94 C5 + 02 07 00 00 04 99 11 00 77 17 00 + 5F 1F 00 4C 2A 00 41 38 00 41 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 + 00 00 1C 1A 18 16 14 12 10 0E 0C + 0A 08 06 04 02 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 28 + 26 24 22 21 20 1F 1E 1D 1C 18 16 + 00 02 04 06 08 0A 0C 0F 10 12 13 + 14 FF FF 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 FE 01 + ]; + +}; diff --git a/rk3588/rp-lcd-mipi0-gm8775-lvds-10.1-1024-600.dtsi b/rk3588/rp-lcd-mipi0-gm8775-lvds-10.1-1024-600.dtsi new file mode 100755 index 0000000..ec7b668 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-gm8775-lvds-10.1-1024-600.dtsi @@ -0,0 +1,223 @@ + +&backlight_lvds { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < +/* + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 +*/ + + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + + + + + +&dsi0 { + status = "okay"; +// rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + + + diff --git a/rk3588/rp-lcd-mipi0-gm8775-lvds-32-1920-1080.dtsi b/rk3588/rp-lcd-mipi0-gm8775-lvds-32-1920-1080.dtsi new file mode 100755 index 0000000..0dfb9f9 --- /dev/null +++ b/rk3588/rp-lcd-mipi0-gm8775-lvds-32-1920-1080.dtsi @@ -0,0 +1,222 @@ + +&backlight_lvds { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < +/* + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 +*/ + + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + + + + + +&dsi0 { + status = "okay"; +// rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + //mipi clk + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 80 + 23 08 02 02 38 + 23 08 02 03 47 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 13 + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 63 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 34 + 23 08 02 19 20 + 23 08 02 1A 10 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + + + diff --git a/rk3588/rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi b/rk3588/rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi new file mode 100755 index 0000000..6b1f50f --- /dev/null +++ b/rk3588/rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi @@ -0,0 +1,220 @@ + +&backlight_lvds { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < +/* + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 +*/ + + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + + + + +&dsi1 { + status = "okay"; + rockchip,lane-rate = <444000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing1>; + dsi1_timing1: timing0 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + + diff --git a/rk3588/rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi b/rk3588/rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi new file mode 100755 index 0000000..e8bb07e --- /dev/null +++ b/rk3588/rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi @@ -0,0 +1,220 @@ + +&backlight_lvds { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < +/* + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 +*/ + + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + + + + +&dsi1 { + status = "okay"; +// rockchip,lane-rate = <480000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + //enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + //mipi clk + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 80 + 23 08 02 02 38 + 23 08 02 03 47 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 13 + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 63 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 34 + 23 08 02 19 20 + 23 08 02 1A 10 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + 05 78 01 11//delay 120MS + 05 78 01 29 + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing1>; + dsi1_timing1: timing0 { + clock-frequency = <130000000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + + diff --git a/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi b/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi new file mode 100644 index 0000000..a15d9ee --- /dev/null +++ b/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi @@ -0,0 +1,3 @@ +#include "rp-lcd-hdmi0.dtsi" // batch ignore +#include "rp-lcd-hdmi1.dtsi" // batch ignore +#include "rp-lcd-typec-dp0.dtsi" // usb dp0, must be enable rp-usb-typec.dtsi, batch ignore diff --git a/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-edp1.dtsi b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-edp1.dtsi new file mode 100755 index 0000000..8c8ea8d --- /dev/null +++ b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-edp1.dtsi @@ -0,0 +1,672 @@ +/ { + vcc33_lcd_n: vcc33-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc33_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; + }; + + + panel-edp0 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + + + panel-edp1 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp1: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + +}; + + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2m1_pins>; +}; +&backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&backlight_edp { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp1>; + }; + }; + }; +}; + + + + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd_n>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1{ + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; + + rockchip,lane-rate = <444000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + +//enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + /*note: dsi0 uses the same pin,so dsi can not be configed*/ + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + + + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing1>; + dsi1_timing1: timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +/*dis0--->dcphy0--->vp2*/ +&vp2_out_dsi0{ + remote-endpoint = <&dsi0_in_vp2>; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; +&mipi_dcphy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; + + + +/*dis1--->dcphy1--->vp3*/ +&dsi1_in_vp2 { + status = "disabled"; +}; + +&vp3_out_dsi1 { + remote-endpoint = <&dsi1_in_vp3>; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; +&mipi_dcphy1 { + status = "okay"; +}; + + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + + + + +/**** edp0 ****/ + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&route_edp0 { + status = "okay"; + connect = <&vp0_out_edp0>; +}; + + +&edp0_in_vp0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "disabled"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + + + +/**** edp1 ****/ +&route_edp1 { + status = "okay"; + connect = <&vp1_out_edp1>; +}; + + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&hdptxphy1 { + status = "okay"; +}; + + + +&goodix_ts { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; diff --git a/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi new file mode 100755 index 0000000..fb05489 --- /dev/null +++ b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi @@ -0,0 +1,625 @@ +/ { + vcc33_lcd_n: vcc33-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc33_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; + }; + + + panel-edp0 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + +}; + + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2m1_pins>; +}; +&backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&backlight_edp { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + power-supply = <&vcc3v3_lcd_n>; + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1{ + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; + + rockchip,lane-rate = <444000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + +//enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + /*note: dsi0 uses the same pin,so dsi can not be configed*/ + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + + + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing1>; + dsi1_timing1: timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +/*dis0--->dcphy0--->vp2*/ +&vp2_out_dsi0{ + remote-endpoint = <&dsi0_in_vp2>; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; +&mipi_dcphy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; + + + +/*dis1--->dcphy1--->vp3*/ +&dsi1_in_vp2 { + status = "disabled"; +}; + +&vp3_out_dsi1 { + remote-endpoint = <&dsi1_in_vp3>; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; +&mipi_dcphy1 { + status = "okay"; +}; + + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + + + + +/****edp0****/ + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&route_edp0 { + status = "okay"; + connect = <&vp0_out_edp0>; +}; + + +&edp0_in_vp0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "disabled"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + + + +/**** hdmi1 ****/ +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + + +&hdptxphy_hdmi1 { + status = "okay"; +}; + + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; +}; + + + +&goodix_ts { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; diff --git a/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi new file mode 100755 index 0000000..466f636 --- /dev/null +++ b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-edp1.dtsi @@ -0,0 +1,596 @@ +/ { + vcc33_lcd_n: vcc33-lcd-n { + compatible = "regulator-fixed"; + regulator-name = "vcc33_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; + }; + + panel_edp1 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc33_lcd_n>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp1: endpoint { + remote-endpoint = <&edp1_out_panel>; + }; + }; + }; + + +}; + + +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + +&pwm2 { + status = "okay"; + pinctrl-0 = <&pwm2m1_pins>; +}; + +&backlight_lvds { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 25000 0>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + +&backlight_edp { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; +&edp1 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp1_out_panel: endpoint { + remote-endpoint = <&panel_in_edp1>; + }; + }; + }; +}; + + + + + + +/**dsi0**/ +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + + + + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1{ + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; + + rockchip,lane-rate = <444000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + +//enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + /*note: dsi0 uses the same pin,so dsi can not be configed*/ + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + + + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing1>; + dsi1_timing1: timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +/*dis0--->dcphy0--->vp2*/ +&vp2_out_dsi0{ + remote-endpoint = <&dsi0_in_vp2>; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; +&mipi_dcphy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; + + + +/*dis1--->dcphy1--->vp3*/ +&dsi1_in_vp2 { + status = "disabled"; +}; + +&vp3_out_dsi1 { + remote-endpoint = <&dsi1_in_vp3>; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; +&mipi_dcphy1 { + status = "okay"; +}; + + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + + +/****hdmi0****/ +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + + + +/****edp1****/ +&route_edp1 { + status = "okay"; + connect = <&vp1_out_edp1>; +}; + + +&edp1_in_vp0 { + status = "disabled"; +}; + +&edp1_in_vp1 { + status = "okay"; +}; + +&edp1_in_vp2 { + status = "disabled"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&goodix_ts { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; \ No newline at end of file diff --git a/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi new file mode 100755 index 0000000..620b2b4 --- /dev/null +++ b/rk3588/rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-hdmi0-hdmi1.dtsi @@ -0,0 +1,468 @@ +&backlight_mipi { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + +&backlight_lvds { + compatible = "pwm-backlight"; + //pwms = <&pwm1 0 25000 0>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + + + + +&vcc3v3_lcd_n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + //gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s3>; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1m1_pins>; +}; + + + + + + + + + + + +&dsi0 { + status = "okay"; + //rockchip,lane-rate = <480000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + + power-supply = <&vcc3v3_lcd_n>; + + + + + + //reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + backlight = <&backlight_mipi>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + 39 00 04 B9 F1 12 83 + + 39 00 1C BA 33 81 05 F9 0E 0E 20 00 00 00 00 00 00 00 44 25 00 91 0A 00 00 02 4F D1 00 00 37 + + 39 00 02 B8 26 + + 39 00 04 BF 02 10 00 + + 39 00 0B B3 07 0B 1E 1E 03 FF 00 00 00 00 + + 39 00 0A C0 73 73 50 50 00 00 08 70 00 + + 39 00 02 BC 46 + + 39 00 02 CC 0B + + 39 00 02 B4 80 + + 39 00 04 B2 C8 12 A0 + + 39 00 0F E3 07 07 0B 0B 03 0B 00 00 00 00 FF 80 C0 10 + + 39 00 0D C1 53 00 32 32 77 F1 FF FF CC CC 77 77 + + 39 00 03 B5 09 09 + + 39 00 03 B6 B7 B7 + + 39 00 40 E9 C2 10 0A 00 00 81 80 12 30 00 37 86 81 80 37 18 00 05 00 00 00 00 00 05 00 00 00 00 F8 BA 46 02 08 28 88 88 88 88 88 F8 BA 57 13 18 38 88 88 88 88 88 00 00 00 03 00 00 00 00 00 00 00 00 00 + + 39 00 3E EA 07 12 01 01 02 3C 00 00 00 00 00 00 8F BA 31 75 38 18 88 88 88 88 88 8F BA 20 64 28 08 88 88 88 88 88 23 10 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + 39 00 23 E0 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 00 02 04 1A 23 3F 2C 28 05 09 0B 10 11 10 12 12 19 + + 05 ff 01 11 ////Sleep Out + + 05 32 01 29 ///Display On + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <50000000>; + hactive = <720>; + vactive = <1280>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <11>; + vfront-porch = <16>; + hsync-len = <10>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1{ + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; + + rockchip,lane-rate = <444000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + +//enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + /*note: dsi0 uses the same pin,so dsi can not be configed*/ + /delete-property/ reset-gpios; + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + + backlight = <&backlight_lvds>; + init-delay-ms = <60>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + + panel-init-sequence = [ + + 23 08 02 27 AA + 23 08 02 48 02 + 23 08 02 B6 20 + 23 08 02 01 00 + 23 08 02 02 58 + 23 08 02 03 24 + 23 08 02 04 50 + 23 08 02 05 12 + 23 08 02 06 50 + 23 08 02 07 00 + 23 08 02 08 18 + 23 08 02 09 04 + 23 08 02 0A 18 + 23 08 02 0B 82 + 23 08 02 0C 1F + 23 08 02 0D 01 + 23 08 02 0E 80 + 23 08 02 0F 20 + 23 08 02 10 20 + 23 08 02 11 03 + 23 08 02 12 1B + 23 08 02 13 07 + 23 08 02 14 34 + 23 08 02 15 20 + 23 08 02 16 10 + 23 08 02 17 00 + 23 08 02 18 01 + 23 08 02 19 23 + 23 08 02 1A 40 + 23 08 02 1B 00 + 23 08 02 1E 46 + 23 08 02 51 30 + 23 08 02 1F 10 + 23 08 02 2A 01 + + + + + 05 78 01 11 //sleep out + 05 20 01 29 //display on + ]; + + panel-exit-sequence = [ + 05 78 01 28 + 05 78 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi1_timing1>; + dsi1_timing1: timing1 { + clock-frequency = <50000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <80>; + hfront-porch = <80>; + vback-porch = <24>; + vfront-porch = <24>; + hsync-len = <18>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + + + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; +}; + +/*dis0--->dcphy0--->vp2*/ +&vp2_out_dsi0{ + remote-endpoint = <&dsi0_in_vp2>; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; +&mipi_dcphy0 { + status = "okay"; +}; + + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; + + + +/*dis1--->dcphy1--->vp3*/ +&dsi1_in_vp2 { + status = "disabled"; +}; + +&vp3_out_dsi1 { + remote-endpoint = <&dsi1_in_vp3>; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; +&mipi_dcphy1 { + status = "okay"; +}; + + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + + +/**** hdmi0 ****/ +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&route_hdmi0 { + status = "okay"; + connect = <&vp0_out_hdmi0>; +}; + + +/**** hdmi1 ****/ +&hdmi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>; +}; + +&hdmi1_in_vp1 { + status = "okay"; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + + +&hdptxphy_hdmi1 { + status = "okay"; +}; + + +&route_hdmi1 { + status = "okay"; + connect = <&vp1_out_hdmi1>; +}; + + + + + diff --git a/rk3588/rp-lcd-rk3588s-edp0-13.3-15.6-1920-1080.dtsi b/rk3588/rp-lcd-rk3588s-edp0-13.3-15.6-1920-1080.dtsi new file mode 100755 index 0000000..fcb4cab --- /dev/null +++ b/rk3588/rp-lcd-rk3588s-edp0-13.3-15.6-1920-1080.dtsi @@ -0,0 +1,165 @@ + +/ { + panel-edp0 { + compatible = "simple-panel"; + backlight = <&backlight_edp>; + power-supply = <&vcc3v3_lcd>; + init-delay-ms = <120>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <129>; + height-mm = <171>; + + panel-timing { + clock-frequency = <150000000>; + hactive = <1920>; + vactive = <1080>; + hfront-porch = <160>; + hsync-len = <32>; + hback-porch = <160>; + vfront-porch = <3>; + vsync-len = <5>; + vback-porch = <23>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp0: endpoint { + remote-endpoint = <&edp0_out_panel>; + }; + }; + }; + +}; + +&vcc3v3_lcd{ + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd"; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_s0>; +}; + + +&backlight_edp { + compatible = "pwm-backlight"; + //pwms = <&pwm0 0 25000 1>; + status = "okay"; + brightness-levels = < + 80 82 84 86 88 90 92 94 + 100 100 100 100 100 100 100 100 + 110 110 110 110 110 110 110 110 + 120 120 120 120 120 120 120 120 + 130 130 130 130 130 130 130 130 + 140 150 150 150 150 150 150 150 + 170 170 170 170 170 170 170 170 + 170 170 170 170 170 170 170 170 + 180 180 180 180 180 180 180 180 + 180 180 180 180 180 180 180 180 + 190 190 190 190 190 190 190 190 + 190 190 190 190 190 190 190 190 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 200 200 200 200 200 200 200 200 + 210 210 210 210 210 210 210 210 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 220 220 220 220 220 220 220 220 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 230 230 230 230 230 230 230 230 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 240 240 240 240 240 240 240 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp0_out_panel: endpoint { + remote-endpoint = <&panel_in_edp0>; + }; + }; + }; +}; + +&route_edp0 { + status = "okay"; + connect = <&vp0_out_edp0>; +}; + + +&edp0_in_vp0 { + status = "okay"; +}; + +&edp0_in_vp1 { + status = "disabled"; +}; + +&edp0_in_vp2 { + status = "disabled"; +}; + +&hdptxphy0 { + status = "okay"; +}; + + + + +&goodix_ts { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + gtp_resolution_x = <1920>; + gtp_resolution_y = <1080>; + gtp_int_tarigger = <1>; + gtp_change_x2y = <0>; + gtp_overturn_x = <0>; + gtp_overturn_y = <0>; + gtp_send_cfg = <1>; + gtp_touch_wakeup = <1>; + + goodix,cfg-group0 = [ + 43 80 07 38 04 0A 3D 00 01 06 + 28 08 55 32 03 05 00 00 00 00 + 00 00 06 18 1A 1E 14 95 35 FF + 2D 2F A6 0F 00 00 00 01 03 2C + 00 00 00 00 00 00 00 00 00 00 + 00 2D 5A 94 D0 42 00 08 00 04 + 79 30 00 6E 37 00 65 3F 00 5D + 49 00 57 54 00 57 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 + 00 00 1D 1C 1B 1A 19 18 17 16 + 15 14 13 12 11 10 0F 0E 0D 0C + 0B 0A 09 08 07 06 05 04 03 02 + 01 00 00 01 02 03 04 05 06 07 + 08 09 0A 0B 0C 0D 0E 0F 10 11 + 12 13 14 15 16 17 18 19 1B 1C + 1D 1E 1F 20 21 22 23 24 25 26 + 27 28 29 2A 86 01 + ]; +}; + diff --git a/rk3588/rp-lcd-typec-dp0.dtsi b/rk3588/rp-lcd-typec-dp0.dtsi new file mode 100644 index 0000000..61d3f5d --- /dev/null +++ b/rk3588/rp-lcd-typec-dp0.dtsi @@ -0,0 +1,16 @@ +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + diff --git a/rk3588/rp-multi-lcd-edp0-13.3-edp1-13.3-dp0.dtsi b/rk3588/rp-multi-lcd-edp0-13.3-edp1-13.3-dp0.dtsi new file mode 100644 index 0000000..ef578fd --- /dev/null +++ b/rk3588/rp-multi-lcd-edp0-13.3-edp1-13.3-dp0.dtsi @@ -0,0 +1,12 @@ +#include "rp-lcd-edp0-13.3-15.6-1920-1080.dtsi" +#include "rp-lcd-edp1-13.3-15.6-1920-1080.dtsi" +#include "rp-lcd-typec-dp0.dtsi" // usb dp0, must be enable rp-usb-typec.dtsi + + +&route_edp0 { + status = "disabled"; +}; + +&route_edp1 { + status = "disabled"; +}; \ No newline at end of file diff --git a/rk3588/rp-multi-lcd-edp0-13.3-edp1-15.6-dp0.dtsi b/rk3588/rp-multi-lcd-edp0-13.3-edp1-15.6-dp0.dtsi new file mode 100644 index 0000000..deea5f5 --- /dev/null +++ b/rk3588/rp-multi-lcd-edp0-13.3-edp1-15.6-dp0.dtsi @@ -0,0 +1,12 @@ +#include "rp-lcd-edp0-13.3-15.6-1920-1080.dtsi" +#include "rp-lcd-edp1-13.3-15.6-1920-1080.dtsi" +#include "rp-lcd-typec-dp0.dtsi" // usb dp0, must be enable rp-usb-typec.dtsi + + +&route_edp0 { + status = "okay"; +}; + +&route_edp1 { + status = "okay"; +}; \ No newline at end of file diff --git a/rk3588/rp-pcie-5g.dtsi b/rk3588/rp-pcie-5g.dtsi new file mode 100755 index 0000000..ceacb2c --- /dev/null +++ b/rk3588/rp-pcie-5g.dtsi @@ -0,0 +1,45 @@ +/{ + vdd_5G: vdd-5G{ + compatible = "regulator-fixed"; + regulator-name = "vdd_5G"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + }; +}; + +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + phys = <&combphy2_psu PHY_TYPE_PCIE>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + //modem-pwr-gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + modem-en-gpios = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>; + pcie-waken-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&modem_wakup>,<&modem_rst>,<&modem_pwr>,<&modem_en>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + + +&pinctrl { + modem { + modem_pwr: modem-pwr { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + modem_en: modem-en { + rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + modem_rst: modem-rst { + rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + modem_wakup: modem-wakup { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588/rp-pcie-m2.dtsi b/rk3588/rp-pcie-m2.dtsi new file mode 100755 index 0000000..35acc09 --- /dev/null +++ b/rk3588/rp-pcie-m2.dtsi @@ -0,0 +1,12 @@ +&combphy2_psu { + status = "okay"; +}; + +&pcie2x1l1 { + phys = <&combphy2_psu PHY_TYPE_PCIE>; + reset-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + + diff --git a/rk3588/rp-pcie-power-rk3588.dtsi b/rk3588/rp-pcie-power-rk3588.dtsi new file mode 100755 index 0000000..e1f81f7 --- /dev/null +++ b/rk3588/rp-pcie-power-rk3588.dtsi @@ -0,0 +1,35 @@ + +/ { + pcie20_avdd0v85: pcie20-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + pcie20_avdd1v8: pcie20-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie20_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + +}; diff --git a/rk3588/rp-pcie-power-rk3588s.dtsi b/rk3588/rp-pcie-power-rk3588s.dtsi new file mode 100755 index 0000000..93003b7 --- /dev/null +++ b/rk3588/rp-pcie-power-rk3588s.dtsi @@ -0,0 +1,23 @@ + +/ { + + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; +}; diff --git a/rk3588/rp-pcie3.dtsi b/rk3588/rp-pcie3.dtsi new file mode 100755 index 0000000..6542be0 --- /dev/null +++ b/rk3588/rp-pcie3.dtsi @@ -0,0 +1,33 @@ +/ { + + pcie30_avdd1v8: pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-name = "pcie30_avdd0v75"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + vin-supply = <&avdd_0v75_s0>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + diff --git a/rk3588/rp-rk3588-board.dtsi b/rk3588/rp-rk3588-board.dtsi new file mode 100755 index 0000000..fc340c3 --- /dev/null +++ b/rk3588/rp-rk3588-board.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +/* merage dtsi in rk3588-evb4-lp4-v10-linux.dts */ + +#include "dt-bindings/usb/pd.h" +#include "../rk3588j.dtsi" +#include "../rk3588-evb.dtsi" +#include "../rk3588-rk806-single.dtsi" +#include "../rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588 EVB4 LP4 V10 Board"; + compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&dsi0 { + status = "disabled"; + /delete-node/ panel@0; + ports { + /delete-node/ port@1; + }; +}; + +&dsi1 { + status = "disabled"; + /delete-node/ panel@0; + ports { + /delete-node/ port@1; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + + +&fiq_debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + + +/delete-node/ &backlight; diff --git a/rk3588/rp-rk3588.dts b/rk3588/rp-rk3588.dts new file mode 100755 index 0000000..4a1c440 --- /dev/null +++ b/rk3588/rp-rk3588.dts @@ -0,0 +1,240 @@ +/* board base */ +//#include "../rk3588-evb4-lp4-v10-linux.dts" +#include "rp-rk3588-board.dtsi" + +#include "rp-tp-i2c6-gt911.dtsi" +#include "rd-rk3588-lcd-gpio.dtsi" + +/* usb */ +#include "rp-usb-typec-rk3588.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588.dtsi" +#include "rp-eth-gmac1.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588.dtsi" +#include "rp-pcie3.dtsi" //need comment when use board of make it youself,and remove the pcie function +#include "rp-pcie-5g.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-vs2275p-rk3588.dtsi" + +/* hdmi rx */ +#include "rp-hdmirx.dtsi" + +/* mipi camera */ +/* use dcphy0 camera , need to disabled rp-hdmirx.dtsi*/ +/***********all camera config********/ + + +//#include "rp-camera-dcphy0.dtsi" +#include "rp-camera-dcphy1.dtsi" +#include "rp-camera-dphy0.dtsi" +#include "rp-camera-dphy1.dtsi" + +//#include "rp-camera-dcphy0-ov13855.dtsi" +//#include "rp-camera-dcphy1-ov13855.dtsi" +//#include "rp-camera-dphy0-ov13855.dtsi" +//#include "rp-camera-dphy1-ov13855.dtsi" + +//#include "rp-camera-dcphy0-gc8034.dtsi" +//#include "rp-camera-dcphy1-gc8034.dtsi" +//#include "rp-camera-dphy0-gc8034.dtsi" +//#include "rp-camera-dphy1-gc8034.dtsi" + +//#include "rp-camera-dcphy0-imx415.dtsi" +//#include "rp-camera-dcphy1-imx415.dtsi" +//#include "rp-camera-dphy0-imx415.dtsi" +//#include "rp-camera-dphy1-imx415.dtsi" + +/**********4 channel must be disabled hdmi in*********/ +//#include "rp-camera-dcphy1-gc8034.dtsi" +//#include "rp-camera-dphy1-gc8034.dtsi" +//#include "rp-camera-dcphy0-imx415.dtsi" +//#include "rp-camera-dphy0-imx415.dtsi" +/******************************************/ + +//#include "rp-lcd-hdmi0.dtsi" //batch ignore +//#include "rp-lcd-hdmi1.dtsi" //batch ignore +//#include "rp-lcd-typec-dp0.dtsi" //usb edp0,must be enable rp-usb-typec.dtsi, batch ignore +#include "rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" + +/* lcd */ +#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" + +/ { + model = "rp-rk3588"; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma_trans: dma-trans@3c000000 { + reg = <0x0 0x3c000000 0x0 0x04000000>; + }; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + //fan { + // gpio_num = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power { + gpio_num = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio1d2 { + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + gpio3c6 { + gpio_num = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + + + + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m0_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m0_xfer>; +}; + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + //pinctrl-names = "default"; + //pinctrl-0 = <&hym8563_int>; + //interrupt-parent = <&gpio0>; + //interrupts = ; + //wakeup-source; + }; + +}; + + +&sdmmc { + status = "okay"; + //vmmc-supply = <&vccio_sd_s0>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; + diff --git a/rk3588/rp-rk3588s-board.dtsi b/rk3588/rp-rk3588s-board.dtsi new file mode 100755 index 0000000..0fd5868 --- /dev/null +++ b/rk3588/rp-rk3588s-board.dtsi @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +/* merage dtsi in rk3588s-evb4-lp4-v10-linux.dts */ + +#include "dt-bindings/usb/pd.h" +#include "../rk3588s.dtsi" +#include "../rk3588s-evb.dtsi" +#include "../rk3588-rk806-single.dtsi" +#include "../rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588S EVB4 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb4-lp4x-v10", "rockchip,rk3588"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_HIGH>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + vsel-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&fiq_debugger { + compatible = "rockchip,fiq-debugger"; + rockchip,serial-id = <2>; + rockchip,wake-irq = <0>; + /* If enable uart uses irq instead of fiq */ + rockchip,irq-mode-enable = <1>; + rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + + + + diff --git a/rk3588/rp-rk3588s-lcd-gpio.dtsi b/rk3588/rp-rk3588s-lcd-gpio.dtsi new file mode 100755 index 0000000..3d6f464 --- /dev/null +++ b/rk3588/rp-rk3588s-lcd-gpio.dtsi @@ -0,0 +1,76 @@ + +/ { + vcc3v3_lcd_n: vcc3v3-lcd0-n { + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + }; + + vcc3v3_lcd: vcc3v3-lcd { + gpio = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; + }; + + backlight_mipi: backlight { + pwms = <&pwm12 0 25000 0>; + }; + + backlight_edp: backlight-edp { + pwms = <&pwm8 0 25000 1>; + }; + + backlight_lvds: backlight-lvds { + pwms = <&pwm8 0 25000 1>; + }; +}; + + +&pwm8 { + status = "okay"; + pinctrl-0 = <&pwm8m0_pins>; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + + +&dsi0 { + status = "disabled"; + dsi0_panel: panel@0 { + status = "disabled"; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + +&dsi1 { + status = "disabled"; + dsi1_panel: panel@0 { + status = "disabled"; + enable-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + }; +}; + +&pinctrl { + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + goodix { + goodix_irq: goodix-irq { + rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&goodix_ts { + goodix_rst_gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + goodix_irq_gpio = <&gpio1 RK_PA7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_irq>; +}; diff --git a/rk3588/rp-rk3588s.dts b/rk3588/rp-rk3588s.dts new file mode 100755 index 0000000..5fe3f8d --- /dev/null +++ b/rk3588/rp-rk3588s.dts @@ -0,0 +1,283 @@ +/* board base */ +//#include "../rk3588s-evb4-lp4x-v10-linux.dts" +#include "rp-rk3588s-board.dtsi" + +#include "rp-tp-i2c4-gt911.dtsi" +#include "rp-rk3588s-lcd-gpio.dtsi" + +#include "rpdzkj_config.dtsi" + +/* usb */ +#include "rp-usb-typec-rk3588s.dtsi" +#include "rp-usb-host.dtsi" + +/* ethernet */ +#include "rp-eth-pcie2gmac-rk3588s.dtsi" + +/* pcie */ +#include "rp-pcie-power-rk3588s.dtsi" + +/* audio */ +#include "rp-audio-rt5640.dtsi" + +/* wifi/bt */ +#include "rp-wifi-bt-ap6275p-rk3588s.dtsi" + +/* camera */ +#include "rp-camera-mipi-xs9922b.dtsi" + + +#include "rp-lcd-typec-dp0.dtsi" //usb edp0,must be enable rp-usb-typec.dtsi, batch ignore +#include "rp-lcd-hdmi0.dtsi" + +/* signel lcd */ +#include "rp-lcd-mipi0-5-720-1280-v2-boxTP.dtsi" +//#include "rp-lcd-mipi0-7-720-1280.dtsi" +//#include "rp-lcd-mipi0-8-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-8-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-800-1280-v3.dtsi" +//#include "rp-lcd-mipi0-10-1200-1920.dtsi" +//#include "rp-lcd-mipi0-10-1920-1200-jc.dtsi" +//#include "rp-lcd-rk3588s-edp0-13.3-15.6-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-21-1920-1080.dtsi" +//#include "rp-lcd-mipi1-gm8775-lvds-10.1-1024-600.dtsi" + +/* quadplex lcd */ +//#include "rp-lcd-quadplex-mipi0-5-720-1280-v2-boxTP-mipi1-gm8775-lvds-10.1-1024-600-edp0-hdmi1.dtsi" + + +/ { + model = "rp-rk3588s"; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + fan_gpio_control { + compatible = "fan_gpio_control"; + gpio-pin = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + thermal-zone = "soc-thermal"; + threshold-temp = <60000>; //60C + running-time = <10000>; //10s + status = "okay"; + }; + + rp_power{ + status = "okay"; + compatible = "rp_power"; + rp_not_deep_sleep = <1>; + +//#define GPIO_FUNCTION_OUTPUT 0 +//#define GPIO_FUNCTION_INPUT 1 +//#define GPIO_FUNCTION_IRQ 2 +//#define GPIO_FUNCTION_FLASH 3 +//#define GPIO_FUNCTION_OUTPUT_CTRL 4 + + vdd-3v { + gpio_num = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + //fan { + // gpio_num = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>; + // gpio_function = <4>; + //}; + + led { + gpio_num = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; + gpio_function = <3>; + }; + + usb-host-power1 { + gpio_num = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-host-power2 { + gpio_num = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-host-power3 { + gpio_num = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-host-power4 { + gpio_num = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + usb-hub-reset { + gpio_num = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; + gpio_function = <4>; + }; + + sd-pwren { + gpio_num = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + + pwren-4g { + gpio_num = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; + gpio_function = <4>; + }; + }; + + rp_gpio{ + status = "okay"; + compatible = "rp_gpio"; + + gpio0d3 { + gpio_num = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio0b0 { + gpio_num = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1c1 { + gpio_num = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1c4 { + gpio_num = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1c6 { + gpio_num = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1d2 { + gpio_num = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + gpio1d3 { + gpio_num = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; + gpio_function = <0>; + }; + }; +}; + + +&uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m2_xfer>; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; +}; + +&uart3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m2_xfer>; +}; + +&uart4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m2_xfer>; +}; + + +&uart5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; +}; + +&uart6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; +}; + +&uart7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; +}; + +&fiq_debugger { + rockchip,baudrate = <115200>; +}; + + +&can0 { + assigned-clocks = <&cru CLK_CAN0>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; +}; + +&can1 { + assigned-clocks = <&cru CLK_CAN1>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m1_pins>; +}; + +&can2 { + assigned-clocks = <&cru CLK_CAN2>; + assigned-clock-rates = <200000000>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m1_pins>; +}; + +&sdmmc { + status = "okay"; + /delete-property/ vmmc-supply; +}; +/* +&rk_headset { + headset_gpio = <&gpio1 RK_PC0 GPIO_ACTIVE_HIGH>; +}; +*/ + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + }; + +}; + +&display_subsystem { +clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; +clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; +}; + +&hdptxphy_hdmi_clk0 { + status = "okay"; +}; + +&hdptxphy_hdmi_clk1 { + status = "okay"; +}; diff --git a/rk3588/rp-tp-i2c4-gt911.dtsi b/rk3588/rp-tp-i2c4-gt911.dtsi new file mode 100755 index 0000000..4e9b65c --- /dev/null +++ b/rk3588/rp-tp-i2c4-gt911.dtsi @@ -0,0 +1,13 @@ + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + goodix_ts:goodix_ts@5d { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + }; +}; + diff --git a/rk3588/rp-tp-i2c6-gt911.dtsi b/rk3588/rp-tp-i2c6-gt911.dtsi new file mode 100755 index 0000000..e8a3966 --- /dev/null +++ b/rk3588/rp-tp-i2c6-gt911.dtsi @@ -0,0 +1,12 @@ + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + + goodix_ts:goodix_ts@5d { + status = "okay"; + compatible = "goodix,gt9xx"; + reg = <0x5d>; + }; +}; diff --git a/rk3588/rp-usb-host.dtsi b/rk3588/rp-usb-host.dtsi new file mode 100755 index 0000000..5603215 --- /dev/null +++ b/rk3588/rp-usb-host.dtsi @@ -0,0 +1,48 @@ + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; +/* +&u2phy1_otg { + status = "disabled"; +}; +*/ +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + + + + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + diff --git a/rk3588/rp-usb-typea-rk3588.dtsi b/rk3588/rp-usb-typea-rk3588.dtsi new file mode 100644 index 0000000..22eb179 --- /dev/null +++ b/rk3588/rp-usb-typea-rk3588.dtsi @@ -0,0 +1,9 @@ +&usbdrd_dwc3_0 { + dr_mode = "otg"; + extcon=<&u2phy0>; + status="okay"; +}; + +&u2phy0 { + status = "okay"; +}; diff --git a/rk3588/rp-usb-typec-rk3588.dtsi b/rk3588/rp-usb-typec-rk3588.dtsi new file mode 100755 index 0000000..149fb08 --- /dev/null +++ b/rk3588/rp-usb-typec-rk3588.dtsi @@ -0,0 +1,137 @@ + +/ { + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + + + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&pinctrl { + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; +}; diff --git a/rk3588/rp-usb-typec-rk3588s.dtsi b/rk3588/rp-usb-typec-rk3588s.dtsi new file mode 100755 index 0000000..89cd241 --- /dev/null +++ b/rk3588/rp-usb-typec-rk3588s.dtsi @@ -0,0 +1,137 @@ + +/ { + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + + + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + + +&pinctrl { + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + }; +}; diff --git a/rk3588/rp-wifi-bt-ap6275p-rd-rk3588s-ahd.dtsi b/rk3588/rp-wifi-bt-ap6275p-rd-rk3588s-ahd.dtsi new file mode 100755 index 0000000..a836ee3 --- /dev/null +++ b/rk3588/rp-wifi-bt-ap6275p-rd-rk3588s-ahd.dtsi @@ -0,0 +1,66 @@ + +/ { + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + + +&pinctrl { + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588/rp-wifi-bt-ap6275p-rk3588.dtsi b/rk3588/rp-wifi-bt-ap6275p-rk3588.dtsi new file mode 100755 index 0000000..fe662da --- /dev/null +++ b/rk3588/rp-wifi-bt-ap6275p-rk3588.dtsi @@ -0,0 +1,68 @@ + +/ { + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie2x1l0 { + phys = <&combphy1_ps PHY_TYPE_PCIE>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + + +&pinctrl { + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_gpio: bt-gpio { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588/rp-wifi-bt-ap6275p-rk3588s.dtsi b/rk3588/rp-wifi-bt-ap6275p-rk3588s.dtsi new file mode 100755 index 0000000..9118363 --- /dev/null +++ b/rk3588/rp-wifi-bt-ap6275p-rk3588s.dtsi @@ -0,0 +1,66 @@ + +/ { + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m2_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; +}; + + +&pinctrl { + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>, + <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>, + <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588/rp-wifi-bt-vs2275p-rk3588.dtsi b/rk3588/rp-wifi-bt-vs2275p-rk3588.dtsi new file mode 100755 index 0000000..4867305 --- /dev/null +++ b/rk3588/rp-wifi-bt-vs2275p-rk3588.dtsi @@ -0,0 +1,101 @@ + +/ { + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart9m0_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart9_gpios>; + BT,reset_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + bt-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion = <1>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + // sound-dai = <&sai2>; + sound-dai = <&i2s2_2ch>; + }; + + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + bt_sco: bt-sco { + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + status = "okay"; + }; +}; + +&i2s2_2ch { + status = "okay"; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s2m0_sdi + &i2s2m0_sdo>; + pinctrl-1 = <&i2s2m0_idle>; + pinctrl-2 = <&i2s2m0_lrck + &i2s2m0_sclk>; + +}; + +&combphy1_ps { + status = "okay"; +}; + +&pcie2x1l0 { + phys = <&combphy1_ps PHY_TYPE_PCIE>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&uart9 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; +}; + + +&pinctrl { + wireless-bluetooth { + uart9_gpios: uart9-gpios { + rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + bt_gpio: bt-gpio { + rockchip,pins = + <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, + <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>, + <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; diff --git a/rk3588/rpdzkj_config.dtsi b/rk3588/rpdzkj_config.dtsi new file mode 100644 index 0000000..d74199b --- /dev/null +++ b/rk3588/rpdzkj_config.dtsi @@ -0,0 +1,20 @@ + +/ { + rpdzkj:rpdzkj_config { + compatible = "rp_config"; + + lcd_device0 = "DSI-1"; + lcd_rotate0 = "0"; + + lcd_device1 = "HDMI-1"; + lcd_rotate1 = "0"; + + lcd_device2 = "HDMI-2"; + lcd_rotate2 = "0"; + + lcd_device3 = "DP-1"; + lcd_rotate3 = "0"; + + status = "okay"; + }; +}; diff --git a/rk3588j.dtsi b/rk3588j.dtsi new file mode 100644 index 0000000..7b084b2 --- /dev/null +++ b/rk3588j.dtsi @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" + +&cluster0_opp_table { + /* + * The Max frequency is 1296MHz in default normal mode. + * The Max frequency is 1704MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-1416000000; + /delete-node/ opp-j-m-1608000000; + /delete-node/ opp-j-m-1704000000; +}; + +&cluster1_opp_table { + /* + * The Max frequency is 1608MHz in default normal mode. + * The Max frequency is 2016MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-1800000000; + /delete-node/ opp-j-m-2016000000; +}; + +&cluster2_opp_table { + /* + * The Max frequency is 1608MHz in default normal mode. + * The Max frequency is 2016MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-1800000000; + /delete-node/ opp-j-m-2016000000; +}; + +&gpu_opp_table { + /* + * The Max frequency is 700MHz in default normal mode. + * The Max frequency is 850MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-850000000; +}; + +&npu_opp_table { + /* + * The Max frequency is 800MHz in default normal mode. + * The Max frequency is 950MHz in overdrive mode, + * but under the overdrive mode for a long time, + * the chipset may shorten the lifetime, + * especially in high temperature condition. + */ + /delete-node/ opp-j-m-950000000; +}; diff --git a/rk3588m.dtsi b/rk3588m.dtsi new file mode 100644 index 0000000..38b9dbf --- /dev/null +++ b/rk3588m.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588.dtsi" diff --git a/rk3588s-evb.dtsi b/rk3588s-evb.dtsi new file mode 100644 index 0000000..586c627 --- /dev/null +++ b/rk3588s-evb.dtsi @@ -0,0 +1,1153 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + + menu-key { + label = "menu"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + + back-key { + label = "back"; + linux,code = ; + press-threshold-microvolt = <1235000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + dp0_sound: dp0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + hdmi0_sound: hdmi0-sound { + status = "disabled"; + compatible = "rockchip,hdmi"; + rockchip,mclk-fs = <128>; + rockchip,card-name = "rockchip-hdmi0"; + rockchip,cpu = <&i2s5_8ch>; + rockchip,codec = <&hdmi0>; + rockchip,jack-det; + }; + + spdif_tx1_dc: spdif-tx1-dc { + status = "disabled"; + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_tx1_sound: spdif-tx1-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,name = "rockchip,spdif-tx1"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,cpu { + sound-dai = <&spdif_tx1>; + }; + simple-audio-card,codec { + sound-dai = <&spdif_tx1_dc>; + }; + }; + + test-power { + status = "okay"; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usbdcin: vcc5v0-usbdcin { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usbdcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usbdcin>; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dsi0 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "disabled"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; +}; + +&u2phy3_host { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbhost3_0 { + status = "okay"; +}; + +&usbhost_dwc3_0 { + status = "okay"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +/* vp0 & vp1 splice for 8K output */ +&vp0 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; + rockchip,primary-plane = ; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; + rockchip,primary-plane = ; +}; + +&vp3 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588s-evb1-lp4x-v10-camera.dtsi b/rk3588s-evb1-lp4x-v10-camera.dtsi new file mode 100644 index 0000000..086eee3 --- /dev/null +++ b/rk3588s-evb1-lp4x-v10-camera.dtsi @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp_mipi_in: endpoint@1 { + reg = <1>; + remote-endpoint = <<7911d_out>; + data-lanes = <1 2 3 4>; + }; + mipi_in_dcphy0: endpoint@2 { + reg = <2>; + remote-endpoint = <&ov50c40_out0>; + data-lanes = <1 2 3 4>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_dcphy1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov50c40_out1>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m4_xfer>; + + aw8601: aw8601@c { + compatible = "awinic,aw8601"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <56>; + rockchip,vcm-rated-current = <96>; + rockchip,vcm-step-mode = <4>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + lt7911d: lt7911d@2b { + compatible = "lontium,lt7911d"; + status = "okay"; + reg = <0x2b>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + interrupt-parent = <&gpio3>; + interrupts = ; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + // hpd-ctl-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + // plugin-det-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "LT7911D"; + rockchip,camera-module-lens-name = "NC"; + port { + lt7911d_out: endpoint { + remote-endpoint = <&dp_mipi_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + ov50c40: ov50c40@36 { + compatible = "ovti,ov50c40"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HZGA06"; + rockchip,camera-module-lens-name = "ZE0082C1"; + eeprom-ctrl = <&otp_eeprom>; + lens-focus = <&aw8601>; + port { + ov50c40_out0: endpoint { + remote-endpoint = <&mipi_in_dcphy0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + otp_eeprom: otp_eeprom@50 { + compatible = "rk,otp_eeprom"; + status = "okay"; + reg = <0x50>; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + + aw8601b: aw8601b@c { + compatible = "awinic,aw8601"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <56>; + rockchip,vcm-rated-current = <96>; + rockchip,vcm-step-mode = <4>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + }; + + ov50c40b: ov50c40b@36 { + compatible = "ovti,ov50c40"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera2_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HZGA06"; + rockchip,camera-module-lens-name = "ZE0082C1"; + eeprom-ctrl = <&otp_eeprom_b>; + lens-focus = <&aw8601b>; + port { + ov50c40_out1: endpoint { + remote-endpoint = <&mipi_in_dcphy1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + otp_eeprom_b: otp_eeprom_b@50 { + compatible = "rk,otp_eeprom"; + status = "okay"; + reg = <0x50>; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp_unite { + status = "okay"; + +}; + +&rkisp_unite_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + */ + rockchip,hw = <&rkisp_unite>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp1_in2: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; diff --git a/rk3588s-evb1-lp4x-v10-linux.dts b/rk3588s-evb1-lp4x-v10-linux.dts new file mode 100644 index 0000000..4d8157b --- /dev/null +++ b/rk3588s-evb1-lp4x-v10-linux.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb1-lp4x.dtsi" +#include "rk3588s-evb1-lp4x-v10-camera.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588S EVB1 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb1-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb1-lp4x-v10.dts b/rk3588s-evb1-lp4x-v10.dts new file mode 100644 index 0000000..ec195f6 --- /dev/null +++ b/rk3588s-evb1-lp4x-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb1-lp4x.dtsi" +#include "rk3588s-evb1-lp4x-v10-camera.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB1 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb1-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb1-lp4x.dtsi b/rk3588s-evb1-lp4x.dtsi new file mode 100644 index 0000000..8c1d0f3 --- /dev/null +++ b/rk3588s-evb1-lp4x.dtsi @@ -0,0 +1,870 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588s-evb.dtsi" +#include "rk3588s-rk806-dual.dtsi" + +/ { + aw883xx_sound: aw883x-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-aw883xx"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&aw883xx_1 &aw883xx_2 &aw883xx_3 &aw883xx_4>; + }; + + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8326_sound: es8326-sound { + status = "disabled"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8326"; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s1_8ch>; + rockchip,codec = <&es8326>; + rockchip,audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "MIC1", "Headset Mic", + "MIC2", "Main Mic"; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm11 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio0 RK_PD4 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + panel-edp { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <120>; + height-mm = <160>; + + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_edp"; + gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm12 0 25000 0>; + power-supply = <&vcc3v3_lcd_edp>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ + training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + >; + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es8326: es8326@18 { + status = "disabled"; + #sound-dai-cells = <0>; + compatible = "everest,es8326"; + reg = <0x18>; + clocks = <&mclkout_i2s1>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s1>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_mclk>; + mclk-rate = <12288000>; + mic1-src = [22]; + mic2-src = [44]; + jack-pol = [0e]; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; + + aw883xx_1: aw883xx@34 { + compatible = "awinic,aw883xx_smartpa"; + reg = <0x34>; + #sound-dai-cells = <0>; + reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&aw_rst1_gpio>; + pinctrl-names = "default"; + sound-channel = <0>; + re-min = <1000>; + re-max= <40000>; + status = "disabled"; + }; + + aw883xx_2: aw883xx@35 { + compatible = "awinic,aw883xx_smartpa"; + reg = <0x35>; + #sound-dai-cells = <0>; + reset-gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&aw_rst2_gpio>; + pinctrl-names = "default"; + sound-channel = <1>; + re-min = <1000>; + re-max= <40000>; + status = "disabled"; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; + + aw883xx_3: aw883xx@34 { + compatible = "awinic,aw883xx_smartpa"; + reg = <0x34>; + #sound-dai-cells = <0>; + reset-gpio = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&aw_rst3_gpio>; + pinctrl-names = "default"; + sound-channel = <2>; + re-min = <1000>; + re-max= <40000>; + status = "disabled"; + }; + + aw883xx_4: aw883xx@35 { + compatible = "awinic,aw883xx_smartpa"; + reg = <0x35>; + #sound-dai-cells = <0>; + reset-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&aw_rst4_gpio>; + pinctrl-names = "default"; + sound-channel = <3>; + re-min = <1000>; + re-max= <40000>; + status = "disabled"; + }; + + gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c5 { + status = "okay"; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + aw883x { + aw_rst1_gpio: aw-rst1-gpio { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + aw_rst2_gpio: aw-rst2-gpio { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + aw_rst3_gpio: aw-rst3-gpio { + rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + aw_rst4_gpio: aw-rst4-gpio { + rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sensor { + mh248_irq_gpio: mh248_irq_gpio { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + mpu6500_irq_gpio: mpu6500_irq_gpio { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3m3_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&pwm11 { + pinctrl-0 = <&pwm11m1_pins>; + status = "okay"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&route_edp0 { + connect = <&vp2_out_edp0>; + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&spdif_tx1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m1_tx>; +}; + +&spdif_tx1_dc { + status = "okay"; +}; + +&spdif_tx1_sound { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +/* vp0 & vp3 are not used on this board */ +&vp0 { + /delete-property/ rockchip,plane-mask; + /delete-property/ rockchip,primary-plane; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&vp3 { + /delete-property/ rockchip,plane-mask; + /delete-property/ rockchip,primary-plane; +}; diff --git a/rk3588s-evb2-lp5-v10-linux.dts b/rk3588s-evb2-lp5-v10-linux.dts new file mode 100644 index 0000000..2dcd6a6 --- /dev/null +++ b/rk3588s-evb2-lp5-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb2-lp5.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588S EVB2 LP5 V10 Board"; + compatible = "rockchip,rk3588s-evb2-lp5-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb2-lp5-v10.dts b/rk3588s-evb2-lp5-v10.dts new file mode 100644 index 0000000..b34c15e --- /dev/null +++ b/rk3588s-evb2-lp5-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb2-lp5.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB2 LP5 V10 Board"; + compatible = "rockchip,rk3588s-evb2-lp5-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb2-lp5.dtsi b/rk3588s-evb2-lp5.dtsi new file mode 100644 index 0000000..5c07f76 --- /dev/null +++ b/rk3588s-evb2-lp5.dtsi @@ -0,0 +1,953 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "rk3588s.dtsi" +#include "rk3588s-evb.dtsi" +#include "rk3588s-rk806-dual.dtsi" + +/ { + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc5v0_u2host: vcc5v0-u2host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_u2host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_u2host_en>; + }; + + vcc5v0_u3host: vcc5v0-u3host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_u3host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_u3host_en>; + }; +}; + +&backlight { + pwms = <&pwm7 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + pinctrl-0 = <&dp0m2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi0 enable and dsi1 disabled + * case. + */ + //reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + phy-c-option; + dsi,lanes = <3>; + + panel-init-sequence = [ + 23 00 02 FF 20 + 23 00 02 FB 01 + 23 00 02 05 D9 + /* VGH=17V */ + 23 00 02 07 78 + /* VGL=-14V */ + 23 00 02 08 5A + /* EN_VMODGATE2=1 */ + 23 00 02 0D 63 + /* VGH=16V */ + 23 00 02 0E 91 + /* VGL=-13V */ + 23 00 02 0F 73 + /* GVDD=5.2V */ + 23 00 02 95 EB + 23 00 02 96 EB + /* Disable VDDI LV */ + 23 00 02 30 11 + /* ISOP */ + 23 00 02 6D 66 + /* EN_GMACP */ + 23 00 02 75 A2 + /* V128 */ + 23 00 02 77 3B + /* R(+) */ + 29 00 11 B0 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B1 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B2 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B3 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* G(+) */ + 29 00 11 B4 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B5 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 B6 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D B7 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* B(+) */ + 29 00 11 B8 00 08 00 23 00 4D 00 6D 00 89 00 A1 00 B6 00 C9 + 29 00 11 B9 00 DA 01 13 01 3C 01 7E 01 AB 01 F7 02 2F 02 31 + 29 00 11 BA 02 67 02 A6 02 D1 03 08 03 2E 03 5B 03 6B 03 7B + 29 00 0D BB 03 8E 03 A2 03 B7 03 E7 03 FD 03 FF + /* CMD2_Page1 */ + 23 00 02 FF 21 + 23 00 02 FB 01 + /* R(-) */ + 29 00 11 B0 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B1 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B2 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B3 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* G(-) */ + 29 00 11 B4 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B5 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 B6 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D B7 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + /* B(-) */ + 29 00 11 B8 00 00 00 1B 00 45 00 65 00 81 00 99 00 AE 00 C1 + 29 00 11 B9 00 D2 01 0B 01 34 01 76 01 A3 01 EF 02 27 02 29 + 29 00 11 BA 02 5F 02 9E 02 C9 03 00 03 26 03 53 03 63 03 73 + 29 00 0D BB 03 86 03 9A 03 AF 03 DF 03 F5 03 F7 + + 29 00 02 FF 24 + 29 00 02 FB 01 + /* VGL */ + 29 00 02 00 00 + 29 00 02 01 00 + /* VDDO */ + 29 00 02 02 1C + 29 00 02 03 1C + /* VDDE */ + 29 00 02 04 1D + 29 00 02 05 1D + /* STV0 */ + 29 00 02 06 04 + 29 00 02 07 04 + /* CLK8 */ + 29 00 02 08 0F + 29 00 02 09 0F + /* CLK6 */ + 29 00 02 0A 0E + 29 00 02 0B 0E + /* CLK4 */ + 29 00 02 0C 0D + 29 00 02 0D 0D + /* CLK2 */ + 29 00 02 0E 0C + 29 00 02 0F 0C + /* STV2 */ + 29 00 02 10 08 + 29 00 02 11 08 + + 29 00 02 12 00 + 29 00 02 13 00 + 29 00 02 14 00 + 29 00 02 15 00 + /* VGL */ + 29 00 02 16 00 + 29 00 02 17 00 + /* VDDO */ + 29 00 02 18 1C + 29 00 02 19 1C + /* VDDE */ + 29 00 02 1A 1D + 29 00 02 1B 1D + /* STV0 */ + 29 00 02 1C 04 + 29 00 02 1D 04 + /* CLK7 */ + 29 00 02 1E 0F + 29 00 02 1F 0F + /* CLK5 */ + 29 00 02 20 0E + 29 00 02 21 0E + /* CLK3 */ + 29 00 02 22 0D + 29 00 02 23 0D + /* CLK1 */ + 29 00 02 24 0C + 29 00 02 25 0C + /* STV1 */ + 29 00 02 26 08 + 29 00 02 27 08 + + 29 00 02 28 00 + 29 00 02 29 00 + 29 00 02 2A 00 + 29 00 02 2B 00 + /* STV0 */ + 29 00 02 2D 20 + 29 00 02 2F 0A + 29 00 02 30 44 + 29 00 02 33 0C + 29 00 02 34 32 + + 29 00 02 37 44 + 29 00 02 38 40 + 29 00 02 39 00 + 29 00 02 3A 50 + 29 00 02 3B 50 + 29 00 02 3D 42 + /* STV */ + 29 00 02 3F 06 + 29 00 02 43 06 + + 29 00 02 47 66 + 29 00 02 4A 50 + 29 00 02 4B 50 + 29 00 02 4C 91 + /* GCK */ + 29 00 02 4D 21 + 29 00 02 4E 43 + 29 00 02 51 12 + 29 00 02 52 34 + 29 00 03 55 82 02 + 29 00 02 56 04 + 29 00 02 58 21 + 29 00 02 59 30 + 29 00 02 5A 50 + 29 00 02 5B 50 + 29 00 03 5E 00 06 + 29 00 02 5F 00 + /* EN_LFD_SOURCE=0 */ + 29 00 02 65 82 + /* VDDO, VDDE */ + 29 00 02 7E 20 + 29 00 02 7F 3C + 29 00 02 82 04 + 29 00 02 97 C0 + + 29 00 0D B6 05 00 05 00 00 00 00 00 05 05 00 00 + /* qclk=96/5 Mhz */ + 29 00 02 91 44 + 29 00 02 92 55 + 29 00 02 93 1A + 29 00 02 94 5F + /* SOG_HBP */ + 29 00 02 D7 55 + 29 00 02 DA 0A + 29 00 02 DE 08 + /* Normal */ + 29 00 02 DB 05 + 29 00 02 DC 55 + 29 00 02 DD 22 + /* Line N */ + 29 00 02 DF 05 + 29 00 02 E0 55 + /* Line N+1 */ + 29 00 02 E1 05 + 29 00 02 E2 55 + /* TP0 */ + 29 00 02 E3 05 + 29 00 02 E4 55 + /* TP3 */ + 29 00 02 E5 05 + 29 00 02 E6 55 + /* Gate EQ */ + 29 00 02 5C 00 + 29 00 02 5D 00 + /* TP3 */ + 29 00 02 8D 00 + 29 00 02 8E 00 + /* No Sync @ TP */ + 29 00 02 B5 90 + + 29 00 02 FF 25 + 29 00 02 FB 01 + /* disable auto_vbp_vfp */ + 29 00 02 05 00 + /* ESD_DET_ERR_SEL */ + 29 00 02 19 07 + /* DP_N_GCK */ + 29 00 02 1F 50 + 29 00 02 20 50 + /* DP_N_1_GCK */ + 29 00 02 26 50 + 29 00 02 27 50 + /* TP0_GCK */ + 29 00 02 33 50 + 29 00 02 34 50 + /* TP3 GCK/MUX=1 */ + 29 00 02 3F E0 + /* TP3_GCK_START_LINE */ + 29 00 02 40 00 + /* TP3_STV */ + 29 00 02 44 00 + 29 00 02 45 40 + /* TP3_GCK */ + 29 00 02 48 50 + 29 00 02 49 50 + /* LSTP0 */ + 29 00 02 5B 00 + 29 00 02 5C 00 + 29 00 02 5D 00 + 29 00 02 5E D0 + + 29 00 02 61 50 + 29 00 02 62 50 + /* en_vfp_addvsync */ + 29 00 02 F1 10 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + /* PWRONOFF */ + /* STV */ + 29 00 02 64 16 + /* CLR */ + 29 00 02 67 16 + /* GCK */ + 29 00 02 6A 16 + /* POL */ + 29 00 02 70 30 + /* ABOFF */ + 29 00 02 A2 F3 + 29 00 02 A3 FF + 29 00 02 A4 FF + 29 00 02 A5 FF + /* Long_V_TIMING disable */ + 29 00 02 D6 08 + /* CMD2,Page6 */ + 29 00 02 FF 26 + 29 00 02 FB 01 + /* TPEN */ + 29 00 02 00 81 + /* 90Hz */ + 29 00 02 01 30 + + 29 00 02 02 31 + 29 00 02 0A F2 + //Table A (90Hz) + 29 00 02 04 28 + 29 00 02 06 3C + 29 00 02 0C 0B + 29 00 02 0D 0C + 29 00 02 0F 00 + 29 00 02 11 00 + 29 00 02 12 50 + 29 00 02 13 AE + 29 00 02 14 A6 + 29 00 02 16 10 + 29 00 02 19 08 + 29 00 02 1A FF + 29 00 02 1B 08 + 29 00 02 1C 80 + 29 00 02 22 00 + 29 00 02 23 00 + 29 00 02 2A 08 + 29 00 02 2B FF + + 29 00 02 1D 00 + 29 00 02 1E 55 + 29 00 02 1F 55 + 29 00 02 24 00 + 29 00 02 25 55 + 29 00 02 2F 05 + 29 00 02 30 55 + 29 00 02 31 05 + 29 00 02 32 6D + 29 00 02 39 00 + 29 00 02 3A 55 + /* Table B (60Hz,81*1+101*19=2000, Extra=20) */ + 29 00 02 8B 28 + 29 00 02 8C 13 + 29 00 02 8D 0A + 29 00 02 8F 0A + 29 00 02 91 00 + 29 00 02 92 50 + 29 00 02 93 51 + 29 00 02 94 65 + 29 00 02 96 10 + 29 00 02 99 0A + 29 00 02 9A 7F + 29 00 02 9B 0A + 29 00 02 9C 0C + 29 00 02 9D 0A + 29 00 02 9E 7F + + 29 00 02 3F 00 + 29 00 02 40 75 + 29 00 02 41 75 + 29 00 02 42 75 + 29 00 02 43 00 + 29 00 02 44 75 + 29 00 02 45 05 + 29 00 02 46 75 + 29 00 02 47 05 + 29 00 02 48 8D + 29 00 02 49 00 + 29 00 02 4A 75 + /* STV0 */ + 29 00 02 4D 5D + 29 00 02 4E 60 + /* STV */ + 29 00 02 4F 5D + 29 00 02 50 60 + /* GCK */ + 29 00 02 51 70 + 29 00 02 52 60 + /* DP_N_GCK */ + 29 00 02 56 70 + 29 00 02 58 60 + /* DP_N_1_GCK */ + 29 00 02 5B 70 + 29 00 02 5C 60 + /* TP0_GCK */ + 29 00 02 60 70 + 29 00 02 61 60 + /* TP3_GCK */ + 29 00 02 64 70 + 29 00 02 65 60 + /* LSTP0 */ + 29 00 02 72 70 + 29 00 02 73 60 + /* PRZ1 */ + 29 00 02 20 01 + /* PRZ3 */ + /* Rescan=3 */ + 29 00 02 33 11 + 29 00 02 34 78 + 29 00 02 35 16 + /* DLH */ + 29 00 02 C8 04 + 29 00 02 C9 80 + 29 00 02 CA 4E + 29 00 02 CB 00 + 29 00 02 A9 4C + 29 00 02 AA 47 + /* CMD2,Page7 */ + 29 00 02 FF 27 + 29 00 02 FB 01 + /* VPOR_DYNH_EN=1, VPOR_CNT_REV=1 */ + 29 00 02 56 06 + /* FR0(60Hz) */ + 29 00 02 58 80 + 29 00 02 59 53 + 29 00 02 5A 00 + 29 00 02 5B 14 + 29 00 02 5C 00 + 29 00 02 5D 01 + 29 00 02 5E 20 + 29 00 02 5F 10 + 29 00 02 60 00 + 29 00 02 61 1D + 29 00 02 62 00 + 29 00 02 63 01 + 29 00 02 64 24 + 29 00 02 65 1C + 29 00 02 66 00 + 29 00 02 67 01 + 29 00 02 68 25 + /* FR1(90Hz) */ + 29 00 02 78 80 + 29 00 02 79 73 + 29 00 02 7A 00 + 29 00 02 7B 14 + 29 00 02 7C 00 + 29 00 02 7D 02 + 29 00 02 7E 20 + 29 00 02 7F 21 + 29 00 02 80 00 + 29 00 02 81 2A + 29 00 02 82 00 + 29 00 02 83 01 + 29 00 02 84 1C + 29 00 02 85 28 + 29 00 02 86 00 + 29 00 02 87 01 + 29 00 02 88 1D + + 29 00 02 00 00 + 29 00 02 C3 00 + /* FTE output TE, FTE1 output TSVD, LEDPWM output TSHD */ + 29 00 02 D1 24 + 29 00 02 D2 53 + /* CMD2,Page10 */ + 29 00 02 FF 2A + 29 00 02 FB 01 + 29 00 02 01 05 + 29 00 02 02 55 + /* TP0 */ + 29 00 02 03 05 + 29 00 02 04 75 + /* TP3 */ + 29 00 02 05 05 + 29 00 02 06 75 + /* PEN_EN=1, UL_FREQ=0 */ + 29 00 02 22 2F + /* 90Hz */ + 29 00 02 23 11 + /* FR0 (60Hz) */ + 29 00 02 24 00 + 29 00 02 25 75 + 29 00 02 27 00 + 29 00 02 28 1A + 29 00 02 29 00 + 29 00 02 2A 1A + 29 00 02 2B 00 + 29 00 02 2D 1A + /* FR1 (90Hz) */ + 29 00 02 2F 00 + 29 00 02 30 55 + 29 00 02 32 00 + 29 00 02 33 1A + 29 00 02 34 00 + 29 00 02 35 1A + 29 00 02 36 00 + 29 00 02 37 1A + /* CMD2,Page3 */ + 29 00 02 FF 23 + 29 00 02 FB 01 + /* DBV=12 bit */ + 29 00 02 00 80 + /* PWM frequency */ + 29 00 02 07 00 + /* CMD3,PageA */ + 29 00 02 FF E0 + 29 00 02 FB 01 + /* VCOM Driving Ability */ + 29 00 02 14 60 + 29 00 02 16 C0 + /* CMD3,PageB */ + 29 00 02 FF F0 + 29 00 02 FB 01 + /* slave osc workaround */ + 29 00 02 3A 08 + /* CMD3,PageC */ + 29 00 02 FF D0 + 29 00 02 FB 01 + 29 00 02 1C 88 + 29 00 02 1D 08 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Only Write Slave */ + 29 00 02 B9 01 + /* CMD2,Page0 */ + 29 00 02 FF 20 + 29 00 02 FB 01 + 29 00 02 18 40 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + /* Write Master & Slave */ + 29 00 02 B9 02 + 29 00 02 35 00 + 29 00 03 51 00 FF + 29 00 02 53 24 + 29 00 02 55 00 + 29 00 02 BB 13 + /* VBP+VFP=121 */ + 29 00 06 3B 03 5F 1A 04 04 + /* CMD2,Page5 */ + 29 00 02 FF 25 + /* FRM */ + 29 00 02 EC 00 + /* CMD1 */ + 29 00 02 FF 10 + 29 00 02 FB 01 + 05 FF 01 11 + 05 FF 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <241300000>; + hactive = <1200>; + vactive = <2000>; + hfront-porch = <31>; + hsync-len = <4>; + hback-porch = <32>; + vfront-porch = <26>; + vsync-len = <2>; + vback-porch = <93>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "okay"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "okay"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +&hdmi0 { + enable-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi0_in_vp0 { + status = "okay"; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy_hdmi0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c5 { + status = "okay"; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <8>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <8>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio4 RK_PB4 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&pdm0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sensor { + mpu6500_irq_gpio: mpu6500_irq_gpio { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + typec5v_pwren: typec5v-pwren { + rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_u2host_en: vcc5v0-u2host-en { + rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_u3host_en: vcc5v0-u3host-en { + rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm7 { + status = "okay"; +}; + +&route_dsi0 { + status = "disabled"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "okay"; + connect = <&vp3_out_dsi1>; +}; + +&sata0 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,sel-pipe-phystatus; + vbus-supply = <&vbus5v0_typec>; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_u2host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_u3host>; +}; + +&usbdp_phy0 { + rockchip,dp-lane-mux = <0 1 2 3>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + extcon = <&u2phy0>; +}; diff --git a/rk3588s-evb3-lp4x-v10-linux.dts b/rk3588s-evb3-lp4x-v10-linux.dts new file mode 100644 index 0000000..2db6250 --- /dev/null +++ b/rk3588s-evb3-lp4x-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb3-lp4x.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588S EVB3 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb3-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts b/rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts new file mode 100644 index 0000000..abd332a --- /dev/null +++ b/rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3588s-evb3-lp4x.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard"; + compatible = "rockchip,rk3588s-evb3-lp4x-v10-nvp6158-ahd-to-bt1120", "rockchip,rk3588"; +}; + +&i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m4_xfer>; + + nvp6158: nvp6158@30 { + compatible = "nvp6158-v4l2"; + status = "okay"; + reg = <0x30>; + clocks = <&cru CLK_CIFOUT_OUT>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus8 &cif_dvp_bus16>; + // pwr-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + pwr2-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + // rst2-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + // pwdn-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + // pwdn2-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + rockchip,dvp_mode = "BT1120"; //BT656 or BT1120 or BT656_TEST + rockchip,channel_nums = <4>; //channel nums, 1/2/4 + rockchip,dual_edge = <1>; // pclk dual edge, 0/1 + rockchip,default_rect= <1920 1080>; // default resolution + port { + nvp6158_out: endpoint { + remote-endpoint = <&dvp_in_bcam1>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_dvp { + status = "okay"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + /* Parallel bus endpoint */ + dvp_in_bcam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&nvp6158_out>; + bus-width = <16>; + }; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; diff --git a/rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts b/rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts new file mode 100644 index 0000000..5d6a840 --- /dev/null +++ b/rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3588s-evb3-lp4x.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard1"; + compatible = "rockchip,rk3588s-evb3-lp4x-v10-rk630-bt656-to-cvbs", "rockchip,rk3588"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +&i2c4 { + status = "okay"; + clock-frequency = <100000>; + + rk630: rk630@50 { + compatible = "rockchip,rk630"; + reg = <0x50>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + status = "okay"; + + rk630_tve: rk630-tve { + compatible = "rockchip,rk630-tve"; + status = "okay"; + + ports { + port { + rk630_tve_in_rgb: endpoint { + remote-endpoint = <&rgb_out_rk630_tve>; + }; + }; + }; + }; + }; +}; + +&rgb { + pinctrl-names = "default"; + pinctrl-0 = <&bt656_pins>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_rk630_tve: endpoint@0 { + reg = <0>; + remote-endpoint = <&rk630_tve_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp3 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts b/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts new file mode 100644 index 0000000..4a03bc6 --- /dev/null +++ b/rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include "rk3588s-evb3-lp4x.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB3 LP4 V10 Board + Rockchip RK3588S EVB V10 Extboard2"; + compatible = "rockchip,rk3588s-evb3-lp4x-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3588"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * The pins of gt1x and sii9022 are multiplexed + */ +>1x { + status = "disabled"; +}; + +&i2c4 { + clock-frequency = <400000>; + status = "okay"; + + sii9022: sii9022@39 { + compatible = "sil,sii9022"; + reg = <0x39>; + pinctrl-names = "default"; + pinctrl-0 = <&sii902x_hdmi_int>; + interrupt-parent = <&gpio3>; + interrupts = ; + reset-gpio = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>; + enable-gpio = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; + /* + * MEDIA_BUS_FMT_UYVY8_1X16 for bt1120 + * MEDIA_BUS_FMT_UYVY8_2X8 for bt656 + */ + bus-format = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + sii9022_in_rgb: endpoint { + remote-endpoint = <&rgb_out_sii9022>; + }; + }; + }; + }; +}; + +&pinctrl { + sii902x { + sii902x_hdmi_int: sii902x-hdmi-int { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&rgb { + status = "okay"; + pinctrl-names = "default"; + /* + * <&bt1120_pins> for bt1120 + * <&bt656_pins> for bt656 + */ + pinctrl-0 = <&bt1120_pins>; + + ports { + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_out_sii9022: endpoint@0 { + reg = <0>; + remote-endpoint = <&sii9022_in_rgb>; + }; + }; + }; +}; + +&rgb_in_vp3 { + status = "okay"; +}; + +&vop { + status = "okay"; +}; diff --git a/rk3588s-evb3-lp4x-v10.dts b/rk3588s-evb3-lp4x-v10.dts new file mode 100644 index 0000000..8f42839 --- /dev/null +++ b/rk3588s-evb3-lp4x-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb3-lp4x.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB3 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb3-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb3-lp4x.dtsi b/rk3588s-evb3-lp4x.dtsi new file mode 100644 index 0000000..cfdbcae --- /dev/null +++ b/rk3588s-evb3-lp4x.dtsi @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588s-evb.dtsi" +#include "rk3588s-rk806-dual.dtsi" + +/ { + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm7 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_1v8_s0>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "disabled"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "disabled"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm11 { + status = "okay"; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&sata2 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy2 { + status = "disabled"; +}; + +&u2phy3 { + status = "disabled"; +}; + +&u2phy2_host { + status = "disabled"; +}; + +&u2phy3_host { + status = "disabled"; +}; + +&usb_host0_ehci { + status = "disabled"; +}; + +&usb_host0_ohci { + status = "disabled"; +}; + +&usb_host1_ehci { + status = "disabled"; +}; + +&usb_host1_ohci { + status = "disabled"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588s-evb4-lp4x-v10-linux.dts b/rk3588s-evb4-lp4x-v10-linux.dts new file mode 100644 index 0000000..cf1d324 --- /dev/null +++ b/rk3588s-evb4-lp4x-v10-linux.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb4-lp4x.dtsi" +#include "rk3588-linux.dtsi" + +/ { + model = "Rockchip RK3588S EVB4 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb4-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb4-lp4x-v10.dts b/rk3588s-evb4-lp4x-v10.dts new file mode 100644 index 0000000..d3f9264 --- /dev/null +++ b/rk3588s-evb4-lp4x-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb4-lp4x.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB4 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb4-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb4-lp4x.dtsi b/rk3588s-evb4-lp4x.dtsi new file mode 100644 index 0000000..ee707d4 --- /dev/null +++ b/rk3588s-evb4-lp4x.dtsi @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588s-evb.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm11 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc_1v2_cam_s0: vcc-1v2-cam-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v2_cam_s0"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: vcc-1v8-cam-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_cam_s0"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_2v8_cam_s0: vcc-2v8-cam-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v8_cam_s0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_sd_s0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_LOW>; + enable-active-low; + vin-supply = <&vcc_3v3_s3>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm13 0 25000 0>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp2 { + status = "okay"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "disabled"; +}; + +&dsi0_in_vp3 { + status = "okay"; +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; +}; + +/* + * mipi_dcphy1 needs to be enabled + * when dsi1 is enabled + */ +&dsi1 { + //rockchip,lane-rate = <650>; + pinctrl-names = "default"; + pinctrl-0 = <&mipi_te1>; + status = "disabled"; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + compressed-data; + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + slice-width = <720>; + slice-height = <65>; + version-major = <1>; + version-minor = <1>; + + panel-init-sequence = [ + 29 10 03 f0 5a 5a + /* Dsc Setting */ + /* Compression Enable */ + 07 10 01 01 + /* Scaler Disable */ + 15 10 02 c3 00 + /* PPS Setting */ + 0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00 + 29 10 03 f0 a5 a5 + /** Sleep Out */ + 05 00 01 11 + /* 4. Common Setting */ + /* 4.1 TE(Vync) ON/OFF */ + 15 00 02 35 00 + /* 4.2 CASET/PASET Setting */ + 39 00 05 2a 00 00 05 9F + 39 00 05 2b 00 00 0c 2f + /* 4.3 TSP SYNC Setting */ + 39 00 03 f0 5a 5a + 39 00 0a B9 01 c0 3c 0b 00 00 00 11 03 + 39 00 03 f0 a5 a5 + /* FD(Fast Discharge) Setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 45 + 15 00 02 b5 48 + 39 00 03 f0 a5 a5 + /* 4.6 FFC Setting (MIPI CLK 529MHz) */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 1E + 39 00 06 c5 09 10 b4 24 fb + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* OSC Spread Setting */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 37 + /* FFC Setting; 0x04 : Disable */ + 39 00 06 c5 04 ff 00 01 64 + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* Dither IP Setting */ + 39 00 03 FC 5A 5A + 15 00 02 b0 86 + 15 00 02 eb 01 + 39 00 03 FC a5 a5 + /* 5 Brightness Control */ + /* 5.1 Dimming Setting */ + 39 10 03 f0 5a 5a + 15 10 02 b0 05 + 15 10 02 b1 01 + 15 10 02 b0 02 + 15 10 02 b5 d3 + 15 10 02 53 20 + 39 10 03 f0 a5 a5 + 39 10 03 51 02 ff + 05 32 01 29 + ]; + + panel-exit-sequence = [ + /* Display off */ + 05 14 01 28 + /* Sleep In */ + 05 00 01 10 + /* VCI stabilization setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 05 + 15 00 02 f4 01 + 39 a0 03 f0 a5 a5 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <280000000>; + hactive = <1140>; + vactive = <3120>; + hfront-porch = <16>; + hsync-len = <8>; + hback-porch = <8>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + gt1x: gt1x@14 { + compatible = "goodix,gt1x"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + goodix,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + goodix,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + power-supply = <&vcc3v3_lcd_n>; + }; +}; + +&i2c5 { + status = "okay"; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <8>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <8>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + status = "okay"; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "disabled"; +}; + +&pdm0 { + status = "okay"; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sensor { + mpu6500_irq_gpio: mpu6500_irq_gpio { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm11 { + pinctrl-0 = <&pwm11m1_pins>; + status = "okay"; +}; + +&pwm13 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +&pwm15 { + compatible = "rockchip,remotectl-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pwm15m0_pins>; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp3_out_dsi0>; +}; + +&route_dsi1 { + status = "disabled"; + connect = <&vp3_out_dsi1>; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&spdif_tx1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m1_tx>; +}; + +&spdif_tx1_dc { + status = "okay"; +}; + +&spdif_tx1_sound { + status = "okay"; +}; + +&spi2 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; diff --git a/rk3588s-evb8-lp4x-v10.dts b/rk3588s-evb8-lp4x-v10.dts new file mode 100644 index 0000000..300553e --- /dev/null +++ b/rk3588s-evb8-lp4x-v10.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-evb8-lp4x.dtsi" +#include "rk3588s-evb1-lp4x-v10-camera.dtsi" +#include "rk3588-android.dtsi" + +/ { + model = "Rockchip RK3588S EVB8 LP4X V10 Board"; + compatible = "rockchip,rk3588s-evb8-lp4x-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-evb8-lp4x.dtsi b/rk3588s-evb8-lp4x.dtsi new file mode 100644 index 0000000..982461d --- /dev/null +++ b/rk3588s-evb8-lp4x.dtsi @@ -0,0 +1,831 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include "dt-bindings/usb/pd.h" +#include "rk3588s.dtsi" +#include "rk3588s-evb.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip-es8388"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm11 0 50000 0>; + cooling-levels = <0 50 100 150 200 255>; + rockchip,temp-trips = < + 50000 1 + 55000 2 + 60000 3 + 65000 4 + 70000 5 + >; + }; + + panel-edp { + compatible = "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <120>; + disable-delay-ms = <120>; + width-mm = <120>; + height-mm = <160>; + + panel-timing { + clock-frequency = <200000000>; + hactive = <1536>; + vactive = <2048>; + hfront-porch = <12>; + hsync-len = <16>; + hback-porch = <48>; + vfront-porch = <8>; + vsync-len = <4>; + vback-porch = <8>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + vbus5v0_typec: vbus5v0-typec { + compatible = "regulator-fixed"; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&typec5v_pwren>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_edp"; + gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc3v3_pcie20: vcc3v3-pcie20 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie20"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-name = "vcc_3v3_sd_s0"; + enable-active-high; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_gpio>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&backlight { + pwms = <&pwm12 0 25000 0>; + power-supply = <&vcc3v3_lcd_edp>; + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dp0_sound{ + status = "okay"; +}; + +&edp0 { + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ + training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + >; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + status = "okay"; + + gsl3673@40 { + compatible = "GSL,GSL3673"; + reg = <0x40>; + screen_max_x = <1536>; + screen_max_y = <2048>; + irq_gpio_number = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + rst_gpio_number = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c5 { + status = "okay"; + + ls_stk3332: light@47 { + compatible = "ls_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ + poll_delay_ms = <100>; + }; + + ps_stk3332: proximity@47 { + compatible = "ps_stk3332"; + status = "disabled"; + reg = <0x47>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + //irq_enable = <1>; + ps_threshold_high = <0x200>; + ps_threshold_low = <0x100>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ + poll_delay_ms = <100>; + }; + + mpu6500_acc: mpu_acc@68 { + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&pcie2x1l1 { + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie20>; + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm0 { + status = "okay"; +}; + +&pinctrl { + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sensor { + mpu6500_irq_gpio: mpu6500_irq_gpio { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + typec5v_pwren: typec5v-pwren { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_gpio: bt-gpio { + rockchip,pins = + <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>, + <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm3 { + compatible = "rockchip,remotectl-pwm"; + remote_pwm_id = <3>; + handle_cpu_id = <1>; + remote_support_psci = <0>; + status = "okay"; + + ir_key1 { + rockchip,usercode = <0x4040>; + rockchip,key_table = + <0xf2 KEY_REPLY>, + <0xba KEY_BACK>, + <0xf4 KEY_UP>, + <0xf1 KEY_DOWN>, + <0xef KEY_LEFT>, + <0xee KEY_RIGHT>, + <0xbd KEY_HOME>, + <0xea KEY_VOLUMEUP>, + <0xe3 KEY_VOLUMEDOWN>, + <0xe2 KEY_SEARCH>, + <0xb2 KEY_POWER>, + <0xbc KEY_MUTE>, + <0xec KEY_MENU>, + <0xbf 0x190>, + <0xe0 0x191>, + <0xe1 0x192>, + <0xe9 183>, + <0xe6 248>, + <0xe8 185>, + <0xe7 186>, + <0xf0 388>, + <0xbe 0x175>; + }; + + ir_key2 { + rockchip,usercode = <0xff00>; + rockchip,key_table = + <0xf9 KEY_HOME>, + <0xbf KEY_BACK>, + <0xfb KEY_MENU>, + <0xaa KEY_REPLY>, + <0xb9 KEY_UP>, + <0xe9 KEY_DOWN>, + <0xb8 KEY_LEFT>, + <0xea KEY_RIGHT>, + <0xeb KEY_VOLUMEDOWN>, + <0xef KEY_VOLUMEUP>, + <0xf7 KEY_MUTE>, + <0xe7 KEY_POWER>, + <0xfc KEY_POWER>, + <0xa9 KEY_VOLUMEDOWN>, + <0xa8 KEY_PLAYPAUSE>, + <0xe0 KEY_VOLUMEDOWN>, + <0xa5 KEY_VOLUMEDOWN>, + <0xab 183>, + <0xb7 388>, + <0xe8 388>, + <0xf8 184>, + <0xaf 185>, + <0xed KEY_VOLUMEDOWN>, + <0xee 186>, + <0xb3 KEY_VOLUMEDOWN>, + <0xf1 KEY_VOLUMEDOWN>, + <0xf2 KEY_VOLUMEDOWN>, + <0xf3 KEY_SEARCH>, + <0xb4 KEY_VOLUMEDOWN>, + <0xa4 KEY_SETUP>, + <0xbe KEY_SEARCH>; + }; + + ir_key3 { + rockchip,usercode = <0x1dcc>; + rockchip,key_table = + <0xee KEY_REPLY>, + <0xf0 KEY_BACK>, + <0xf8 KEY_UP>, + <0xbb KEY_DOWN>, + <0xef KEY_LEFT>, + <0xed KEY_RIGHT>, + <0xfc KEY_HOME>, + <0xf1 KEY_VOLUMEUP>, + <0xfd KEY_VOLUMEDOWN>, + <0xb7 KEY_SEARCH>, + <0xff KEY_POWER>, + <0xf3 KEY_MUTE>, + <0xbf KEY_MENU>, + <0xf9 0x191>, + <0xf5 0x192>, + <0xb3 388>, + <0xbe KEY_1>, + <0xba KEY_2>, + <0xb2 KEY_3>, + <0xbd KEY_4>, + <0xf9 KEY_5>, + <0xb1 KEY_6>, + <0xfc KEY_7>, + <0xf8 KEY_8>, + <0xb0 KEY_9>, + <0xb6 KEY_0>, + <0xb5 KEY_BACKSPACE>; + }; +}; + +&pwm11 { + pinctrl-0 = <&pwm11m1_pins>; + status = "okay"; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&route_edp0 { + connect = <&vp2_out_edp0>; + status = "okay"; +}; + +&sdmmc { + status = "okay"; + vmmc-supply = <&vcc_3v3_sd_s0>; +}; + +&spdif_tx1 { + status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m1_tx>; +}; + +&spdif_tx1_dc { + status = "okay"; +}; + +&spdif_tx1_sound { + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdrd_dwc3_0 { + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +/* vp0 & vp3 are not used on this board */ +&vp0 { + /delete-property/ rockchip,plane-mask; + /delete-property/ rockchip,primary-plane; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; + +&vp3 { + /delete-property/ rockchip,plane-mask; + /delete-property/ rockchip,primary-plane; +}; diff --git a/rk3588s-pinconf.dtsi b/rk3588s-pinconf.dtsi new file mode 100644 index 0000000..660cf29 --- /dev/null +++ b/rk3588s-pinconf.dtsi @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2023 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <1>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <2>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <3>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <4>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <5>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6_smt: pcfg-pull-none-drv-level-6-smt { + bias-disable; + drive-strength = <6>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_up: pcfg-output-high-pull-up { + output-high; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_down: pcfg-output-high-pull-down { + output-high; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_none: pcfg-output-high-pull-none { + output-high; + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_up: pcfg-output-low-pull-up { + output-low; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_down: pcfg-output-low-pull-down { + output-low; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_none: pcfg-output-low-pull-none { + output-low; + bias-disable; + }; +}; diff --git a/rk3588s-pinctrl.dtsi b/rk3588s-pinctrl.dtsi new file mode 100644 index 0000000..c8a8060 --- /dev/null +++ b/rk3588s-pinctrl.dtsi @@ -0,0 +1,3481 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rk3588s-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + auddsm { + /omit-if-no-ref/ + auddsm_pins: auddsm-pins { + rockchip,pins = + /* auddsm_ln */ + <3 RK_PA1 4 &pcfg_pull_none>, + /* auddsm_lp */ + <3 RK_PA2 4 &pcfg_pull_none>, + /* auddsm_rn */ + <3 RK_PA3 4 &pcfg_pull_none>, + /* auddsm_rp */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + bt1120 { + /omit-if-no-ref/ + bt1120_pins: bt1120-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none>, + /* bt1120_d8 */ + <4 RK_PB2 2 &pcfg_pull_none>, + /* bt1120_d9 */ + <4 RK_PB3 2 &pcfg_pull_none>, + /* bt1120_d10 */ + <4 RK_PB4 2 &pcfg_pull_none>, + /* bt1120_d11 */ + <4 RK_PB5 2 &pcfg_pull_none>, + /* bt1120_d12 */ + <4 RK_PB6 2 &pcfg_pull_none>, + /* bt1120_d13 */ + <4 RK_PB7 2 &pcfg_pull_none>, + /* bt1120_d14 */ + <4 RK_PC0 2 &pcfg_pull_none>, + /* bt1120_d15 */ + <4 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + can0 { + /omit-if-no-ref/ + can0m0_pins: can0m0-pins { + rockchip,pins = + /* can0_rx_m0 */ + <0 RK_PC0 11 &pcfg_pull_none>, + /* can0_tx_m0 */ + <0 RK_PB7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can0m1_pins: can0m1-pins { + rockchip,pins = + /* can0_rx_m1 */ + <4 RK_PD5 9 &pcfg_pull_none>, + /* can0_tx_m1 */ + <4 RK_PD4 9 &pcfg_pull_none>; + }; + }; + + can1 { + /omit-if-no-ref/ + can1m0_pins: can1m0-pins { + rockchip,pins = + /* can1_rx_m0 */ + <3 RK_PB5 9 &pcfg_pull_none>, + /* can1_tx_m0 */ + <3 RK_PB6 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can1m1_pins: can1m1-pins { + rockchip,pins = + /* can1_rx_m1 */ + <4 RK_PB2 12 &pcfg_pull_none>, + /* can1_tx_m1 */ + <4 RK_PB3 12 &pcfg_pull_none>; + }; + }; + + can2 { + /omit-if-no-ref/ + can2m0_pins: can2m0-pins { + rockchip,pins = + /* can2_rx_m0 */ + <3 RK_PC4 9 &pcfg_pull_none>, + /* can2_tx_m0 */ + <3 RK_PC5 9 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + can2m1_pins: can2m1-pins { + rockchip,pins = + /* can2_rx_m1 */ + <0 RK_PD4 10 &pcfg_pull_none>, + /* can2_tx_m1 */ + <0 RK_PD5 10 &pcfg_pull_none>; + }; + }; + + cif { + /omit-if-no-ref/ + cif_clk: cif-clk { + rockchip,pins = + /* cif_clkout */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_clk: cif-dvp-clk { + rockchip,pins = + /* cif_clkin */ + <4 RK_PB0 1 &pcfg_pull_none>, + /* cif_href */ + <4 RK_PB2 1 &pcfg_pull_none>, + /* cif_vsync */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus16: cif-dvp-bus16 { + rockchip,pins = + /* cif_d8 */ + <3 RK_PC4 1 &pcfg_pull_none>, + /* cif_d9 */ + <3 RK_PC5 1 &pcfg_pull_none>, + /* cif_d10 */ + <3 RK_PC6 1 &pcfg_pull_none>, + /* cif_d11 */ + <3 RK_PC7 1 &pcfg_pull_none>, + /* cif_d12 */ + <3 RK_PD0 1 &pcfg_pull_none>, + /* cif_d13 */ + <3 RK_PD1 1 &pcfg_pull_none>, + /* cif_d14 */ + <3 RK_PD2 1 &pcfg_pull_none>, + /* cif_d15 */ + <3 RK_PD3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + cif_dvp_bus8: cif-dvp-bus8 { + rockchip,pins = + /* cif_d0 */ + <4 RK_PA0 1 &pcfg_pull_none>, + /* cif_d1 */ + <4 RK_PA1 1 &pcfg_pull_none>, + /* cif_d2 */ + <4 RK_PA2 1 &pcfg_pull_none>, + /* cif_d3 */ + <4 RK_PA3 1 &pcfg_pull_none>, + /* cif_d4 */ + <4 RK_PA4 1 &pcfg_pull_none>, + /* cif_d5 */ + <4 RK_PA5 1 &pcfg_pull_none>, + /* cif_d6 */ + <4 RK_PA6 1 &pcfg_pull_none>, + /* cif_d7 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + clk32k { + /omit-if-no-ref/ + clk32k_in: clk32k-in { + rockchip,pins = + /* clk32k_in */ + <0 RK_PB2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clk32k_out0: clk32k-out0 { + rockchip,pins = + /* clk32k_out0 */ + <0 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + cpu { + /omit-if-no-ref/ + cpu_pins: cpu-pins { + rockchip,pins = + /* cpu_big0_avs */ + <0 RK_PD1 2 &pcfg_pull_none>, + /* cpu_big1_avs */ + <0 RK_PD5 2 &pcfg_pull_none>; + }; + }; + + ddrphych0 { + /omit-if-no-ref/ + ddrphych0_pins: ddrphych0-pins { + rockchip,pins = + /* ddrphych0_dtb0 */ + <4 RK_PA0 7 &pcfg_pull_none>, + /* ddrphych0_dtb1 */ + <4 RK_PA1 7 &pcfg_pull_none>, + /* ddrphych0_dtb2 */ + <4 RK_PA2 7 &pcfg_pull_none>, + /* ddrphych0_dtb3 */ + <4 RK_PA3 7 &pcfg_pull_none>; + }; + }; + + ddrphych1 { + /omit-if-no-ref/ + ddrphych1_pins: ddrphych1-pins { + rockchip,pins = + /* ddrphych1_dtb0 */ + <4 RK_PA4 7 &pcfg_pull_none>, + /* ddrphych1_dtb1 */ + <4 RK_PA5 7 &pcfg_pull_none>, + /* ddrphych1_dtb2 */ + <4 RK_PA6 7 &pcfg_pull_none>, + /* ddrphych1_dtb3 */ + <4 RK_PA7 7 &pcfg_pull_none>; + }; + }; + + ddrphych2 { + /omit-if-no-ref/ + ddrphych2_pins: ddrphych2-pins { + rockchip,pins = + /* ddrphych2_dtb0 */ + <4 RK_PB0 7 &pcfg_pull_none>, + /* ddrphych2_dtb1 */ + <4 RK_PB1 7 &pcfg_pull_none>, + /* ddrphych2_dtb2 */ + <4 RK_PB2 7 &pcfg_pull_none>, + /* ddrphych2_dtb3 */ + <4 RK_PB3 7 &pcfg_pull_none>; + }; + }; + + ddrphych3 { + /omit-if-no-ref/ + ddrphych3_pins: ddrphych3-pins { + rockchip,pins = + /* ddrphych3_dtb0 */ + <4 RK_PB4 7 &pcfg_pull_none>, + /* ddrphych3_dtb1 */ + <4 RK_PB5 7 &pcfg_pull_none>, + /* ddrphych3_dtb2 */ + <4 RK_PB6 7 &pcfg_pull_none>, + /* ddrphych3_dtb3 */ + <4 RK_PB7 7 &pcfg_pull_none>; + }; + }; + + dp0 { + /omit-if-no-ref/ + dp0m0_pins: dp0m0-pins { + rockchip,pins = + /* dp0_hpdin_m0 */ + <4 RK_PB4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m1_pins: dp0m1-pins { + rockchip,pins = + /* dp0_hpdin_m1 */ + <0 RK_PC4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp0m2_pins: dp0m2-pins { + rockchip,pins = + /* dp0_hpdin_m2 */ + <1 RK_PA0 5 &pcfg_pull_none>; + }; + }; + + dp1 { + /omit-if-no-ref/ + dp1m0_pins: dp1m0-pins { + rockchip,pins = + /* dp1_hpdin_m0 */ + <3 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m1_pins: dp1m1-pins { + rockchip,pins = + /* dp1_hpdin_m1 */ + <0 RK_PC5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + dp1m2_pins: dp1m2-pins { + rockchip,pins = + /* dp1_hpdin_m2 */ + <1 RK_PA1 5 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <2 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <2 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <2 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <2 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <2 RK_PD3 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <2 RK_PD4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <2 RK_PD5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <2 RK_PD6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <2 RK_PD7 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clkout */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_data_strobe: emmc-data-strobe { + rockchip,pins = + /* emmc_data_strobe */ + <2 RK_PA2 1 &pcfg_pull_none>; + }; + }; + + eth1 { + /omit-if-no-ref/ + eth1_pins: eth1-pins { + rockchip,pins = + /* eth1_refclko_25m */ + <3 RK_PA6 1 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspim0_pins: fspim0-pins { + rockchip,pins = + /* fspi_clk_m0 */ + <2 RK_PA0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m0 */ + <2 RK_PD6 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m0 */ + <2 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m0 */ + <2 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m0 */ + <2 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m0 */ + <2 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim0_cs1: fspim0-cs1 { + rockchip,pins = + /* fspi_cs1n_m0 */ + <2 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_pins: fspim2-pins { + rockchip,pins = + /* fspi_clk_m2 */ + <3 RK_PA5 5 &pcfg_pull_up_drv_level_2>, + /* fspi_cs0n_m2 */ + <3 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* fspi_d0_m2 */ + <3 RK_PA0 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d1_m2 */ + <3 RK_PA1 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d2_m2 */ + <3 RK_PA2 5 &pcfg_pull_up_drv_level_2>, + /* fspi_d3_m2 */ + <3 RK_PA3 5 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + fspim2_cs1: fspim2-cs1 { + rockchip,pins = + /* fspi_cs1n_m2 */ + <3 RK_PC5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + + gmac1 { + /omit-if-no-ref/ + gmac1_miim: gmac1-miim { + rockchip,pins = + /* gmac1_mdc */ + <3 RK_PC2 1 &pcfg_pull_none>, + /* gmac1_mdio */ + <3 RK_PC3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_clkinout: gmac1-clkinout { + rockchip,pins = + /* gmac1_mclkinout */ + <3 RK_PB6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rx_bus2: gmac1-rx-bus2 { + rockchip,pins = + /* gmac1_rxd0 */ + <3 RK_PA7 1 &pcfg_pull_none>, + /* gmac1_rxd1 */ + <3 RK_PB0 1 &pcfg_pull_none>, + /* gmac1_rxdv_crs */ + <3 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_tx_bus2: gmac1-tx-bus2 { + rockchip,pins = + /* gmac1_txd0 */ + <3 RK_PB3 1 &pcfg_pull_none>, + /* gmac1_txd1 */ + <3 RK_PB4 1 &pcfg_pull_none>, + /* gmac1_txen */ + <3 RK_PB5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_clk: gmac1-rgmii-clk { + rockchip,pins = + /* gmac1_rxclk */ + <3 RK_PA5 1 &pcfg_pull_none>, + /* gmac1_txclk */ + <3 RK_PA4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_rgmii_bus: gmac1-rgmii-bus { + rockchip,pins = + /* gmac1_rxd2 */ + <3 RK_PA2 1 &pcfg_pull_none>, + /* gmac1_rxd3 */ + <3 RK_PA3 1 &pcfg_pull_none>, + /* gmac1_txd2 */ + <3 RK_PA0 1 &pcfg_pull_none>, + /* gmac1_txd3 */ + <3 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppsclk: gmac1-ppsclk { + rockchip,pins = + /* gmac1_ppsclk */ + <3 RK_PC1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ppstrig: gmac1-ppstrig { + rockchip,pins = + /* gmac1_ppstrig */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_ptp_ref_clk: gmac1-ptp-ref-clk { + rockchip,pins = + /* gmac1_ptp_ref_clk */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + gmac1_txer: gmac1-txer { + rockchip,pins = + /* gmac1_txer */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <0 RK_PC5 2 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmim0_rx_cec: hdmim0-rx-cec { + rockchip,pins = + /* hdmim0_rx_cec */ + <4 RK_PB5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_hpdin: hdmim0-rx-hpdin { + rockchip,pins = + /* hdmim0_rx_hpdin */ + <4 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_scl: hdmim0-rx-scl { + rockchip,pins = + /* hdmim0_rx_scl */ + <0 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_rx_sda: hdmim0-rx-sda { + rockchip,pins = + /* hdmim0_rx_sda */ + <0 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_cec: hdmim0-tx0-cec { + rockchip,pins = + /* hdmim0_tx0_cec */ + <4 RK_PC1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_hpd: hdmim0-tx0-hpd { + rockchip,pins = + /* hdmim0_tx0_hpd */ + <1 RK_PA5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_scl: hdmim0-tx0-scl { + rockchip,pins = + /* hdmim0_tx0_scl */ + <4 RK_PB7 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim0_tx0_sda: hdmim0-tx0-sda { + rockchip,pins = + /* hdmim0_tx0_sda */ + <4 RK_PC0 5 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmim0_tx1_hpd: hdmim0-tx1-hpd { + rockchip,pins = + /* hdmim0_tx1_hpd */ + <1 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx: hdmim1-rx { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>, + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none_smt>, + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none_smt>, + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_cec: hdmim1-rx-cec { + rockchip,pins = + /* hdmim1_rx_cec */ + <3 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_hpdin: hdmim1-rx-hpdin { + rockchip,pins = + /* hdmim1_rx_hpdin */ + <3 RK_PD4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_rx_scl: hdmim1-rx-scl { + rockchip,pins = + /* hdmim1_rx_scl */ + <3 RK_PD2 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + hdmim1_rx_sda: hdmim1-rx-sda { + rockchip,pins = + /* hdmim1_rx_sda */ + <3 RK_PD3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_cec: hdmim1-tx0-cec { + rockchip,pins = + /* hdmim1_tx0_cec */ + <0 RK_PD1 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_hpd: hdmim1-tx0-hpd { + rockchip,pins = + /* hdmim1_tx0_hpd */ + <3 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_scl: hdmim1-tx0-scl { + rockchip,pins = + /* hdmim1_tx0_scl */ + <0 RK_PD5 11 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx0_sda: hdmim1-tx0-sda { + rockchip,pins = + /* hdmim1_tx0_sda */ + <0 RK_PD4 11 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_cec: hdmim1-tx1-cec { + rockchip,pins = + /* hdmim1_tx1_cec */ + <0 RK_PD2 13 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_hpd: hdmim1-tx1-hpd { + rockchip,pins = + /* hdmim1_tx1_hpd */ + <3 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_scl: hdmim1-tx1-scl { + rockchip,pins = + /* hdmim1_tx1_scl */ + <3 RK_PC6 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim1_tx1_sda: hdmim1-tx1-sda { + rockchip,pins = + /* hdmim1_tx1_sda */ + <3 RK_PC5 5 &pcfg_pull_none_drv_level_1_smt>; + }; + /omit-if-no-ref/ + hdmim2_rx_cec: hdmim2-rx-cec { + rockchip,pins = + /* hdmim2_rx_cec */ + <1 RK_PB7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_hpdin: hdmim2-rx-hpdin { + rockchip,pins = + /* hdmim2_rx_hpdin */ + <1 RK_PB6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_scl: hdmim2-rx-scl { + rockchip,pins = + /* hdmim2_rx_scl */ + <1 RK_PD6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_rx_sda: hdmim2-rx-sda { + rockchip,pins = + /* hdmim2_rx_sda */ + <1 RK_PD7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_scl: hdmim2-tx0-scl { + rockchip,pins = + /* hdmim2_tx0_scl */ + <3 RK_PC7 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim2_tx0_sda: hdmim2-tx0-sda { + rockchip,pins = + /* hdmim2_tx0_sda */ + <3 RK_PD0 5 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_cec: hdmim2-tx1-cec { + rockchip,pins = + /* hdmim2_tx1_cec */ + <3 RK_PC4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_scl: hdmim2-tx1-scl { + rockchip,pins = + /* hdmim2_tx1_scl */ + <1 RK_PA4 5 &pcfg_pull_none_drv_level_5_smt>; + }; + + /omit-if-no-ref/ + hdmim2_tx1_sda: hdmim2-tx1-sda { + rockchip,pins = + /* hdmim2_tx1_sda */ + <1 RK_PA3 5 &pcfg_pull_none_drv_level_1_smt>; + }; + + /omit-if-no-ref/ + hdmi_debug0: hdmi-debug0 { + rockchip,pins = + /* hdmi_debug0 */ + <1 RK_PA7 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug1: hdmi-debug1 { + rockchip,pins = + /* hdmi_debug1 */ + <1 RK_PB0 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug2: hdmi-debug2 { + rockchip,pins = + /* hdmi_debug2 */ + <1 RK_PB1 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug3: hdmi-debug3 { + rockchip,pins = + /* hdmi_debug3 */ + <1 RK_PB2 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug4: hdmi-debug4 { + rockchip,pins = + /* hdmi_debug4 */ + <1 RK_PB3 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug5: hdmi-debug5 { + rockchip,pins = + /* hdmi_debug5 */ + <1 RK_PB4 7 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hdmi_debug6: hdmi-debug6 { + rockchip,pins = + /* hdmi_debug6 */ + <1 RK_PA0 7 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <0 RK_PB3 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <0 RK_PA6 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m2_xfer: i2c0m2-xfer { + rockchip,pins = + /* i2c0_scl_m2 */ + <0 RK_PD1 3 &pcfg_pull_none_smt>, + /* i2c0_sda_m2 */ + <0 RK_PD2 3 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <0 RK_PB5 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <0 RK_PB6 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <0 RK_PB0 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <0 RK_PB1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m2_xfer: i2c1m2-xfer { + rockchip,pins = + /* i2c1_scl_m2 */ + <0 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m2 */ + <0 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m3_xfer: i2c1m3-xfer { + rockchip,pins = + /* i2c1_scl_m3 */ + <2 RK_PD4 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m3 */ + <2 RK_PD5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m4_xfer: i2c1m4-xfer { + rockchip,pins = + /* i2c1_scl_m4 */ + <1 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c1_sda_m4 */ + <1 RK_PD3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m2_xfer: i2c2m2-xfer { + rockchip,pins = + /* i2c2_scl_m2 */ + <2 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m2 */ + <2 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m3_xfer: i2c2m3-xfer { + rockchip,pins = + /* i2c2_scl_m3 */ + <1 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m3 */ + <1 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m4_xfer: i2c2m4-xfer { + rockchip,pins = + /* i2c2_scl_m4 */ + <1 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c2_sda_m4 */ + <1 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PC1 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PB7 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m2_xfer: i2c3m2-xfer { + rockchip,pins = + /* i2c3_scl_m2 */ + <4 RK_PA4 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m2 */ + <4 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m4_xfer: i2c3m4-xfer { + rockchip,pins = + /* i2c3_scl_m4 */ + <4 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c3_sda_m4 */ + <4 RK_PD1 9 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4m0_xfer: i2c4m0-xfer { + rockchip,pins = + /* i2c4_scl_m0 */ + <3 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m0 */ + <3 RK_PA5 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m2_xfer: i2c4m2-xfer { + rockchip,pins = + /* i2c4_scl_m2 */ + <0 RK_PC5 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m2 */ + <0 RK_PC4 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m3_xfer: i2c4m3-xfer { + rockchip,pins = + /* i2c4_scl_m3 */ + <1 RK_PA3 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m3 */ + <1 RK_PA2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c4m4_xfer: i2c4m4-xfer { + rockchip,pins = + /* i2c4_scl_m4 */ + <1 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c4_sda_m4 */ + <1 RK_PC6 9 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <3 RK_PC7 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <3 RK_PD0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <4 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <4 RK_PB7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m2_xfer: i2c5m2-xfer { + rockchip,pins = + /* i2c5_scl_m2 */ + <4 RK_PA6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m2 */ + <4 RK_PA7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m3_xfer: i2c5m3-xfer { + rockchip,pins = + /* i2c5_scl_m3 */ + <1 RK_PB6 9 &pcfg_pull_none_smt>, + /* i2c5_sda_m3 */ + <1 RK_PB7 9 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <0 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <0 RK_PC7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PC3 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PC2 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m3_xfer: i2c6m3-xfer { + rockchip,pins = + /* i2c6_scl_m3 */ + <4 RK_PB1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m3 */ + <4 RK_PB0 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m4_xfer: i2c6m4-xfer { + rockchip,pins = + /* i2c6_scl_m4 */ + <3 RK_PA1 9 &pcfg_pull_none_smt>, + /* i2c6_sda_m4 */ + <3 RK_PA0 9 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7m0_xfer: i2c7m0-xfer { + rockchip,pins = + /* i2c7_scl_m0 */ + <1 RK_PD0 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m0 */ + <1 RK_PD1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m2_xfer: i2c7m2-xfer { + rockchip,pins = + /* i2c7_scl_m2 */ + <3 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m2 */ + <3 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c7m3_xfer: i2c7m3-xfer { + rockchip,pins = + /* i2c7_scl_m3 */ + <4 RK_PB2 9 &pcfg_pull_none_smt>, + /* i2c7_sda_m3 */ + <4 RK_PB3 9 &pcfg_pull_none_smt>; + }; + }; + + i2c8 { + /omit-if-no-ref/ + i2c8m0_xfer: i2c8m0-xfer { + rockchip,pins = + /* i2c8_scl_m0 */ + <4 RK_PD2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m0 */ + <4 RK_PD3 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m2_xfer: i2c8m2-xfer { + rockchip,pins = + /* i2c8_scl_m2 */ + <1 RK_PD6 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m2 */ + <1 RK_PD7 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m3_xfer: i2c8m3-xfer { + rockchip,pins = + /* i2c8_scl_m3 */ + <4 RK_PC0 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m3 */ + <4 RK_PC1 9 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c8m4_xfer: i2c8m4-xfer { + rockchip,pins = + /* i2c8_scl_m4 */ + <3 RK_PC2 9 &pcfg_pull_none_smt>, + /* i2c8_sda_m4 */ + <3 RK_PC3 9 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0_idle: i2s0-idle { + rockchip,pins = + /* i2s0_lrck_gpio */ + <1 RK_PC5 0 &pcfg_pull_none>, + /* i2s0_sclk_gpio */ + <1 RK_PC3 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_lrck: i2s0-lrck { + rockchip,pins = + /* i2s0_lrck */ + <1 RK_PC5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0_mclk: i2s0-mclk { + rockchip,pins = + /* i2s0_mclk */ + <1 RK_PC2 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0_sclk: i2s0-sclk { + rockchip,pins = + /* i2s0_sclk */ + <1 RK_PC3 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0_sdi0: i2s0-sdi0 { + rockchip,pins = + /* i2s0_sdi0 */ + <1 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi1: i2s0-sdi1 { + rockchip,pins = + /* i2s0_sdi1 */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi2: i2s0-sdi2 { + rockchip,pins = + /* i2s0_sdi2 */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdi3: i2s0-sdi3 { + rockchip,pins = + /* i2s0_sdi3 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo0: i2s0-sdo0 { + rockchip,pins = + /* i2s0_sdo0 */ + <1 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo1: i2s0-sdo1 { + rockchip,pins = + /* i2s0_sdo1 */ + <1 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo2: i2s0-sdo2 { + rockchip,pins = + /* i2s0_sdo2 */ + <1 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0_sdo3: i2s0-sdo3 { + rockchip,pins = + /* i2s0_sdo3 */ + <1 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1m0_lrck: i2s1m0-lrck { + rockchip,pins = + /* i2s1m0_lrck */ + <4 RK_PA2 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_mclk: i2s1m0-mclk { + rockchip,pins = + /* i2s1m0_mclk */ + <4 RK_PA0 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sclk: i2s1m0-sclk { + rockchip,pins = + /* i2s1m0_sclk */ + <4 RK_PA1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi0: i2s1m0-sdi0 { + rockchip,pins = + /* i2s1m0_sdi0 */ + <4 RK_PA5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi1: i2s1m0-sdi1 { + rockchip,pins = + /* i2s1m0_sdi1 */ + <4 RK_PA6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi2: i2s1m0-sdi2 { + rockchip,pins = + /* i2s1m0_sdi2 */ + <4 RK_PA7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdi3: i2s1m0-sdi3 { + rockchip,pins = + /* i2s1m0_sdi3 */ + <4 RK_PB0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo0: i2s1m0-sdo0 { + rockchip,pins = + /* i2s1m0_sdo0 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo1: i2s1m0-sdo1 { + rockchip,pins = + /* i2s1m0_sdo1 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo2: i2s1m0-sdo2 { + rockchip,pins = + /* i2s1m0_sdo2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m0_sdo3: i2s1m0-sdo3 { + rockchip,pins = + /* i2s1m0_sdo3 */ + <4 RK_PB4 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s1m1_lrck: i2s1m1-lrck { + rockchip,pins = + /* i2s1m1_lrck */ + <0 RK_PB7 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_mclk: i2s1m1-mclk { + rockchip,pins = + /* i2s1m1_mclk */ + <0 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sclk: i2s1m1-sclk { + rockchip,pins = + /* i2s1m1_sclk */ + <0 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi0: i2s1m1-sdi0 { + rockchip,pins = + /* i2s1m1_sdi0 */ + <0 RK_PC5 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi1: i2s1m1-sdi1 { + rockchip,pins = + /* i2s1m1_sdi1 */ + <0 RK_PC6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi2: i2s1m1-sdi2 { + rockchip,pins = + /* i2s1m1_sdi2 */ + <0 RK_PC7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdi3: i2s1m1-sdi3 { + rockchip,pins = + /* i2s1m1_sdi3 */ + <0 RK_PD0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo0: i2s1m1-sdo0 { + rockchip,pins = + /* i2s1m1_sdo0 */ + <0 RK_PD1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo1: i2s1m1-sdo1 { + rockchip,pins = + /* i2s1m1_sdo1 */ + <0 RK_PD2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo2: i2s1m1-sdo2 { + rockchip,pins = + /* i2s1m1_sdo2 */ + <0 RK_PD4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1m1_sdo3: i2s1m1-sdo3 { + rockchip,pins = + /* i2s1m1_sdo3 */ + <0 RK_PD5 1 &pcfg_pull_none>; + }; + }; + + i2s2 { + /omit-if-no-ref/ + i2s2m1_idle: i2s2m1-idle { + rockchip,pins = + /* i2s2m1_lrck_gpio */ + <3 RK_PB6 0 &pcfg_pull_none>, + /* i2s2m1_sclk_gpio */ + <3 RK_PB5 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_lrck: i2s2m1-lrck { + rockchip,pins = + /* i2s2m1_lrck */ + <3 RK_PB6 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_mclk: i2s2m1-mclk { + rockchip,pins = + /* i2s2m1_mclk */ + <3 RK_PB4 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sclk: i2s2m1-sclk { + rockchip,pins = + /* i2s2m1_sclk */ + <3 RK_PB5 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s2m1_sdi: i2s2m1-sdi { + rockchip,pins = + /* i2s2m1_sdi */ + <3 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s2m1_sdo: i2s2m1-sdo { + rockchip,pins = + /* i2s2m1_sdo */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + i2s3 { + /omit-if-no-ref/ + i2s3_idle: i2s3-idle { + rockchip,pins = + /* i2s3_lrck_gpio */ + <3 RK_PA2 0 &pcfg_pull_none>, + /* i2s3_sclk_gpio */ + <3 RK_PA1 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_lrck: i2s3-lrck { + rockchip,pins = + /* i2s3_lrck */ + <3 RK_PA2 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3_mclk: i2s3-mclk { + rockchip,pins = + /* i2s3_mclk */ + <3 RK_PA0 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3_sclk: i2s3-sclk { + rockchip,pins = + /* i2s3_sclk */ + <3 RK_PA1 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s3_sdi: i2s3-sdi { + rockchip,pins = + /* i2s3_sdi */ + <3 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s3_sdo: i2s3-sdo { + rockchip,pins = + /* i2s3_sdo */ + <3 RK_PA3 3 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_tck_m0 */ + <4 RK_PD2 5 &pcfg_pull_none>, + /* jtag_tms_m0 */ + <4 RK_PD3 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_tck_m1 */ + <4 RK_PD0 5 &pcfg_pull_none>, + /* jtag_tms_m1 */ + <4 RK_PD1 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm2_pins: jtagm2-pins { + rockchip,pins = + /* jtag_tck_m2 */ + <0 RK_PB5 2 &pcfg_pull_none>, + /* jtag_tms_m2 */ + <0 RK_PB6 2 &pcfg_pull_none>; + }; + }; + + litcpu { + /omit-if-no-ref/ + litcpu_pins: litcpu-pins { + rockchip,pins = + /* litcpu_avs */ + <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + mcu { + /omit-if-no-ref/ + mcum0_pins: mcum0-pins { + rockchip,pins = + /* mcu_jtag_tck_m0 */ + <4 RK_PD4 5 &pcfg_pull_none>, + /* mcu_jtag_tms_m0 */ + <4 RK_PD5 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mcum1_pins: mcum1-pins { + rockchip,pins = + /* mcu_jtag_tck_m1 */ + <3 RK_PD4 6 &pcfg_pull_none>, + /* mcu_jtag_tms_m1 */ + <3 RK_PD5 6 &pcfg_pull_none>; + }; + }; + + mipi { + /omit-if-no-ref/ + mipim0_camera0_clk: mipim0-camera0-clk { + rockchip,pins = + /* mipim0_camera0_clk */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera1_clk: mipim0-camera1-clk { + rockchip,pins = + /* mipim0_camera1_clk */ + <1 RK_PB6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera2_clk: mipim0-camera2-clk { + rockchip,pins = + /* mipim0_camera2_clk */ + <1 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera3_clk: mipim0-camera3-clk { + rockchip,pins = + /* mipim0_camera3_clk */ + <1 RK_PD6 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim0_camera4_clk: mipim0-camera4-clk { + rockchip,pins = + /* mipim0_camera4_clk */ + <1 RK_PD7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera0_clk: mipim1-camera0-clk { + rockchip,pins = + /* mipim1_camera0_clk */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera1_clk: mipim1-camera1-clk { + rockchip,pins = + /* mipim1_camera1_clk */ + <3 RK_PA6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera2_clk: mipim1-camera2-clk { + rockchip,pins = + /* mipim1_camera2_clk */ + <3 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera3_clk: mipim1-camera3-clk { + rockchip,pins = + /* mipim1_camera3_clk */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipim1_camera4_clk: mipim1-camera4-clk { + rockchip,pins = + /* mipim1_camera4_clk */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te0: mipi-te0 { + rockchip,pins = + /* mipi_te0 */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + mipi_te1: mipi-te1 { + rockchip,pins = + /* mipi_te1 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + npu { + /omit-if-no-ref/ + npu_pins: npu-pins { + rockchip,pins = + /* npu_avs */ + <0 RK_PC6 2 &pcfg_pull_none>; + }; + }; + + pcie20x1 { + /omit-if-no-ref/ + pcie20x1m0_pins: pcie20x1m0-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m0 */ + <3 RK_PC7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m0 */ + <3 RK_PD1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m0 */ + <3 RK_PD0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1m1_pins: pcie20x1m1-pins { + rockchip,pins = + /* pcie20x1_2_clkreqn_m1 */ + <4 RK_PB7 4 &pcfg_pull_none>, + /* pcie20x1_2_perstn_m1 */ + <4 RK_PC1 4 &pcfg_pull_none>, + /* pcie20x1_2_waken_m1 */ + <4 RK_PC0 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie20x1_2_button_rstn: pcie20x1-2-button-rstn { + rockchip,pins = + /* pcie20x1_2_button_rstn */ + <4 RK_PB3 4 &pcfg_pull_none>; + }; + }; + + pcie30phy { + /omit-if-no-ref/ + pcie30phy_pins: pcie30phy-pins { + rockchip,pins = + /* pcie30phy_dtb0 */ + <1 RK_PC4 4 &pcfg_pull_none>, + /* pcie30phy_dtb1 */ + <1 RK_PD1 4 &pcfg_pull_none>; + }; + }; + + pcie30x1 { + /omit-if-no-ref/ + pcie30x1m0_pins: pcie30x1m0-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m0 */ + <0 RK_PC0 12 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m0 */ + <0 RK_PC5 12 &pcfg_pull_none>, + /* pcie30x1_0_waken_m0 */ + <0 RK_PC4 12 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m0 */ + <0 RK_PB5 12 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m0 */ + <0 RK_PB7 12 &pcfg_pull_none>, + /* pcie30x1_1_waken_m0 */ + <0 RK_PB6 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m1_pins: pcie30x1m1-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m1 */ + <4 RK_PA3 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m1 */ + <4 RK_PA5 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m1 */ + <4 RK_PA4 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m1 */ + <4 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m1 */ + <4 RK_PA2 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m1 */ + <4 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1m2_pins: pcie30x1m2-pins { + rockchip,pins = + /* pcie30x1_0_clkreqn_m2 */ + <1 RK_PB5 4 &pcfg_pull_none>, + /* pcie30x1_0_perstn_m2 */ + <1 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x1_0_waken_m2 */ + <1 RK_PB3 4 &pcfg_pull_none>, + /* pcie30x1_1_clkreqn_m2 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie30x1_1_perstn_m2 */ + <1 RK_PA7 4 &pcfg_pull_none>, + /* pcie30x1_1_waken_m2 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_0_button_rstn: pcie30x1-0-button-rstn { + rockchip,pins = + /* pcie30x1_0_button_rstn */ + <4 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x1_1_button_rstn: pcie30x1-1-button-rstn { + rockchip,pins = + /* pcie30x1_1_button_rstn */ + <4 RK_PB2 4 &pcfg_pull_none>; + }; + }; + + pcie30x2 { + /omit-if-no-ref/ + pcie30x2m0_pins: pcie30x2m0-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m0 */ + <0 RK_PD1 12 &pcfg_pull_none>, + /* pcie30x2_perstn_m0 */ + <0 RK_PD4 12 &pcfg_pull_none>, + /* pcie30x2_waken_m0 */ + <0 RK_PD2 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m1_pins: pcie30x2m1-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m1 */ + <4 RK_PA6 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m1 */ + <4 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x2_waken_m1 */ + <4 RK_PA7 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m2_pins: pcie30x2m2-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m2 */ + <3 RK_PD2 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m2 */ + <3 RK_PD4 4 &pcfg_pull_none>, + /* pcie30x2_waken_m2 */ + <3 RK_PD3 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2m3_pins: pcie30x2m3-pins { + rockchip,pins = + /* pcie30x2_clkreqn_m3 */ + <1 RK_PD7 4 &pcfg_pull_none>, + /* pcie30x2_perstn_m3 */ + <1 RK_PB7 4 &pcfg_pull_none>, + /* pcie30x2_waken_m3 */ + <1 RK_PB6 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x2_button_rstn: pcie30x2-button-rstn { + rockchip,pins = + /* pcie30x2_button_rstn */ + <3 RK_PC1 4 &pcfg_pull_none>; + }; + }; + + pcie30x4 { + /omit-if-no-ref/ + pcie30x4m0_pins: pcie30x4m0-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m0 */ + <0 RK_PC6 12 &pcfg_pull_none>, + /* pcie30x4_perstn_m0 */ + <0 RK_PD0 12 &pcfg_pull_none>, + /* pcie30x4_waken_m0 */ + <0 RK_PC7 12 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m1_pins: pcie30x4m1-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m1 */ + <4 RK_PB4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m1 */ + <4 RK_PB6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m1 */ + <4 RK_PB5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m2_pins: pcie30x4m2-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m2 */ + <3 RK_PC4 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m2 */ + <3 RK_PC6 4 &pcfg_pull_none>, + /* pcie30x4_waken_m2 */ + <3 RK_PC5 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4m3_pins: pcie30x4m3-pins { + rockchip,pins = + /* pcie30x4_clkreqn_m3 */ + <1 RK_PB0 4 &pcfg_pull_none>, + /* pcie30x4_perstn_m3 */ + <1 RK_PB2 4 &pcfg_pull_none>, + /* pcie30x4_waken_m3 */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pcie30x4_button_rstn: pcie30x4-button-rstn { + rockchip,pins = + /* pcie30x4_button_rstn */ + <3 RK_PD5 4 &pcfg_pull_none>; + }; + }; + + pdm0 { + /omit-if-no-ref/ + pdm0m0_clk: pdm0m0-clk { + rockchip,pins = + /* pdm0_clk0_m0 */ + <1 RK_PC6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_clk1: pdm0m0-clk1 { + rockchip,pins = + /* pdm0m0_clk1 */ + <1 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_idle: pdm0m0-idle { + rockchip,pins = + /* pdm0m0_clk0_gpio */ + <1 RK_PC6 0 &pcfg_pull_none>, + /* pdm0m0_clk1_gpio */ + <1 RK_PC4 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi0: pdm0m0-sdi0 { + rockchip,pins = + /* pdm0m0_sdi0 */ + <1 RK_PD5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi1: pdm0m0-sdi1 { + rockchip,pins = + /* pdm0m0_sdi1 */ + <1 RK_PD1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi2: pdm0m0-sdi2 { + rockchip,pins = + /* pdm0m0_sdi2 */ + <1 RK_PD2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m0_sdi3: pdm0m0-sdi3 { + rockchip,pins = + /* pdm0m0_sdi3 */ + <1 RK_PD3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + pdm0m1_clk: pdm0m1-clk { + rockchip,pins = + /* pdm0_clk0_m1 */ + <0 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_clk1: pdm0m1-clk1 { + rockchip,pins = + /* pdm0m1_clk1 */ + <0 RK_PC4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_idle: pdm0m1-idle { + rockchip,pins = + /* pdm0m1_clk0_gpio */ + <0 RK_PC0 0 &pcfg_pull_none>, + /* pdm0m1_clk1_gpio */ + <0 RK_PC4 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi0: pdm0m1-sdi0 { + rockchip,pins = + /* pdm0m1_sdi0 */ + <0 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi1: pdm0m1-sdi1 { + rockchip,pins = + /* pdm0m1_sdi1 */ + <0 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi2: pdm0m1-sdi2 { + rockchip,pins = + /* pdm0m1_sdi2 */ + <0 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm0m1_sdi3: pdm0m1-sdi3 { + rockchip,pins = + /* pdm0m1_sdi3 */ + <0 RK_PD6 2 &pcfg_pull_none>; + }; + }; + + pdm1 { + /omit-if-no-ref/ + pdm1m0_clk: pdm1m0-clk { + rockchip,pins = + /* pdm1_clk0_m0 */ + <4 RK_PD5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_clk1: pdm1m0-clk1 { + rockchip,pins = + /* pdm1m0_clk1 */ + <4 RK_PD4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_idle: pdm1m0-idle { + rockchip,pins = + /* pdm1m0_clk0_gpio */ + <4 RK_PD5 0 &pcfg_pull_none>, + /* pdm1m0_clk1_gpio */ + <4 RK_PD4 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi0: pdm1m0-sdi0 { + rockchip,pins = + /* pdm1m0_sdi0 */ + <4 RK_PD3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi1: pdm1m0-sdi1 { + rockchip,pins = + /* pdm1m0_sdi1 */ + <4 RK_PD2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi2: pdm1m0-sdi2 { + rockchip,pins = + /* pdm1m0_sdi2 */ + <4 RK_PD1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m0_sdi3: pdm1m0-sdi3 { + rockchip,pins = + /* pdm1m0_sdi3 */ + <4 RK_PD0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk: pdm1m1-clk { + rockchip,pins = + /* pdm1_clk0_m1 */ + <1 RK_PB4 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_clk1: pdm1m1-clk1 { + rockchip,pins = + /* pdm1m1_clk1 */ + <1 RK_PB3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_idle: pdm1m1-idle { + rockchip,pins = + /* pdm1m1_clk0_gpio */ + <1 RK_PB4 0 &pcfg_pull_none>, + /* pdm1m1_clk1_gpio */ + <1 RK_PB3 0 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi0: pdm1m1-sdi0 { + rockchip,pins = + /* pdm1m1_sdi0 */ + <1 RK_PA7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi1: pdm1m1-sdi1 { + rockchip,pins = + /* pdm1m1_sdi1 */ + <1 RK_PB0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi2: pdm1m1-sdi2 { + rockchip,pins = + /* pdm1m1_sdi2 */ + <1 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm1m1_sdi3: pdm1m1-sdi3 { + rockchip,pins = + /* pdm1m1_sdi3 */ + <1 RK_PB2 2 &pcfg_pull_none>; + }; + }; + + pmic { + /omit-if-no-ref/ + pmic_pins: pmic-pins { + rockchip,pins = + /* pmic_int_l */ + <0 RK_PA7 0 &pcfg_pull_up>, + /* pmic_sleep1 */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* pmic_sleep2 */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* pmic_sleep3 */ + <0 RK_PC1 1 &pcfg_pull_none>, + /* pmic_sleep4 */ + <0 RK_PC2 1 &pcfg_pull_none>, + /* pmic_sleep5 */ + <0 RK_PC3 1 &pcfg_pull_none>, + /* pmic_sleep6 */ + <0 RK_PD6 1 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <0 RK_PA5 3 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <0 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PD2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm0m2_pins: pwm0m2-pins { + rockchip,pins = + /* pwm0_m2 */ + <1 RK_PA2 11 &pcfg_pull_none>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <0 RK_PC0 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm1m2_pins: pwm1m2-pins { + rockchip,pins = + /* pwm1_m2 */ + <1 RK_PA3 11 &pcfg_pull_none>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <0 RK_PC4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <3 RK_PB1 11 &pcfg_pull_none>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_ir_m0 */ + <0 RK_PD4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_ir_m1 */ + <3 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m2_pins: pwm3m2-pins { + rockchip,pins = + /* pwm3_ir_m2 */ + <1 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm3m3_pins: pwm3m3-pins { + rockchip,pins = + /* pwm3_ir_m3 */ + <1 RK_PA7 11 &pcfg_pull_none>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <0 RK_PC5 11 &pcfg_pull_none>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <0 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <0 RK_PC6 11 &pcfg_pull_none>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <0 RK_PC7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <4 RK_PC1 11 &pcfg_pull_none>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_ir_m0 */ + <0 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_ir_m1 */ + <4 RK_PD4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm7m2_pins: pwm7m2-pins { + rockchip,pins = + /* pwm7_ir_m2 */ + <1 RK_PC3 11 &pcfg_pull_none>; + }; + }; + + pwm8 { + /omit-if-no-ref/ + pwm8m0_pins: pwm8m0-pins { + rockchip,pins = + /* pwm8_m0 */ + <3 RK_PA7 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m1_pins: pwm8m1-pins { + rockchip,pins = + /* pwm8_m1 */ + <4 RK_PD0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm8m2_pins: pwm8m2-pins { + rockchip,pins = + /* pwm8_m2 */ + <3 RK_PD0 11 &pcfg_pull_none>; + }; + }; + + pwm9 { + /omit-if-no-ref/ + pwm9m0_pins: pwm9m0-pins { + rockchip,pins = + /* pwm9_m0 */ + <3 RK_PB0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m1_pins: pwm9m1-pins { + rockchip,pins = + /* pwm9_m1 */ + <4 RK_PD1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm9m2_pins: pwm9m2-pins { + rockchip,pins = + /* pwm9_m2 */ + <3 RK_PD1 11 &pcfg_pull_none>; + }; + }; + + pwm10 { + /omit-if-no-ref/ + pwm10m0_pins: pwm10m0-pins { + rockchip,pins = + /* pwm10_m0 */ + <3 RK_PA0 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m1_pins: pwm10m1-pins { + rockchip,pins = + /* pwm10_m1 */ + <4 RK_PD3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm10m2_pins: pwm10m2-pins { + rockchip,pins = + /* pwm10_m2 */ + <3 RK_PD3 11 &pcfg_pull_none>; + }; + }; + + pwm11 { + /omit-if-no-ref/ + pwm11m0_pins: pwm11m0-pins { + rockchip,pins = + /* pwm11_ir_m0 */ + <3 RK_PA1 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m1_pins: pwm11m1-pins { + rockchip,pins = + /* pwm11_ir_m1 */ + <4 RK_PB4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m2_pins: pwm11m2-pins { + rockchip,pins = + /* pwm11_ir_m2 */ + <1 RK_PC4 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm11m3_pins: pwm11m3-pins { + rockchip,pins = + /* pwm11_ir_m3 */ + <3 RK_PD5 11 &pcfg_pull_none>; + }; + }; + + pwm12 { + /omit-if-no-ref/ + pwm12m0_pins: pwm12m0-pins { + rockchip,pins = + /* pwm12_m0 */ + <3 RK_PB5 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm12m1_pins: pwm12m1-pins { + rockchip,pins = + /* pwm12_m1 */ + <4 RK_PB5 11 &pcfg_pull_none>; + }; + }; + + pwm13 { + /omit-if-no-ref/ + pwm13m0_pins: pwm13m0-pins { + rockchip,pins = + /* pwm13_m0 */ + <3 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m1_pins: pwm13m1-pins { + rockchip,pins = + /* pwm13_m1 */ + <4 RK_PB6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm13m2_pins: pwm13m2-pins { + rockchip,pins = + /* pwm13_m2 */ + <1 RK_PB7 11 &pcfg_pull_none>; + }; + }; + + pwm14 { + /omit-if-no-ref/ + pwm14m0_pins: pwm14m0-pins { + rockchip,pins = + /* pwm14_m0 */ + <3 RK_PC2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m1_pins: pwm14m1-pins { + rockchip,pins = + /* pwm14_m1 */ + <4 RK_PB2 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm14m2_pins: pwm14m2-pins { + rockchip,pins = + /* pwm14_m2 */ + <1 RK_PD6 11 &pcfg_pull_none>; + }; + }; + + pwm15 { + /omit-if-no-ref/ + pwm15m0_pins: pwm15m0-pins { + rockchip,pins = + /* pwm15_ir_m0 */ + <3 RK_PC3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m1_pins: pwm15m1-pins { + rockchip,pins = + /* pwm15_ir_m1 */ + <4 RK_PB3 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m2_pins: pwm15m2-pins { + rockchip,pins = + /* pwm15_ir_m2 */ + <1 RK_PC6 11 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pwm15m3_pins: pwm15m3-pins { + rockchip,pins = + /* pwm15_ir_m3 */ + <1 RK_PD7 11 &pcfg_pull_none>; + }; + }; + + refclk { + /omit-if-no-ref/ + refclk_pins: refclk-pins { + rockchip,pins = + /* refclk_out */ + <0 RK_PA0 1 &pcfg_pull_none>; + }; + }; + + sata { + /omit-if-no-ref/ + sata_pins: sata-pins { + rockchip,pins = + /* sata_cp_pod */ + <0 RK_PC6 13 &pcfg_pull_none>, + /* sata_cpdet */ + <0 RK_PD4 13 &pcfg_pull_none>, + /* sata_mp_switch */ + <0 RK_PD5 13 &pcfg_pull_none>; + }; + }; + + sata0 { + /omit-if-no-ref/ + sata0m0_pins: sata0m0-pins { + rockchip,pins = + /* sata0_act_led_m0 */ + <4 RK_PB6 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata0m1_pins: sata0m1-pins { + rockchip,pins = + /* sata0_act_led_m1 */ + <1 RK_PB3 6 &pcfg_pull_none>; + }; + }; + + sata1 { + /omit-if-no-ref/ + sata1m0_pins: sata1m0-pins { + rockchip,pins = + /* sata1_act_led_m0 */ + <4 RK_PB5 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata1m1_pins: sata1m1-pins { + rockchip,pins = + /* sata1_act_led_m1 */ + <1 RK_PA1 6 &pcfg_pull_none>; + }; + }; + + sata2 { + /omit-if-no-ref/ + sata2m0_pins: sata2m0-pins { + rockchip,pins = + /* sata2_act_led_m0 */ + <4 RK_PB1 6 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + sata2m1_pins: sata2m1-pins { + rockchip,pins = + /* sata2_act_led_m1 */ + <1 RK_PB7 6 &pcfg_pull_none>; + }; + }; + + sdio { + /omit-if-no-ref/ + sdiom1_pins: sdiom1-pins { + rockchip,pins = + /* sdio_clk_m1 */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* sdio_cmd_m1 */ + <3 RK_PA4 2 &pcfg_pull_up>, + /* sdio_d0_m1 */ + <3 RK_PA0 2 &pcfg_pull_up>, + /* sdio_d1_m1 */ + <3 RK_PA1 2 &pcfg_pull_up>, + /* sdio_d2_m1 */ + <3 RK_PA2 2 &pcfg_pull_up>, + /* sdio_d3_m1 */ + <3 RK_PA3 2 &pcfg_pull_up>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <4 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <4 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <4 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <4 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <4 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <4 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_det */ + <0 RK_PA4 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <0 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + spdif0 { + /omit-if-no-ref/ + spdif0m0_tx: spdif0m0-tx { + rockchip,pins = + /* spdif0m0_tx */ + <1 RK_PB6 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif0m1_tx: spdif0m1-tx { + rockchip,pins = + /* spdif0m1_tx */ + <4 RK_PB4 6 &pcfg_pull_none>; + }; + }; + + spdif1 { + /omit-if-no-ref/ + spdif1m0_tx: spdif1m0-tx { + rockchip,pins = + /* spdif1m0_tx */ + <1 RK_PB7 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m1_tx: spdif1m1-tx { + rockchip,pins = + /* spdif1m1_tx */ + <4 RK_PB1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdif1m2_tx: spdif1m2-tx { + rockchip,pins = + /* spdif1m2_tx */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0m0_pins: spi0m0-pins { + rockchip,pins = + /* spi0_clk_m0 */ + <0 RK_PC6 8 &pcfg_pull_up_drv_level_6>, + /* spi0_miso_m0 */ + <0 RK_PC7 8 &pcfg_pull_up_drv_level_6>, + /* spi0_mosi_m0 */ + <0 RK_PC0 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m0_cs0: spi0m0-cs0 { + rockchip,pins = + /* spi0_cs0_m0 */ + <0 RK_PD1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m0_cs1: spi0m0-cs1 { + rockchip,pins = + /* spi0_cs1_m0 */ + <0 RK_PB7 8 &pcfg_pull_up_drv_level_6>; + }; + /omit-if-no-ref/ + spi0m1_pins: spi0m1-pins { + rockchip,pins = + /* spi0_clk_m1 */ + <4 RK_PA2 8 &pcfg_pull_up_drv_level_6>, + /* spi0_miso_m1 */ + <4 RK_PA0 8 &pcfg_pull_up_drv_level_6>, + /* spi0_mosi_m1 */ + <4 RK_PA1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m1_cs0: spi0m1-cs0 { + rockchip,pins = + /* spi0_cs0_m1 */ + <4 RK_PB2 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m1_cs1: spi0m1-cs1 { + rockchip,pins = + /* spi0_cs1_m1 */ + <4 RK_PB1 8 &pcfg_pull_up_drv_level_6>; + }; + /omit-if-no-ref/ + spi0m2_pins: spi0m2-pins { + rockchip,pins = + /* spi0_clk_m2 */ + <1 RK_PB3 8 &pcfg_pull_up_drv_level_6>, + /* spi0_miso_m2 */ + <1 RK_PB1 8 &pcfg_pull_up_drv_level_6>, + /* spi0_mosi_m2 */ + <1 RK_PB2 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m2_cs0: spi0m2-cs0 { + rockchip,pins = + /* spi0_cs0_m2 */ + <1 RK_PB4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m2_cs1: spi0m2-cs1 { + rockchip,pins = + /* spi0_cs1_m2 */ + <1 RK_PB5 8 &pcfg_pull_up_drv_level_6>; + }; + /omit-if-no-ref/ + spi0m3_pins: spi0m3-pins { + rockchip,pins = + /* spi0_clk_m3 */ + <3 RK_PD3 8 &pcfg_pull_up_drv_level_6>, + /* spi0_miso_m3 */ + <3 RK_PD1 8 &pcfg_pull_up_drv_level_6>, + /* spi0_mosi_m3 */ + <3 RK_PD2 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m3_cs0: spi0m3-cs0 { + rockchip,pins = + /* spi0_cs0_m3 */ + <3 RK_PD4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi0m3_cs1: spi0m3-cs1 { + rockchip,pins = + /* spi0_cs1_m3 */ + <3 RK_PD5 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1m1_pins: spi1m1-pins { + rockchip,pins = + /* spi1_clk_m1 */ + <3 RK_PC1 8 &pcfg_pull_up_drv_level_6>, + /* spi1_miso_m1 */ + <3 RK_PC0 8 &pcfg_pull_up_drv_level_6>, + /* spi1_mosi_m1 */ + <3 RK_PB7 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m1_cs0: spi1m1-cs0 { + rockchip,pins = + /* spi1_cs0_m1 */ + <3 RK_PC2 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m1_cs1: spi1m1-cs1 { + rockchip,pins = + /* spi1_cs1_m1 */ + <3 RK_PC3 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m2_pins: spi1m2-pins { + rockchip,pins = + /* spi1_clk_m2 */ + <1 RK_PD2 8 &pcfg_pull_up_drv_level_6>, + /* spi1_miso_m2 */ + <1 RK_PD0 8 &pcfg_pull_up_drv_level_6>, + /* spi1_mosi_m2 */ + <1 RK_PD1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m2_cs0: spi1m2-cs0 { + rockchip,pins = + /* spi1_cs0_m2 */ + <1 RK_PD3 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi1m2_cs1: spi1m2-cs1 { + rockchip,pins = + /* spi1_cs1_m2 */ + <1 RK_PD5 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + spi2 { + /omit-if-no-ref/ + spi2m0_pins: spi2m0-pins { + rockchip,pins = + /* spi2_clk_m0 */ + <1 RK_PA6 8 &pcfg_pull_up_drv_level_6>, + /* spi2_miso_m0 */ + <1 RK_PA4 8 &pcfg_pull_up_drv_level_6>, + /* spi2_mosi_m0 */ + <1 RK_PA5 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m0_cs0: spi2m0-cs0 { + rockchip,pins = + /* spi2_cs0_m0 */ + <1 RK_PA7 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m0_cs1: spi2m0-cs1 { + rockchip,pins = + /* spi2_cs1_m0 */ + <1 RK_PB0 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m1_pins: spi2m1-pins { + rockchip,pins = + /* spi2_clk_m1 */ + <4 RK_PA6 8 &pcfg_pull_up_drv_level_6>, + /* spi2_miso_m1 */ + <4 RK_PA4 8 &pcfg_pull_up_drv_level_6>, + /* spi2_mosi_m1 */ + <4 RK_PA5 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m1_cs0: spi2m1-cs0 { + rockchip,pins = + /* spi2_cs0_m1 */ + <4 RK_PA7 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m1_cs1: spi2m1-cs1 { + rockchip,pins = + /* spi2_cs1_m1 */ + <4 RK_PB0 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi2m2_pins: spi2m2-pins { + rockchip,pins = + /* spi2_clk_m2 */ + <0 RK_PA5 1 &pcfg_pull_up_drv_level_1>, + /* spi2_miso_m2 */ + <0 RK_PB3 1 &pcfg_pull_up_drv_level_1>, + /* spi2_mosi_m2 */ + <0 RK_PA6 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs0: spi2m2-cs0 { + rockchip,pins = + /* spi2_cs0_m2 */ + <0 RK_PB1 1 &pcfg_pull_up_drv_level_1>; + }; + + /omit-if-no-ref/ + spi2m2_cs1: spi2m2-cs1 { + rockchip,pins = + /* spi2_cs1_m2 */ + <0 RK_PB0 1 &pcfg_pull_up_drv_level_1>; + }; + }; + + spi3 { + /omit-if-no-ref/ + spi3m1_pins: spi3m1-pins { + rockchip,pins = + /* spi3_clk_m1 */ + <4 RK_PB7 8 &pcfg_pull_up_drv_level_6>, + /* spi3_miso_m1 */ + <4 RK_PB5 8 &pcfg_pull_up_drv_level_6>, + /* spi3_mosi_m1 */ + <4 RK_PB6 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m1_cs0: spi3m1-cs0 { + rockchip,pins = + /* spi3_cs0_m1 */ + <4 RK_PC0 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m1_cs1: spi3m1-cs1 { + rockchip,pins = + /* spi3_cs1_m1 */ + <4 RK_PC1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m2_pins: spi3m2-pins { + rockchip,pins = + /* spi3_clk_m2 */ + <0 RK_PD3 8 &pcfg_pull_up_drv_level_6>, + /* spi3_miso_m2 */ + <0 RK_PD0 8 &pcfg_pull_up_drv_level_6>, + /* spi3_mosi_m2 */ + <0 RK_PD2 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m2_cs0: spi3m2-cs0 { + rockchip,pins = + /* spi3_cs0_m2 */ + <0 RK_PD4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m2_cs1: spi3m2-cs1 { + rockchip,pins = + /* spi3_cs1_m2 */ + <0 RK_PD5 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m3_pins: spi3m3-pins { + rockchip,pins = + /* spi3_clk_m3 */ + <3 RK_PD0 8 &pcfg_pull_up_drv_level_6>, + /* spi3_miso_m3 */ + <3 RK_PC6 8 &pcfg_pull_up_drv_level_6>, + /* spi3_mosi_m3 */ + <3 RK_PC7 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m3_cs0: spi3m3-cs0 { + rockchip,pins = + /* spi3_cs0_m3 */ + <3 RK_PC4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi3m3_cs1: spi3m3-cs1 { + rockchip,pins = + /* spi3_cs1_m3 */ + <3 RK_PC5 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + spi4 { + /omit-if-no-ref/ + spi4m0_pins: spi4m0-pins { + rockchip,pins = + /* spi4_clk_m0 */ + <1 RK_PC2 8 &pcfg_pull_up_drv_level_6>, + /* spi4_miso_m0 */ + <1 RK_PC0 8 &pcfg_pull_up_drv_level_6>, + /* spi4_mosi_m0 */ + <1 RK_PC1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m0_cs0: spi4m0-cs0 { + rockchip,pins = + /* spi4_cs0_m0 */ + <1 RK_PC3 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m0_cs1: spi4m0-cs1 { + rockchip,pins = + /* spi4_cs1_m0 */ + <1 RK_PC4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m1_pins: spi4m1-pins { + rockchip,pins = + /* spi4_clk_m1 */ + <3 RK_PA2 8 &pcfg_pull_up_drv_level_6>, + /* spi4_miso_m1 */ + <3 RK_PA0 8 &pcfg_pull_up_drv_level_6>, + /* spi4_mosi_m1 */ + <3 RK_PA1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m1_cs0: spi4m1-cs0 { + rockchip,pins = + /* spi4_cs0_m1 */ + <3 RK_PA3 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m1_cs1: spi4m1-cs1 { + rockchip,pins = + /* spi4_cs1_m1 */ + <3 RK_PA4 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m2_pins: spi4m2-pins { + rockchip,pins = + /* spi4_clk_m2 */ + <1 RK_PA2 8 &pcfg_pull_up_drv_level_6>, + /* spi4_miso_m2 */ + <1 RK_PA0 8 &pcfg_pull_up_drv_level_6>, + /* spi4_mosi_m2 */ + <1 RK_PA1 8 &pcfg_pull_up_drv_level_6>; + }; + + /omit-if-no-ref/ + spi4m2_cs0: spi4m2-cs0 { + rockchip,pins = + /* spi4_cs0_m2 */ + <1 RK_PA3 8 &pcfg_pull_up_drv_level_6>; + }; + }; + + tsadc { + /omit-if-no-ref/ + tsadcm1_shut: tsadcm1-shut { + rockchip,pins = + /* tsadcm1_shut */ + <0 RK_PA2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut: tsadc-shut { + rockchip,pins = + /* tsadc_shut */ + <0 RK_PA1 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + tsadc_shut_org: tsadc-shut-org { + rockchip,pins = + /* tsadc_shut_org */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <0 RK_PC4 4 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <0 RK_PC5 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <0 RK_PB0 4 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <0 RK_PB1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m2_xfer: uart0m2-xfer { + rockchip,pins = + /* uart0_rx_m2 */ + <4 RK_PA4 10 &pcfg_pull_up>, + /* uart0_tx_m2 */ + <4 RK_PA3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + /* uart0_ctsn */ + <0 RK_PD1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + /* uart0_rtsn */ + <0 RK_PC6 4 &pcfg_pull_none>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <1 RK_PB7 10 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <1 RK_PB6 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_ctsn: uart1m1-ctsn { + rockchip,pins = + /* uart1m1_ctsn */ + <1 RK_PD7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m1_rtsn: uart1m1-rtsn { + rockchip,pins = + /* uart1m1_rtsn */ + <1 RK_PD6 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_xfer: uart1m2-xfer { + rockchip,pins = + /* uart1_rx_m2 */ + <0 RK_PD2 10 &pcfg_pull_up>, + /* uart1_tx_m2 */ + <0 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m2_ctsn: uart1m2-ctsn { + rockchip,pins = + /* uart1m2_ctsn */ + <0 RK_PD0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart1m2_rtsn: uart1m2-rtsn { + rockchip,pins = + /* uart1m2_rtsn */ + <0 RK_PC7 10 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <0 RK_PB6 10 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <0 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <4 RK_PD1 10 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <4 RK_PD0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m2_xfer: uart2m2-xfer { + rockchip,pins = + /* uart2_rx_m2 */ + <3 RK_PB2 10 &pcfg_pull_up>, + /* uart2_tx_m2 */ + <3 RK_PB1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2_ctsn: uart2-ctsn { + rockchip,pins = + /* uart2_ctsn */ + <3 RK_PB4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2_rtsn: uart2-rtsn { + rockchip,pins = + /* uart2_rtsn */ + <3 RK_PB3 10 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <1 RK_PC0 10 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <1 RK_PC1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <3 RK_PB6 10 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <3 RK_PB5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m2_xfer: uart3m2-xfer { + rockchip,pins = + /* uart3_rx_m2 */ + <4 RK_PA6 10 &pcfg_pull_up>, + /* uart3_tx_m2 */ + <4 RK_PA5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <1 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <1 RK_PC2 10 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <1 RK_PD3 10 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <1 RK_PD2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m1_xfer: uart4m1-xfer { + rockchip,pins = + /* uart4_rx_m1 */ + <3 RK_PD0 10 &pcfg_pull_up>, + /* uart4_tx_m1 */ + <3 RK_PD1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4m2_xfer: uart4m2-xfer { + rockchip,pins = + /* uart4_rx_m2 */ + <1 RK_PB2 10 &pcfg_pull_up>, + /* uart4_tx_m2 */ + <1 RK_PB3 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <1 RK_PC7 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <1 RK_PC5 10 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <4 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <4 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <4 RK_PD2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <4 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <3 RK_PC5 10 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <3 RK_PC4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <2 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <2 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m2_xfer: uart5m2-xfer { + rockchip,pins = + /* uart5_rx_m2 */ + <2 RK_PD4 10 &pcfg_pull_up>, + /* uart5_tx_m2 */ + <2 RK_PD5 10 &pcfg_pull_up>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <1 RK_PA0 10 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <1 RK_PA1 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_ctsn: uart6m1-ctsn { + rockchip,pins = + /* uart6m1_ctsn */ + <1 RK_PA3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m1_rtsn: uart6m1-rtsn { + rockchip,pins = + /* uart6m1_rtsn */ + <1 RK_PA2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart6m2_xfer: uart6m2-xfer { + rockchip,pins = + /* uart6_rx_m2 */ + <1 RK_PD1 10 &pcfg_pull_up>, + /* uart6_tx_m2 */ + <1 RK_PD0 10 &pcfg_pull_up>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <3 RK_PC1 10 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <3 RK_PC0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <3 RK_PC3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <3 RK_PC2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m2_xfer: uart7m2-xfer { + rockchip,pins = + /* uart7_rx_m2 */ + <1 RK_PB4 10 &pcfg_pull_up>, + /* uart7_tx_m2 */ + <1 RK_PB5 10 &pcfg_pull_up>; + }; + }; + + uart8 { + /omit-if-no-ref/ + uart8m0_xfer: uart8m0-xfer { + rockchip,pins = + /* uart8_rx_m0 */ + <4 RK_PB1 10 &pcfg_pull_up>, + /* uart8_tx_m0 */ + <4 RK_PB0 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m0_ctsn: uart8m0-ctsn { + rockchip,pins = + /* uart8m0_ctsn */ + <4 RK_PB3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m0_rtsn: uart8m0-rtsn { + rockchip,pins = + /* uart8m0_rtsn */ + <4 RK_PB2 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_xfer: uart8m1-xfer { + rockchip,pins = + /* uart8_rx_m1 */ + <3 RK_PA3 10 &pcfg_pull_up>, + /* uart8_tx_m1 */ + <3 RK_PA2 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart8m1_ctsn: uart8m1-ctsn { + rockchip,pins = + /* uart8m1_ctsn */ + <3 RK_PA5 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8m1_rtsn: uart8m1-rtsn { + rockchip,pins = + /* uart8m1_rtsn */ + <3 RK_PA4 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart8_xfer: uart8-xfer { + rockchip,pins = + /* uart8_rx_ */ + <4 RK_PB1 10 &pcfg_pull_up>; + }; + }; + + uart9 { + /omit-if-no-ref/ + uart9m1_xfer: uart9m1-xfer { + rockchip,pins = + /* uart9_rx_m1 */ + <4 RK_PB5 10 &pcfg_pull_up>, + /* uart9_tx_m1 */ + <4 RK_PB4 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m1_ctsn: uart9m1-ctsn { + rockchip,pins = + /* uart9m1_ctsn */ + <4 RK_PA1 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m1_rtsn: uart9m1-rtsn { + rockchip,pins = + /* uart9m1_rtsn */ + <4 RK_PA0 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_xfer: uart9m2-xfer { + rockchip,pins = + /* uart9_rx_m2 */ + <3 RK_PD4 10 &pcfg_pull_up>, + /* uart9_tx_m2 */ + <3 RK_PD5 10 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart9m2_ctsn: uart9m2-ctsn { + rockchip,pins = + /* uart9m2_ctsn */ + <3 RK_PD3 10 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart9m2_rtsn: uart9m2-rtsn { + rockchip,pins = + /* uart9m2_rtsn */ + <3 RK_PD2 10 &pcfg_pull_none>; + }; + }; + + vop { + /omit-if-no-ref/ + vop_pins: vop-pins { + rockchip,pins = + /* vop_post_empty */ + <1 RK_PA2 1 &pcfg_pull_none>; + }; + }; +}; + +/* + * This part is edited handly. + */ +&pinctrl { + bt656 { + /omit-if-no-ref/ + bt656_pins: bt656-pins { + rockchip,pins = + /* bt1120_clkout */ + <4 RK_PB0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d0 */ + <4 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d1 */ + <4 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d2 */ + <4 RK_PA2 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d3 */ + <4 RK_PA3 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d4 */ + <4 RK_PA4 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d5 */ + <4 RK_PA5 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d6 */ + <4 RK_PA6 2 &pcfg_pull_none_drv_level_2>, + /* bt1120_d7 */ + <4 RK_PA7 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + gpio-func { + /omit-if-no-ref/ + tsadc_gpio_func: tsadc-gpio-func { + rockchip,pins = + <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588s-rk806-dual.dtsi b/rk3588s-rk806-dual.dtsi new file mode 100644 index 0000000..0433738 --- /dev/null +++ b/rk3588s-rk806-dual.dtsi @@ -0,0 +1,777 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include + +&spi2 { + status = "okay"; + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <2>; + + rk806master: rk806master@0 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x0>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-power-off"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; + pinctrl-1 = <&rk806_dvs1_pwrdn>; + + /* 2800mv-3500mv */ + low_voltage_threshold = <3000>; + /* 2700mv-3400mv */ + shutdown_voltage_threshold = <2700>; + /* 140 160 */ + shutdown_temperture_threshold = <160>; + hotdie_temperture_threshold = <115>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + /* PWRON_ON_TIME: 0:500mS; 1:20mS */ + pwron-on-time-20ms; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc5v0_sys>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "okay"; + }; + + pinctrl_rk806: pinctrl_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_dvs1_null: rk806_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: rk806_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: rk806_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_null: rk806_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_slp: rk806_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: rk806_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: rk806_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: rk806_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: rk806_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_slp: rk806_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: rk806_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: rk806_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: rk806_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_gpu_s0: DCDC_REG1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu_mem_s0: DCDC_REG5 { + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-enable-ramp-delay = <400>; + regulator-name = "vdd_gpu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_mem_s0: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_2v0_pldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vdd_vdenc_mem_s0: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd2_ddr_s3: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_1v1_nldo_s3: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1100000>; + }; + }; + + avcc_1v8_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd1_1v8_ddr_s3: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd1_1v8_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_1v8_s3: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + master_pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "master_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd2l_0v9_ddr_s3: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd2l_0v9_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + master_nldo3: NLDO_REG3 { + regulator-name = "master_nldo3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_0v75_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; + + rk806slave: rk806slave@1 { + compatible = "rockchip,rk806"; + spi-max-frequency = <1000000>; + reg = <0x01>; + + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default", "pmic-sleep"; + pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; + pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; + + /* 0: restart PMU; + * 1: reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode; + * 2: Reset all the power off reset registers, + * forcing the state to switch to ACTIVE mode, + * and simultaneously pull down the RESETB PIN for 5mS before releasing + */ + pmic-reset-func = <1>; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_2v0_pldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + pwrkey { + status = "disabled"; + }; + + pinctrl_slave_rk806: pinctrl_slave_rk806 { + gpio-controller; + #gpio-cells = <2>; + + rk806_slave_dvs1_null: rk806_slave_dvs1_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs1_slp: rk806_slave_dvs1_slp { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_slave_dvs1_rst: rk806_slave_dvs1_rst { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_slave_dvs2_null: rk806_slave_dvs2_null { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_slave_dvs2_slp: rk806_slave_dvs2_slp { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_slave_dvs2_rst: rk806_slave_dvs2_rst { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_slave_dvs3_null: rk806_slave_dvs3_null { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_slave_dvs3_slp: rk806_slave_dvs3_slp { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_slave_dvs3_rst: rk806_slave_dvs3_rst { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + }; + + regulators { + vdd_cpu_big1_s0: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big0_s0: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s3: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_cpu_big1_mem_s0: DCDC_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big1_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + + vdd_cpu_big0_mem_s0: DCDC_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big0_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: DCDC_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_mem_s0: DCDC_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_mem_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vddq_ddr_s0: DCDC_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: DCDC_REG10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_cam_s0: PLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_1v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd1v8_ddr_pll_s0: PLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd1v8_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_1v8_pll_s0: PLDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_1v8_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_sd_s0: PLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_3v3_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_2v8_cam_s0: PLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-ramp-delay = <12500>; + regulator-name = "vcc_2v8_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: PLDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_pll_s0: NLDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_0v75_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_pll_s0: NLDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + slave_nldo3: NLDO_REG3 { + regulator-name = "slave_nldo3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_cam_s0: NLDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_cam_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + avdd_1v2_s0: NLDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-ramp-delay = <12500>; + regulator-name = "avdd_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; diff --git a/rk3588s-tablet-rk806-single-camera.dtsi b/rk3588s-tablet-rk806-single-camera.dtsi new file mode 100644 index 0000000..dd1bae1 --- /dev/null +++ b/rk3588s-tablet-rk806-single-camera.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + * + */ +/ { + vcc_mipidcphy0: vcc-mipidcphy0-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy0_pwr>; + regulator-name = "vcc_mipidcphy0"; + enable-active-high; + regulator-boot-on; + regulator-always-on; + }; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&s5k3l6_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m4_xfer>; + + fp5510: fp5510@c { + compatible = "fitipower,fp5510"; + status = "okay"; + reg = <0x0c>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + s5k3l6: s5k3l6@10 { + compatible = "samsung,s5k3l6xx"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + // power-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + //pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "default"; + rockchip,camera-module-lens-name = "default"; + lens-focus = <&fp5510>; + port { + s5k3l6_out0: endpoint { + remote-endpoint = <&mipi_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "okay"; +}; + +&isp0_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + }; +}; + +&pinctrl { + cam { + mipidcphy0_pwr: mipidcphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/rk3588s-tablet-rk806-single-v10.dts b/rk3588s-tablet-rk806-single-v10.dts new file mode 100644 index 0000000..2333237 --- /dev/null +++ b/rk3588s-tablet-rk806-single-v10.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-tablet-rk806-single.dtsi" +#include "rk3588s-tablet-rk806-single-camera.dtsi" + +/ { + model = "Rockchip RK3588S TABLET RK806 SINGLE Board"; + compatible = "rockchip,rk3588s-tablet-rk806-single-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-tablet-rk806-single.dtsi b/rk3588s-tablet-rk806-single.dtsi new file mode 100644 index 0000000..450a913 --- /dev/null +++ b/rk3588s-tablet-rk806-single.dtsi @@ -0,0 +1,1674 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-android.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <890000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm13 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + combophy_avdd0v85: combophy-avdd0v85 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd0v85"; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + vin-supply = <&vdd_0v85_s0>; + }; + + combophy_avdd1v8: combophy-avdd1v8 { + compatible = "regulator-fixed"; + regulator-name = "combophy_avdd1v8"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&avcc_1v8_s0>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <0>; + rockchip,android-charge-on = <1>; + rockchip,uboot-low-power-voltage = <3350>; + rockchip,screen-on-voltage = <3400>; + status = "okay"; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,es8388-codec"; + simple-audio-card,aux-devs = <&aw87xxx_pa1 &aw87xxx_pa2>; + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&i2s0_8ch>; + }; + codec { + sound-dai = <&es8388>; + }; + }; + }; + + vcc3v3_lcd_n: vcc3v3-lcd0-n { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd0_n"; + regulator-boot-on; + enable-active-high; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc_3v3_s0>; + }; + + VDD5V8_LCD: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + /*vin-supply = <&vcc5v0_usb>;*/ + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + VEE5V8_LCD: vcc5v0-host1 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host1"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + /*vin-supply = <&vcc5v0_usb>;*/ + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en1>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_wake_host_irq>; + pinctrl-1 = <&uart8_gpios>; + BT,reset_gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6255"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&combphy2_psu { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dmc { + system-status-level = < + /*system status freq level*/ + SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH + SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW + SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH + SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH + SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH + SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH + >; +}; + +&dp0 { + status = "disabled"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&dsi0_in_vp2 { + status = "okay"; +}; + +&dsi0_in_vp3 { + status = "disabled"; +}; + +/* + * mipi_dcphy0 needs to be enabled + * when dsi0 is enabled + */ +&dsi0 { + status = "okay"; + rockchip,dual-channel = <&dsi1>; + //rockchip,lane-rate = <1000>; + dsi0_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi: endpoint { + remote-endpoint = <&dsi_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi>; + }; + }; + }; + +}; + +&dsi1 { + status = "okay"; + //rockchip,lane-rate = <1000>; + dsi1_panel: panel@0 { + status = "okay"; + compatible = "simple-panel-dsi"; + reg = <0>; + backlight = <&backlight>; + reset-delay-ms = <60>; + enable-delay-ms = <60>; + prepare-delay-ms = <60>; + unprepare-delay-ms = <60>; + disable-delay-ms = <60>; + dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + dsi,format = ; + dsi,lanes = <4>; + panel-init-sequence = [ + 23 00 02 FE 21 + 23 00 02 04 00 + 23 00 02 00 64 + 23 00 02 2A 00 + 23 00 02 26 64 + 23 00 02 54 00 + 23 00 02 50 64 + 23 00 02 7B 00 + 23 00 02 77 64 + 23 00 02 A2 00 + 23 00 02 9D 64 + 23 00 02 C9 00 + 23 00 02 C5 64 + 23 00 02 01 71 + 23 00 02 27 71 + 23 00 02 51 71 + 23 00 02 78 71 + 23 00 02 9E 71 + 23 00 02 C6 71 + 23 00 02 02 89 + 23 00 02 28 89 + 23 00 02 52 89 + 23 00 02 79 89 + 23 00 02 9F 89 + 23 00 02 C7 89 + 23 00 02 03 9E + 23 00 02 29 9E + 23 00 02 53 9E + 23 00 02 7A 9E + 23 00 02 A0 9E + 23 00 02 C8 9E + 23 00 02 09 00 + 23 00 02 05 B0 + 23 00 02 31 00 + 23 00 02 2B B0 + 23 00 02 5A 00 + 23 00 02 55 B0 + 23 00 02 80 00 + 23 00 02 7C B0 + 23 00 02 A7 00 + 23 00 02 A3 B0 + 23 00 02 CE 00 + 23 00 02 CA B0 + 23 00 02 06 C0 + 23 00 02 2D C0 + 23 00 02 56 C0 + 23 00 02 7D C0 + 23 00 02 A4 C0 + 23 00 02 CB C0 + 23 00 02 07 CF + 23 00 02 2F CF + 23 00 02 58 CF + 23 00 02 7E CF + 23 00 02 A5 CF + 23 00 02 CC CF + 23 00 02 08 DD + 23 00 02 30 DD + 23 00 02 59 DD + 23 00 02 7F DD + 23 00 02 A6 DD + 23 00 02 CD DD + 23 00 02 0E 15 + 23 00 02 0A E9 + 23 00 02 36 15 + 23 00 02 32 E9 + 23 00 02 5F 15 + 23 00 02 5B E9 + 23 00 02 85 15 + 23 00 02 81 E9 + 23 00 02 AD 15 + 23 00 02 A9 E9 + 23 00 02 D3 15 + 23 00 02 CF E9 + 23 00 02 0B 14 + 23 00 02 33 14 + 23 00 02 5C 14 + 23 00 02 82 14 + 23 00 02 AA 14 + 23 00 02 D0 14 + 23 00 02 0C 36 + 23 00 02 34 36 + 23 00 02 5D 36 + 23 00 02 83 36 + 23 00 02 AB 36 + 23 00 02 D1 36 + 23 00 02 0D 6B + 23 00 02 35 6B + 23 00 02 5E 6B + 23 00 02 84 6B + 23 00 02 AC 6B + 23 00 02 D2 6B + 23 00 02 13 5A + 23 00 02 0F 94 + 23 00 02 3B 5A + 23 00 02 37 94 + 23 00 02 64 5A + 23 00 02 60 94 + 23 00 02 8A 5A + 23 00 02 86 94 + 23 00 02 B2 5A + 23 00 02 AE 94 + 23 00 02 D8 5A + 23 00 02 D4 94 + 23 00 02 10 D1 + 23 00 02 38 D1 + 23 00 02 61 D1 + 23 00 02 87 D1 + 23 00 02 AF D1 + 23 00 02 D5 D1 + 23 00 02 11 04 + 23 00 02 39 04 + 23 00 02 62 04 + 23 00 02 88 04 + 23 00 02 B0 04 + 23 00 02 D6 04 + 23 00 02 12 05 + 23 00 02 3A 05 + 23 00 02 63 05 + 23 00 02 89 05 + 23 00 02 B1 05 + 23 00 02 D7 05 + 23 00 02 18 AA + 23 00 02 14 36 + 23 00 02 42 AA + 23 00 02 3D 36 + 23 00 02 69 AA + 23 00 02 65 36 + 23 00 02 8F AA + 23 00 02 8B 36 + 23 00 02 B7 AA + 23 00 02 B3 36 + 23 00 02 DD AA + 23 00 02 D9 36 + 23 00 02 15 74 + 23 00 02 3F 74 + 23 00 02 66 74 + 23 00 02 8C 74 + 23 00 02 B4 74 + 23 00 02 DA 74 + 23 00 02 16 9F + 23 00 02 40 9F + 23 00 02 67 9F + 23 00 02 8D 9F + 23 00 02 B5 9F + 23 00 02 DB 9F + 23 00 02 17 DC + 23 00 02 41 DC + 23 00 02 68 DC + 23 00 02 8E DC + 23 00 02 B6 DC + 23 00 02 DC DC + 23 00 02 1D FF + 23 00 02 19 03 + 23 00 02 47 FF + 23 00 02 43 03 + 23 00 02 6E FF + 23 00 02 6A 03 + 23 00 02 94 FF + 23 00 02 90 03 + 23 00 02 BC FF + 23 00 02 B8 03 + 23 00 02 E2 FF + 23 00 02 DE 03 + 23 00 02 1A 35 + 23 00 02 44 35 + 23 00 02 6B 35 + 23 00 02 91 35 + 23 00 02 B9 35 + 23 00 02 DF 35 + 23 00 02 1B 45 + 23 00 02 45 45 + 23 00 02 6C 45 + 23 00 02 92 45 + 23 00 02 BA 45 + 23 00 02 E0 45 + 23 00 02 1C 55 + 23 00 02 46 55 + 23 00 02 6D 55 + 23 00 02 93 55 + 23 00 02 BB 55 + 23 00 02 E1 55 + 23 00 02 22 FF + 23 00 02 1E 68 + 23 00 02 4C FF + 23 00 02 48 68 + 23 00 02 73 FF + 23 00 02 6F 68 + 23 00 02 99 FF + 23 00 02 95 68 + 23 00 02 C1 FF + 23 00 02 BD 68 + 23 00 02 E7 FF + 23 00 02 E3 68 + 23 00 02 1F 7E + 23 00 02 49 7E + 23 00 02 70 7E + 23 00 02 96 7E + 23 00 02 BE 7E + 23 00 02 E4 7E + 23 00 02 20 97 + 23 00 02 4A 97 + 23 00 02 71 97 + 23 00 02 97 97 + 23 00 02 BF 97 + 23 00 02 E5 97 + 23 00 02 21 B5 + 23 00 02 4B B5 + 23 00 02 72 B5 + 23 00 02 98 B5 + 23 00 02 C0 B5 + 23 00 02 E6 B5 + 23 00 02 25 F0 + 23 00 02 23 E8 + 23 00 02 4F F0 + 23 00 02 4D E8 + 23 00 02 76 F0 + 23 00 02 74 E8 + 23 00 02 9C F0 + 23 00 02 9A E8 + 23 00 02 C4 F0 + 23 00 02 C2 E8 + 23 00 02 EA F0 + 23 00 02 E8 E8 + 23 00 02 24 FF + 23 00 02 4E FF + 23 00 02 75 FF + 23 00 02 9B FF + 23 00 02 C3 FF + 23 00 02 E9 FF + 23 00 02 FE 3D + 23 00 02 00 04 + 23 00 02 FE 23 + 23 00 02 08 82 + 23 00 02 0A 00 + 23 00 02 0B 00 + 23 00 02 0C 01 + 23 00 02 16 00 + 23 00 02 18 02 + 23 00 02 1B 04 + 23 00 02 19 04 + 23 00 02 1C 81 + 23 00 02 1F 00 + 23 00 02 20 03 + 23 00 02 23 04 + 23 00 02 21 01 + 23 00 02 54 63 + 23 00 02 55 54 + 23 00 02 6E 45 + 23 00 02 6D 36 + 23 00 02 FE 3D + 23 00 02 55 78 + 23 00 02 FE 20 + 23 00 02 26 30 + 23 00 02 FE 3D + 23 00 02 20 71 + 23 00 02 50 8F + 23 00 02 51 8F + 23 00 02 FE 00 + 23 00 02 35 00 + 05 78 01 11 + 05 1E 01 29 + ]; + + panel-exit-sequence = [ + 05 00 01 28 + 05 00 01 10 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <132000000>; + hactive = <1080>; + vactive = <1920>; + hfront-porch = <15>; + hsync-len = <4>; + hback-porch = <30>; + vfront-porch = <15>; + vsync-len = <2>; + vback-porch = <15>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + panel_in_dsi1: endpoint { + remote-endpoint = <&dsi1_out_panel>; + }; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + dsi1_out_panel: endpoint { + remote-endpoint = <&panel_in_dsi1>; + }; + }; + }; + +}; + +&dsi0_panel { + power-supply = <&vcc3v3_lcd_n>; + reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_rst_gpio>; + dsi,lanes = <8>; + panel-init-sequence = [ + 29 02 02 00 00 + 29 02 03 99 95 27 + 05 78 01 11 + 05 01 01 29 + 29 00 02 00 00 + 29 01 03 99 00 00 + ]; + + panel-exit-sequence = [ + 29 00 02 00 00 + 29 00 03 99 95 27 + 05 01 01 28 + 05 01 01 10 + ]; + + disp_timings0: display-timings { + native-mode = <&dsi0_timing0>; + dsi0_timing0: timing0 { + clock-frequency = <246000000>; + hactive = <1600>; + vactive = <2176>; + hfront-porch = <18>; + hsync-len = <8>; + hback-porch = <32>; + vfront-porch = <255>; + vsync-len = <6>; + vback-porch = <34>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +&dsi1_in_vp2 { + status = "disabled"; +}; + +&dsi1_in_vp3 { + status = "disabled"; +}; + +&dsi1_panel { + power-supply = <&vcc3v3_lcd_n>; + compressed-data; + /* + * because in hardware, the two screens share the reset pin, + * so reset-gpios need only in dsi1 enable and dsi0 disabled + * case. + */ + + //reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>; + //pinctrl-names = "default"; + //pinctrl-0 = <&lcd_rst_gpio>; + + dsi,flags = <(MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; + + slice-width = <720>; + slice-height = <65>; + version-major = <1>; + version-minor = <1>; + + panel-init-sequence = [ + 29 10 03 f0 5a 5a + /* Dsc Setting */ + /* Compression Enable */ + 07 10 01 01 + /* Scaler Disable */ + 15 10 02 c3 00 + /* PPS Setting */ + 0a 31 59 10 00 00 89 30 80 0c 30 05 a0 00 41 02 d0 02 d0 02 00 02 c2 00 20 06 58 00 0a 00 0f 01 e0 01 2d 18 00 10 f0 03 0c 20 00 06 0b 0b 33 0e 1c 2a 38 46 54 62 69 70 77 79 7b 7d 7e 01 02 01 00 09 40 09 be 19 fc 19 fa 19 f8 1a 38 1a 78 1a b6 2a b6 2a f4 2a f4 4b 34 63 74 00 + 29 10 03 f0 a5 a5 + /** Sleep Out */ + 05 00 01 11 + /* 4. Common Setting */ + /* 4.1 TE(Vync) ON/OFF */ + 15 00 02 35 00 + /* 4.2 CASET/PASET Setting */ + 39 00 05 2a 00 00 05 9F + 39 00 05 2b 00 00 0c 2f + /* 4.3 TSP SYNC Setting */ + 39 00 03 f0 5a 5a + 39 00 0a B9 01 c0 3c 0b 00 00 00 11 03 + 39 00 03 f0 a5 a5 + /* FD(Fast Discharge) Setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 45 + 15 00 02 b5 48 + 39 00 03 f0 a5 a5 + /* 4.6 FFC Setting (MIPI CLK 529MHz) */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 1E + 39 00 06 c5 09 10 b4 24 fb + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* OSC Spread Setting */ + 39 00 03 f0 5a 5a + 39 00 03 fc 5a 5a + 15 00 02 b0 37 + /* FFC Setting; 0x04 : Disable */ + 39 00 06 c5 04 ff 00 01 64 + 39 00 03 f0 a5 a5 + 39 00 03 fc a5 a5 + /* Dither IP Setting */ + 39 00 03 FC 5A 5A + 15 00 02 b0 86 + 15 00 02 eb 01 + 39 00 03 FC a5 a5 + /* 5 Brightness Control */ + /* 5.1 Dimming Setting */ + 39 10 03 f0 5a 5a + 15 10 02 b0 05 + 15 10 02 b1 01 + 15 10 02 b0 02 + 15 10 02 b5 d3 + 15 10 02 53 20 + 39 10 03 f0 a5 a5 + 39 10 03 51 02 ff + 05 32 01 29 + ]; + + panel-exit-sequence = [ + /* Display off */ + 05 14 01 28 + /* Sleep In */ + 05 00 01 10 + /* VCI stabilization setting */ + 39 00 03 f0 5a 5a + 15 00 02 b0 05 + 15 00 02 f4 01 + 39 a0 03 f0 a5 a5 + ]; + + disp_timings1: display-timings { + native-mode = <&dsi1_timing0>; + dsi1_timing0: timing0 { + clock-frequency = <280000000>; + hactive = <1140>; + vactive = <3120>; + hfront-porch = <16>; + hsync-len = <8>; + hback-porch = <8>; + vfront-porch = <4>; + vsync-len = <2>; + vback-porch = <16>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + upthreshold = <60>; + downdifferential = <30>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + cw2015@62 { + status = "okay"; + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 + <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B + 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D + 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 + 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 + 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 + 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 + 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; + cellwise,monitor-interval-ms = <5000>; + power-supplies = <&bq25895>; + }; + + bq25895: charger@6a { + compatible = "ti,bq25895", "ti,bq25890"; + reg = <0x6a>; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok>; + interrupt-parent = <&gpio3>; + interrupts = ; + otg-mode-en-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + ti,usb-charger-detection = <&usbc0>; + + ti,battery-regulation-voltage = <4400000>; /* 4.4V */ + ti,charge-current = <1600000>; /* 1.6A */ + ti,termination-current = <66000>; /* 66mA */ + ti,precharge-current = <130000>; /* 130mA */ + ti,minimum-sys-voltage = <3000000>; /* 3V */ + ti,boost-voltage = <5000000>; /* 5V */ + ti,boost-max-current = <1600000>; /* 1600mA */ + regulators { + vbus5v0_typec: vbus5v0-typec { + regulator-compatible = "otg-vbus"; + regulator-name = "vbus5v0_typec"; + }; + }; + }; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + aw87xxx_pa1: aw87xxx_pa1@58 { + compatible = "awinic,aw87xxx_pa"; + #sound-dai-cells = <0>; + reg = <0x58>; + dev_index = < 0 >; + status = "okay"; + }; + + aw87xxx_pa2: aw87xxx_pa2@59 { + compatible = "awinic,aw87xxx_pa"; + #sound-dai-cells = <0>; + reg = <0x59>; + dev_index = < 1 >; + status = "okay"; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + focaltech: focaltech@38 { + status = "okay"; + compatible = "focaltech,fts"; + reg = <0x38>; + power-supply = <&vcc3v3_lcd_n>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + focaltech,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + focaltech,reset-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + focaltech,have-key = <0>; + focaltech,key-number = <3>; + focaltech,keys = <256 1068 64 64 128 1068 64 64 192 1068 64 64>; + focaltech,key-x-coord = <1600>; + focaltech,key-y-coord = <2176>; + focaltech,max-touch-number = <5>; + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + //pinctrl-0 = <&i2c5m3_xfer>; + pinctrl-0 = <&i2c5m0_xfer>; + + ls_ucs14620: light@38 { + compatible = "ls_ucs14620"; + status = "okay"; + reg = <0x38>; + type = ; + irq_enable = <0>; + als_threshold_high = <100>; + als_threshold_low = <10>; + als_ctrl_gain = <3>;/* 0:x1 1:x4 2:x16 3:x64 */ + als_ctrl_time = <0x9f>; + poll_delay_ms = <100>; + }; + + ps_ucs14620: proximity@38 { + status = "okay"; + compatible = "ps_ucs14620"; + reg = <0x38>; + type = ; + //pinctrl-names = "default"; + //pinctrl-0 = <&gpio3_c6>; + irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; + irq_enable = <0>; + ps_threshold_high = <0x20>; + ps_threshold_low = <0x1d>; + ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ + ps_led_current = <3>; /* 0:12.5mA 1:100mA 2:150mA 3:200mA*/ + poll_delay_ms = <100>; + }; + + regulator@3e { + compatible = "tps65132"; + reg = <0x3e>; + + outp { + regulator-name = "LCD_AVDD"; //P + vin-supply = <&vcc5v0_sys>; + /*pinctrl-names = "default";*/ + /*pinctrl-0 = <&pinctrl_dsibiasen>;*/ + /*enable = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;*/ + /*enable-active-high;*/ + }; + + outn { + regulator-name = "LCD_AVEE"; + vin-supply = <&vcc5v0_sys>; + /*enable = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;*/ + }; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&u2phy0_orientation_switch>; + }; + }; + }; + + }; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + status = "okay"; + }; +}; + +&i2s0_8ch { + status = "okay"; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm0 { + status = "okay"; +}; + +&pinctrl { + charger { + charger_ok: charger_ok { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, + <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lcd { + lcd_rst_gpio: lcd-rst-gpio { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_host_en1: vcc5v0-host-en1 { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + /* + *typec5v_pwren: typec5v-pwren { + * rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + *}; + */ + }; + + wireless-bluetooth { + uart8_gpios: uart8-gpios { + rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_host_irq: bt-wake-host-irq { + rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm13 { + status = "okay"; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m1_pins>; +}; + +&rga2 { + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_dsi0 { + status = "okay"; + connect = <&vp2_out_dsi0>; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + num-cs = <1>; +}; + +&tsadc { + status = "okay"; +}; + +&uart8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; +}; + +&u2phy0 { + orientation-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + u2phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&u2phy0_otg { + rockchip,sel-pipe-phystatus; + rockchip,typec-vbus-det; + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + + maximum-speed = "high-speed"; + phys = <&u2phy0_otg>; + phy-names = "usb2-phy"; + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588s-tablet-single.dtsi b/rk3588s-tablet-single.dtsi new file mode 100644 index 0000000..1d60dca --- /dev/null +++ b/rk3588s-tablet-single.dtsi @@ -0,0 +1,1393 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-android.dtsi" +#include "rk3588-rk806-single.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm14 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <6800>; + rockchip,screen-on-voltage = <6900>; + rockchip,uboot-exit-charge-level = <2>; + rockchip,uboot-exit-charge-auto = <0>; + rockchip,system-suspend = <1>; + regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>, + <&vdd2_ddr_s3>, <&vcc_1v8_s3>, <&avcc_1v8_s0>, + <&vcc_1v8_s0>, <&vdd_0v75_s3>, <&pldo6_s3>, + <&vcc_3v3_s3>; + + regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>, + <&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>, + <&vdd_vdenc_mem_s0>, <&vcc_3v3_s0>, + <&vccio_sd_s0>, <&avdd_0v75_s0>, <&vdd_0v85_s0>, + <&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>, <&vdd_cpu_lit_s0>, + <&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>, <&vdd_cpu_lit_mem_s0>, + <&vddq_ddr_s0>, <&vdd_ddr_s0>, <&vdd_ddr_pll_s0>, + <&avdd_1v2_s0>, <&vdd_0v75_s0>; + status = "okay"; + }; + + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,es8388-codec"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio0 RK_PD3 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + panel-edp { + compatible = "innolux,p120zdg-bf4", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <500>; + disable-delay-ms = <120>; + width-mm = <254>; + height-mm = <169>; + + panel-timing { + clock-frequency = <206000000>; + hactive = <2160>; + vactive = <1440>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <10>; + vback-porch = <27>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + /* + * On the module itself this is one of these (depending + * on the actual card populated): + * - SDIO_RESET_L_WL_REG_ON + * - PDN (power down when low) + */ + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_sys>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_en>; + }; + + vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_edp"; + regulator-boot-on; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sd_s0_pwr>; + regulator-always-on; + regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3000000>; + regulator-name = "vcc_3v3_sd_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc_mipidcphy: vcc-mipidcphy-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy_pwr>; + regulator-name = "vcc_mipidcphy"; + enable-active-high; + regulator-boot-on; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart7_gpios>; + BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6398s"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&combphy0_ps { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov50c40: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov50c40_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&edp0 { + support-psr; + force-hpd; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + edp_out_panel: endpoint { + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + upthreshold = <60>; + downdifferential = <30>; + status = "okay"; +}; + +&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ + training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + >; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + + vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big0_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { + compatible = "rockchip,rk8603"; + reg = <0x43>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_cpu_big1_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + vin-supply = <&vcc5v0_sys>; + regulator-compatible = "rk860x-reg"; + regulator-name = "vdd_npu_s0"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <2300>; + rockchip,suspend-voltage-selector = <1>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&avcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + elan_touch: elan_ktf@10 { + status = "okay"; + compatible = "elan,ektf"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + elan,rst-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>; + elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + chip_type = <0x01>; /* 1:HID IIC, 0: NORMAL IIC */ + report_type = <0x01>; /* 1:B protocol, 0:A protocol */ + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m2_xfer>; + + mpu6500_acc: mpu_acc@68 { + status = "okay"; + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio1 RK_PD3 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + status = "okay"; + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&i2c6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m3_xfer>; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + cw2015@62 { + status = "okay"; + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 + <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B + 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D + 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 + 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 + 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 + 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 + 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; + cellwise,dual-cell = <1>; + cellwise,monitor-interval-ms = <5000>; + power-supplies = <&bq25703>; + }; + + bq25703: bq25703@6b { + status = "okay"; + compatible = "ti,bq25703"; + reg = <0x6b>; + ti,usb-charger-detection = <&usbc0>; + + interrupt-parent = <&gpio0>; + interrupts = ; + otg-mode-en-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok>; + extcon = <&u2phy0>; + ti,charge-current = <2500000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,max-charge-voltage = <8750000>; + ti,input-current = <500000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,minimum-sys-voltage = <7400000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <1500000>; + pd-charge-only = <0>; + regulators { + vbus5v0_typec: vbus5v0-typec { + regulator-compatible = "otg-vbus"; + regulator-name = "vbus5v0_typec"; + }; + }; + }; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + + aw8601: aw8601@c { + compatible = "awinic,aw8601"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <56>; + rockchip,vcm-rated-current = <96>; + rockchip,vcm-step-mode = <4>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13855: ov13855@10 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera4_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + avdd-supply = <&vcc_mipidcphy>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + port { + ov13855_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + ov50c40: ov50c40@36 { + compatible = "ovti,ov50c40"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + avdd-supply = <&vcc_mipidcphy>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HZGA06"; + rockchip,camera-module-lens-name = "ZE0082C1"; + eeprom-ctrl = <&otp_eeprom>; + lens-focus = <&aw8601>; + port { + ov50c40_out: endpoint { + remote-endpoint = <&mipi_in_ov50c40>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + otp_eeprom: otp_eeprom@50 { + compatible = "rk,otp_eeprom"; + status = "okay"; + reg = <0x50>; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&mpp_srv { + status = "okay"; +}; + +&pdm0 { + rockchip,path-map = <2 0 1 3>; + status = "okay"; +}; + +&pinctrl { + cam { + mipidcphy_pwr: mipidcphy-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + charger { + charger_ok: charger_ok { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sd_s0_pwr: sd-s0-pwr { + rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sensor { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mh248_irq_gpio: mh248-irq-gpio { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + vcc5v0_usb_en: vcc5v0-usb-en { + rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart7_gpios: uart7-gpios { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm14 { + pinctrl-0 = <&pwm14m1_pins>; + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp_unite { + status = "okay"; + +}; + +&rkisp_unite_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + */ + rockchip,hw = <&rkisp_unite>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp1_in2: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_edp0 { + connect = <&vp2_out_edp0>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&vcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdio { + max-frequency = <150000000>; + no-sd; + no-mmc; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + sd-uhs-sdr104; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588s-tablet-v10.dts b/rk3588s-tablet-v10.dts new file mode 100644 index 0000000..0394d8e --- /dev/null +++ b/rk3588s-tablet-v10.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-tablet.dtsi" + +/ { + model = "Rockchip RK3588S TABLET V10 Board"; + compatible = "rockchip,rk3588s-tablet-v10", "rockchip,rk3588"; +}; diff --git a/rk3588s-tablet-v11.dts b/rk3588s-tablet-v11.dts new file mode 100644 index 0000000..0cdfd47 --- /dev/null +++ b/rk3588s-tablet-v11.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +/dts-v1/; + +#include "rk3588s-tablet-single.dtsi" + +/ { + model = "Rockchip RK3588S TABLET V11 Board"; + compatible = "rockchip,rk3588s-tablet-v11", "rockchip,rk3588"; +}; diff --git a/rk3588s-tablet.dtsi b/rk3588s-tablet.dtsi new file mode 100644 index 0000000..6a971d6 --- /dev/null +++ b/rk3588s-tablet.dtsi @@ -0,0 +1,1320 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "rk3588s.dtsi" +#include "rk3588-android.dtsi" +#include "rk3588s-rk806-dual.dtsi" + +/ { + adc_keys: adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + vol-up-key { + label = "volume up"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + + vol-down-key { + label = "volume down"; + linux,code = ; + press-threshold-microvolt = <417000>; + }; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm12 0 25000 0>; + brightness-levels = < + 0 20 20 21 21 22 22 23 + 23 24 24 25 25 26 26 27 + 27 28 28 29 29 30 30 31 + 31 32 32 33 33 34 34 35 + 35 36 36 37 37 38 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + >; + default-brightness-level = <200>; + }; + + battery: battery { + compatible = "simple-battery"; + charge-full-design-microamp-hours = <4500000>; + }; + + bt_sco: bt-sco { + status = "disabled"; + compatible = "delta,dfbmcs320"; + #sound-dai-cells = <1>; + }; + + bt_sound: bt-sound { + status = "disabled"; + compatible = "simple-audio-card"; + simple-audio-card,format = "dsp_a"; + simple-audio-card,bitclock-inversion; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "rockchip,bt"; + simple-audio-card,cpu { + sound-dai = <&i2s2_2ch>; + }; + simple-audio-card,codec { + sound-dai = <&bt_sco 1>; + }; + }; + + charge-animation { + compatible = "rockchip,uboot-charge"; + rockchip,uboot-charge-on = <1>; + rockchip,android-charge-on = <0>; + rockchip,uboot-low-power-voltage = <6800>; + rockchip,screen-on-voltage = <6900>; + rockchip,uboot-exit-charge-level = <2>; + rockchip,uboot-exit-charge-auto = <0>; + rockchip,system-suspend = <1>; + regulator-on-in-mem = <&vdd_log_s0>, <&vcc_2v0_pldo_s3>, + <&vdd2_ddr_s3>, <&vcc_1v1_nldo_s3>, + <&vdd1_1v8_ddr_s3>, <&vcc_1v8_s3>, + <&master_pldo6_s3>, <&vdd_0v75_s3>, + <&vdd2l_0v9_ddr_s3>, <&vdd_1v8_pll_s0>, <&pldo6_s3>; + + regulator-off-in-mem = <&vdd_gpu_s0>, <&vdd_npu_s0>, + <&vdd_vdenc_s0>, <&vdd_gpu_mem_s0>, <&vdd_npu_mem_s0>, + <&vdd_vdenc_mem_s0>, <&avcc_1v8_s0>, <&vcc_3v3_s0>, + <&vccio_sd_s0>, <&master_nldo3>, <&avdd_0v75_s0>, + <&vdd_0v85_s0>, <&vdd_cpu_big1_s0>, <&vdd_cpu_big0_s0>, + <&vdd_cpu_lit_s0>, <&vdd_cpu_big1_mem_s0>, <&vdd_cpu_big0_mem_s0>, + <&vcc_1v8_s0>, <&vdd_cpu_lit_mem_s0>, <&vddq_ddr_s0>, + <&vdd_ddr_s0>, <&vcc_1v8_cam_s0>, <&avdd1v8_ddr_pll_s0>, + <&vcc_3v3_sd_s0>, <&vcc_2v8_cam_s0>, <&vdd_0v75_pll_s0>, + <&vdd_ddr_pll_s0>, <&slave_nldo3>, <&avdd_1v2_cam_s0>, + <&avdd_1v2_s0>, <&vcc_3v3_s3>; + status = "okay"; + }; + + dp0_sound: dp0-sound { + status = "okay"; + compatible = "rockchip,hdmi"; + rockchip,card-name= "rockchip-dp0"; + rockchip,mclk-fs = <512>; + rockchip,cpu = <&spdif_tx2>; + rockchip,codec = <&dp0 1>; + rockchip,jack-det; + }; + + es7202_sound_micarray: es7202-sound-micarray { + status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "rockchip,sound-micarray"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,dai-link@0 { + format = "pdm"; + cpu { + sound-dai = <&pdm0>; + }; + codec { + sound-dai = <&es7202>; + }; + }; + }; + + es8388_sound: es8388-sound { + status = "okay"; + compatible = "rockchip,multicodecs-card"; + rockchip,card-name = "rockchip,es8388-codec"; + hp-det-gpio = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + io-channels = <&saradc 3>; + io-channel-names = "adc-detect"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + spk-con-gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; + hp-con-gpio = <&gpio4 RK_PA4 GPIO_ACTIVE_HIGH>; + rockchip,format = "i2s"; + rockchip,mclk-fs = <256>; + rockchip,cpu = <&i2s0_8ch>; + rockchip,codec = <&es8388>; + rockchip,audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2", + "Headphone", "Headphone Power", + "Headphone", "Headphone Power", + "Speaker", "Speaker Power", + "Speaker", "Speaker Power", + "LINPUT1", "Main Mic", + "LINPUT2", "Main Mic", + "RINPUT1", "Headset Mic", + "RINPUT2", "Headset Mic"; + pinctrl-names = "default"; + pinctrl-0 = <&hp_det>; + play-pause-key { + label = "playpause"; + linux,code = ; + press-threshold-microvolt = <2000>; + }; + }; + + hall_sensor: hall-mh248 { + compatible = "hall-mh248"; + pinctrl-names = "default"; + pinctrl-0 = <&mh248_irq_gpio>; + irq-gpio = <&gpio1 RK_PA1 IRQ_TYPE_EDGE_BOTH>; + hall-active = <1>; + status = "okay"; + }; + + panel-edp { + compatible = "innolux,p120zdg-bf4", "simple-panel"; + backlight = <&backlight>; + power-supply = <&vcc3v3_lcd_edp>; + prepare-delay-ms = <120>; + enable-delay-ms = <120>; + unprepare-delay-ms = <500>; + disable-delay-ms = <120>; + width-mm = <254>; + height-mm = <169>; + + panel-timing { + clock-frequency = <206000000>; + hactive = <2160>; + vactive = <1440>; + hfront-porch = <48>; + hsync-len = <32>; + hback-porch = <80>; + vfront-porch = <3>; + vsync-len = <10>; + vback-porch = <27>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_in_edp: endpoint { + remote-endpoint = <&edp0_out>; + }; + }; + }; + + vcc3v3_lcd_edp: vcc3v3-lcd-edp { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_lcd_edp"; + regulator-boot-on; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc5v0_host: vcc5v0-host { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; + vin-supply = <&vcc5v0_usb>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_mipidcphy1: vcc-mipidcphy1-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidcphy1_pwr>; + regulator-name = "vcc_mipidcphy1"; + enable-active-high; + regulator-always-on; + regulator-boot-on; + }; + + wireless_bluetooth: wireless-bluetooth { + compatible = "bluetooth-platdata"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + uart_rts_gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "rts_gpio"; + pinctrl-0 = <&uart7m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; + pinctrl-1 = <&uart7_gpios>; + BT,reset_gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; + BT,wake_gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; + BT,wake_host_irq = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + wireless_wlan: wireless-wlan { + compatible = "wlan-platdata"; + wifi_chip_type = "ap6275p"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; + WIFI,host_wake_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + WIFI,poweren_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; +}; + +&av1d_mmu { + status = "okay"; +}; + +&avdd_1v2_cam_s0 { + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <12500>; +}; + +&combphy0_ps { + status = "okay"; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; + mem-supply = <&vdd_cpu_lit_mem_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; + mem-supply = <&vdd_cpu_big0_mem_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; + mem-supply = <&vdd_cpu_big1_mem_s0>; +}; + +&dp0 { + status = "okay"; +}; + +&dp0_out { + link-frequencies = /bits/ 64 <5400000000>; +}; + +&dp0_in_vp1 { + status = "okay"; +}; + +&edp0 { + support-psr; + force-hpd; + status = "okay"; +}; + +&edp0_in_vp2 { + status = "okay"; +}; + +&edp0_out { + remote-endpoint = <&panel_in_edp>; +}; + +&fiq_debugger { + pinctrl-0 = <&uart2m1_xfer>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + mem-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdptxphy0 { + /* Single Vdiff Training Table for power reduction (optional) */ + training-table = /bits/ 8 < + /* voltage swing 0, pre-emphasis 0->3 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 1, pre-emphasis 0->2 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 2, pre-emphasis 0->1 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + 0x0d 0x00 0x00 0x00 0x00 0x00 + /* voltage swing 3, pre-emphasis 0 */ + 0x0d 0x00 0x00 0x00 0x00 0x00 + >; + status = "okay"; +}; + +&i2c2 { + status = "okay"; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; + + cw2015@62 { + status = "okay"; + compatible = "cellwise,cw2015"; + reg = <0x62>; + cellwise,battery-profile = /bits/ 8 + <0x17 0x67 0x6C 0x66 0x65 0x64 0x61 0x5B + 0x5F 0x75 0x49 0x52 0x50 0x51 0x48 0x3D + 0x34 0x2C 0x29 0x21 0x23 0x2D 0x40 0x49 + 0x25 0x5C 0x0B 0x85 0x10 0x1F 0x31 0x49 + 0x58 0x5E 0x63 0x6C 0x3E 0x1D 0x9A 0x35 + 0x0A 0x33 0x15 0x3B 0x70 0x99 0xAB 0x17 + 0x40 0x75 0x99 0xC4 0x80 0xB5 0xDE 0xCB + 0x2F 0x00 0x64 0xA5 0xB5 0x00 0xF8 0x39>; + cellwise,dual-cell = <1>; + cellwise,monitor-interval-ms = <5000>; + monitored-battery = <&battery>; + power-supplies = <&bq25703>; + }; + + bq25703: bq25703@6b { + status = "okay"; + compatible = "ti,bq25703"; + reg = <0x6b>; + ti,usb-charger-detection = <&usbc0>; + + interrupt-parent = <&gpio0>; + interrupts = ; + otg-mode-en-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&charger_ok>; + extcon = <&u2phy0>; + ti,charge-current = <2500000>; + ti,max-input-voltage = <20000000>; + ti,max-input-current = <6000000>; + ti,max-charge-voltage = <8750000>; + ti,input-current = <500000>; + ti,input-current-sdp = <500000>; + ti,input-current-dcp = <2000000>; + ti,input-current-cdp = <2000000>; + ti,minimum-sys-voltage = <7400000>; + ti,otg-voltage = <5000000>; + ti,otg-current = <1500000>; + pd-charge-only = <0>; + regulators { + vbus5v0_typec: vbus5v0-typec { + regulator-compatible = "otg-vbus"; + regulator-name = "vbus5v0_typec"; + }; + }; + }; +}; + +&i2c3 { + status = "okay"; + + es8388: es8388@11 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "everest,es8388", "everest,es8323"; + reg = <0x11>; + clocks = <&mclkout_i2s0>; + clock-names = "mclk"; + assigned-clocks = <&mclkout_i2s0>; + assigned-clock-rates = <12288000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_mclk>; + }; + + es7202: es7202@32 { + status = "okay"; + #sound-dai-cells = <0>; + compatible = "ES7202_PDM_ADC_1"; + power-supply = <&vcc_1v8_s0>; /* only 1v8 or 3v3, default is 3v3 */ + reg = <0x32>; + }; +}; + +&i2c4 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m3_xfer>; + + elan_touch: elan_ktf@10 { + status = "okay"; + compatible = "elan,ektf"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_gpio>; + elan,rst-gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + elan,irq-gpio = <&gpio1 RK_PB5 IRQ_TYPE_LEVEL_LOW>; + chip_type = <0x01>; /* 1:HID IIC, 0: NORMAL IIC */ + report_type = <0x01>; /* 1:B protocol, 0:A protocol */ + }; +}; + +&i2c5 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + + mpu6500_acc: mpu_acc@68 { + status = "okay"; + compatible = "mpu6500_acc"; + reg = <0x68>; + irq-gpio = <&gpio3 RK_PB4 IRQ_TYPE_EDGE_RISING>; + irq_enable = <0>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; + + mpu6500_gyro: mpu_gyro@68 { + status = "okay"; + compatible = "mpu6500_gyro"; + reg = <0x68>; + poll_delay_ms = <30>; + type = ; + layout = <5>; + }; +}; + +&i2c6 { + status = "disabled"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m2_xfer>; + + aw8601: aw8601@c { + compatible = "awinic,aw8601"; + status = "okay"; + reg = <0x0c>; + rockchip,vcm-start-current = <56>; + rockchip,vcm-rated-current = <96>; + rockchip,vcm-step-mode = <4>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + }; + + ov13855: ov13855@10 { + compatible = "ovti,ov13855"; + status = "okay"; + reg = <0x10>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera2_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; + rockchip,camera-module-index = <1>; + rockchip,camera-module-facing = "front"; + rockchip,camera-module-name = "CMK-OT2016-FV1"; + rockchip,camera-module-lens-name = "default"; + port { + ov13855_out: endpoint { + remote-endpoint = <&mipi_in_ucam1>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + ov50c40: ov50c40@36 { + compatible = "ovti,ov50c40"; + status = "okay"; + reg = <0x36>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + power-domains = <&power RK3588_PD_VI>; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + rockchip,grf = <&sys_grf>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + pwdn-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "HZGA06"; + rockchip,camera-module-lens-name = "ZE0082C1"; + eeprom-ctrl = <&otp_eeprom>; + lens-focus = <&aw8601>; + port { + ov50c40_out: endpoint { + remote-endpoint = <&mipi_in_ov50c40>; + data-lanes = <1 2 3 4>; + }; + }; + }; + + otp_eeprom: otp_eeprom@50 { + compatible = "rk,otp_eeprom"; + status = "okay"; + reg = <0x50>; + }; +}; + +&csi2_dcphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ov50c40: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov50c40_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi0_csi2_input>; + }; + }; + }; +}; + +&csi2_dcphy1 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi_in_ucam1: endpoint@1 { + reg = <1>; + remote-endpoint = <&ov13855_out>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidcphy1_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi1_csi2_input>; + }; + }; + }; +}; + +&mipi_dcphy0 { + status = "okay"; +}; + +&mipi_dcphy1 { + status = "okay"; +}; + +&mipi0_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi0_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in0>; + }; + }; + }; +}; + +&mipi1_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidcphy1_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi1_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi_in1>; + }; + }; + }; +}; + +&i2c8 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m2_xfer>; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio0>; + interrupts = ; + int-n-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + vbus-supply = <&vbus5v0_typec>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_role_sw: endpoint@0 { + remote-endpoint = <&dwc3_0_role_switch>; + }; + }; + }; + + usb_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + source-pdos = + ; + + altmodes { + #address-cells = <1>; + #size-cells = <0>; + + altmode@0 { + reg = <0>; + svid = <0xff01>; + vdo = <0xffffffff>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdp_phy0_orientation_switch>; + }; + }; + + port@1 { + reg = <1>; + dp_altmode_mux: endpoint { + remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; + }; + }; + }; + }; + }; +}; + +&i2s0_8ch { + status = "okay"; + rockchip,clk-trcm = <1>; + pinctrl-0 = <&i2s0_lrck + &i2s0_sclk + &i2s0_sdi0 + &i2s0_sdo0>; +}; + +&i2s2_2ch { + pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>; + rockchip,bclk-fs = <32>; + status = "disabled"; +}; + +&iep { + status = "okay"; +}; + +&iep_mmu { + status = "okay"; +}; + +&jpegd { + status = "okay"; +}; + +&jpegd_mmu { + status = "okay"; +}; + +&jpege_ccu { + status = "okay"; +}; + +&jpege0 { + status = "okay"; +}; + +&jpege0_mmu { + status = "okay"; +}; + +&jpege1 { + status = "okay"; +}; + +&jpege1_mmu { + status = "okay"; +}; + +&jpege2 { + status = "okay"; +}; + +&jpege2_mmu { + status = "okay"; +}; + +&jpege3 { + status = "okay"; +}; + +&jpege3_mmu { + status = "okay"; +}; + +&mpp_srv { + status = "okay"; +}; + +&pcie2x1l2 { + reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; + rockchip,skip-scan-in-resume; + status = "okay"; +}; + +&pdm0 { + rockchip,path-map = <2 0 1 3>; + status = "okay"; +}; + +&pinctrl { + cam { + mipidcphy1_pwr: mipidcphy1-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + charger { + charger_ok: charger_ok { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + headphone { + hp_det: hp-det { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sensor { + mpu6500_irq_gpio: mpu6500-irq-gpio { + rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + mh248_irq_gpio: mh248-irq-gpio { + rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + touch { + touch_gpio: touch-gpio { + rockchip,pins = + <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_host_en: vcc5v0-host-en { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-typec { + usbc0_int: usbc0-int { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wireless-bluetooth { + uart7_gpios: uart7-gpios { + rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_reset_gpio: bt-reset-gpio { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_wake_gpio: bt-wake-gpio { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_irq_gpio: bt-irq-gpio { + rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; + + wireless-wlan { + wifi_host_wake_irq: wifi-host-wake-irq { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + wifi_poweren_gpio: wifi-poweren-gpio { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&pwm12 { + pinctrl-0 = <&pwm12m1_pins>; + status = "okay"; +}; + +&rga3_core0 { + status = "okay"; +}; + +&rga3_0_mmu { + status = "okay"; +}; + +&rga3_core1 { + status = "okay"; +}; + +&rga3_1_mmu { + status = "okay"; +}; + +&rga2 { + status = "okay"; +}; + +&rkcif { + status = "okay"; +}; + +&rkcif_mipi_lvds { + status = "okay"; + + port { + cif_mipi_in0: endpoint { + remote-endpoint = <&mipi0_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds_sditf { + status = "okay"; + + port { + mipi_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in1>; + }; + }; +}; + +&rkcif_mipi_lvds1 { + status = "okay"; + + port { + cif_mipi_in1: endpoint { + remote-endpoint = <&mipi1_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds1_sditf { + status = "okay"; + + port { + mipi1_lvds_sditf: endpoint { + remote-endpoint = <&isp1_in2>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp_unite { + status = "okay"; + +}; + +&rkisp_unite_mmu { + status = "okay"; +}; + +&rkisp0_vir0 { + status = "okay"; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + */ + rockchip,hw = <&rkisp_unite>; + port { + #address-cells = <1>; + #size-cells = <0>; + + isp1_in1: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_sditf>; + }; + isp1_in2: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi1_lvds_sditf>; + }; + }; +}; + +&rknpu { + rknpu-supply = <&vdd_npu_s0>; + mem-supply = <&vdd_npu_mem_s0>; + status = "okay"; +}; + +&rknpu_mmu { + status = "okay"; +}; + +&rkvdec_ccu { + status = "okay"; +}; + +&rkvdec0 { + status = "okay"; +}; + +&rkvdec0_mmu { + status = "okay"; +}; + +&rkvdec1 { + status = "okay"; +}; + +&rkvdec1_mmu { + status = "okay"; +}; + +&rkvenc_ccu { + status = "okay"; +}; + +&rkvenc0 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc0_mmu { + status = "okay"; +}; + +&rkvenc1 { + venc-supply = <&vdd_vdenc_s0>; + mem-supply = <&vdd_vdenc_mem_s0>; + status = "okay"; +}; + +&rkvenc1_mmu { + status = "okay"; +}; + +&rockchip_suspend { + status = "okay"; + rockchip,sleep-debug-en = <1>; +}; + +&route_edp0 { + connect = <&vp2_out_edp0>; + status = "okay"; +}; + +&saradc { + status = "okay"; + vref-supply = <&avcc_1v8_s0>; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&sdmmc { + max-frequency = <150000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_sd_s0>; + vqmmc-supply = <&vccio_sd_s0>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>; + status = "okay"; +}; + +&spdif_tx2 { + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer &uart7m1_ctsn>; + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy0_otg { + rockchip,typec-vbus-det; + status = "okay"; +}; + +&u2phy2_host { + status = "okay"; + phy-supply = <&vcc5v0_host>; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usbdp_phy0 { + orientation-switch; + svid = <0xff01>; + sbu1-dc-gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_HIGH>; + sbu2-dc-gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + usbdp_phy0_orientation_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_orien_sw>; + }; + + usbdp_phy0_dp_altmode_mux: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_altmode_mux>; + }; + }; +}; + +&usbdp_phy0_dp { + status = "okay"; +}; + +&usbdp_phy0_u3 { + status = "okay"; +}; + +&usbdrd3_0 { + status = "okay"; +}; + +&usbdrd_dwc3_0 { + dr_mode = "otg"; + status = "okay"; + + usb-role-switch; + port { + #address-cells = <1>; + #size-cells = <0>; + dwc3_0_role_switch: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbhost3_0 { + status = "disabled"; +}; + +&usbhost_dwc3_0 { + status = "disabled"; +}; + +&vdpu { + status = "okay"; +}; + +&vdpu_mmu { + status = "okay"; +}; + +&vepu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0 | + 1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; + rockchip,primary-plane = ; +}; + +&vp2 { + rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2 | + 1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; + rockchip,primary-plane = ; +}; diff --git a/rk3588s.dtsi b/rk3588s.dtsi new file mode 100644 index 0000000..2948a03 --- /dev/null +++ b/rk3588s.dtsi @@ -0,0 +1,6887 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3588"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + csi2dcphy0 = &csi2_dcphy0; + csi2dcphy1 = &csi2_dcphy1; + csi2dphy0 = &csi2_dphy0; + csi2dphy1 = &csi2_dphy1; + csi2dphy2 = &csi2_dphy2; + csi2dphy3 = &csi2_dphy3; + csi2dphy4 = &csi2_dphy4; + csi2dphy5 = &csi2_dphy5; + dsi0 = &dsi0; + dsi1 = &dsi1; + ethernet1 = &gmac1; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + rkcif_mipi_lvds0= &rkcif_mipi_lvds; + rkcif_mipi_lvds1= &rkcif_mipi_lvds1; + rkcif_mipi_lvds2= &rkcif_mipi_lvds2; + rkcif_mipi_lvds3= &rkcif_mipi_lvds3; + rkvdec0 = &rkvdec0; + rkvdec1 = &rkvdec1; + rkvenc0 = &rkvenc0; + rkvenc1 = &rkvenc1; + jpege0 = &jpege0; + jpege1 = &jpege1; + jpege2 = &jpege2; + jpege3 = &jpege3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &sfc; + hdcp0 = &hdcp0; + hdcp1 = &hdcp1; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + spll: spll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <702000000>; + clock-output-names = "spll"; + }; + + xin32k: xin32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + }; + + hclk_vo1: hclk_vo1@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08ec 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08b0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_vo0: hclk_vo0@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08dc 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_usb: hclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a8 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_nvm: hclk_nvm@fd7c087c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c087c 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_NVM_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_usb: aclk_usb@fd7c08a8 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a8 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_isp1_pre: hclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0868 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VI_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_isp1_pre: aclk_isp1_pre@fd7c0868 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0868 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VI_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a0 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a4 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08a4 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08b0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08c0 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_RKVENC0>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08c0 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_RKVENC0>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08dc 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VOP_LOW_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c08ec 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VO1USB_TOP_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + pclk_av1_pre: pclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0910 0 0x10>; + clock-names = "link"; + clocks = <&cru HCLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + aclk_av1_pre: aclk_av1_pre@fd7c0910 { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c0910 0 0x10>; + clock-names = "link"; + clocks = <&cru ACLK_VDPU_ROOT>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + hclk_sdio_pre: hclk_sdio_pre@fd7c092c { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0 0xfd7c092c 0 0x10>; + clock-names = "link"; + clocks = <&hclk_nvm>; + #power-domain-cells = <1>; + #clock-cells = <0>; + }; + + pclk_vo0_grf: pclk_vo0_grf@fd7c08dc { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08dc 0x0 0x4>; + clocks = <&hclk_vo0>; + clock-names = "link"; + #clock-cells = <0>; + }; + + pclk_vo1_grf: pclk_vo1_grf@fd7c08ec { + compatible = "rockchip,rk3588-clock-gate-link"; + reg = <0x0 0xfd7c08ec 0x0 0x4>; + clocks = <&hclk_vo1>; + clock-names = "link"; + #clock-cells = <0>; + }; + + mclkin_i2s0: mclkin-i2s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s0_mclkin"; + }; + + mclkin_i2s1: mclkin-i2s1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s1_mclkin"; + }; + + mclkin_i2s2: mclkin-i2s2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s2_mclkin"; + }; + + mclkin_i2s3: mclkin-i2s3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "i2s3_mclkin"; + }; + + mclkout_i2s0: mclkout-i2s0@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <22288000>; + #clock-cells = <0>; + clock-output-names = "i2s0_mclkout_to_io"; + rockchip,bit-shift = <0>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; /* for OLD SDK */ + }; + + mclkout_i2s1: mclkout-i2s1@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s1_mclkout_to_io"; + rockchip,bit-shift = <1>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; /* for OLD SDK */ + }; + + mclkout_i2s1m1: mclkout-i2s1@fd58a000 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58a000 0 0x4>; + clocks = <&cru I2S1_8CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s1m1_mclkout_to_io"; + rockchip,bit-shift = <6>; + rockchip,clk-ignore-unused; /* for OLD SDK */ + }; + + mclkout_i2s2: mclkout-i2s2@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S2_2CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s2_mclkout_to_io"; + rockchip,bit-shift = <2>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; /* for OLD SDK */ + }; + + mclkout_i2s3: mclkout-i2s3@fd58c318 { + compatible = "rockchip,clk-out"; + reg = <0 0xfd58c318 0 0x4>; + clocks = <&cru I2S3_2CH_MCLKOUT>; + #clock-cells = <0>; + clock-output-names = "i2s3_mclkout_to_io"; + rockchip,bit-shift = <7>; + rockchip,bit-set-to-disable; + rockchip,clk-ignore-unused; /* for OLD SDK */ + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu_b2>; + }; + core1 { + cpu = <&cpu_b3>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <100>; + }; + + cpu_l1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l1>; + }; + + cpu_l2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l2>; + }; + + cpu_l3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <530>; + clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <32768>; + i-cache-line-size = <64>; + i-cache-sets = <128>; + d-cache-size = <32768>; + d-cache-line-size = <64>; + d-cache-sets = <128>; + next-level-cache = <&l2_cache_l3>; + }; + + cpu_b0: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b0>; + #cooling-cells = <2>; + dynamic-power-coefficient = <300>; + }; + + cpu_b1: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 = <&cluster1_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b1>; + }; + + cpu_b2: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b2>; + #cooling-cells = <2>; + dynamic-power-coefficient = <300>; + }; + + cpu_b3: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a76"; + reg = <0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + clocks = <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 = <&cluster2_opp_table>; + cpu-idle-states = <&CPU_SLEEP>; + i-cache-size = <65536>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <65536>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_b3>; + }; + + idle-states { + entry-method = "psci"; + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + local-timer-stop; + arm,psci-suspend-param = <0x0010000>; + entry-latency-us = <100>; + exit-latency-us = <120>; + min-residency-us = <1000>; + }; + }; + + l2_cache_l0: l2-cache-l0 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l1: l2-cache-l1 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l2: l2-cache-l2 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_l3: l2-cache-l3 { + compatible = "cache"; + cache-size = <131072>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b0: l2-cache-b0 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b1: l2-cache-b1 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b2: l2-cache-b2 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l2_cache_b3: l2-cache-b3 { + compatible = "cache"; + cache-size = <524288>; + cache-line-size = <64>; + cache-sets = <1024>; + next-level-cache = <&l3_cache>; + }; + + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + }; + }; + + cluster0_opp_table: cluster0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + rockchip,opp-shared-dsu; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1365 0 + 1366 1387 1 + 1388 1409 2 + 1410 1431 3 + 1432 1453 4 + 1454 1475 5 + 1476 9999 6 + >; + rockchip,pvtm-voltage-sel = < + 0 1410 0 + 1411 1434 1 + 1435 1458 2 + 1459 1482 3 + 1483 1506 4 + 1507 1530 5 + 1531 9999 6 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x64>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1416000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <244 244>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + + rockchip,grf = <&litcore_grf>; + rockchip,dsu-grf = <&dsu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <1008000>; /* KHz */ + rockchip,reboot-freq = <1416000>; /* KHz */ + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <1608000>; + + /* RK3588 cluster0 OPPs */ + opp-408000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L1 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L2 = <700000 700000 950000>, + <700000 700000 950000>; + opp-microvolt-L3 = <687500 687500 950000>, + <687500 687500 950000>; + opp-microvolt-L4 = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L5 = <675000 675000 950000>, + <675000 675000 950000>; + opp-microvolt-L6 = <675000 675000 950000>, + <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L1 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L2 = <737500 737500 950000>, + <737500 737500 950000>; + opp-microvolt-L3 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L4 = <725000 725000 950000>, + <725000 725000 950000>; + opp-microvolt-L5 = <712500 712500 950000>, + <712500 712500 950000>; + opp-microvolt-L6 = <712500 712500 950000>, + <712500 712500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L1 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L2 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L3 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L4 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L5 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L6 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L2 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L3 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L4 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L5 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L6 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + + /* RK3588J/M cluster0 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-1296000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L1 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L1 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L2 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L1 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L2 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L3 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L4 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L5 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L6 = <812500 812500 950000>, + <812500 812500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1704000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1704000000>; + opp-microvolt = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L1 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L2 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L3 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L4 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L5 = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L6 = <862500 862500 950000>, + <862500 862500 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: cluster1-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1539 0 + 1540 1564 1 + 1565 1589 2 + 1590 1614 3 + 1615 1644 4 + 1645 1674 5 + 1675 1704 6 + 1705 9999 7 + >; + rockchip,pvtm-voltage-sel = < + 0 1595 0 + 1596 1615 1 + 1616 1640 2 + 1641 1675 3 + 1676 1710 4 + 1711 1743 5 + 1744 1776 6 + 1777 9999 7 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <270 270>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <3>; + + rockchip,grf = <&bigcore0_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <1008000>; /* KHz */ + rockchip,idle-threshold-freq = <2208000>; /* KHz */ + rockchip,reboot-freq = <1800000>; /* KHz */ + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <2208000>; + + /* RK3588 cluster1 OPPs */ + opp-408000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L2 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L3 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L4 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L5 = <687500 687500 1000000>, + <687500 687500 1000000>; + opp-microvolt-L6 = <675000 675000 1000000>, + <675000 675000 1000000>; + opp-microvolt-L7 = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L2 = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L3 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L4 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L5 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L6 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L7 = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L1 = <837500 837500 1000000>, + <837500 837500 1000000>; + opp-microvolt-L2 = <825000 825000 1000000>, + <825000 825000 1000000>; + opp-microvolt-L3 = <812500 812500 1000000>, + <812500 812500 1000000>; + opp-microvolt-L4 = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L5 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L6 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L7 = <762500 762500 1000000>, + <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L1 = <912500 912500 1000000>, + <912500 912500 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>, + <900000 900000 1000000>; + opp-microvolt-L3 = <887500 887500 1000000>, + <887500 887500 1000000>; + opp-microvolt-L4 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L5 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L6 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L7 = <837500 837500 1000000>, + <837500 837500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>, + <987500 987500 1000000>; + opp-microvolt-L1 = <975000 975000 1000000>, + <975000 975000 1000000>; + opp-microvolt-L2 = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L3 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L4 = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L5 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L6 = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L7 = <912500 912500 1000000>, + <912500 912500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + + /* RK3588J/M cluster1 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L6 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L7 = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L1 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L2 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L3 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L4 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L5 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L6 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L7 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: cluster2-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 1539 0 + 1540 1564 1 + 1565 1589 2 + 1590 1614 3 + 1615 1644 4 + 1645 1674 5 + 1675 1704 6 + 1705 9999 7 + >; + rockchip,pvtm-voltage-sel = < + 0 1595 0 + 1596 1615 1 + 1616 1640 2 + 1641 1675 3 + 1676 1710 4 + 1711 1743 5 + 1744 1776 6 + 1777 9999 7 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x18>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <1608000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <270 270>; + rockchip,pvtm-thermal-zone = "soc-thermal"; + rockchip,pvtm-low-len-sel = <3>; + + rockchip,grf = <&bigcore1_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <1008000>; /* KHz */ + rockchip,idle-threshold-freq = <2208000>; /* KHz */ + rockchip,reboot-freq = <1800000>; /* KHz */ + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <2208000>; + + /* RK3588 cluster2 OPPs */ + opp-408000000 { + opp-supported-hw = <0xf9 0x0ffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L2 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L3 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L4 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L5 = <687500 687500 1000000>, + <687500 687500 1000000>; + opp-microvolt-L6 = <675000 675000 1000000>, + <675000 675000 1000000>; + opp-microvolt-L7 = <675000 675000 1000000>, + <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>, + <762500 762500 1000000>; + opp-microvolt-L2 = <750000 750000 1000000>, + <750000 750000 1000000>; + opp-microvolt-L3 = <737500 737500 1000000>, + <737500 737500 1000000>; + opp-microvolt-L4 = <725000 725000 1000000>, + <725000 725000 1000000>; + opp-microvolt-L5 = <712500 712500 1000000>, + <712500 712500 1000000>; + opp-microvolt-L6 = <700000 700000 1000000>, + <700000 700000 1000000>; + opp-microvolt-L7 = <700000 700000 1000000>, + <700000 700000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L1 = <837500 837500 1000000>, + <837500 837500 1000000>; + opp-microvolt-L2 = <825000 825000 1000000>, + <825000 825000 1000000>; + opp-microvolt-L3 = <812500 812500 1000000>, + <812500 812500 1000000>; + opp-microvolt-L4 = <800000 800000 1000000>, + <800000 800000 1000000>; + opp-microvolt-L5 = <787500 787500 1000000>, + <787500 787500 1000000>; + opp-microvolt-L6 = <775000 775000 1000000>, + <775000 775000 1000000>; + opp-microvolt-L7 = <762500 762500 1000000>, + <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L1 = <912500 912500 1000000>, + <912500 912500 1000000>; + opp-microvolt-L2 = <900000 900000 1000000>, + <900000 900000 1000000>; + opp-microvolt-L3 = <887500 887500 1000000>, + <887500 887500 1000000>; + opp-microvolt-L4 = <875000 875000 1000000>, + <875000 875000 1000000>; + opp-microvolt-L5 = <862500 862500 1000000>, + <862500 862500 1000000>; + opp-microvolt-L6 = <850000 850000 1000000>, + <850000 850000 1000000>; + opp-microvolt-L7 = <837500 837500 1000000>, + <837500 837500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>, + <987500 987500 1000000>; + opp-microvolt-L3 = <975000 975000 1000000>, + <975000 975000 1000000>; + opp-microvolt-L4 = <962500 962500 1000000>, + <962500 962500 1000000>; + opp-microvolt-L5 = <950000 950000 1000000>, + <950000 950000 1000000>; + opp-microvolt-L6 = <925000 925000 1000000>, + <925000 925000 1000000>; + opp-microvolt-L7 = <912500 912500 1000000>, + <912500 912500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-supported-hw = <0xf9 0x13>; + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-supported-hw = <0xf9 0x24>; + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-supported-hw = <0xf9 0x48>; + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-supported-hw = <0xf9 0x80>; + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>, + <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + + /* RK3588J/M cluster2 OPPs */ + opp-j-m-408000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-816000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1008000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1200000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1416000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L0 = <762500 762500 950000>, + <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-j-m-1608000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <787500 787500 950000>, + <787500 787500 950000>; + opp-microvolt-L2 = <775000 775000 950000>, + <775000 775000 950000>; + opp-microvolt-L3 = <762500 762500 950000>, + <762500 762500 950000>; + opp-microvolt-L4 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L5 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L6 = <750000 750000 950000>, + <750000 750000 950000>; + opp-microvolt-L7 = <750000 750000 950000>, + <750000 750000 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-1800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <875000 875000 950000>, + <875000 875000 950000>; + opp-microvolt-L1 = <862500 862500 950000>, + <862500 862500 950000>; + opp-microvolt-L2 = <850000 850000 950000>, + <850000 850000 950000>; + opp-microvolt-L3 = <837500 837500 950000>, + <837500 837500 950000>; + opp-microvolt-L4 = <825000 825000 950000>, + <825000 825000 950000>; + opp-microvolt-L5 = <812500 812500 950000>, + <812500 812500 950000>; + opp-microvolt-L6 = <800000 800000 950000>, + <800000 800000 950000>; + opp-microvolt-L7 = <787500 787500 950000>, + <787500 787500 950000>; + clock-latency-ns = <40000>; + }; + opp-j-m-2016000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L1 = <950000 950000 950000>, + <950000 950000 950000>; + opp-microvolt-L2 = <937500 937500 950000>, + <937500 937500 950000>; + opp-microvolt-L3 = <925000 925000 950000>, + <925000 925000 950000>; + opp-microvolt-L4 = <912500 912500 950000>, + <912500 912500 950000>; + opp-microvolt-L5 = <900000 900000 950000>, + <900000 900000 950000>; + opp-microvolt-L6 = <887500 887500 950000>, + <887500 887500 950000>; + opp-microvolt-L7 = <875000 875000 950000>, + <875000 875000 950000>; + clock-latency-ns = <40000>; + }; + }; + + arm_pmu: arm-pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, + <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; + }; + + cpuinfo { + compatible = "rockchip,cpuinfo"; + nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; + nvmem-cell-names = "id", "cpu-version", "cpu-code"; + }; + + csi2_dcphy0: csi2-dcphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dcphy1: csi2-dcphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy0: csi2-dphy0 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy1: csi2-dphy1 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy2: csi2-dphy2 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy3: csi2-dphy3 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy4: csi2-dphy4 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + csi2_dphy5: csi2-dphy5 { + compatible = "rockchip,rk3588-csi2-dphy"; + rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; + phys = <&mipidcphy0>, <&mipidcphy1>; + phy-names = "dcphy0", "dcphy1"; + status = "disabled"; + }; + + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + + route { + route_dp0: route-dp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp1_out_dp0>; + }; + + route_dsi0: route-dsi0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp3_out_dsi0>; + }; + + route_dsi1: route-dsi1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp3_out_dsi1>; + }; + + route_edp0: route-edp0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp2_out_edp0>; + }; + + route_edp1: route-edp1 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + }; + + route_hdmi0: route-hdmi0 { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp0_out_hdmi0>; + }; + + route_rgb: route-rgb { + status = "disabled"; + logo,uboot = "logo.bmp"; + logo,kernel = "logo_kernel.bmp"; + logo,mode = "center"; + charge_logo,mode = "center"; + connect = <&vp3_out_rgb>; + }; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3588-dmc"; + interrupts = ; + interrupt-names = "complete"; + devfreq-events = <&dfi>; + clocks = <&scmi_clk 4>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + upthreshold = <40>; + downdifferential = <20>; + system-status-level = < + /*system status freq level*/ + SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH + SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW + SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH + SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH + SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH + SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH + SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH + SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH + SYS_STATUS_DEEP_SUSPEND DMC_FREQ_LEVEL_HIGH + >; + auto-freq-en = <1>; + status = "disabled"; + }; + + dmc_opp_table: dmc-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,leakage-voltage-sel = < + 1 31 0 + 32 44 1 + 45 57 2 + 58 254 3 + >; + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + + /* RK3588 dmc OPPs */ + opp-528000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <675000 675000 875000>, + <725000 725000 750000>; + opp-microvolt-L1 = <675000 675000 875000>, + <700000 700000 750000>; + opp-microvolt-L2 = <675000 675000 875000>, + <687500 687500 750000>; + opp-microvolt-L3 = <675000 675000 875000>, + <675000 675000 750000>; + }; + opp-1068000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <725000 725000 875000>, + <737500 737500 750000>; + opp-microvolt-L1 = <700000 700000 875000>, + <712500 712500 750000>; + opp-microvolt-L2 = <675000 675000 875000>, + <700000 700000 750000>; + opp-microvolt-L3 = <675000 675000 875000>, + <687500 687500 750000>; + }; + opp-1560000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <800000 800000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <775000 775000 875000>, + <725000 725000 750000>; + opp-microvolt-L2 = <750000 750000 875000>, + <712500 712500 750000>; + opp-microvolt-L3 = <725000 725000 875000>, + <700000 700000 750000>; + }; + opp-2750000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <2750000000>; + opp-microvolt = <875000 875000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <850000 850000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <837500 837500 875000>, + <725000 725000 750000>; + opp-microvolt-L3 = <825000 820000 875000>, + <700000 700000 750000>; + }; + + /* RK3588J/M dmc OPPs */ + opp-j-m-528000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <528000000>; + opp-microvolt = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-1068000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1068000000>; + opp-microvolt = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-1560000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <1560000000>; + opp-microvolt = <800000 800000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <775000 775000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <750000 750000 875000>, + <750000 750000 750000>; + opp-microvolt-L3 = <750000 750000 875000>, + <750000 750000 750000>; + }; + opp-j-m-2750000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <2750000000>; + opp-microvolt = <875000 875000 875000>, + <750000 750000 750000>; + opp-microvolt-L1 = <850000 850000 875000>, + <750000 750000 750000>; + opp-microvolt-L2 = <837500 837500 875000>, + <750000 750000 750000>; + opp-microvolt-L3 = <825000 820000 875000>, + <750000 750000 750000>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + shmem = <&scmi_shmem>; + arm,smc-id = <0x82000010>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + + assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>, + <&scmi_clk SCMI_CLK_CPUB01>, + <&scmi_clk SCMI_CLK_CPUB23>; + assigned-clock-rates = <816000000>, + <816000000>, + <816000000>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + sdei: sdei { + compatible = "arm,sdei-1.0"; + method = "smc"; + }; + }; + + jpege_ccu: jpege-ccu { + compatible = "rockchip,vpu-jpege-ccu"; + status = "disabled"; + }; + + /omit-if-no-ref/ + mipi_dcphy1: mipi_dcphy0: mipi-dcphy-dummy { + }; + + mipi0_csi2: mipi0-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi1_csi2: mipi1-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi2_csi2: mipi2-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi3_csi2: mipi3-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi4_csi2: mipi4-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mipi5_csi2: mipi5-csi2 { + compatible = "rockchip,rk3588-mipi-csi2"; + rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, + <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, + <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; + status = "disabled"; + }; + + mpp_srv: mpp-srv { + compatible = "rockchip,mpp-service"; + rockchip,taskqueue-count = <12>; + rockchip,resetgroup-count = <1>; + status = "disabled"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + rkcif_dvp: rkcif-dvp { + compatible = "rockchip,rkcif-dvp"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_dvp_sditf: rkcif-dvp-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_dvp>; + status = "disabled"; + }; + + rkcif_mipi_lvds: rkcif-mipi-lvds { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds>; + status = "disabled"; + }; + + rkcif_mipi_lvds1: rkcif-mipi-lvds1 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds1>; + status = "disabled"; + }; + + rkcif_mipi_lvds2: rkcif-mipi-lvds2 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds2>; + status = "disabled"; + }; + + rkcif_mipi_lvds3: rkcif-mipi-lvds3 { + compatible = "rockchip,rkcif-mipi-lvds"; + rockchip,hw = <&rkcif>; + iommus = <&rkcif_mmu>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { + compatible = "rockchip,rkcif-sditf"; + rockchip,cif = <&rkcif_mipi_lvds3>; + status = "disabled"; + }; + + rkisp0_vir0: rkisp0-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + /* + * dual isp process image case + * other rkisp hw and virtual nodes should disabled + * rockchip,hw = <&rkisp_unite>; + */ + status = "disabled"; + }; + + rkisp0_vir1: rkisp0-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + status = "disabled"; + }; + + rkisp0_vir2: rkisp0-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + status = "disabled"; + }; + + rkisp0_vir3: rkisp0-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp0>; + status = "disabled"; + }; + + rkisp1_vir0: rkisp1-vir0 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkisp1_vir1: rkisp1-vir1 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkisp1_vir2: rkisp1-vir2 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkisp1_vir3: rkisp1-vir3 { + compatible = "rockchip,rkisp-vir"; + rockchip,hw = <&rkisp1>; + status = "disabled"; + }; + + rkispp0_vir0: rkispp0-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <&rkispp0>; + status = "disabled"; + }; + + rkispp1_vir0: rkispp1-vir0 { + compatible = "rockchip,rk3588-rkispp-vir"; + rockchip,hw = <&rkispp1>; + status = "disabled"; + }; + + rkvenc_ccu: rkvenc-ccu { + compatible = "rockchip,rkv-encoder-v2-ccu"; + status = "disabled"; + }; + + rkvtunnel: rkvtunnel { + compatible = "rockchip,video-tunnel"; + status = "disabled"; + }; + + rockchip_suspend: rockchip-suspend { + compatible = "rockchip,pm-rk3588"; + status = "disabled"; + rockchip,sleep-debug-en = <0>; + rockchip,sleep-mode-config = < + (0 + | RKPM_SLP_ARMOFF_LOGOFF + | RKPM_SLP_PMU_PMUALIVE_32K + | RKPM_SLP_PMU_DIS_OSC + | RKPM_SLP_32K_EXT + ) + >; + rockchip,wakeup-config = < + (0 + | RKPM_GPIO_WKUP_EN + ) + >; + }; + + rockchip_system_monitor: rockchip-system-monitor { + compatible = "rockchip,system-monitor"; + + rockchip,thermal-zone = "soc-thermal"; + }; + + thermal_zones: thermal-zones { + soc_thermal: soc-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + sustainable-power = <2100>; /* milliwatts */ + + thermal-sensors = <&tsadc 0>; + trips { + threshold: trip-point-0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + target: trip-point-1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + soc_crit: soc-crit { + /* millicelsius */ + temperature = <115000>; + /* millicelsius */ + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map1 { + trip = <&target>; + cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map2 { + trip = <&target>; + cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + map3 { + trip = <&target>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 1>; + }; + + bigcore1_thermal: bigcore1-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 2>; + }; + + little_core_thermal: littlecore-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 3>; + }; + + center_thermal: center-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 4>; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 5>; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <20>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&tsadc 6>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + sram@10f000 { + compatible = "mmio-sram"; + reg = <0x0 0x0010f000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x0010f000 0x100>; + + scmi_shmem: sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x100>; + }; + }; + + gpu: gpu@fb000000 { + compatible = "arm,mali-bifrost"; + reg = <0x0 0xfb000000 0x0 0x200000>; + interrupts = , + , + ; + interrupt-names = "GPU", "MMU", "JOB"; + + clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>; + clock-names = "clk_mali", "clk_gpu_coregroup", + "clk_gpu_stacks", "clk_gpu"; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; + assigned-clock-rates = <200000000>; + power-domains = <&power RK3588_PD_GPU>; + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; + dynamic-power-coefficient = <2982>; + + upthreshold = <30>; + downdifferential = <10>; + + status = "disabled"; + }; + + gpu_opp_table: gpu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x04>; + rockchip,pvtm-voltage-sel-hw = < + 0 799 0 + 800 819 1 + 820 844 2 + 845 869 3 + 870 894 4 + 895 9999 5 + >; + rockchip,pvtm-voltage-sel = < + 0 815 0 + 816 835 1 + 836 860 2 + 861 885 3 + 886 910 4 + 911 9999 5 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x1c>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <800000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <(-135) (-135)>; + rockchip,pvtm-thermal-zone = "gpu-thermal"; + + rockchip,opp-clocks = <&cru CLK_GPU>; + rockchip,grf = <&gpu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <400000>; /* KHz */ + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <800000>; + + /* RK3588 gpu OPPs */ + opp-300000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-400000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-500000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-700000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L2 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L1 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L2 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L3 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L4 = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L5 = <700000 700000 850000>, + <700000 700000 850000>; + }; + opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <737500 737500 850000>, + <737500 737500 850000>; + }; + opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + + /* RK3588J/M gpu OPPs */ + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + /* RK3588J gpu OPPs */ + opp-j-850000000 { + opp-supported-hw = <0x04 0xffff>; + opp-hz = /bits/ 64 <850000000>; + opp-microvolt = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L3 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <750000 750000 850000>, + <750000 750000 850000>; + }; + /* RK3588M gpu OPPs */ + opp-m-800000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-m-900000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-m-1000000000 { + opp-supported-hw = <0x02 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + }; + + usbdrd3_0: usbdrd3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref", "suspend", "bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbdrd_dwc3_0: usb@fc000000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfc000000 0x0 0x400000>; + interrupts = ; + power-domains = <&power RK3588_PD_USB>; + resets = <&cru SRST_A_USB3OTG0>; + reset-names = "usb3-otg"; + dr_mode = "otg"; + phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + quirk-skip-phy-init; + status = "disabled"; + }; + }; + + usb_host0_ehci: usb@fc800000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc800000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + companion = <&usb_host0_ohci>; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host0_ohci: usb@fc840000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc840000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + phys = <&u2phy2_host>; + phy-names = "usb2-phy"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ehci: usb@fc880000 { + compatible = "rockchip,rk3588-ehci", "generic-ehci"; + reg = <0x0 0xfc880000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + companion = <&usb_host1_ohci>; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + usb_host1_ohci: usb@fc8c0000 { + compatible = "rockchip,rk3588-ohci", "generic-ohci"; + reg = <0x0 0xfc8c0000 0x0 0x40000>; + interrupts = ; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>, <&aclk_usb>; + clock-names = "usbhost", "arbiter", "utmi", "alk_usb"; + phys = <&u2phy3_host>; + phy-names = "usb2-phy"; + power-domains = <&power RK3588_PD_USB>; + status = "disabled"; + }; + + mmu600_pcie: iommu@fc900000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfc900000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + mmu600_php: iommu@fcb00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0xfcb00000 0x0 0x200000>; + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + #iommu-cells = <1>; + status = "disabled"; + }; + + usbhost3_0: usbhost3_0 { + compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usbhost_dwc3_0: usb@fcd00000 { + compatible = "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = ; + resets = <&cru SRST_A_USB3OTG2>; + reset-names = "usb3-host"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + }; + + pmu0_grf: syscon@fd588000 { + compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd588000 0x0 0x2000>; + + reboot_mode: reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x80>; + mode-bootloader = ; + mode-charge = ; + mode-fastboot = ; + mode-loader = ; + mode-normal = ; + mode-recovery = ; + mode-ums = ; + mode-panic = ; + mode-watchdog = ; + mode-quiescent = ; + /* add a mode to capture the ramdump through usb */ + mode-winusb = ; + }; + }; + + pmu1_grf: syscon@fd58a000 { + compatible = "rockchip,rk3588-pmu1-grf", "syscon"; + reg = <0x0 0xfd58a000 0x0 0x2000>; + }; + + sys_grf: syscon@fd58c000 { + compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd"; + reg = <0x0 0xfd58c000 0x0 0x1000>; + + rgb: rgb { + compatible = "rockchip,rk3588-rgb"; + pinctrl-names = "default"; + pinctrl-0 = <&bt1120_pins>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + rgb_in_vp3: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp3_out_rgb>; + status = "disabled"; + }; + }; + }; + }; + }; + + bigcore0_grf: syscon@fd590000 { + compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; + reg = <0x0 0xfd590000 0x0 0x100>; + }; + + bigcore1_grf: syscon@fd592000 { + compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; + reg = <0x0 0xfd592000 0x0 0x100>; + }; + + litcore_grf: syscon@fd594000 { + compatible = "rockchip,rk3588-litcore-grf", "syscon"; + reg = <0x0 0xfd594000 0x0 0x100>; + }; + + dsu_grf: syscon@fd598000 { + compatible = "rockchip,rk3588-dsu-grf", "syscon"; + reg = <0x0 0xfd598000 0x0 0x100>; + }; + + gpu_grf: syscon@fd5a0000 { + compatible = "rockchip,rk3588-gpu-grf", "syscon"; + reg = <0x0 0xfd5a0000 0x0 0x100>; + }; + + npu_grf: syscon@fd5a2000 { + compatible = "rockchip,rk3588-npu-grf", "syscon"; + reg = <0x0 0xfd5a2000 0x0 0x100>; + }; + + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo0_grf: syscon@fd5a6000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a6000 0x0 0x2000>; + clocks = <&pclk_vo0_grf>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + clocks = <&pclk_vo1_grf>; + }; + + usb_grf: syscon@fd5ac000 { + compatible = "rockchip,rk3588-usb-grf", "syscon"; + reg = <0x0 0xfd5ac000 0x0 0x4000>; + }; + + php_grf: syscon@fd5b0000 { + compatible = "rockchip,rk3588-php-grf", "syscon"; + reg = <0x0 0xfd5b0000 0x0 0x1000>; + }; + + mipidphy0_grf: syscon@fd5b4000 { + compatible = "rockchip,mipi-dphy-grf", "syscon"; + reg = <0x0 0xfd5b4000 0x0 0x1000>; + }; + + mipidphy1_grf: syscon@fd5b5000 { + compatible = "rockchip,mipi-dphy-grf", "syscon"; + reg = <0x0 0xfd5b5000 0x0 0x1000>; + }; + + pipe_phy0_grf: syscon@fd5bc000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5bc000 0x0 0x100>; + }; + + pipe_phy2_grf: syscon@fd5c4000 { + compatible = "rockchip,pipe-phy-grf", "syscon"; + reg = <0x0 0xfd5c4000 0x0 0x100>; + }; + + usbdpphy0_grf: syscon@fd5c8000 { + compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; + reg = <0x0 0xfd5c8000 0x0 0x4000>; + }; + + usb2phy0_grf: syscon@fd5d0000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d0000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy0: usb2-phy@0 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x0 0x10>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy0"; + #clock-cells = <0>; + rockchip,usbctrl-grf = <&usb_grf>; + status = "disabled"; + + u2phy0_otg: otg-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy2_grf: syscon@fd5d8000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5d8000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy2: usb2-phy@8000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0x8000 0x10>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy2"; + #clock-cells = <0>; + status = "disabled"; + + u2phy2_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + usb2phy3_grf: syscon@fd5dc000 { + compatible = "rockchip,rk3588-usb2phy-grf", "syscon", + "simple-mfd"; + reg = <0x0 0xfd5dc000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + u2phy3: usb2-phy@c000 { + compatible = "rockchip,rk3588-usb2phy"; + reg = <0xc000 0x10>; + interrupts = ; + resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; + reset-names = "phy", "apb"; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy3"; + #clock-cells = <0>; + status = "disabled"; + + u2phy3_host: host-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + hdptxphy0_grf: syscon@fd5e0000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e0000 0x0 0x100>; + }; + + mipidcphy0_grf: syscon@fd5e8000 { + compatible = "rockchip,mipi-dcphy-grf", "syscon"; + reg = <0x0 0xfd5e8000 0x0 0x4000>; + }; + + mipidcphy1_grf: syscon@fd5ec000 { + compatible = "rockchip,mipi-dcphy-grf", "syscon"; + reg = <0x0 0xfd5ec000 0x0 0x4000>; + }; + + ioc: syscon@fd5f0000 { + compatible = "rockchip,rk3588-ioc", "syscon"; + reg = <0x0 0xfd5f0000 0x0 0x10000>; + }; + + cru: clock-controller@fd7c0000 { + compatible = "rockchip,rk3588-cru"; + rockchip,grf = <&php_grf>; + reg = <0x0 0xfd7c0000 0x0 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + + assigned-clocks = + <&cru PLL_PPLL>, <&cru PLL_AUPLL>, + <&cru PLL_NPLL>, <&cru PLL_GPLL>, + <&cru ACLK_CENTER_ROOT>, + <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, + <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, + <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, + <&cru HCLK_PMU_CM0_ROOT>, + <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, + <&cru CLK_GPU>, <&cru CLK_SPDIF2_DP0>, + <&cru CLK_SPDIF5_DP1>, <&cru CLK_HDMIRX_AUD>, + <&cru DCLK_DECOM>; + assigned-clock-rates = + <1100000000>, <786432000>, + <850000000>, <1188000000>, + <702000000>, + <400000000>, <500000000>, + <750000000>, <100000000>, + <400000000>, <100000000>, + <200000000>, + <375000000>, <150000000>, + <200000000>, <12000000>, + <12000000>, <99000000>, + <20000000>; + }; + + i2c0: i2c@fd880000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfd880000 0x0 0x1000>; + clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m0_xfer>; + resets = <&cru SRST_I2C0>, <&cru SRST_P_I2C0>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@fd890000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfd890000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 6>, <&dmac0 7>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0m1_xfer>; + status = "disabled"; + }; + + pwm0: pwm@fd8b0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm0m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm1: pwm@fd8b0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm1m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm2: pwm@fd8b0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm2m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm3: pwm@fd8b0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfd8b0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm3m0_pins>; + clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pmu: power-management@fd8d8000 { + compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; + reg = <0x0 0xfd8d8000 0x0 0x400>; + + power: power-controller { + compatible = "rockchip,rk3588-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* These power domains are grouped by VD_NPU */ + power-domain@RK3588_PD_NPU { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_NPUTOP { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>, + <&cru HCLK_NPU_CM0_ROOT>; + pm_qos = <&qos_npu0_mwr>, + <&qos_npu0_mro>, + <&qos_mcu_npu>; + + power-domain@RK3588_PD_NPU1 { + reg = ; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu1>; + }; + power-domain@RK3588_PD_NPU2 { + reg = ; + clocks = <&cru HCLK_NPU_ROOT>, + <&cru PCLK_NPU_ROOT>, + <&cru CLK_NPU_DSU0>; + pm_qos = <&qos_npu2>; + }; + }; + }; + /* These power domains are grouped by VD_GPU */ + power-domain@RK3588_PD_GPU { + reg = ; + clocks = <&cru CLK_GPU>, + <&cru CLK_GPU_COREGROUP>, + <&cru CLK_GPU_STACKS>; + pm_qos = <&qos_gpu_m0>, + <&qos_gpu_m1>, + <&qos_gpu_m2>, + <&qos_gpu_m3>; + }; + /* These power domains are grouped by VD_VCODEC */ + power-domain@RK3588_PD_VCODEC { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RK3588_PD_RKVDEC0 { + reg = ; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>, + <&cru ACLK_RKVDEC_CCU>; + pm_qos = <&qos_rkvdec0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = ; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC1>; + pm_qos = <&qos_rkvdec1>; + }; + power-domain@RK3588_PD_VENC0 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>; + pm_qos = <&qos_rkvenc0_m0ro>, + <&qos_rkvenc0_m1ro>, + <&qos_rkvenc0_m2wo>; + + power-domain@RK3588_PD_VENC1 { + reg = ; + clocks = <&cru HCLK_RKVENC1>, + <&cru HCLK_RKVENC0>, + <&cru ACLK_RKVENC0>, + <&cru ACLK_RKVENC1>; + pm_qos = <&qos_rkvenc1_m0ro>, + <&qos_rkvenc1_m1ro>, + <&qos_rkvenc1_m2wo>; + }; + }; + }; + /* These power domains are grouped by VD_LOGIC */ + power-domain@RK3588_PD_VDPU { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_LOW_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_JPEG_DECODER_ROOT>, + <&cru ACLK_IEP2P0>, + <&cru HCLK_IEP2P0>, + <&cru ACLK_JPEG_ENCODER0>, + <&cru HCLK_JPEG_ENCODER0>, + <&cru ACLK_JPEG_ENCODER1>, + <&cru HCLK_JPEG_ENCODER1>, + <&cru ACLK_JPEG_ENCODER2>, + <&cru HCLK_JPEG_ENCODER2>, + <&cru ACLK_JPEG_ENCODER3>, + <&cru HCLK_JPEG_ENCODER3>, + <&cru ACLK_JPEG_DECODER>, + <&cru HCLK_JPEG_DECODER>, + <&cru ACLK_RGA2>, + <&cru HCLK_RGA2>; + pm_qos = <&qos_iep>, + <&qos_jpeg_dec>, + <&qos_jpeg_enc0>, + <&qos_jpeg_enc1>, + <&qos_jpeg_enc2>, + <&qos_jpeg_enc3>, + <&qos_rga2_mro>, + <&qos_rga2_mwo>; + + power-domain@RK3588_PD_AV1 { + reg = ; + clocks = <&cru PCLK_AV1>, + <&cru ACLK_AV1>, + <&cru HCLK_VDPU_ROOT>; + pm_qos = <&qos_av1>; + }; + power-domain@RK3588_PD_RKVDEC0 { + reg = ; + clocks = <&cru HCLK_RKVDEC0>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>, + <&cru ACLK_RKVDEC0>; + pm_qos = <&qos_rkvdec0>; + }; + power-domain@RK3588_PD_RKVDEC1 { + reg = ; + clocks = <&cru HCLK_RKVDEC1>, + <&cru HCLK_VDPU_ROOT>, + <&cru ACLK_VDPU_ROOT>; + pm_qos = <&qos_rkvdec1>; + }; + power-domain@RK3588_PD_RGA30 { + reg = ; + clocks = <&cru ACLK_RGA3_0>, + <&cru HCLK_RGA3_0>; + pm_qos = <&qos_rga3_0>; + }; + }; + power-domain@RK3588_PD_VOP { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru PCLK_VOP_ROOT>, + <&cru HCLK_VOP_ROOT>, + <&cru ACLK_VOP>; + pm_qos = <&qos_vop_m0>, + <&qos_vop_m1>; + + power-domain@RK3588_PD_VO0 { + reg = ; + clocks = <&cru PCLK_VO0_ROOT>, + <&cru PCLK_VO0_S_ROOT>, + <&cru HCLK_VO0_S_ROOT>, + <&cru ACLK_VO0_ROOT>, + <&cru HCLK_HDCP0>, + <&cru ACLK_HDCP0>, + <&cru HCLK_VOP_ROOT>; + pm_qos = <&qos_hdcp0>; + }; + }; + power-domain@RK3588_PD_VO1 { + reg = ; + clocks = <&cru PCLK_VO1_ROOT>, + <&cru PCLK_VO1_S_ROOT>, + <&cru HCLK_VO1_S_ROOT>, + <&cru HCLK_HDCP1>, + <&cru ACLK_HDCP1>, + <&cru ACLK_HDMIRX_ROOT>, + <&cru HCLK_VO1USB_TOP_ROOT>; + pm_qos = <&qos_hdcp1>, + <&qos_hdmirx>; + }; + power-domain@RK3588_PD_VI { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>, + <&cru HCLK_ISP0>, + <&cru ACLK_ISP0>, + <&cru HCLK_VICAP>, + <&cru ACLK_VICAP>; + pm_qos = <&qos_isp0_mro>, + <&qos_isp0_mwo>, + <&qos_vicap_m0>, + <&qos_vicap_m1>; + + power-domain@RK3588_PD_ISP1 { + reg = ; + clocks = <&cru HCLK_ISP1>, + <&cru ACLK_ISP1>, + <&cru HCLK_VI_ROOT>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_isp1_mwo>, + <&qos_isp1_mro>; + }; + power-domain@RK3588_PD_FEC { + reg = ; + clocks = <&cru HCLK_FISHEYE0>, + <&cru ACLK_FISHEYE0>, + <&cru HCLK_FISHEYE1>, + <&cru ACLK_FISHEYE1>, + <&cru PCLK_VI_ROOT>; + pm_qos = <&qos_fisheye0>, + <&qos_fisheye1>; + }; + }; + power-domain@RK3588_PD_RGA31 { + reg = ; + clocks = <&cru HCLK_RGA3_1>, + <&cru ACLK_RGA3_1>; + pm_qos = <&qos_rga3_1>; + }; + power-domain@RK3588_PD_USB { + reg = ; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_USB3OTG0>, + <&cru ACLK_USB3OTG1>, + <&cru HCLK_HOST0>, + <&cru HCLK_HOST_ARB0>, + <&cru HCLK_HOST1>, + <&cru HCLK_HOST_ARB1>; + pm_qos = <&qos_usb3_0>, + <&qos_usb3_1>, + <&qos_usb2host_0>, + <&qos_usb2host_1>; + }; + power-domain@RK3588_PD_GMAC { + reg = ; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + }; + power-domain@RK3588_PD_PCIE { + reg = ; + clocks = <&cru PCLK_PHP_ROOT>, + <&cru ACLK_PCIE_ROOT>, + <&cru ACLK_PHP_ROOT>; + }; + power-domain@RK3588_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru HCLK_NVM_ROOT>; + pm_qos = <&qos_sdio>; + }; + power-domain@RK3588_PD_AUDIO { + reg = ; + clocks = <&cru HCLK_AUDIO_ROOT>, + <&cru PCLK_AUDIO_ROOT>; + }; + power-domain@RK3588_PD_SDMMC { + reg = ; + pm_qos = <&qos_sdmmc>; + }; + }; + }; + + pvtm@fda40000 { + compatible = "rockchip,rk3588-bigcore0-pvtm"; + reg = <0x0 0xfda40000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@0 { + reg = <0>; + clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fda50000 { + compatible = "rockchip,rk3588-bigcore1-pvtm"; + reg = <0x0 0xfda50000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@1 { + reg = <1>; + clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fda60000 { + compatible = "rockchip,rk3588-litcore-pvtm"; + reg = <0x0 0xfda60000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@2 { + reg = <2>; + clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; + clock-names = "clk", "pclk"; + }; + }; + + pvtm@fdaf0000 { + compatible = "rockchip,rk3588-npu-pvtm"; + reg = <0x0 0xfdaf0000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@3 { + reg = <3>; + clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; + clock-names = "clk", "pclk"; + resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; + reset-names = "rts", "rst-p"; + }; + }; + + pvtm@fdb30000 { + compatible = "rockchip,rk3588-gpu-pvtm"; + reg = <0x0 0xfdb30000 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + pvtm@4 { + reg = <4>; + clocks = <&cru CLK_GPU_PVTM>; + clock-names = "clk"; + resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; + reset-names = "rts", "rst-p"; + }; + }; + + rknpu: npu@fdab0000 { + compatible = "rockchip,rk3588-rknpu"; + reg = <0x0 0xfdab0000 0x0 0x10000>, + <0x0 0xfdac0000 0x0 0x10000>, + <0x0 0xfdad0000 0x0 0x10000>; + interrupts = , + , + ; + interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; + clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>, + <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, + <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, + <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>; + clock-names = "clk_npu", "aclk0", + "aclk1", "aclk2", + "hclk0", "hclk1", + "hclk2", "pclk"; + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates = <200000000>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>, + <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>; + reset-names = "srst_a0", "srst_a1", "srst_a2", + "srst_h0", "srst_h1", "srst_h2"; + power-domains = <&power RK3588_PD_NPUTOP>, + <&power RK3588_PD_NPU1>, + <&power RK3588_PD_NPU2>; + power-domain-names = "npu0", "npu1", "npu2"; + operating-points-v2 = <&npu_opp_table>; + iommus = <&rknpu_mmu>; + status = "disabled"; + }; + + npu_opp_table: npu-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>; + nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; + rockchip,supported-hw; + + rockchip,pvtm-hw = <0x06>; + rockchip,pvtm-voltage-sel-hw = < + 0 799 0 + 800 819 1 + 820 844 2 + 845 869 3 + 870 894 4 + 895 9999 5 + >; + rockchip,pvtm-voltage-sel = < + 0 815 0 + 816 835 1 + 836 860 2 + 861 885 3 + 886 910 4 + 911 9999 5 + >; + rockchip,pvtm-pvtpll; + rockchip,pvtm-offset = <0x50>; + rockchip,pvtm-sample-time = <1100>; + rockchip,pvtm-freq = <800000>; + rockchip,pvtm-volt = <750000>; + rockchip,pvtm-ref-temp = <25>; + rockchip,pvtm-temp-prop = <(-113) (-113)>; + rockchip,pvtm-thermal-zone = "npu-thermal"; + + rockchip,opp-clocks = <&cru PCLK_NPU_GRF>, <&cru HCLK_NPU_ROOT>; + rockchip,grf = <&npu_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + low-volt-mem-read-margin = <4>; + intermediate-threshold-freq = <500000>; /* KHz*/ + rockchip,init-freq = <1000000>; /* KHz */ + + rockchip,temp-hysteresis = <5000>; + rockchip,low-temp = <10000>; + rockchip,low-temp-min-volt = <750000>; + rockchip,high-temp = <85000>; + rockchip,high-temp-max-freq = <800000>; + + /* RK3588 npu OPPs */ + opp-300000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-400000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-500000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-600000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L1 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L2 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L3 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-700000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <700000 700000 850000>, + <700000 700000 850000>; + opp-microvolt-L3 = <687500 687500 850000>, + <687500 687500 850000>; + opp-microvolt-L4 = <675000 675000 850000>, + <675000 675000 850000>; + opp-microvolt-L5 = <675000 675000 850000>, + <675000 675000 850000>; + }; + opp-800000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L2 = <737500 737500 850000>, + <737500 737500 850000>; + opp-microvolt-L3 = <725000 725000 850000>, + <725000 725000 850000>; + opp-microvolt-L4 = <712500 712500 850000>, + <712500 712500 850000>; + opp-microvolt-L5 = <700000 700000 850000>, + <700000 700000 850000>; + }; + opp-900000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L2 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L3 = <762500 762500 850000>, + <762500 762500 850000>; + opp-microvolt-L4 = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L5 = <737500 737500 850000>, + <737500 737500 850000>; + }; + opp-1000000000 { + opp-supported-hw = <0xf9 0xffff>; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <850000 850000 850000>, + <850000 850000 850000>; + opp-microvolt-L1 = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L2 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L3 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L4 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L5 = <787500 787500 850000>, + <787500 787500 850000>; + }; + + /* RK3588J/M npu OPPs */ + opp-j-m-300000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-400000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-500000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-600000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-700000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-800000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + }; + opp-j-m-950000000 { + opp-supported-hw = <0x06 0xffff>; + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <837500 837500 850000>, + <837500 837500 850000>; + opp-microvolt-L1 = <825000 825000 850000>, + <825000 825000 850000>; + opp-microvolt-L2 = <812500 812500 850000>, + <812500 812500 850000>; + opp-microvolt-L3 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L4 = <787500 787500 850000>, + <787500 787500 850000>; + opp-microvolt-L5 = <775000 775000 850000>, + <775000 775000 850000>; + }; + }; + + rknpu_mmu: iommu@fdab9000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdab9000 0x0 0x100>, + <0x0 0xfdaba000 0x0 0x100>, + <0x0 0xfdaca000 0x0 0x100>, + <0x0 0xfdada000 0x0 0x100>; + interrupts = , + , + ; + interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu"; + clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, + <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>; + clock-names = "aclk0", "aclk1", "aclk2", + "iface0", "iface1", "iface2"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vepu: vepu@fdb50000 { + compatible = "rockchip,vpu-encoder-v2"; + reg = <0x0 0xfdb50000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_vepu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_VPU>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; + reset-names = "shared_video_a", "shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&vdpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + vdpu: vdpu@fdb50400 { + compatible = "rockchip,vpu-decoder-v2"; + reg = <0x0 0xfdb50400 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_vdpu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_VPU>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; + reset-names = "shared_video_a", "shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&vdpu_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + vdpu_mmu: iommu@fdb50800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb50800 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_vdpu_mmu"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + avsd: avsd-plus@fdb51000 { + compatible = "rockchip,avs-plus-decoder"; + reg = <0x0 0xfdb51000 0x0 0x200>; + interrupts = ; + interrupt-names = "irq_avsd"; + clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_VPU>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; + reset-names = "shared_video_a", "shared_video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&vdpu_mmu>; + power-domains = <&power RK3588_PD_VDPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <0>; + rockchip,resetgroup-node = <0>; + status = "disabled"; + }; + + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rga3_core0"; + reg = <0x0 0xfdb60000 0x0 0x1000>; + interrupts = ; + interrupt-names = "rga3_core0_irq"; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; + clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0"; + power-domains = <&power RK3588_PD_RGA30>; + iommus = <&rga3_0_mmu>; + status = "disabled"; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = ; + interrupt-names = "rga3_0_mmu"; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RGA30>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rga3_core1"; + reg = <0x0 0xfdb70000 0x0 0x1000>; + interrupts = ; + interrupt-names = "rga3_core1_irq"; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; + clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1"; + power-domains = <&power RK3588_PD_RGA31>; + iommus = <&rga3_1_mmu>; + status = "disabled"; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = ; + interrupt-names = "rga3_1_mmu"; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_RGA31>; + #iommu-cells = <0>; + status = "disabled"; + }; + + rga2: rga@fdb80000 { + compatible = "rockchip,rga2_core0"; + reg = <0x0 0xfdb80000 0x0 0x1000>; + interrupts = ; + interrupt-names = "rga2_irq"; + clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; + clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + jpegd: jpegd@fdb90000 { + compatible = "rockchip,rkv-jpeg-decoder-v1"; + reg = <0x0 0xfdb90000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_jpegd"; + clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <600000000>, <0>; + assigned-clocks = <&cru ACLK_JPEG_DECODER>; + assigned-clock-rates = <600000000>; + resets = <&cru SRST_A_JPEG_DECODER>, <&cru SRST_H_JPEG_DECODER>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + iommus = <&jpegd_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <1>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + jpegd_mmu: iommu@fdb90480 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdb90480 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_jpegd_mmu"; + clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege0: jpege-core@fdba0000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba0000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_jpege0"; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_JPEG_ENCODER0>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_JPEG_ENCODER0>, <&cru SRST_H_JPEG_ENCODER0>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege0_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + jpege0_mmu: iommu@fdba0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba0800 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_jpege0_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege1: jpege-core@fdba4000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba4000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_jpege1"; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_JPEG_ENCODER1>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_JPEG_ENCODER1>, <&cru SRST_H_JPEG_ENCODER1>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege1_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + jpege1_mmu: iommu@fdba4800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba4800 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_jpege1_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege2: jpege-core@fdba8000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdba8000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_jpege2"; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_JPEG_ENCODER2>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_JPEG_ENCODER2>, <&cru SRST_H_JPEG_ENCODER2>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege2_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + jpege2_mmu: iommu@fdba8800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdba8800 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_jpege2_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + jpege3: jpege-core@fdbac000 { + compatible = "rockchip,vpu-jpege-core"; + reg = <0x0 0xfdbac000 0x0 0x400>; + interrupts = ; + interrupt-names = "irq_jpege3"; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_JPEG_ENCODER3>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_JPEG_ENCODER3>, <&cru SRST_H_JPEG_ENCODER3>; + reset-names = "video_a", "video_h"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + iommus = <&jpege3_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <2>; + rockchip,ccu = <&jpege_ccu>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + jpege3_mmu: iommu@fdbac800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbac800 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_jpege3_mmu"; + clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VDPU>; + #iommu-cells = <0>; + status = "disabled"; + }; + + iep: iep@fdbb0000 { + compatible = "rockchip,iep-v2"; + reg = <0x0 0xfdbb0000 0x0 0x500>; + interrupts = ; + interrupt-names = "irq_iep"; + clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + rockchip,normal-rates = <594000000>, <0>; + assigned-clocks = <&cru ACLK_IEP2P0>; + assigned-clock-rates = <594000000>; + resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>; + reset-names = "rst_a", "rst_h", "rst_s"; + rockchip,skip-pmu-idle-request; + rockchip,disable-auto-freq; + power-domains = <&power RK3588_PD_VDPU>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <6>; + iommus = <&iep_mmu>; + status = "disabled"; + }; + + iep_mmu: iommu@fdbb0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbb0800 0x0 0x100>; + interrupts = ; + interrupt-names = "irq_iep_mmu"; + clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VDPU>; + status = "disabled"; + }; + + rkvenc0: rkvenc-core@fdbd0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbd0000 0x0 0x6000>; + interrupts = ; + interrupt-names = "irq_rkvenc0"; + clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <500000000>, <0>, <800000000>; + assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; + assigned-clock-rates = <500000000>, <800000000>; + resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>; + reset-names = "video_a", "video_h", "video_core"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvenc0_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvenc_ccu>; + rockchip,taskqueue-node = <7>; + rockchip,task-capacity = <8>; + power-domains = <&power RK3588_PD_VENC0>; + operating-points-v2 = <&venc_opp_table>; + status = "disabled"; + }; + + rkvenc0_mmu: iommu@fdbdf000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; + interrupts = , + ; + interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; + clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VENC0>; + status = "disabled"; + }; + + rkvenc1: rkvenc-core@fdbe0000 { + compatible = "rockchip,rkv-encoder-v2-core"; + reg = <0x0 0xfdbe0000 0x0 0x6000>; + interrupts = ; + interrupt-names = "irq_rkvenc1"; + clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; + rockchip,normal-rates = <500000000>, <0>, <800000000>; + assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; + assigned-clock-rates = <500000000>, <800000000>; + resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>; + reset-names = "video_a", "video_h", "video_core"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvenc1_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvenc_ccu>; + rockchip,taskqueue-node = <7>; + rockchip,task-capacity = <8>; + power-domains = <&power RK3588_PD_VENC1>; + operating-points-v2 = <&venc_opp_table>; + status = "disabled"; + }; + + rkvenc1_mmu: iommu@fdbef000 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; + interrupts = , + ; + interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; + clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; + lock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VENC1>; + status = "disabled"; + }; + + venc_opp_table: venc-opp-table { + compatible = "operating-points-v2"; + + nvmem-cells = <&codec_leakage>, <&venc_opp_info>; + nvmem-cell-names = "leakage", "opp-info"; + rockchip,leakage-voltage-sel = < + 1 15 0 + 16 25 1 + 26 254 2 + >; + + rockchip,grf = <&sys_grf>; + volt-mem-read-margin = < + 855000 1 + 765000 2 + 675000 3 + 495000 4 + >; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <750000 750000 850000>, + <750000 750000 850000>; + opp-microvolt-L0 = <800000 800000 850000>, + <800000 800000 850000>; + opp-microvolt-L1 = <775000 775000 850000>, + <775000 775000 850000>; + opp-microvolt-L2 = <750000 750000 850000>, + <750000 750000 850000>; + }; + }; + + rkvdec_ccu: rkvdec-ccu@fdc30000 { + compatible = "rockchip,rkv-decoder-v2-ccu"; + reg = <0x0 0xfdc30000 0x0 0x100>; + reg-names = "ccu"; + clocks = <&cru ACLK_RKVDEC_CCU>; + clock-names = "aclk_ccu"; + assigned-clocks = <&cru ACLK_RKVDEC_CCU>; + assigned-clock-rates = <600000000>; + resets = <&cru SRST_A_RKVDEC_CCU>; + reset-names = "video_ccu"; + rockchip,skip-pmu-idle-request; + /* 1: soft ccu 2: hw ccu */ + rockchip,ccu-mode = <1>; + power-domains = <&power RK3588_PD_RKVDEC0>; + status = "disabled"; + }; + + rkvdec0: rkvdec-core@fdc38000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_rkvdec0"; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", + "clk_cabac", "clk_hevc_cabac"; + rockchip,normal-rates = <800000000>, <0>, <600000000>, + <600000000>, <1000000000>; + assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, + <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CORE>, + <&cru SRST_RKVDEC0_CA>, <&cru SRST_RKVDEC0_HEVC_CA>; + reset-names = "video_a", "video_h", "video_core", + "video_cabac", "video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvdec0_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvdec_ccu>; + rockchip,core-mask = <0x00010001>; + rockchip,task-capacity = <16>; + rockchip,taskqueue-node = <9>; + rockchip,sram = <&rkvdec0_sram>; + /* rcb_iova: start and size 1M@4095M */ + rockchip,rcb-iova = <0xFFF00000 0x100000>; + rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>, + <139 180224>, <133 49152>, <134 8192>, <135 4352>, + <138 13056>, <142 291584>; + rockchip,rcb-min-width = <512>; + power-domains = <&power RK3588_PD_RKVDEC0>; + status = "disabled"; + }; + + rkvdec0_mmu: iommu@fdc38700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_rkvdec0_mmu"; + clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RKVDEC0>; + status = "disabled"; + }; + + rkvdec1: rkvdec-core@fdc48000 { + compatible = "rockchip,rkv-decoder-v2"; + reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>; + reg-names = "regs", "link"; + interrupts = ; + interrupt-names = "irq_rkvdec1"; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", + "clk_cabac", "clk_hevc_cabac"; + rockchip,normal-rates = <800000000>, <0>, <600000000>, + <600000000>, <1000000000>; + assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, + <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; + assigned-clock-rates = <800000000>, <600000000>, + <600000000>, <1000000000>; + resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CORE>, + <&cru SRST_RKVDEC1_CA>, <&cru SRST_RKVDEC1_HEVC_CA>; + reset-names = "video_a", "video_h", "video_core", + "video_cabac", "video_hevc_cabac"; + rockchip,skip-pmu-idle-request; + iommus = <&rkvdec1_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,ccu = <&rkvdec_ccu>; + rockchip,core-mask = <0x00020002>; + rockchip,task-capacity = <16>; + rockchip,taskqueue-node = <9>; + rockchip,sram = <&rkvdec1_sram>; + /* rcb_iova: start and size 1M@4094M */ + rockchip,rcb-iova = <0xFFE00000 0x100000>; + rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>, + <139 180224>, <133 49152>, <134 8192>, <135 4352>, + <138 13056>, <142 291584>; + rockchip,rcb-min-width = <512>; + power-domains = <&power RK3588_PD_RKVDEC1>; + status = "disabled"; + }; + + rkvdec1_mmu: iommu@fdc48700 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; + interrupts = ; + interrupt-names = "irq_rkvdec1_mmu"; + clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; + clock-names = "aclk", "iface"; + rockchip,disable-mmu-reset; + rockchip,enable-cmd-retry; + rockchip,shootdown-entire; + rockchip,master-handle-irq; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RKVDEC1>; + status = "disabled"; + }; + + av1d: av1d@fdc70000 { + compatible = "rockchip,av1-decoder"; + reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>, + <0x0 0xfdc90000 0x0 0x400>; + reg-names = "vcd", "cache", "afbc"; + interrupts = , , + ; + interrupt-names = "irq_av1d", "irq_cache", "irq_afbc"; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk_vcodec", "hclk_vcodec"; + rockchip,normal-rates = <400000000>, <400000000>; + assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + assigned-clock-rates = <400000000>, <400000000>; + resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>; + reset-names = "video_a", "video_h"; + iommus = <&av1d_mmu>; + rockchip,srv = <&mpp_srv>; + rockchip,taskqueue-node = <11>; + power-domains = <&power RK3588_PD_AV1>; + status = "disabled"; + }; + + av1d_mmu: iommu@fdca0000 { + compatible = "rockchip,iommu-av1"; + reg = <0x0 0xfdca0000 0x0 0x600>; + interrupts = ; + interrupt-names = "irq_av1d_mmu"; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_AV1>; + status = "disabled"; + }; + + rkisp_unite: rkisp-unite@fdcb0000 { + compatible = "rockchip,rk3588-rkisp-unite"; + reg = <0x0 0xfdcb0000 0x0 0x10000>, + <0x0 0xfdcc0000 0x0 0x10000>; + interrupts = , + , + ; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, + <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, + <&cru CLK_ISP0_CORE_VICAP>, <&cru ACLK_ISP1>, + <&cru HCLK_ISP1>, <&cru CLK_ISP1_CORE>, + <&cru CLK_ISP1_CORE_MARVIN>, <&cru CLK_ISP1_CORE_VICAP>; + clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0", + "clk_isp_core_marvin0", "clk_isp_core_vicap0", + "aclk_isp1", "hclk_isp1", "clk_isp_core1", + "clk_isp_core_marvin1", "clk_isp_core_vicap1"; + power-domains = <&power RK3588_PD_ISP1>; + iommus = <&rkisp_unite_mmu>; + status = "disabled"; + }; + + rkisp0: rkisp@fdcb0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x0 0xfdcb0000 0x0 0x7f00>; + interrupts = , + , + ; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, + <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, + <&cru CLK_ISP0_CORE_VICAP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", + "clk_isp_core_marvin", "clk_isp_core_vicap"; + power-domains = <&power RK3588_PD_VI>; + iommus = <&isp0_mmu>; + status = "disabled"; + }; + + rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>; + interrupts = , + ; + interrupt-names = "isp0_mmu", "isp1_mmu"; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, + <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; + clock-names = "aclk0", "iface0", "aclk1", "iface1"; + power-domains = <&power RK3588_PD_ISP1>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + isp0_mmu: iommu@fdcb7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcb7f00 0x0 0x100>; + interrupts = ; + interrupt-names = "isp0_mmu"; + clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VI>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkisp1: rkisp@fdcc0000 { + compatible = "rockchip,rk3588-rkisp"; + reg = <0x0 0xfdcc0000 0x0 0x7f00>; + interrupts = , + , + ; + interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, + <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>, + <&cru CLK_ISP1_CORE_VICAP>; + clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", + "clk_isp_core_marvin", "clk_isp_core_vicap"; + power-domains = <&power RK3588_PD_ISP1>; + iommus = <&isp1_mmu>; + status = "disabled"; + }; + + isp1_mmu: iommu@fdcc7f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcc7f00 0x0 0x100>; + interrupts = ; + interrupt-names = "isp1_mmu"; + clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_ISP1>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkispp0: rkispp@fdcd0000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x0 0xfdcd0000 0x0 0x0f00>; + interrupts = ; + interrupt-names = "fec_irq"; + clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, + <&cru CLK_FISHEYE0_CORE>; + clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; + assigned-clocks = <&cru HCLK_FISHEYE0>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3588_PD_FEC>; + iommus = <&fec0_mmu>; + status = "disabled"; + }; + + fec0_mmu: iommu@fdcd0f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcd0f00 0x0 0x100>; + interrupts = ; + interrupt-names = "fec0_mmu"; + clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, <&cru CLK_FISHEYE0_CORE>; + clock-names = "aclk", "iface", "pclk"; + power-domains = <&power RK3588_PD_FEC>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkispp1: rkispp@fdcd8000 { + compatible = "rockchip,rk3588-rkispp"; + reg = <0x0 0xfdcd8000 0x0 0x0f00>; + interrupts = ; + interrupt-names = "fec_irq"; + clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, + <&cru CLK_FISHEYE1_CORE>; + clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; + assigned-clocks = <&cru HCLK_FISHEYE1>; + assigned-clock-rates = <100000000>; + power-domains = <&power RK3588_PD_FEC>; + iommus = <&fec1_mmu>; + status = "disabled"; + }; + + fec1_mmu: iommu@fdcd8f00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdcd8f00 0x0 0x100>; + interrupts = ; + interrupt-names = "fec1_mmu"; + clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, <&cru CLK_FISHEYE1_CORE>; + clock-names = "aclk", "iface", "pclk"; + power-domains = <&power RK3588_PD_FEC>; + #iommu-cells = <0>; + rockchip,disable-mmu-reset; + status = "disabled"; + }; + + rkcif: rkcif@fdce0000 { + compatible = "rockchip,rk3588-cif"; + reg = <0x0 0xfdce0000 0x0 0x800>; + reg-names = "cif_regs"; + interrupts = ; + interrupt-names = "cif-intr"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, + <&cru ICLK_CSIHOST0>, <&cru ICLK_CSIHOST1>; + clock-names = "aclk_cif", "hclk_cif", "dclk_cif", + "iclk_host0", "iclk_host1"; + resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, + <&cru SRST_CSIHOST0_VICAP>, <&cru SRST_CSIHOST1_VICAP>, + <&cru SRST_CSIHOST2_VICAP>, <&cru SRST_CSIHOST3_VICAP>, + <&cru SRST_CSIHOST4_VICAP>, <&cru SRST_CSIHOST5_VICAP>; + reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", + "rst_cif_host0", "rst_cif_host1", "rst_cif_host2", + "rst_cif_host3", "rst_cif_host4", "rst_cif_host5"; + assigned-clocks = <&cru DCLK_VICAP>; + assigned-clock-rates = <600000000>; + power-domains = <&power RK3588_PD_VI>; + rockchip,grf = <&sys_grf>; + iommus = <&rkcif_mmu>; + nvmem-cells = <&specification_serial_number>, + <&package_serial_number_low>, + <&package_serial_number_high>; + nvmem-cell-names = "specification", + "package_low", + "package_high"; + status = "disabled"; + }; + + rkcif_mmu: iommu@fdce0800 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdce0800 0x0 0x100>, + <0x0 0xfdce0900 0x0 0x100>; + interrupts = ; + interrupt-names = "cif_mmu"; + clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; + clock-names = "aclk", "iface"; + power-domains = <&power RK3588_PD_VI>; + rockchip,disable-mmu-reset; + #iommu-cells = <0>; + status = "disabled"; + }; + + mipi0_csi2_hw: mipi0-csi2-hw@fdd10000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd10000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_0>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_0>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi1_csi2_hw: mipi1-csi2-hw@fdd20000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd20000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_1>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_1>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi2_csi2_hw: mipi2-csi2-hw@fdd30000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd30000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_2>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_2>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi3_csi2_hw: mipi3-csi2-hw@fdd40000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd40000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_3>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_3>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi4_csi2_hw: mipi4-csi2-hw@fdd50000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd50000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_4>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_4>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + mipi5_csi2_hw: mipi5-csi2-hw@fdd60000 { + compatible = "rockchip,rk3588-mipi-csi2-hw"; + reg = <0x0 0xfdd60000 0x0 0x10000>; + reg-names = "csihost_regs"; + interrupts = , + ; + interrupt-names = "csi-intr1", "csi-intr2"; + clocks = <&cru PCLK_CSI_HOST_5>; + clock-names = "pclk_csi2host"; + resets = <&cru SRST_P_CSI_HOST_5>; + reset-names = "srst_csihost_p"; + status = "okay"; + }; + + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "regs", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&cru DCLK_VOP0_SRC>, + <&cru DCLK_VOP1_SRC>, + <&cru DCLK_VOP2_SRC>; + clock-names = "aclk_vop", + "hclk_vop", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "dclk_src_vp0", + "dclk_src_vp1", + "dclk_src_vp2"; + assigned-clocks = <&cru ACLK_VOP>; + assigned-clock-rates = <750000000>; + resets = <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP0>, + <&cru SRST_D_VOP1>, + <&cru SRST_D_VOP2>, + <&cru SRST_D_VOP3>; + reset-names = "axi", + "ahb", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + vp0_out_dp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dp0_in_vp0>; + }; + + vp0_out_edp0: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp0_in_vp0>; + }; + + vp0_out_hdmi0: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi0_in_vp0>; + }; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + vp1_out_dp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dp0_in_vp1>; + }; + + vp1_out_edp0: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp0_in_vp1>; + }; + + vp1_out_hdmi0: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi0_in_vp1>; + }; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + assigned-clocks = <&cru DCLK_VOP2_SRC>; + assigned-clock-parents = <&cru PLL_V0PLL>; + + vp2_out_dp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dp0_in_vp2>; + }; + + vp2_out_edp0: endpoint@1 { + reg = <1>; + remote-endpoint = <&edp0_in_vp2>; + }; + + vp2_out_hdmi0: endpoint@2 { + reg = <2>; + remote-endpoint = <&hdmi0_in_vp2>; + }; + + vp2_out_dsi0: endpoint@3 { + reg = <3>; + remote-endpoint = <&dsi0_in_vp2>; + }; + + vp2_out_dsi1: endpoint@4 { + reg = <4>; + remote-endpoint = <&dsi1_in_vp2>; + }; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + vp3_out_dsi0: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_in_vp3>; + }; + + vp3_out_dsi1: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi1_in_vp3>; + }; + + vp3_out_rgb: endpoint@2 { + reg = <2>; + remote-endpoint = <&rgb_in_vp3>; + }; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,iommu-v2"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + rockchip,disable-device-link-resume; + rockchip,shootdown-entire; + status = "disabled"; + }; + + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 6>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; + assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s4_8ch: i2s@fddc0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddc0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 0>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO0>; + resets = <&cru SRST_M_I2S4_8CH_TX>; + reset-names = "tx-m"; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + assigned-clocks = <&cru CLK_SPDIF3_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s5_8ch: i2s@fddf0000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddf0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; + assigned-clock-parents = <&cru PLL_GPLL>; + dmas = <&dmac2 2>; + dma-names = "tx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S5_8CH_TX>; + reset-names = "tx-m"; + rockchip,always-on; + rockchip,hdmi-path; + rockchip,playback-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s9_8ch: i2s@fddfc000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfddfc000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac2 23>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_I2S9_8CH_RX>; + reset-names = "rx-m"; + rockchip,capture-only; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_rx0: spdif-rx@fde08000 { + compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; + reg = <0x0 0xfde08000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; + clock-names = "mclk", "hclk"; + assigned-clocks = <&cru MCLK_SPDIFRX0>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac0 21>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_M_SPDIFRX0>; + reset-names = "spdifrx-m"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + dsi0: dsi@fde20000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde20000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; + clock-names = "pclk", "sys_clk"; + resets = <&cru SRST_P_DSIHOST0>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy0>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi0_in_vp2: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp2_out_dsi0>; + status = "disabled"; + }; + + dsi0_in_vp3: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp3_out_dsi0>; + status = "disabled"; + }; + }; + }; + }; + + dsi1: dsi@fde30000 { + compatible = "rockchip,rk3588-mipi-dsi2"; + reg = <0x0 0xfde30000 0x0 0x10000>; + interrupts = ; + clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; + clock-names = "pclk", "sys_clk"; + resets = <&cru SRST_P_DSIHOST1>; + reset-names = "apb"; + power-domains = <&power RK3588_PD_VOP>; + phys = <&mipidcphy1>; + phy-names = "dcphy"; + rockchip,grf = <&vop_grf>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dsi1_in_vp2: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp2_out_dsi1>; + status = "disabled"; + }; + + dsi1_in_vp3: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp3_out_dsi1>; + status = "disabled"; + }; + }; + }; + }; + + hdcp0: hdcp@fde40000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x0 0xfde40000 0x0 0x80>; + interrupts = ; + clocks = <&cru ACLK_HDCP0>, <&cru PCLK_HDCP0>, + <&cru HCLK_HDCP0>, <&cru HCLK_HDCP_KEY0>, + <&cru ACLK_TRNG0>, <&cru PCLK_TRNG0>; + clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng"; + resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>, + <&cru SRST_A_HDCP0>, <&cru SRST_H_HDCP_KEY0>, + <&cru SRST_P_TRNG0>; + reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng"; + power-domains = <&power RK3588_PD_VO0>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + }; + + dp0: dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = ; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_SPDIF2_DP0>, + <&hclk_vo0>, <&cru CLK_DP0>; + clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp"; + assigned-clocks = <&cru CLK_AUX16M_0>; + assigned-clock-rates = <16000000>; + resets = <&cru SRST_DP0>; + phys = <&usbdp_phy0_dp>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dp0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_dp0>; + status = "disabled"; + }; + + dp0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_dp0>; + status = "disabled"; + }; + + dp0_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_dp0>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + dp0_out: endpoint { }; + }; + }; + }; + + hdcp1: hdcp@fde70000 { + compatible = "rockchip,rk3588-hdcp"; + reg = <0x0 0xfde70000 0x0 0x80>; + interrupts = ; + clocks = <&cru ACLK_HDCP1>, <&cru PCLK_HDCP1>, + <&cru HCLK_HDCP1>, <&cru HCLK_HDCP_KEY1>, + <&cru ACLK_TRNG1>, <&cru PCLK_TRNG1>; + clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng"; + resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>, + <&cru SRST_A_HDCP1>, <&cru SRST_H_HDCP_KEY1>, + <&cru SRST_P_TRNG1>; + reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng"; + power-domains = <&power RK3588_PD_VO1>; + rockchip,vo-grf = <&vo1_grf>; + status = "disabled"; + }; + + hdmi0: hdmi@fde80000 { + compatible = "rockchip,rk3588-dw-hdmi"; + reg = <0x0 0xfde80000 0x0 0x10000>, <0x0 0xfde90000 0x0 0x10000>; + interrupts = , + , + , + , + ; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMIHDP0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_I2S5_8CH_TX>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&hclk_vo1>, + <&hdptxphy_hdmi_clk0>; + clock-names = "pclk", + "hpd", + "earc", + "hdmitx_ref", + "aud", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "hclk_vo1", + "link_clk"; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; + reset-names = "ref", "hdp"; + power-domains = <&power RK3588_PD_VO1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; + reg-io-width = <4>; + rockchip,grf = <&sys_grf>; + rockchip,vo1_grf = <&vo1_grf>; + phys = <&hdptxphy_hdmi0>; + phy-names = "hdmi"; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + hdmi0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_hdmi0>; + status = "disabled"; + }; + + hdmi0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_hdmi0>; + status = "disabled"; + }; + + hdmi0_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_hdmi0>; + status = "disabled"; + }; + }; + }; + }; + + edp0: edp@fdec0000 { + compatible = "rockchip,rk3588-edp"; + reg = <0x0 0xfdec0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, + <&cru CLK_EDP0_200M>, <&hclk_vo1>; + clock-names = "dp", "pclk", "spdif", "hclk"; + resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; + reset-names = "dp", "apb"; + phys = <&hdptxphy0>; + phy-names = "dp"; + power-domains = <&power RK3588_PD_VO1>; + rockchip,grf = <&vo1_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + edp0_in_vp0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vp0_out_edp0>; + status = "disabled"; + }; + + edp0_in_vp1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vp1_out_edp0>; + status = "disabled"; + }; + + edp0_in_vp2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vp2_out_edp0>; + status = "disabled"; + }; + }; + + port@1 { + reg = <1>; + + edp0_out: endpoint { }; + }; + }; + }; + + qos_gpu_m0: qos@fdf35000 { + compatible = "syscon"; + reg = <0x0 0xfdf35000 0x0 0x20>; + }; + + qos_gpu_m1: qos@fdf35200 { + compatible = "syscon"; + reg = <0x0 0xfdf35200 0x0 0x20>; + }; + + qos_gpu_m2: qos@fdf35400 { + compatible = "syscon"; + reg = <0x0 0xfdf35400 0x0 0x20>; + }; + + qos_gpu_m3: qos@fdf35600 { + compatible = "syscon"; + reg = <0x0 0xfdf35600 0x0 0x20>; + }; + + qos_rga3_1: qos@fdf36000 { + compatible = "syscon"; + reg = <0x0 0xfdf36000 0x0 0x20>; + }; + + qos_sdio: qos@fdf39000 { + compatible = "syscon"; + reg = <0x0 0xfdf39000 0x0 0x20>; + }; + + qos_sdmmc: qos@fdf3d800 { + compatible = "syscon"; + reg = <0x0 0xfdf3d800 0x0 0x20>; + }; + + qos_usb3_1: qos@fdf3e000 { + compatible = "syscon"; + reg = <0x0 0xfdf3e000 0x0 0x20>; + }; + + qos_usb3_0: qos@fdf3e200 { + compatible = "syscon"; + reg = <0x0 0xfdf3e200 0x0 0x20>; + }; + + qos_usb2host_0: qos@fdf3e400 { + compatible = "syscon"; + reg = <0x0 0xfdf3e400 0x0 0x20>; + }; + + qos_usb2host_1: qos@fdf3e600 { + compatible = "syscon"; + reg = <0x0 0xfdf3e600 0x0 0x20>; + }; + + qos_fisheye0: qos@fdf40000 { + compatible = "syscon"; + reg = <0x0 0xfdf40000 0x0 0x20>; + }; + + qos_fisheye1: qos@fdf40200 { + compatible = "syscon"; + reg = <0x0 0xfdf40200 0x0 0x20>; + }; + + qos_isp0_mro: qos@fdf40400 { + compatible = "syscon"; + reg = <0x0 0xfdf40400 0x0 0x20>; + }; + + qos_isp0_mwo: qos@fdf40500 { + compatible = "syscon"; + reg = <0x0 0xfdf40500 0x0 0x20>; + }; + + qos_vicap_m0: qos@fdf40600 { + compatible = "syscon"; + reg = <0x0 0xfdf40600 0x0 0x20>; + }; + + qos_vicap_m1: qos@fdf40800 { + compatible = "syscon"; + reg = <0x0 0xfdf40800 0x0 0x20>; + }; + + qos_isp1_mwo: qos@fdf41000 { + compatible = "syscon"; + reg = <0x0 0xfdf41000 0x0 0x20>; + }; + + qos_isp1_mro: qos@fdf41100 { + compatible = "syscon"; + reg = <0x0 0xfdf41100 0x0 0x20>; + }; + + qos_rkvenc0_m0ro: qos@fdf60000 { + compatible = "syscon"; + reg = <0x0 0xfdf60000 0x0 0x20>; + }; + + qos_rkvenc0_m1ro: qos@fdf60200 { + compatible = "syscon"; + reg = <0x0 0xfdf60200 0x0 0x20>; + }; + + qos_rkvenc0_m2wo: qos@fdf60400 { + compatible = "syscon"; + reg = <0x0 0xfdf60400 0x0 0x20>; + }; + + qos_rkvenc1_m0ro: qos@fdf61000 { + compatible = "syscon"; + reg = <0x0 0xfdf61000 0x0 0x20>; + }; + + qos_rkvenc1_m1ro: qos@fdf61200 { + compatible = "syscon"; + reg = <0x0 0xfdf61200 0x0 0x20>; + }; + + qos_rkvenc1_m2wo: qos@fdf61400 { + compatible = "syscon"; + reg = <0x0 0xfdf61400 0x0 0x20>; + }; + + qos_rkvdec0: qos@fdf62000 { + compatible = "syscon"; + reg = <0x0 0xfdf62000 0x0 0x20>; + }; + + qos_rkvdec1: qos@fdf63000 { + compatible = "syscon"; + reg = <0x0 0xfdf63000 0x0 0x20>; + }; + + qos_av1: qos@fdf64000 { + compatible = "syscon"; + reg = <0x0 0xfdf64000 0x0 0x20>; + }; + + qos_iep: qos@fdf66000 { + compatible = "syscon"; + reg = <0x0 0xfdf66000 0x0 0x20>; + }; + + qos_jpeg_dec: qos@fdf66200 { + compatible = "syscon"; + reg = <0x0 0xfdf66200 0x0 0x20>; + }; + + qos_jpeg_enc0: qos@fdf66400 { + compatible = "syscon"; + reg = <0x0 0xfdf66400 0x0 0x20>; + }; + + qos_jpeg_enc1: qos@fdf66600 { + compatible = "syscon"; + reg = <0x0 0xfdf66600 0x0 0x20>; + }; + + qos_jpeg_enc2: qos@fdf66800 { + compatible = "syscon"; + reg = <0x0 0xfdf66800 0x0 0x20>; + }; + + qos_jpeg_enc3: qos@fdf66a00 { + compatible = "syscon"; + reg = <0x0 0xfdf66a00 0x0 0x20>; + }; + + qos_rga2_mro: qos@fdf66c00 { + compatible = "syscon"; + reg = <0x0 0xfdf66c00 0x0 0x20>; + }; + + qos_rga2_mwo: qos@fdf66e00 { + compatible = "syscon"; + reg = <0x0 0xfdf66e00 0x0 0x20>; + }; + + qos_rga3_0: qos@fdf67000 { + compatible = "syscon"; + reg = <0x0 0xfdf67000 0x0 0x20>; + }; + + qos_vdpu: qos@fdf67200 { + compatible = "syscon"; + reg = <0x0 0xfdf67200 0x0 0x20>; + }; + + qos_npu1: qos@fdf70000 { + compatible = "syscon"; + reg = <0x0 0xfdf70000 0x0 0x20>; + }; + + qos_npu2: qos@fdf71000 { + compatible = "syscon"; + reg = <0x0 0xfdf71000 0x0 0x20>; + }; + + qos_npu0_mwr: qos@fdf72000 { + compatible = "syscon"; + reg = <0x0 0xfdf72000 0x0 0x20>; + }; + + qos_npu0_mro: qos@fdf72200 { + compatible = "syscon"; + reg = <0x0 0xfdf72200 0x0 0x20>; + }; + + qos_mcu_npu: qos@fdf72400 { + compatible = "syscon"; + reg = <0x0 0xfdf72400 0x0 0x20>; + }; + + qos_hdcp0: qos@fdf80000 { + compatible = "syscon"; + reg = <0x0 0xfdf80000 0x0 0x20>; + }; + + qos_hdcp1: qos@fdf81000 { + compatible = "syscon"; + reg = <0x0 0xfdf81000 0x0 0x20>; + }; + + qos_hdmirx: qos@fdf81200 { + compatible = "syscon"; + reg = <0x0 0xfdf81200 0x0 0x20>; + }; + + qos_vop_m0: qos@fdf82000 { + compatible = "syscon"; + reg = <0x0 0xfdf82000 0x0 0x20>; + }; + + qos_vop_m1: qos@fdf82200 { + compatible = "syscon"; + reg = <0x0 0xfdf82200 0x0 0x20>; + }; + + dfi: dfi@fe060000 { + compatible = "rockchip,rk3588-dfi"; + reg = <0x00 0xfe060000 0x00 0x10000>; + rockchip,pmu_grf = <&pmu1_grf>; + status = "disabled"; + }; + + pcie2x1l1: pcie@fe180000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x30 0x3f>; + clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, + <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, + <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, + <0 0 0 2 &pcie2x1l1_intc 1>, + <0 0 0 3 &pcie2x1l1_intc 2>, + <0 0 0 4 &pcie2x1l1_intc 3>; + linux,pci-domain = <3>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x3000 &its0 0x3000 0x1000>; + num-lanes = <1>; + phys = <&combphy2_psu PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 + 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 + 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 + 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; + reg = <0x0 0xfe180000 0x0 0x10000>, + <0xa 0x40c00000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l1_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pcie2x1l2: pcie@fe190000 { + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x40 0x4f>; + clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, + <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, + <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + device_type = "pci"; + interrupts = , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, + <0 0 0 2 &pcie2x1l2_intc 1>, + <0 0 0 3 &pcie2x1l2_intc 2>, + <0 0 0 4 &pcie2x1l2_intc 3>; + linux,pci-domain = <4>; + num-ib-windows = <8>; + num-ob-windows = <8>; + num-viewport = <4>; + max-link-speed = <2>; + msi-map = <0x4000 &its0 0x4000 0x1000>; + num-lanes = <1>; + phys = <&combphy0_ps PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 + 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 + 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 + 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; + reg = <0x0 0xfe190000 0x0 0x10000>, + <0xa 0x41000000 0x0 0x400000>; + reg-names = "pcie-apb", "pcie-dbi"; + resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; + reset-names = "pcie", "periph"; + rockchip,pipe-grf = <&php_grf>; + status = "disabled"; + + pcie2x1l2_intc: legacy-interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + gmac_uio1: uio@fe1c0000 { + compatible = "rockchip,uio-gmac"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + rockchip,ethernet = <&gmac1>; + status = "disabled"; + }; + + gmac1: ethernet@fe1c0000 { + compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; + reg = <0x0 0xfe1c0000 0x0 0x10000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&sys_grf>; + rockchip,php_grf = <&php_grf>; + clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, + <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, + <&cru CLK_GMAC1_PTP_REF>; + clock-names = "stmmaceth", "clk_mac_ref", + "pclk_mac", "aclk_mac", + "ptp_ref"; + resets = <&cru SRST_A_GMAC1>; + reset-names = "stmmaceth"; + power-domains = <&power RK3588_PD_GMAC>; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&gmac1_stmmac_axi_setup>; + snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; + status = "disabled"; + + mdio1: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + gmac1_stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + gmac1_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + gmac1_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + sata0: sata@fe210000 { + compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; + reg = <0 0xfe210000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, + <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, + <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy0_ps PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + sata2: sata@fe230000 { + compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; + reg = <0 0xfe230000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, + <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, + <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; + clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; + interrupts = ; + interrupt-names = "hostc"; + phys = <&combphy2_psu PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + status = "disabled"; + }; + + sfc: spi@fe2b0000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe2b0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + assigned-clocks = <&cru SCLK_SFC>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc: mmc@fe2c0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2c0000 0x0 0x4000>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; + power-domains = <&power RK3588_PD_SDMMC>; + status = "disabled"; + }; + + sdio: mmc@fe2d0000 { + compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe2d0000 0x0 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdiom1_pins>; + power-domains = <&power RK3588_PD_SDIO>; + status = "disabled"; + }; + + sdhci: mmc@fe2e0000 { + compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; + reg = <0x0 0xfe2e0000 0x0 0x10000>; + interrupts = ; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, <200000000>; + clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TMCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + max-frequency = <200000000>; + status = "disabled"; + }; + + crypto: crypto@fe370000 { + compatible = "rockchip,rk3588-crypto"; + reg = <0x0 0xfe370000 0x0 0x2000>; + interrupts = ; + clocks = <&scmi_clk SCMI_ACLK_SECURE_NS>, <&scmi_clk SCMI_HCLK_SECURE_NS>, + <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>; + clock-names = "aclk", "hclk", "sclk", "pka"; + resets = <&scmi_reset SRST_CRYPTO_CORE>; + reset-names = "crypto-rst"; + status = "disabled"; + }; + + rng: rng@fe378000 { + compatible = "rockchip,trngv1"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + clock-names = "hclk_trng"; + resets = <&scmi_reset SRST_H_TRNG_NS>; + reset-names = "reset"; + status = "disabled"; + }; + + i2s0_8ch: i2s@fe470000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe470000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; + dmas = <&dmac0 0>, <&dmac0 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s0_sdi0 + &i2s0_sdi1 + &i2s0_sdi2 + &i2s0_sdi3 + &i2s0_sdo0 + &i2s0_sdo1>; + pinctrl-1 = <&i2s0_idle>; + pinctrl-2 = <&i2s0_lrck + &i2s0_sclk>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s1_8ch: i2s@fe480000 { + compatible = "rockchip,rk3588-i2s-tdm"; + reg = <0x0 0xfe480000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; + clock-names = "mclk_tx", "mclk_rx", "hclk"; + dmas = <&dmac0 2>, <&dmac0 3>; + dma-names = "tx", "rx"; + resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; + reset-names = "tx-m", "rx-m"; + rockchip,clk-trcm = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m0_lrck + &i2s1m0_sclk + &i2s1m0_sdi0 + &i2s1m0_sdi1 + &i2s1m0_sdi2 + &i2s1m0_sdi3 + &i2s1m0_sdo0 + &i2s1m0_sdo1 + &i2s1m0_sdo2 + &i2s1m0_sdo3>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s2_2ch: i2s@fe490000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe490000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 0>, <&dmac1 1>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s2m1_sdi + &i2s2m1_sdo>; + pinctrl-1 = <&i2s2m1_idle>; + pinctrl-2 = <&i2s2m1_lrck + &i2s2m1_sclk>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2s3_2ch: i2s@fe4a0000 { + compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xfe4a0000 0x0 0x1000>; + interrupts = ; + clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 2>, <&dmac1 3>; + dma-names = "tx", "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + rockchip,clk-trcm = <1>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&i2s3_sdi + &i2s3_sdo>; + pinctrl-1 = <&i2s3_idle>; + pinctrl-2 = <&i2s3_lrck + &i2s3_sclk>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm0: pdm@fe4b0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4b0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; + clock-names = "pdm_clk", "pdm_hclk"; + dmas = <&dmac0 4>; + dma-names = "rx"; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdm0m0_sdi0 + &pdm0m0_sdi1 + &pdm0m0_sdi2 + &pdm0m0_sdi3>; + pinctrl-1 = <&pdm0m0_idle>; + pinctrl-2 = <&pdm0m0_clk + &pdm0m0_clk1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pdm1: pdm@fe4c0000 { + compatible = "rockchip,rk3588-pdm"; + reg = <0x0 0xfe4c0000 0x0 0x1000>; + clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; + clock-names = "pdm_clk", "pdm_hclk"; + assigned-clocks = <&cru MCLK_PDM1>; + assigned-clock-parents = <&cru PLL_AUPLL>; + dmas = <&dmac1 4>; + dma-names = "rx"; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default", "idle", "clk"; + pinctrl-0 = <&pdm1m0_sdi0 + &pdm1m0_sdi1 + &pdm1m0_sdi2 + &pdm1m0_sdi3>; + pinctrl-1 = <&pdm1m0_idle>; + pinctrl-2 = <&pdm1m0_clk + &pdm1m0_clk1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + vad: vad@fe4d0000 { + compatible = "rockchip,rk3588-vad"; + reg = <0x0 0xfe4d0000 0x0 0x1000>; + reg-names = "vad"; + clocks = <&cru HCLK_VAD>; + clock-names = "hclk"; + interrupts = ; + rockchip,audio-src = <0>; + rockchip,det-channel = <0>; + rockchip,mode = <0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac0 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + assigned-clocks = <&cru CLK_SPDIF0_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + interrupts = ; + dmas = <&dmac1 5>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + assigned-clocks = <&cru CLK_SPDIF1_SRC>; + assigned-clock-parents = <&cru PLL_AUPLL>; + power-domains = <&power RK3588_PD_AUDIO>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif1m0_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + acdcdig_dsm: codec-digital@fe500000 { + compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; + reg = <0x0 0xfe500000 0x0 0x1000>; + clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; + clock-names = "dac", "pclk"; + power-domains = <&power RK3588_PD_AUDIO>; + resets = <&cru SRST_DAC_ACDCDIG>; + reset-names = "reset" ; + rockchip,grf = <&sys_grf>; + rockchip,pwm-output-mode; + pinctrl-names = "default"; + pinctrl-0 = <&auddsm_pins>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + hwlock: hwspinlock@fe5a0000 { + compatible = "rockchip,hwspinlock"; + reg = <0 0xfe5a0000 0 0x100>; + #hwlock-cells = <1>; + }; + + gic: interrupt-controller@fe600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ + <0x0 0xfe680000 0 0x100000>; /* GICR */ + interrupts = ; + its0: msi-controller@fe640000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfe640000 0x0 0x20000>; + }; + its1: msi-controller@fe660000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0x0 0xfe660000 0x0 0x20000>; + }; + }; + + dmac0: dma-controller@fea10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea10000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + dmac1: dma-controller@fea30000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfea30000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + can0: can@fea50000 { + compatible = "rockchip,can-2.0"; + reg = <0x0 0xfea50000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can0m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can1: can@fea60000 { + compatible = "rockchip,can-2.0"; + reg = <0x0 0xfea60000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can1m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + can2: can@fea70000 { + compatible = "rockchip,can-2.0"; + reg = <0x0 0xfea70000 0x0 0x1000>; + interrupts = ; + clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; + clock-names = "baudclk", "apb_pclk"; + resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; + reset-names = "can", "can-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&can2m0_pins>; + tx-fifo-depth = <1>; + rx-fifo-depth = <6>; + status = "disabled"; + }; + + hw_decompress: decompress@fea80000 { + compatible = "rockchip,hw-decompress"; + reg = <0x0 0xfea80000 0x0 0x1000>; + interrupts = ; + clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; + clock-names = "aclk", "dclk", "pclk"; + resets = <&cru SRST_D_DECOM>; + reset-names = "dresetn"; + status = "disabled"; + }; + + i2c1: i2c@fea90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfea90000 0x0 0x1000>; + clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m0_xfer>; + resets = <&cru SRST_I2C1>, <&cru SRST_P_I2C1>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@feaa0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeaa0000 0x0 0x1000>; + clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m0_xfer>; + resets = <&cru SRST_I2C2>, <&cru SRST_P_I2C2>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@feab0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeab0000 0x0 0x1000>; + clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + resets = <&cru SRST_I2C3>, <&cru SRST_P_I2C3>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@feac0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeac0000 0x0 0x1000>; + clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m0_xfer>; + resets = <&cru SRST_I2C4>, <&cru SRST_P_I2C4>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@fead0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfead0000 0x0 0x1000>; + clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5m0_xfer>; + resets = <&cru SRST_I2C5>, <&cru SRST_P_I2C5>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rktimer: timer@feae0000 { + compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; + reg = <0x0 0xfeae0000 0x0 0x20>; + interrupts = ; + clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; + clock-names = "pclk", "timer"; + }; + + wdt: watchdog@feaf0000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xfeaf0000 0x0 0x100>; + clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; + clock-names = "tclk", "pclk"; + interrupts = ; + status = "disabled"; + }; + + spi0: spi@feb00000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb00000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 14>, <&dmac0 15>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi1: spi@feb10000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb10000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac0 16>, <&dmac0 17>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi2: spi@feb20000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb20000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 15>, <&dmac1 16>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; + num-cs = <2>; + status = "disabled"; + }; + + spi3: spi@feb30000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfeb30000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac1 17>, <&dmac1 18>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; + num-cs = <2>; + status = "disabled"; + }; + + uart1: serial@feb40000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb40000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 8>, <&dmac0 9>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m1_xfer>; + status = "disabled"; + }; + + uart2: serial@feb50000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb50000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 10>, <&dmac0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + status = "disabled"; + }; + + uart3: serial@feb60000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb60000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac0 12>, <&dmac0 13>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m1_xfer>; + status = "disabled"; + }; + + uart4: serial@feb70000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb70000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 9>, <&dmac1 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer>; + status = "disabled"; + }; + + uart5: serial@feb80000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb80000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 11>, <&dmac1 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m1_xfer>; + status = "disabled"; + }; + + uart6: serial@feb90000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeb90000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac1 13>, <&dmac1 14>; + pinctrl-names = "default"; + pinctrl-0 = <&uart6m1_xfer>; + status = "disabled"; + }; + + uart7: serial@feba0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfeba0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 7>, <&dmac2 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart7m1_xfer>; + status = "disabled"; + }; + + uart8: serial@febb0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebb0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 9>, <&dmac2 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart8m1_xfer>; + status = "disabled"; + }; + + uart9: serial@febc0000 { + compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; + reg = <0x0 0xfebc0000 0x0 0x100>; + interrupts = ; + clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; + clock-names = "baudclk", "apb_pclk"; + reg-shift = <2>; + reg-io-width = <4>; + dmas = <&dmac2 11>, <&dmac2 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart9m1_xfer>; + status = "disabled"; + }; + + pwm4: pwm@febd0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm4m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm5: pwm@febd0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm5m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm6: pwm@febd0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm6m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm7: pwm@febd0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebd0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm7m0_pins>; + clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm8: pwm@febe0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm8m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm9: pwm@febe0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm9m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm10: pwm@febe0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm10m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm11: pwm@febe0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebe0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm11m0_pins>; + clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm12: pwm@febf0000 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0000 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm12m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm13: pwm@febf0010 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0010 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm13m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm14: pwm@febf0020 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0020 0x0 0x10>; + interrupts = ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm14m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + pwm15: pwm@febf0030 { + compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; + reg = <0x0 0xfebf0030 0x0 0x10>; + interrupts = , + ; + #pwm-cells = <3>; + pinctrl-names = "active"; + pinctrl-0 = <&pwm15m0_pins>; + clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; + clock-names = "pwm", "pclk"; + status = "disabled"; + }; + + tsadc: tsadc@fec00000 { + compatible = "rockchip,rk3588-tsadc"; + reg = <0x0 0xfec00000 0x0 0x400>; + interrupts = ; + clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + assigned-clocks = <&cru CLK_TSADC>; + assigned-clock-rates = <2000000>; + resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; + reset-names = "tsadc", "tsadc-apb"; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <120000>; + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + pinctrl-names = "gpio", "otpout"; + pinctrl-0 = <&tsadc_gpio_func>; + pinctrl-1 = <&tsadc_shut>; + status = "disabled"; + }; + + saradc: saradc@fec10000 { + compatible = "rockchip,rk3588-saradc"; + reg = <0x0 0xfec10000 0x0 0x10000>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + mailbox0: mailbox@fec60000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfec60000 0x0 0x200>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX0>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + mailbox1: mailbox@fec70000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfec70000 0x0 0x200>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX1>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + i2c6: i2c@fec80000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec80000 0x0 0x1000>; + clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + resets = <&cru SRST_I2C6>, <&cru SRST_P_I2C6>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@fec90000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfec90000 0x0 0x1000>; + clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + resets = <&cru SRST_I2C7>, <&cru SRST_P_I2C7>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@feca0000 { + compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; + reg = <0x0 0xfeca0000 0x0 0x1000>; + clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; + clock-names = "i2c", "pclk"; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&i2c8m0_xfer>; + resets = <&cru SRST_I2C8>, <&cru SRST_P_I2C8>; + reset-names = "i2c", "apb"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@fecb0000 { + compatible = "rockchip,rk3066-spi"; + reg = <0x0 0xfecb0000 0x0 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac2 13>, <&dmac2 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; + num-cs = <2>; + status = "disabled"; + }; + + otp: otp@fecc0000 { + compatible = "rockchip,rk3588-otp"; + reg = <0x0 0xfecc0000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; + clock-names = "otpc", "apb", "arb", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, + <&cru SRST_OTPC_ARB>; + reset-names = "otpc", "apb", "arb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + package_serial_number_high: package-serial-number-high@5 { + reg = <0x05 0x1>; + bits = <0 1>; + }; + package_serial_number_low: package-serial-number-low@6 { + reg = <0x06 0x1>; + bits = <5 3>; + }; + specification_serial_number: specification-serial-number@6 { + reg = <0x06 0x1>; + bits = <0 5>; + }; + otp_id: id@7 { + reg = <0x07 0x10>; + }; + otp_cpu_version: cpu-version@1c { + reg = <0x1c 0x1>; + bits = <3 3>; + }; + cpub0_leakage: cpub0-leakage@17 { + reg = <0x17 0x1>; + }; + cpub1_leakage: cpub1-leakage@18 { + reg = <0x18 0x1>; + }; + cpul_leakage: cpul-leakage@19 { + reg = <0x19 0x1>; + }; + log_leakage: log-leakage@1a { + reg = <0x1a 0x1>; + }; + gpu_leakage: gpu-leakage@1b { + reg = <0x1b 0x1>; + }; + npu_leakage: npu-leakage@28 { + reg = <0x28 0x1>; + }; + codec_leakage: codec-leakage@29 { + reg = <0x29 0x1>; + }; + cpul_opp_info: cpul-opp-info@3d { + reg = <0x3d 0x6>; + }; + cpub01_opp_info: cpub01-opp-info@43 { + reg = <0x43 0x6>; + }; + cpub23_opp_info: cpub23-opp-info@49 { + reg = <0x49 0x6>; + }; + gpu_opp_info: gpu-opp-info@4f { + reg = <0x4f 0x6>; + }; + npu_opp_info: npu-opp-info@55 { + reg = <0x55 0x6>; + }; + dmc_opp_info: dmc-opp-info@5b { + reg = <0x5b 0x6>; + }; + vop_opp_info: vop-opp-info@61 { + reg = <0x61 0x6>; + }; + venc_opp_info: venc-opp-info@67 { + reg = <0x67 0x6>; + }; + }; + + mailbox2: mailbox@fece0000 { + compatible = "rockchip,rk3588-mailbox", + "rockchip,rk3368-mailbox"; + reg = <0x0 0xfece0000 0x0 0x200>; + interrupts = , + , + , + ; + clocks = <&cru PCLK_MAILBOX2>; + clock-names = "pclk_mailbox"; + #mbox-cells = <1>; + status = "disabled"; + }; + + dmac2: dma-controller@fed10000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xfed10000 0x0 0x4000>; + interrupts = , + ; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + arm,pl330-periph-burst; + }; + + hdptxphy0: phy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + resets = <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, + <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy0_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + + hdptxphy_hdmi0: hdmiphy@fed60000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed60000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; + clock-names = "ref", "apb"; + resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, + <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, + <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, + <&cru SRST_HDPTX0_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy0_grf>; + #phy-cells = <0>; + status = "disabled"; + + hdptxphy_hdmi_clk0: clk-port { + #clock-cells = <0>; + status = "okay"; + }; + }; + + hdptxphy_hdmi1: hdmiphy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy-hdmi"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + #phy-cells = <0>; + status = "disabled"; + + hdptxphy_hdmi_clk1: clk-port { + #clock-cells = <0>; + status = "okay"; + }; + }; + + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + usbdp_phy0: phy@fed80000 { + compatible = "rockchip,rk3588-usbdp-phy"; + reg = <0x0 0xfed80000 0x0 0x10000>; + rockchip,u2phy-grf = <&usb2phy0_grf>; + rockchip,usb-grf = <&usb_grf>; + rockchip,usbdpphy-grf = <&usbdpphy0_grf>; + rockchip,vo-grf = <&vo0_grf>; + clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, + <&cru CLK_USBDP_PHY0_IMMORTAL>, + <&cru PCLK_USBDPPHY0>, + <&u2phy0>; + clock-names = "refclk", "immortal", "pclk", "utmi"; + resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, + <&cru SRST_USBDP_COMBO_PHY0_CMN>, + <&cru SRST_USBDP_COMBO_PHY0_LANE>, + <&cru SRST_USBDP_COMBO_PHY0_PCS>, + <&cru SRST_P_USBDPPHY0>; + reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; + status = "disabled"; + + usbdp_phy0_dp: dp-port { + #phy-cells = <0>; + status = "disabled"; + }; + + usbdp_phy0_u3: u3-port { + #phy-cells = <0>; + status = "disabled"; + }; + }; + + mipidcphy0: phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy0_grf>; + clocks = <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <0>; + status = "okay"; + }; + + mipidcphy1: phy@fedb0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfedb0000 0x0 0x10000>; + rockchip,grf = <&mipidcphy1_grf>; + clocks = <&cru PCLK_MIPI_DCPHY1>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1>, + <&cru SRST_P_MIPI_DCPHY1_GRF>, + <&cru SRST_S_MIPI_DCPHY1>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + #phy-cells = <0>; + status = "okay"; + }; + + csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc0000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY0>; + clock-names = "pclk"; + resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>; + reset-names = "srst_csiphy0", "srst_p_csiphy0"; + rockchip,grf = <&mipidphy0_grf>; + rockchip,sys_grf = <&sys_grf>; + status = "okay"; + }; + + csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 { + compatible = "rockchip,rk3588-csi2-dphy-hw"; + reg = <0x0 0xfedc8000 0x0 0x8000>; + clocks = <&cru PCLK_CSIPHY1>; + clock-names = "pclk"; + resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>; + reset-names = "srst_csiphy1", "srst_p_csiphy1"; + rockchip,grf = <&mipidphy1_grf>; + rockchip,sys_grf = <&sys_grf>; + status = "okay"; + }; + + combphy0_ps: phy@fee00000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee00000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy0_grf>; + status = "disabled"; + }; + + combphy2_psu: phy@fee20000 { + compatible = "rockchip,rk3588-naneng-combphy"; + reg = <0x0 0xfee20000 0x0 0x100>; + #phy-cells = <1>; + clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, + <&cru PCLK_PHP_ROOT>; + clock-names = "refclk", "apbclk", "phpclk"; + assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; + assigned-clock-rates = <100000000>; + resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; + reset-names = "combphy-apb", "combphy"; + rockchip,pipe-grf = <&php_grf>; + rockchip,pipe-phy-grf = <&pipe_phy2_grf>; + rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; + status = "disabled"; + }; + + syssram: sram@ff001000 { + compatible = "mmio-sram"; + reg = <0x0 0xff001000 0x0 0xef000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xff001000 0xef000>; + /* start address and size should be 4k algin */ + rkvdec0_sram: rkvdec-sram@0 { + reg = <0x0 0x78000>; + }; + rkvdec1_sram: rkvdec-sram@78000 { + reg = <0x78000 0x77000>; + }; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3588-pinctrl"; + rockchip,grf = <&ioc>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@fd8a0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfd8a0000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@fec20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec20000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@fec30000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec30000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@fec40000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec40000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@fec50000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xfec50000 0x0 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rk3588s-pinctrl.dtsi" diff --git a/rockchip-pinconf.dtsi b/rockchip-pinconf.dtsi new file mode 100644 index 0000000..72d6445 --- /dev/null +++ b/rockchip-pinconf.dtsi @@ -0,0 +1,415 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +&pinctrl { + /omit-if-no-ref/ + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 { + bias-disable; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 { + bias-disable; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 { + bias-disable; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 { + bias-disable; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 { + bias-disable; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 { + bias-disable; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 { + bias-disable; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 { + bias-disable; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 { + bias-disable; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 { + bias-disable; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 { + bias-disable; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 { + bias-disable; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 { + bias-disable; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 { + bias-disable; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 { + bias-disable; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 { + bias-disable; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 { + bias-pull-up; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 { + bias-pull-up; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 { + bias-pull-up; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 { + bias-pull-up; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 { + bias-pull-up; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 { + bias-pull-up; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 { + bias-pull-up; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 { + bias-pull-up; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 { + bias-pull-up; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 { + bias-pull-up; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 { + bias-pull-up; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 { + bias-pull-up; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 { + bias-pull-up; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 { + bias-pull-up; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 { + bias-pull-up; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 { + bias-pull-up; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 { + bias-pull-down; + drive-strength = <0>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 { + bias-pull-down; + drive-strength = <1>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 { + bias-pull-down; + drive-strength = <2>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 { + bias-pull-down; + drive-strength = <3>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 { + bias-pull-down; + drive-strength = <4>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 { + bias-pull-down; + drive-strength = <5>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 { + bias-pull-down; + drive-strength = <6>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 { + bias-pull-down; + drive-strength = <7>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 { + bias-pull-down; + drive-strength = <8>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 { + bias-pull-down; + drive-strength = <9>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 { + bias-pull-down; + drive-strength = <10>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 { + bias-pull-down; + drive-strength = <11>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 { + bias-pull-down; + drive-strength = <12>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 { + bias-pull-down; + drive-strength = <13>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 { + bias-pull-down; + drive-strength = <14>; + }; + + /omit-if-no-ref/ + pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 { + bias-pull-down; + drive-strength = <15>; + }; + + /omit-if-no-ref/ + pcfg_pull_up_smt: pcfg-pull-up-smt { + bias-pull-up; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_down_smt: pcfg-pull-down-smt { + bias-pull-down; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_smt: pcfg-pull-none-smt { + bias-disable; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt { + bias-disable; + drive-strength = <0>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt { + bias-disable; + drive-strength = <1>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt { + bias-disable; + drive-strength = <2>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt { + bias-disable; + drive-strength = <3>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt { + bias-disable; + drive-strength = <4>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt { + bias-disable; + drive-strength = <5>; + input-schmitt-enable; + }; + + /omit-if-no-ref/ + pcfg_output_high: pcfg-output-high { + output-high; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_up: pcfg-output-high-pull-up { + output-high; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_down: pcfg-output-high-pull-down { + output-high; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_high_pull_none: pcfg-output-high-pull-none { + output-high; + bias-disable; + }; + + /omit-if-no-ref/ + pcfg_output_low: pcfg-output-low { + output-low; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_up: pcfg-output-low-pull-up { + output-low; + bias-pull-up; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_down: pcfg-output-low-pull-down { + output-low; + bias-pull-down; + }; + + /omit-if-no-ref/ + pcfg_output_low_pull_none: pcfg-output-low-pull-none { + output-low; + bias-disable; + }; +};