rockchip

2025-04-28 11:36:59 +08:00
commit 5dd7a8972b
945 changed files with 332963 additions and 0 deletions
--- a/rk356x/rp-lcd-mipi0-5.5-1080-1920.dtsi
+++ b/rk356x/rp-lcd-mipi0-5.5-1080-1920.dtsi
@@ -0,0 +1,162 @@
+#include "rp-lcd-hdmi.dtsi"
+#define RP_SINGLE_LCD
+
+
+
+&dsi0 {
+    status = "okay";
+    // rockchip,lane-rate = <480>;
+    dsi0_panel:panel@0 {
+        status = "okay";
+        compatible = "simple-panel-dsi";
+        reg = <0>;
+        dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+        MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
+        dsi,format = <MIPI_DSI_FMT_RGB888>;
+        dsi,lanes = <4>;
+        reset-delay-ms = <20>;
+        init-delay-ms = <20>;
+        enable-delay-ms = <120>;
+        prepare-delay-ms = <120>;
+        
+        /**
+         * power-supply = <>;
+         * reset-gpios = <>;
+         *
+         * lcd reset pin and power supply
+         * please refer to ***-lcd-gpio.dtsi
+         * that included in main dts.
+         */
+        
+        panel-init-sequence = [
+            15 00 02 FE 00
+            15 00 02 C2 08
+            15 00 02 35 00
+            15 00 02 53 20
+            15 00 02 51 FF
+            
+            05 78 01 01    //add for reboot init fail
+            
+            05 78 01 29
+            05 78 01 11
+        ];
+
+        panel-exit-sequence = [
+            05 00 01 28
+            05 78 01 10
+        ];
+
+        disp_timings0: display-timings {
+            native-mode = <&dsi0_timing0>;
+            dsi0_timing0:timing0 {
+                clock-frequency = <138000000>;
+                hactive = <1080>;
+                vactive = <1920>;
+                hback-porch = <30>;
+                hfront-porch = <36>;
+                vback-porch = <6>;
+                vfront-porch = <6>;
+                hsync-len = <4>;
+                vsync-len = <2>;
+                hsync-active = <0>;
+                vsync-active = <0>;
+                de-active = <0>;
+                pixelclk-active = <0>;
+            };
+        };
+
+        ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                panel_in_dsi:endpoint {
+                    remote-endpoint = <&dsi_out_panel>;
+                };
+            };
+        };
+    };
+
+    ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        port@1 {
+            reg = <1>;
+            dsi_out_panel:endpoint {
+                remote-endpoint = <&panel_in_dsi>;
+            };
+        };
+    };
+
+};
+
+
+&dsi0_in_vp0 {
+    status = "disabled";
+};
+
+&dsi0_in_vp1 {
+    status = "okay";
+};
+
+&video_phy0 {
+    status = "okay";
+};
+
+&route_dsi0 {
+    status = "okay";
+    connect = <&vp1_out_dsi0>;
+};
+
+
+&gt9xx {
+    status = "okay";
+    compatible = "goodix,gt9xx";
+    reg = <0x5d>;
+    gtp_resolution_x = <1080>;
+    gtp_resolution_y = <1920>;
+    gtp_int_tarigger = <1>;
+    gtp_change_x2y = <0>;
+    gtp_overturn_x = <0>;
+    gtp_overturn_y = <0>;
+    gtp_send_cfg = <1>;
+    gtp_touch_wakeup = <1>;
+
+    /**
+     * goodix_rst_gpio = <>;
+     * goodix_irq_gpio = <>;
+     *
+     * touch panel interrupt and reset pin
+     * please refer to ***-lcd-gpio.dtsi
+     * that included in main dts.
+     */
+
+    goodix,cfg-group0 = [
+        47 38 04 80 07 0A 05 00 
+        01 08 28 05 50 32 03 05 
+        00 00 00 00 00 00 00 00 
+        00 00 00 8B 2B 0D 17 15 
+        31 0D 00 00 00 9A 03 2D 
+        00 00 00 00 00 03 64 32 
+        00 00 00 0F 2C 94 C5 02 
+        07 00 00 04 9E 10 00 82 
+        14 00 6B 19 00 57 20 00 
+        4A 27 00 4A 00 00 00 00 
+        00 00 00 00 00 00 00 00 
+        00 00 00 00 00 00 00 00 
+        00 00 00 00 00 00 00 00 
+        00 00 00 00 00 00 00 00 
+        1A 18 16 14 12 10 0E 0C 
+        0A 08 06 04 02 FF 00 00 
+        00 00 00 00 00 00 00 00 
+        00 00 00 00 00 00 00 02 
+        04 06 08 0A 0C 0F 10 12 
+        13 26 24 22 21 20 1F 1E 
+        1D 1C 18 16 FF FF FF FF 
+        00 00 00 00 00 00 00 00 
+        00 00 00 00 00 00 00 00 
+        8C 01
+    ];    
+};