rockchip
This commit is contained in:
zhangpeng
473
rk3568-evb6-ddr3-v10.dtsi
Normal file
473
rk3568-evb6-ddr3-v10.dtsi
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@@ -0,0 +1,473 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3568.dtsi"
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#include "rk3568-evb.dtsi"
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/ {
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model = "Rockchip RK3568 EVB6 DDR3 V10 Board";
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compatible = "rockchip,rk3568-evb6-ddr3-v10", "rockchip,rk3568";
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rk_headset: rk-headset {
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compatible = "rockchip_headset";
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headset_gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&hp_det>;
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};
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vcc3v3_pcie: gpio-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3_pcie";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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enable-active-high;
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gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <5000>;
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vin-supply = <&dc_12v>;
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};
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vcc_camera: vcc-camera-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&camera_pwr>;
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regulator-name = "vcc_camera";
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&bt_sound {
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status = "disabled";
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simple-audio-card,cpu {
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sound-dai = <&i2s2_2ch>;
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};
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};
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&combphy0_us {
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status = "okay";
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};
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&combphy1_usq {
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rockchip,dis-u3otg1-port;
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status = "okay";
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};
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&combphy2_psq {
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status = "okay";
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};
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/*
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* video_phy0 needs to be enabled
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* when dsi0 is enabled
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*/
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&dsi0 {
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status = "okay";
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};
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&dsi0_in_vp0 {
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status = "disabled";
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};
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&dsi0_in_vp1 {
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status = "okay";
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};
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&dsi0_panel {
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power-supply = <&vcc3v3_lcd0_n>;
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};
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/*
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* video_phy1 needs to be enabled
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* when dsi1 is enabled
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*/
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&dsi1 {
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status = "disabled";
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};
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&dsi1_in_vp0 {
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status = "disabled";
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};
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&dsi1_in_vp1 {
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status = "disabled";
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};
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&dsi1_panel {
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power-supply = <&vcc3v3_lcd1_n>;
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};
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/*
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* power-supply should switche to vcc3v3_lcd1_n
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* when mipi panel is connected to dsi1.
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*/
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>1x {
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power-supply = <&vcc3v3_lcd0_n>;
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};
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&i2c2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2m1_xfer>;
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mxc6655xa: mxc6655xa@15 {
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status = "okay";
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compatible = "gs_mxc6655xa";
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pinctrl-names = "default";
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pinctrl-0 = <&mxc6655xa_irq_gpio>;
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reg = <0x15>;
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irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>;
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irq_enable = <0>;
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poll_delay_ms = <30>;
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type = <SENSOR_TYPE_ACCEL>;
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power-off-in-suspend = <1>;
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layout = <4>;
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};
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};
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&i2c4 {
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status = "okay";
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os04a10: os04a10@36 {
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compatible = "ovti,os04a10";
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reg = <0x36>;
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clocks = <&cru CLK_CAM0_OUT>;
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clock-names = "xvclk";
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power-domains = <&power RK3568_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clkout0>;
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reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
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pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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/* power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; */
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "CMK-OT1607-FV1";
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/* rockchip,camera-module-lens-name = "M12-4IR-4MP-F16"; */
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rockchip,camera-module-lens-name = "M12-40IRC-4MP-F16";
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port {
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ucam_out0: endpoint {
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remote-endpoint = <&mipi_in_ucam0>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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gc8034: gc8034@37 {
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compatible = "galaxycore,gc8034";
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reg = <0x37>;
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clocks = <&cru CLK_CAM0_OUT>;
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clock-names = "xvclk";
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power-domains = <&power RK3568_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clkout0>;
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reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
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pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>;
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rockchip,grf = <&grf>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "RK-CMK-8M-2-v1";
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rockchip,camera-module-lens-name = "CK8401";
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port {
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gc8034_out: endpoint {
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remote-endpoint = <&mipi_in_ucam1>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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ov5695: ov5695@36 {
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status = "okay";
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compatible = "ovti,ov5695";
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reg = <0x36>;
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clocks = <&cru CLK_CAM0_OUT>;
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clock-names = "xvclk";
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power-domains = <&power RK3568_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&cam_clkout0>;
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reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_LOW>;
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pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "TongJu";
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rockchip,camera-module-lens-name = "CHT842-MD";
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port {
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ov5695_out: endpoint {
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remote-endpoint = <&mipi_in_ucam2>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&i2c5 {
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status = "disabled";
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/delete-node/ mxc6655xa@15;
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};
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&i2s2_2ch {
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pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>;
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rockchip,bclk-fs = <32>;
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status = "disabled";
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};
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&csi2_dphy_hw {
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status = "okay";
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};
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ucam_out0>;
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data-lanes = <1 2 3 4>;
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};
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mipi_in_ucam1: endpoint@2 {
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reg = <2>;
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remote-endpoint = <&gc8034_out>;
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data-lanes = <1 2 3 4>;
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};
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mipi_in_ucam2: endpoint@3 {
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reg = <3>;
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remote-endpoint = <&ov5695_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&isp0_in>;
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};
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};
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};
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};
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&rkisp {
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status = "okay";
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};
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&rkisp_mmu {
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status = "okay";
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};
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&rkisp_vir0 {
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&csidphy_out>;
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};
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};
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};
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&video_phy0 {
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status = "okay";
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};
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&video_phy1 {
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status = "disabled";
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};
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&pcie30phy {
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status = "okay";
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};
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&pcie2x1 {
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reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pcie3x1 {
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rockchip,bifurcation;
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reset-gpios = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pcie3x2 {
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rockchip,bifurcation;
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reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
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vpcie3v3-supply = <&vcc3v3_pcie>;
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status = "okay";
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};
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&pinctrl {
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cam {
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camera_pwr: camera-pwr {
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rockchip,pins =
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/* camera power en */
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<0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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headphone {
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hp_det: hp-det {
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rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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sdio-pwrseq {
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wifi_enable_h: wifi-enable-h {
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rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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wifi_32k: wifi-32k {
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rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
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};
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};
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wireless-wlan {
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wifi_host_wake_irq: wifi-host-wake-irq {
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rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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wireless-bluetooth {
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uart1_gpios: uart1-gpios {
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rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&route_dsi0 {
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status = "okay";
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connect = <&vp1_out_dsi0>;
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};
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&sdmmc1 {
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max-frequency = <150000000>;
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no-sd;
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no-mmc;
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-sdio-irq;
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keep-power-in-suspend;
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mmc-pwrseq = <&sdio_pwrseq>;
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non-removable;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
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sd-uhs-sdr104;
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status = "okay";
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};
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&sdmmc2 {
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status = "disabled";
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};
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&sdio_pwrseq {
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clocks = <&pmucru CLK_RTC_32K>;
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pinctrl-0 = <&wifi_enable_h &wifi_32k>;
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/*
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* On the module itself this is one of these (depending
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* on the actual card populated):
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* - SDIO_RESET_L_WL_REG_ON
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* - PDN (power down when low)
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*/
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reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
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};
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&spdif_8ch {
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status = "disabled";
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
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};
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&usbhost_dwc3 {
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phys = <&u2phy0_host>;
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phy-names = "usb2-phy";
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maximum-speed = "high-speed";
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status = "okay";
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};
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&vcc3v3_lcd0_n {
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gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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&vcc3v3_lcd1_n {
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gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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&wireless_wlan {
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pinctrl-names = "default";
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pinctrl-0 = <&wifi_host_wake_irq>;
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WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
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WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
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};
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&wireless_bluetooth {
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compatible = "bluetooth-platdata";
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clocks = <&pmucru CLK_RTC_32K>;
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clock-names = "ext_clock";
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//wifi-bt-power-toggle;
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uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
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pinctrl-names = "default", "rts_gpio";
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pinctrl-0 = <&uart1m0_rtsn>;
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pinctrl-1 = <&uart1_gpios>;
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BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
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BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
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BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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&gmac1 {
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phy-mode = "rgmii";
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clock_in_out = "output";
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snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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/* Reset time is 20ms, 100ms for rtl8211f */
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m0_miim
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&gmac1m0_tx_bus2_level3
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&gmac1m0_rx_bus2
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&gmac1m0_rgmii_clk_level2
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&gmac1m0_rgmii_bus_level3>;
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tx_delay = <0x46>;
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rx_delay = <0x2f>;
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phy-handle = <&rgmii_phy1>;
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status = "okay";
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};
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&mdio1 {
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rgmii_phy1: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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};
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};
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