rockchip
This commit is contained in:
zhangpeng
400
rk3568-dram-default-timing.dtsi
Normal file
400
rk3568-dram-default-timing.dtsi
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@@ -0,0 +1,400 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/rk3568-dram.h>
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/ {
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ddr3_params: ddr3-params {
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/* version information */
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version = <0x100>;
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expanded_version = <IGNORE_THIS>;
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reserved = <IGNORE_THIS>;
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/* freq info, freq_0 is final frequency, unit: MHz */
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freq_0 = <1056>;
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freq_1 = <324>;
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freq_2 = <528>;
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freq_3 = <780>;
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freq_4 = <IGNORE_THIS>;
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freq_5 = <IGNORE_THIS>;
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/* power save setting */
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pd_idle = <13>;
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sr_idle = <93>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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pd_dis_freq = <1066>;
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sr_dis_freq = <800>;
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dram_dll_dis_freq = <300>;
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phy_dll_dis_freq = <IGNORE_THIS>;
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/* drv when odt on */
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phy_dq_drv_odten = <33>;
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phy_ca_drv_odten = <33>;
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phy_clk_drv_odten = <33>;
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dram_dq_drv_odten = <34>;
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/* drv when odt off */
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phy_dq_drv_odtoff = <33>;
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phy_ca_drv_odtoff = <33>;
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phy_clk_drv_odtoff = <33>;
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dram_dq_drv_odtoff = <34>;
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/* odt info */
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dram_odt = <120>;
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phy_odt = <167>;
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phy_odt_puup_en = <1>;
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phy_odt_pudn_en = <1>;
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/* odt enable freq */
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dram_dq_odt_en_freq = <333>;
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phy_odt_en_freq = <333>;
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/* slew rate when odt enable */
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phy_dq_sr_odten = <0xf>;
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phy_ca_sr_odten = <0x3>;
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phy_clk_sr_odten = <0x0>;
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/* slew rate when odt disable */
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phy_dq_sr_odtoff = <0xf>;
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phy_ca_sr_odtoff = <0x3>;
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phy_clk_sr_odtoff = <0x0>;
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/* ssmod setting*/
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ssmod_downspread = <0>;
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ssmod_div = <0>;
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ssmod_spread = <0>;
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/* 2T mode */
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mode_2t = <IGNORE_THIS>;
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/* speed bin */
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speed_bin = <DDR3_DEFAULT>;
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/* dram extended temperature support */
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dram_ext_temp = <0>;
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/* byte map */
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byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
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/* dq map */
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dq_map_cs0_dq_l = <0>;
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dq_map_cs0_dq_h = <0>;
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dq_map_cs1_dq_l = <0>;
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dq_map_cs1_dq_h = <0>;
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};
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ddr4_params: ddr4-params {
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/* version information */
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version = <0x100>;
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expanded_version = <IGNORE_THIS>;
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reserved = <IGNORE_THIS>;
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/* freq info, freq_0 is final frequency, unit: MHz */
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freq_0 = <1056>;
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freq_1 = <324>;
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freq_2 = <528>;
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freq_3 = <780>;
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freq_4 = <IGNORE_THIS>;
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freq_5 = <IGNORE_THIS>;
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/* power save setting */
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pd_idle = <13>;
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sr_idle = <93>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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pd_dis_freq = <1066>;
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sr_dis_freq = <800>;
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dram_dll_dis_freq = <625>;
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phy_dll_dis_freq = <IGNORE_THIS>;
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/* drv when odt on */
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phy_dq_drv_odten = <37>;
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phy_ca_drv_odten = <37>;
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phy_clk_drv_odten = <37>;
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dram_dq_drv_odten = <34>;
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/* drv when odt off */
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phy_dq_drv_odtoff = <37>;
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phy_ca_drv_odtoff = <37>;
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phy_clk_drv_odtoff = <37>;
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dram_dq_drv_odtoff = <34>;
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/* odt info */
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dram_odt = <120>;
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phy_odt = <139>;
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phy_odt_puup_en = <1>;
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phy_odt_pudn_en = <1>;
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/* odt enable freq */
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dram_dq_odt_en_freq = <500>;
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phy_odt_en_freq = <500>;
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/* slew rate when odt enable */
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phy_dq_sr_odten = <0xe>;
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phy_ca_sr_odten = <0x1>;
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phy_clk_sr_odten = <0x1>;
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/* slew rate when odt disable */
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phy_dq_sr_odtoff = <0xe>;
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phy_ca_sr_odtoff = <0x1>;
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phy_clk_sr_odtoff = <0x1>;
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/* ssmod setting*/
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ssmod_downspread = <0>;
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ssmod_div = <0>;
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ssmod_spread = <0>;
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/* 2T mode */
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mode_2t = <IGNORE_THIS>;
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/* speed bin */
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speed_bin = <DDR4_DEFAULT>;
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/* dram extended temperature support */
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dram_ext_temp = <0>;
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/* byte map */
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byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
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/* dq map */
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dq_map_cs0_dq_l = <(((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 0) | \
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((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 8) | \
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((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 16) | \
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((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 24))>;
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dq_map_cs0_dq_h = <(((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 0) | \
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((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 8) | \
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((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 16) | \
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((3 << 0 | 1 << 2 | 1 << 4 | 3 << 6) << 24))>;
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dq_map_cs1_dq_l = <(((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 0) | \
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((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 8) | \
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((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 16) | \
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((2 << 0 | 0 << 2 | 2 << 4 | 0 << 6) << 24))>;
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dq_map_cs1_dq_h = <(((3 << 0 | 1 << 2 | 3 << 4 | 1 << 6) << 0) | \
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((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 8) | \
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((0 << 0 | 2 << 2 | 0 << 4 | 2 << 6) << 16) | \
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((3 << 0 | 1 << 2 | 1 << 4 | 3 << 6) << 24))>;
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};
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lpddr3_params: lpddr3-params {
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/* version information */
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version = <0x100>;
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expanded_version = <IGNORE_THIS>;
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reserved = <IGNORE_THIS>;
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/* freq info, freq_0 is final frequency, unit: MHz */
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freq_0 = <1056>;
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freq_1 = <324>;
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freq_2 = <528>;
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freq_3 = <780>;
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freq_4 = <IGNORE_THIS>;
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freq_5 = <IGNORE_THIS>;
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/* power save setting */
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pd_idle = <13>;
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sr_idle = <93>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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pd_dis_freq = <1066>;
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sr_dis_freq = <800>;
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dram_dll_dis_freq = <IGNORE_THIS>;
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phy_dll_dis_freq = <IGNORE_THIS>;
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/* drv when odt on */
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phy_dq_drv_odten = <37>;
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phy_ca_drv_odten = <37>;
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phy_clk_drv_odten = <39>;
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dram_dq_drv_odten = <34>;
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/* drv when odt off */
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phy_dq_drv_odtoff = <37>;
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phy_ca_drv_odtoff = <37>;
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phy_clk_drv_odtoff = <39>;
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dram_dq_drv_odtoff = <34>;
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/* odt info */
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dram_odt = <120>;
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phy_odt = <148>;
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phy_odt_puup_en = <1>;
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phy_odt_pudn_en = <1>;
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/* odt enable freq */
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dram_dq_odt_en_freq = <333>;
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phy_odt_en_freq = <333>;
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/* slew rate when odt enable */
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phy_dq_sr_odten = <0xf>;
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phy_ca_sr_odten = <0x1>;
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phy_clk_sr_odten = <0xf>;
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/* slew rate when odt disable */
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phy_dq_sr_odtoff = <0xf>;
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phy_ca_sr_odtoff = <0x1>;
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phy_clk_sr_odtoff = <0xf>;
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/* ssmod setting*/
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ssmod_downspread = <0>;
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ssmod_div = <0>;
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ssmod_spread = <0>;
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/* 2T mode */
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mode_2t = <IGNORE_THIS>;
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/* speed bin */
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speed_bin = <IGNORE_THIS>;
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/* dram extended temperature support */
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dram_ext_temp = <0>;
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/* byte map */
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byte_map = <((0x2 << 6) | (0x0 << 4) | (0x3 << 2) | (0x1 << 0))>;
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/* dq map */
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dq_map_cs0_dq_l = <0>;
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dq_map_cs0_dq_h = <0>;
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dq_map_cs1_dq_l = <0>;
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dq_map_cs1_dq_h = <0>;
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};
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lpddr4_params: lpddr4-params {
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/* version information */
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version = <0x100>;
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expanded_version = <IGNORE_THIS>;
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reserved = <IGNORE_THIS>;
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/* freq info, freq_0 is final frequency, unit: MHz */
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freq_0 = <1560>;
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freq_1 = <324>;
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freq_2 = <528>;
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freq_3 = <780>;
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freq_4 = <IGNORE_THIS>;
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freq_5 = <IGNORE_THIS>;
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/* power save setting */
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pd_idle = <13>;
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sr_idle = <93>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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pd_dis_freq = <1066>;
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sr_dis_freq = <800>;
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dram_dll_dis_freq = <IGNORE_THIS>;
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phy_dll_dis_freq = <IGNORE_THIS>;
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/* drv when odt on */
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phy_dq_drv_odten = <30>;
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phy_ca_drv_odten = <38>;
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phy_clk_drv_odten = <38>;
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dram_dq_drv_odten = <40>;
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/* drv when odt off */
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phy_dq_drv_odtoff = <30>;
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phy_ca_drv_odtoff = <38>;
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phy_clk_drv_odtoff = <38>;
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dram_dq_drv_odtoff = <40>;
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/* odt info */
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dram_odt = <80>;
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phy_odt = <60>;
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phy_odt_puup_en = <IGNORE_THIS>;
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phy_odt_pudn_en = <IGNORE_THIS>;
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/* odt enable freq */
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dram_dq_odt_en_freq = <800>;
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phy_odt_en_freq = <800>;
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/* slew rate when odt enable */
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phy_dq_sr_odten = <0x0>;
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phy_ca_sr_odten = <0xf>;
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phy_clk_sr_odten = <0xf>;
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/* slew rate when odt disable */
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phy_dq_sr_odtoff = <0x0>;
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phy_ca_sr_odtoff = <0xf>;
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phy_clk_sr_odtoff = <0xf>;
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/* ssmod setting*/
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ssmod_downspread = <0>;
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ssmod_div = <0>;
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ssmod_spread = <0>;
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/* 2T mode */
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mode_2t = <IGNORE_THIS>;
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/* speed bin */
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speed_bin = <IGNORE_THIS>;
|
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/* dram extended temperature support */
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dram_ext_temp = <0>;
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/* byte map */
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byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
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/* dq map */
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dq_map_cs0_dq_l = <0>;
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dq_map_cs0_dq_h = <0>;
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dq_map_cs1_dq_l = <0>;
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dq_map_cs1_dq_h = <0>;
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/* lp4 odt info */
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lp4_ca_odt = <120>;
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lp4_drv_pu_cal_odten = <LP4_VDDQ_3>;
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lp4_drv_pu_cal_odtoff = <LP4_VDDQ_3>;
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phy_lp4_drv_pulldown_en_odten = <0>;
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phy_lp4_drv_pulldown_en_odtoff = <0>;
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/* lp4 odt enable freq */
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lp4_ca_odt_en_freq = <800>;
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/* lp4 cs drv info and ca odt info */
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phy_lp4_cs_drv_odten = <0>;
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phy_lp4_cs_drv_odtoff = <0>;
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lp4_odte_ck_en = <1>;
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lp4_odte_cs_en = <1>;
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lp4_odtd_ca_en = <0>;
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/* lp4 vref info when odt enable */
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phy_lp4_dq_vref_odten = <166>;
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lp4_dq_vref_odten = <300>;
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lp4_ca_vref_odten = <380>;
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/* lp4 vref info when odt disable */
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phy_lp4_dq_vref_odtoff = <420>;
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lp4_dq_vref_odtoff = <420>;
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||||
lp4_ca_vref_odtoff = <420>;
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||||
};
|
||||
|
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lpddr4x_params: lpddr4x-params {
|
||||
/* version information */
|
||||
version = <0x100>;
|
||||
expanded_version = <IGNORE_THIS>;
|
||||
reserved = <IGNORE_THIS>;
|
||||
/* freq info, freq_0 is final frequency, unit: MHz */
|
||||
freq_0 = <1560>;
|
||||
freq_1 = <324>;
|
||||
freq_2 = <528>;
|
||||
freq_3 = <780>;
|
||||
freq_4 = <IGNORE_THIS>;
|
||||
freq_5 = <IGNORE_THIS>;
|
||||
/* power save setting */
|
||||
pd_idle = <13>;
|
||||
sr_idle = <93>;
|
||||
sr_mc_gate_idle = <0>;
|
||||
srpd_lite_idle = <0>;
|
||||
standby_idle = <0>;
|
||||
pd_dis_freq = <1066>;
|
||||
sr_dis_freq = <800>;
|
||||
dram_dll_dis_freq = <IGNORE_THIS>;
|
||||
phy_dll_dis_freq = <IGNORE_THIS>;
|
||||
/* drv when odt on */
|
||||
phy_dq_drv_odten = <29>;
|
||||
phy_ca_drv_odten = <36>;
|
||||
phy_clk_drv_odten = <36>;
|
||||
dram_dq_drv_odten = <40>;
|
||||
/* drv when odt off */
|
||||
phy_dq_drv_odtoff = <29>;
|
||||
phy_ca_drv_odtoff = <36>;
|
||||
phy_clk_drv_odtoff = <36>;
|
||||
dram_dq_drv_odtoff = <40>;
|
||||
/* odt info */
|
||||
dram_odt = <80>;
|
||||
phy_odt = <60>;
|
||||
phy_odt_puup_en = <IGNORE_THIS>;
|
||||
phy_odt_pudn_en = <IGNORE_THIS>;
|
||||
/* odt enable freq */
|
||||
dram_dq_odt_en_freq = <800>;
|
||||
phy_odt_en_freq = <800>;
|
||||
/* slew rate when odt enable */
|
||||
phy_dq_sr_odten = <0x0>;
|
||||
phy_ca_sr_odten = <0x0>;
|
||||
phy_clk_sr_odten = <0x0>;
|
||||
/* slew rate when odt disable */
|
||||
phy_dq_sr_odtoff = <0x0>;
|
||||
phy_ca_sr_odtoff = <0x0>;
|
||||
phy_clk_sr_odtoff = <0x0>;
|
||||
/* ssmod setting*/
|
||||
ssmod_downspread = <0>;
|
||||
ssmod_div = <0>;
|
||||
ssmod_spread = <0>;
|
||||
/* 2T mode */
|
||||
mode_2t = <IGNORE_THIS>;
|
||||
/* speed bin */
|
||||
speed_bin = <IGNORE_THIS>;
|
||||
/* dram extended temperature support */
|
||||
dram_ext_temp = <0>;
|
||||
/* byte map */
|
||||
byte_map = <((0x3 << 6) | (0x2 << 4) | (0x1 << 2) | (0x0 << 0))>;
|
||||
/* dq map */
|
||||
dq_map_cs0_dq_l = <0>;
|
||||
dq_map_cs0_dq_h = <0>;
|
||||
dq_map_cs1_dq_l = <0>;
|
||||
dq_map_cs1_dq_h = <0>;
|
||||
/* lp4 odt info */
|
||||
lp4_ca_odt = <120>;
|
||||
lp4_drv_pu_cal_odten = <LP4X_VDDQ_0_6>;
|
||||
lp4_drv_pu_cal_odtoff = <LP4X_VDDQ_0_6>;
|
||||
phy_lp4_drv_pulldown_en_odten = <0>;
|
||||
phy_lp4_drv_pulldown_en_odtoff = <0>;
|
||||
/* odt enable freq */
|
||||
lp4_ca_odt_en_freq = <800>;
|
||||
/* lp4 cs drv info and ca odt info */
|
||||
phy_lp4_cs_drv_odten = <0>;
|
||||
phy_lp4_cs_drv_odtoff = <0>;
|
||||
lp4_odte_ck_en = <0>;
|
||||
lp4_odte_cs_en = <0>;
|
||||
lp4_odtd_ca_en = <0>;
|
||||
/* lp4 vref info when odt enable */
|
||||
phy_lp4_dq_vref_odten = <166>;
|
||||
lp4_dq_vref_odten = <228>;
|
||||
lp4_ca_vref_odten = <343>;
|
||||
/* lp4 vref info when odt disable */
|
||||
phy_lp4_dq_vref_odtoff = <420>;
|
||||
lp4_dq_vref_odtoff = <420>;
|
||||
lp4_ca_vref_odtoff = <343>;
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user