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rockchip

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zhangpeng
2025-04-28 11:36:59 +08:00
commit 5dd7a8972b
945 changed files with 332963 additions and 0 deletions
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45
rk3399-dram-default-timing.dtsi Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/memory/rk3399-dram.h>
/ {
ddr_timing: ddr_timing {
compatible = "rockchip,ddr-timing";
ddr3_speed_bin = <21>;
pd_idle = <0>;
sr_idle = <0>;
sr_mc_gate_idle = <0>;
srpd_lite_idle = <0>;
standby_idle = <0>;
auto_lp_dis_freq = <666>;
ddr3_dll_dis_freq = <300>;
phy_dll_dis_freq = <260>;
ddr3_odt_dis_freq = <666>;
ddr3_drv = <DDR3_DS_40ohm>;
ddr3_odt = <DDR3_ODT_120ohm>;
phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
phy_ddr3_odt = <PHY_DRV_ODT_240>;
lpddr3_odt_dis_freq = <666>;
lpddr3_drv = <LP3_DS_34ohm>;
lpddr3_odt = <LP3_ODT_240ohm>;
phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>;
phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>;
phy_lpddr3_odt = <PHY_DRV_ODT_240>;
lpddr4_odt_dis_freq = <800>;
lpddr4_drv = <LP4_PDDS_240ohm>;
lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
lpddr4_ca_odt = <LP4_CA_ODT_DIS>;
phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_40>;
phy_lpddr4_dq_drv = <PHY_DRV_ODT_60>;
phy_lpddr4_odt = <PHY_DRV_ODT_40>;
};
};