2025-10-28 19:08:22 +08:00
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
|
|
|
|
|
&i2c7 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&i2c7m0_xfer>;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
mvcam: mvcam@1a {
|
|
|
|
|
compatible = "veye,mvcam";
|
|
|
|
|
status = "okay";
|
|
|
|
|
reg = <0x3b>;
|
|
|
|
|
clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
|
|
|
|
|
clock-names = "xvclk";
|
|
|
|
|
power-domains = <&power RK3588_PD_VI>;
|
2025-10-28 19:08:22 +08:00
|
|
|
pinctrl-names = "default";
|
2025-11-01 14:21:48 +08:00
|
|
|
pinctrl-0 = <&mipim0_camera2_clk>;
|
|
|
|
|
rockchip,grf = <&sys_grf>;
|
|
|
|
|
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
|
|
|
|
|
rockchip,camera-module-index = <2>;
|
|
|
|
|
rockchip,camera-module-facing = "front";
|
|
|
|
|
rockchip,camera-module-name = "CMK-OT2022-PX1";
|
|
|
|
|
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
|
|
|
|
|
port {
|
|
|
|
|
mvcam_out0: endpoint {
|
|
|
|
|
remote-endpoint = <&mipi_in_ucam2>;
|
|
|
|
|
data-lanes = <1 2 3 4>;
|
|
|
|
|
};
|
|
|
|
|
};
|
2025-10-28 19:08:22 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
&csi2_dphy0_hw {
|
2025-10-28 19:08:22 +08:00
|
|
|
status = "okay";
|
2025-11-01 14:21:48 +08:00
|
|
|
};
|
2025-10-28 19:08:22 +08:00
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
&csi2_dphy0 {
|
|
|
|
|
status = "okay";
|
2025-10-28 19:08:22 +08:00
|
|
|
ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
port@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
2025-11-01 14:21:48 +08:00
|
|
|
mipi_in_ucam2: endpoint@1 {
|
2025-10-28 19:08:22 +08:00
|
|
|
reg = <1>;
|
|
|
|
|
remote-endpoint = <&mvcam_out0>;
|
|
|
|
|
data-lanes = <1 2 3 4>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
csidphy0_out: endpoint@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
remote-endpoint = <&mipi2_csi2_input>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&mipi2_csi2 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
ports {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
port@0 {
|
|
|
|
|
reg = <0>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
mipi2_csi2_input: endpoint@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
remote-endpoint = <&csidphy0_out>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
port@1 {
|
|
|
|
|
reg = <1>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
mipi2_csi2_output: endpoint@0 {
|
|
|
|
|
reg = <0>;
|
2025-11-01 14:21:48 +08:00
|
|
|
remote-endpoint = <&cif_mipi_in2>;
|
2025-10-28 19:08:22 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
&rkcif_mipi_lvds2 {
|
|
|
|
|
status = "okay";
|
|
|
|
|
port {
|
2025-11-01 14:21:48 +08:00
|
|
|
cif_mipi_in2: endpoint {
|
2025-10-28 19:08:22 +08:00
|
|
|
remote-endpoint = <&mipi2_csi2_output>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
&rkcif_mipi_lvds2_sditf {
|
2025-11-01 14:21:48 +08:00
|
|
|
status = "okay";
|
2025-10-28 19:08:22 +08:00
|
|
|
port {
|
2025-11-01 14:21:48 +08:00
|
|
|
mipi2_lvds_sditf: endpoint {
|
|
|
|
|
remote-endpoint = <&isp1_vir1>;
|
2025-10-28 19:08:22 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
&rkisp1 {
|
2025-10-28 19:08:22 +08:00
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
&isp1_mmu {
|
|
|
|
|
status = "okay";
|
2025-10-28 19:08:22 +08:00
|
|
|
};
|
|
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
&rkisp1_vir1 {
|
|
|
|
|
status = "okay";
|
2025-10-28 19:08:22 +08:00
|
|
|
port {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
|
2025-11-01 14:21:48 +08:00
|
|
|
isp1_vir1: endpoint@0 {
|
2025-10-28 19:08:22 +08:00
|
|
|
reg = <0>;
|
2025-11-01 14:21:48 +08:00
|
|
|
remote-endpoint = <&mipi2_lvds_sditf>;
|
2025-10-28 19:08:22 +08:00
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
2025-11-01 14:21:48 +08:00
|
|
|
|