114 lines
2.9 KiB
Plaintext
114 lines
2.9 KiB
Plaintext
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/ {
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vcc_camera: vcc-camera-regulator {
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compatible = "regulator-fixed";
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gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&camera_pwr>;
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regulator-name = "vcc_camera";
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enable-active-high;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&i2c4 {
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status = "okay";
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gc2093: gc2093@37 {
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compatible = "galaxycore,gc2093";
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status = "okay";
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reg = <0x37>;
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clocks = <&cru CLK_CIF_OUT>;
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clock-names = "xvclk";
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power-domains = <&power RK3568_PD_VI>;
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pinctrl-names = "default";
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pinctrl-0 = <&cif_clk>;
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pwdn-gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "SIDB205300385-VA";
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rockchip,camera-module-lens-name = "default";
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port {
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ucam_out0: endpoint {
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remote-endpoint = <&mipi_in_ucam0>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&rkisp {
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status = "okay";
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};
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&rkisp_mmu {
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status = "okay";
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};
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&rkisp_vir0 {
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp0_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&csidphy_out>;
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};
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};
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};
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&csi2_dphy_hw {
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status = "okay";
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};
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&csi2_dphy1 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ucam_out0>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&isp0_in>;
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};
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};
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};
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};
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&pinctrl {
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cam {
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camera_pwr: camera-pwr {
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rockchip,pins =
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/* camera power en */
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<1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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