4 Commits

Author SHA1 Message Date
zhangpeng
58da0ee3c8 优化gmac配置 2025-10-23 10:24:30 +08:00
zhangpeng
4b55c90c22 修改GMAC复位引脚 2025-10-20 13:46:17 +08:00
zhangpeng
d4232d0fe1 更改网口gmac配置 2025-10-20 13:42:33 +08:00
zhangpeng
dde492ee5f 增加地址分配 2025-10-17 11:08:02 +08:00
4 changed files with 44 additions and 47 deletions

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@@ -8839,13 +8839,25 @@ dsi1_panel: panel@0 {
# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1 # 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
&pcie30phy { / {
status = "okay"; reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie_dma: pcie-dma@40000000 {
reg = <0x0 0x40000000 0x0 0x10000000>;
no-map;
};
};
}; };
&pcie3x2 { &pcie3x2 {
compatible = "rockchip,rk3568-pcie-ep"; compatible = "rockchip,rk3568-pcie-ep";
reset-gpios = <&gpio0 22 0>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay"; status = "okay";
memory-region = <&pcie_dma>;
}; };
# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 # 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -9053,26 +9065,26 @@ dsi1_panel: panel@0 {
}; };
&uart3 { &uart3 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>; pinctrl-0 = <&uart3m1_xfer>;
}; };
&uart4 { &uart4 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>; pinctrl-0 = <&uart4m0_xfer>;
}; };
&uart5 { &uart5 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>; pinctrl-0 = <&uart5m0_xfer>;
}; };
&uart6 { &uart6 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>; pinctrl-0 = <&uart6m1_xfer>;
}; };
@@ -9104,20 +9116,6 @@ dsi1_panel: panel@0 {
}; };
}; };
&spi1 {
status = "okay";
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
spi_dev@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <12000000>;
spi-lsb-first;
};
};
&video_phy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };
@@ -9139,7 +9137,7 @@ dsi1_panel: panel@0 {
status = "disabled"; status = "disabled";
}; };
# 435 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 421 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&rk_headset { &rk_headset {
pinctrl-0 = <&hp_det>; pinctrl-0 = <&hp_det>;
headset_gpio = <&gpio2 27 0>; headset_gpio = <&gpio2 27 0>;
@@ -9188,7 +9186,7 @@ dsi1_panel: panel@0 {
BT,wake_host_irq = <&gpio0 28 0>; BT,wake_host_irq = <&gpio0 28 0>;
status = "disabled"; status = "disabled";
}; };
# 533 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 519 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&pinctrl { &pinctrl {
rp_pins { rp_pins {
rp_power: rp-power { rp_power: rp-power {
@@ -9228,7 +9226,7 @@ dsi1_panel: panel@0 {
<3 2 0 &pcfg_pull_none>; <3 2 0 &pcfg_pull_none>;
}; };
}; };
# 587 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 573 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
}; };

Binary file not shown.

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@@ -287,26 +287,26 @@
}; };
&uart3 { &uart3 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>; pinctrl-0 = <&uart3m1_xfer>;
}; };
&uart4 { &uart4 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>; pinctrl-0 = <&uart4m0_xfer>;
}; };
&uart5 { &uart5 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>; pinctrl-0 = <&uart5m0_xfer>;
}; };
&uart6 { &uart6 {
status = "disabled"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>; pinctrl-0 = <&uart6m1_xfer>;
}; };
@@ -338,20 +338,6 @@
}; };
}; };
&spi1 {
status = "okay";
/** redefine pins for cs1 used to be pwm5 */
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
spi_dev@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <12000000>;
spi-lsb-first;
};
};
&video_phy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };
@@ -596,3 +582,4 @@
BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "disabled"; status = "disabled";
}; };

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@@ -1,8 +1,20 @@
&pcie30phy { / {
status = "okay"; reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie_dma: pcie-dma@40000000 {
reg = <0x0 0x40000000 0x0 0x10000000>;
no-map;
};
};
}; };
&pcie3x2 { &pcie3x2 {
compatible = "rockchip,rk3568-pcie-ep"; compatible = "rockchip,rk3568-pcie-ep";
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay"; status = "okay";
memory-region = <&pcie_dma>;
}; };