2 Commits

Author SHA1 Message Date
zhangpeng
6ccbccafae 更改gmac配置 2025-10-23 10:27:56 +08:00
zhangpeng
128ab24eaa 更改gmac配置 2025-10-23 10:24:03 +08:00
2 changed files with 25 additions and 24 deletions

View File

@@ -1,6 +1,6 @@
# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 0 "<built-in>" # 1 "<built-in>"
# 0 "<command-line>" # 1 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -7868,7 +7868,7 @@
}; };
}; };
}; };
# 3892 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2 # 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
/ { / {
@@ -8854,27 +8854,27 @@ dsi1_panel: panel@0 {
&gmac0 { &gmac0 {
phy-mode = "rgmii"; phy-mode = "rgmii";
clock_in_out = "input"; clock_in_out = "input";
snps,reset-gpio = <&gpio2 21 1>; snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low; snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>; snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru 389>, <&cru 386>; assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>; assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
assigned-clock-rates = <0>, <125000000>; assigned-clock-rates = <0>, <125000000>, <25000000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2 &gmac0_tx_bus2
&gmac0_rx_bus2 &gmac0_rx_bus2
&gmac0_rgmii_clk_level2 &gmac0_rgmii_clk
&gmac0_rgmii_bus &gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>; &gmac0_clkinout>;
tx_delay = <0x2d>;
tx_delay = <0x3c>; rx_delay = <0x2c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>; phy-handle = <&rgmii_phy0>;
status = "okay"; status = "okay";
}; };
@@ -8884,6 +8884,7 @@ dsi1_panel: panel@0 {
rgmii_phy0: phy@0 { rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>; reg = <0x0>;
clocks = <&cru 183>;
}; };
}; };
# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 # 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2

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