4 Commits

Author SHA1 Message Date
zhangpeng
6ccbccafae 更改gmac配置 2025-10-23 10:27:56 +08:00
zhangpeng
128ab24eaa 更改gmac配置 2025-10-23 10:24:03 +08:00
zhangpeng
115e957b83 配置spi 2025-10-09 16:18:35 +08:00
zhangpeng
553f0a562e 禁用UART 2025-10-09 15:16:49 +08:00
4 changed files with 72 additions and 68 deletions

View File

@@ -1,6 +1,6 @@
# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 0 "<built-in>" # 1 "<built-in>"
# 0 "<command-line>" # 1 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -7868,7 +7868,7 @@
}; };
}; };
}; };
# 3892 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2 # 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
# 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
/ { / {
@@ -8839,56 +8839,44 @@ dsi1_panel: panel@0 {
# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1 # 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
/ { &pcie30phy {
reserved-memory { status = "okay";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie_dma: pcie-dma@40000000 {
reg = <0x0 0x40000000 0x0 0x10000000>;
no-map;
};
};
}; };
&pcie3x2 { &pcie3x2 {
compatible = "rockchip,rk3568-pcie-ep"; compatible = "rockchip,rk3568-pcie-ep";
reset-gpios = <&gpio0 22 0>; status = "okay";
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
memory-region = <&pcie_dma>;
}; };
# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 # 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1 # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
&gmac0 { &gmac0 {
phy-mode = "rgmii"; phy-mode = "rgmii";
clock_in_out = "input"; clock_in_out = "input";
snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>; snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low;
assigned-clocks = <&cru 389>, <&cru 386>; snps,reset-delays-us = <0 20000 100000>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default"; assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
pinctrl-0 = <&gmac0_miim assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
&gmac0_tx_bus2 assigned-clock-rates = <0>, <125000000>, <25000000>;
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x3c>; tx_delay = <0x2d>;
rx_delay = <0x2f>; rx_delay = <0x2c>;
phy-handle = <&rgmii_phy0>;
phy-handle = <&rgmii_phy0>; status = "okay";
status = "okay";
}; };
@@ -8896,6 +8884,7 @@ dsi1_panel: panel@0 {
rgmii_phy0: phy@0 { rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>; reg = <0x0>;
clocks = <&cru 183>;
}; };
}; };
# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 # 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
@@ -9065,26 +9054,26 @@ dsi1_panel: panel@0 {
}; };
&uart3 { &uart3 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>; pinctrl-0 = <&uart3m1_xfer>;
}; };
&uart4 { &uart4 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>; pinctrl-0 = <&uart4m0_xfer>;
}; };
&uart5 { &uart5 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>; pinctrl-0 = <&uart5m0_xfer>;
}; };
&uart6 { &uart6 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>; pinctrl-0 = <&uart6m1_xfer>;
}; };
@@ -9116,6 +9105,20 @@ dsi1_panel: panel@0 {
}; };
}; };
&spi1 {
status = "okay";
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
spi_dev@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <12000000>;
spi-lsb-first;
};
};
&video_phy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };
@@ -9137,7 +9140,7 @@ dsi1_panel: panel@0 {
status = "disabled"; status = "disabled";
}; };
# 421 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 435 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&rk_headset { &rk_headset {
pinctrl-0 = <&hp_det>; pinctrl-0 = <&hp_det>;
headset_gpio = <&gpio2 27 0>; headset_gpio = <&gpio2 27 0>;
@@ -9186,7 +9189,7 @@ dsi1_panel: panel@0 {
BT,wake_host_irq = <&gpio0 28 0>; BT,wake_host_irq = <&gpio0 28 0>;
status = "disabled"; status = "disabled";
}; };
# 519 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 533 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
&pinctrl { &pinctrl {
rp_pins { rp_pins {
rp_power: rp-power { rp_power: rp-power {
@@ -9226,7 +9229,7 @@ dsi1_panel: panel@0 {
<3 2 0 &pcfg_pull_none>; <3 2 0 &pcfg_pull_none>;
}; };
}; };
# 573 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 587 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
}; };

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@@ -287,26 +287,26 @@
}; };
&uart3 { &uart3 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart3m1_xfer>; pinctrl-0 = <&uart3m1_xfer>;
}; };
&uart4 { &uart4 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart4m0_xfer>; pinctrl-0 = <&uart4m0_xfer>;
}; };
&uart5 { &uart5 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart5m0_xfer>; pinctrl-0 = <&uart5m0_xfer>;
}; };
&uart6 { &uart6 {
status = "okay"; status = "disabled";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart6m1_xfer>; pinctrl-0 = <&uart6m1_xfer>;
}; };
@@ -338,6 +338,20 @@
}; };
}; };
&spi1 {
status = "okay";
/** redefine pins for cs1 used to be pwm5 */
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
spi_dev@0 {
compatible = "rockchip,spidev";
reg = <0>;
spi-max-frequency = <12000000>;
spi-lsb-first;
};
};
&video_phy1 { &video_phy1 {
status = "disabled"; status = "disabled";
}; };
@@ -582,4 +596,3 @@
BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
status = "disabled"; status = "disabled";
}; };

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@@ -1,20 +1,8 @@
/ { &pcie30phy {
reserved-memory { status = "okay";
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie_dma: pcie-dma@40000000 {
reg = <0x0 0x40000000 0x0 0x10000000>;
no-map;
};
};
}; };
&pcie3x2 { &pcie3x2 {
compatible = "rockchip,rk3568-pcie-ep"; compatible = "rockchip,rk3568-pcie-ep";
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; status = "okay";
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
memory-region = <&pcie_dma>;
}; };