优化gmac配置

rk356x/.dr4-rk3568.dtb.dts.tmp

@@ -1,6 +1,6 @@
-# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 1 "<built-in>"
+# 0 "<built-in>"
-# 1 "<command-line>"
+# 0 "<command-line>"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 
 
@@ -7868,7 +7868,7 @@
   };
  };
 };
-# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
+# 3892 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
 
 / {
@@ -8852,31 +8852,31 @@ dsi1_panel: panel@0 {
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
 
 &gmac0 {
-    phy-mode = "rgmii";
+        phy-mode = "rgmii";
-    clock_in_out = "input";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio2 21 1>;
+        snps,reset-active-low;
 
-    snps,reset-gpio = <&gpio2 21 1>;
+        snps,reset-delays-us = <0 20000 100000>;
-    snps,reset-active-low;
 
-    snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru 389>, <&cru 386>;
+        assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
+        assigned-clock-rates = <0>, <125000000>;
 
-    assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
+        pinctrl-names = "default";
-    assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
+        pinctrl-0 = <&gmac0_miim
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk_level2
+                    &gmac0_rgmii_bus
+                    &gmac0_clkinout>;
 
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac0_miim
-             &gmac0_tx_bus2
-             &gmac0_rx_bus2
-             &gmac0_rgmii_clk
-             &gmac0_rgmii_bus
-            &eth0_pins
-            &gmac0_clkinout>;
 
-    tx_delay = <0x2d>;
+        tx_delay = <0x3c>;
-    rx_delay = <0x2c>;
+        rx_delay = <0x2f>;
-    phy-handle = <&rgmii_phy0>;
+
-    status = "okay";
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
 };
 
 
@@ -8884,7 +8884,6 @@ dsi1_panel: panel@0 {
     rgmii_phy0: phy@0 {
         compatible = "ethernet-phy-ieee802.3-c22";
         reg = <0x0>;
-        clocks = <&cru 183>;
     };
 };
 # 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
@@ -9054,26 +9053,26 @@ dsi1_panel: panel@0 {
 };
 
 &uart3 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart3m1_xfer>;
 };
 
 &uart4 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart4m0_xfer>;
 };
 
 &uart5 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart5m0_xfer>;
 };
 
 
 &uart6 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart6m1_xfer>;
 };
@@ -9105,6 +9104,20 @@ dsi1_panel: panel@0 {
     };
 };
 
+&spi1 {
+    status = "okay";
+
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
+
+    spi_dev@0 {
+        compatible = "rockchip,spidev";
+        reg = <0>;
+        spi-max-frequency = <12000000>;
+        spi-lsb-first;
+    };
+};
+
 &video_phy1 {
     status = "disabled";
 };
@@ -9126,7 +9139,7 @@ dsi1_panel: panel@0 {
 
     status = "disabled";
 };
-# 421 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 435 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &rk_headset {
     pinctrl-0 = <&hp_det>;
     headset_gpio = <&gpio2 27 0>;
@@ -9175,7 +9188,7 @@ dsi1_panel: panel@0 {
     BT,wake_host_irq = <&gpio0 28 0>;
     status = "disabled";
 };
-# 519 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 533 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &pinctrl {
     rp_pins {
         rp_power: rp-power {
@@ -9215,7 +9228,7 @@ dsi1_panel: panel@0 {
                 <3 2 0 &pcfg_pull_none>;
         };
     };
-# 573 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 587 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 };
 
 

rk356x/dr4-rk3568.dts

@@ -287,26 +287,26 @@
 };
 
 &uart3 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart3m1_xfer>;
 };
 
 &uart4 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart4m0_xfer>;
 };
 
 &uart5 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart5m0_xfer>;
 };
 
 
 &uart6 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart6m1_xfer>;
 };
@@ -338,6 +338,20 @@
     };
 };
 
+&spi1 {
+    status = "okay";
+    /** redefine pins for cs1 used to be pwm5 */
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
+
+    spi_dev@0 {
+        compatible = "rockchip,spidev";
+        reg = <0>;
+        spi-max-frequency = <12000000>;
+        spi-lsb-first;
+    };
+};
+
 &video_phy1 {
     status = "disabled";
 };

rk356x/rp-gmac0-pro-rk3568.dtsi

@@ -1,30 +1,30 @@
 
 &gmac0 {
-    phy-mode = "rgmii";
+        phy-mode = "rgmii";
-    clock_in_out = "input";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        /* Reset time is 20ms, 100ms for rtl8211f */
+        snps,reset-delays-us = <0 20000 100000>;
 
-    snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
+        assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-    snps,reset-active-low;
+        assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
-    /* Reset time is 20ms, 100ms for rtl8211f */
+        assigned-clock-rates = <0>, <125000000>;
-    snps,reset-delays-us = <0 20000 100000>;
 
-    assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
+        pinctrl-names = "default";
-    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>;
+        pinctrl-0 = <&gmac0_miim
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk_level2
+                    &gmac0_rgmii_bus
+                    &gmac0_clkinout>;
 
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac0_miim
-             &gmac0_tx_bus2
-             &gmac0_rx_bus2
-             &gmac0_rgmii_clk
-             &gmac0_rgmii_bus
-            &eth0_pins
-            &gmac0_clkinout>;
 
-    tx_delay = <0x2d>;
+        tx_delay = <0x3c>;
-    rx_delay = <0x2c>;
+        rx_delay = <0x2f>;
-    phy-handle = <&rgmii_phy0>;
+
-    status = "okay";
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
 };
 
 
@@ -32,6 +32,5 @@
     rgmii_phy0: phy@0 {
         compatible = "ethernet-phy-ieee802.3-c22";
         reg = <0x0>;
-        clocks = <&cru CLK_MAC0_OUT>;
     };
 };