Compare commits
1 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
|
9418df441d |
19
rk3568.dtsi
19
rk3568.dtsi
@@ -227,25 +227,6 @@
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};
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/* RK3568J cpu OPPs */
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opp-j-408000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-j-600000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-j-816000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-j-1008000000 {
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opp-supported-hw = <0x04 0xffff>;
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opp-hz = /bits/ 64 <1008000000>;
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@@ -27,9 +27,8 @@ deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb := \
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arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb)
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@@ -23,6 +23,5 @@ dr4-rk3568.o: arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts \
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arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi
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arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
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arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi
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@@ -1,6 +1,6 @@
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# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 1 "<built-in>"
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# 1 "<command-line>"
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# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 0 "<built-in>"
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# 0 "<command-line>"
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# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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@@ -682,25 +682,6 @@
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};
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opp-j-408000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <408000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-j-600000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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};
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opp-j-816000000 {
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opp-supported-hw = <0xfb 0xffff>;
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opp-hz = /bits/ 64 <816000000>;
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opp-microvolt = <850000 850000 1150000>;
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clock-latency-ns = <40000>;
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opp-suspend;
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};
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opp-j-1008000000 {
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opp-supported-hw = <0x04 0xffff>;
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opp-hz = /bits/ 64 <1008000000>;
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@@ -4185,7 +4166,7 @@
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rockchip,grf = <&grf>;
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status = "disabled";
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};
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# 3745 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
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# 3726 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
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csi2_dphy0: csi2-dphy0 {
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compatible = "rockchip,rk3568-csi2-dphy";
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rockchip,hw = <&csi2_dphy_hw>;
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@@ -7868,7 +7849,7 @@
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};
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};
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};
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# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
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# 3873 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
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# 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
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/ {
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@@ -8836,45 +8817,72 @@ dsi1_panel: panel@0 {
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disable-win-move;
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};
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# 13 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
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# 24 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi" 1
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&gmac1 {
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phy-mode = "rgmii";
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clock_in_out = "input";
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# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
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&pcie30phy {
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snps,reset-gpio = <&gpio3 3 1>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru 393>, <&cru 390>, <&cru 198>;
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assigned-clock-parents = <&cru 391>,<&gmac1_clkin>, <&cru 197>;
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assigned-clock-rates = <0>, <125000000>, <25000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac1m1_miim
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&gmac1m1_tx_bus2
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&gmac1m1_rx_bus2
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&gmac1m1_rgmii_clk
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&gmac1m1_rgmii_bus
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ð1m0_pins
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&gmac1m1_clkinout>;
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tx_delay = <0x3a>;
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rx_delay = <0x29>;
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phy-handle = <&rgmii_phy1>;
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status = "okay";
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};
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&pcie3x2 {
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compatible = "rockchip,rk3568-pcie-ep";
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status = "okay";
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&mdio1 {
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rgmii_phy1: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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clocks = <&cru 198>;
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};
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# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
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# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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};
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# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
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&gmac0 {
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phy-mode = "rgmii";
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clock_in_out = "input";
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snps,reset-gpio = <&gpio2 21 1>;
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snps,reset-gpio = <&gpio3 4 1>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 20000 100000>;
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assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
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assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
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assigned-clock-rates = <0>, <125000000>, <25000000>;
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assigned-clocks = <&cru 389>, <&cru 386>;
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assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
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assigned-clock-rates = <0>, <125000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&gmac0_miim
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&gmac0_tx_bus2
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&gmac0_rx_bus2
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&gmac0_rgmii_clk
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&gmac0_rgmii_clk_level2
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&gmac0_rgmii_bus
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ð0_pins
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&gmac0_clkinout>;
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tx_delay = <0x2d>;
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rx_delay = <0x2c>;
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tx_delay = <0x3c>;
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rx_delay = <0x2f>;
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phy-handle = <&rgmii_phy0>;
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status = "okay";
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};
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@@ -8884,36 +8892,10 @@ dsi1_panel: panel@0 {
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rgmii_phy0: phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x0>;
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clocks = <&cru 183>;
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};
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};
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# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
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# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi" 1
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&can0 {
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compatible = "rockchip,rk3568-can-2.0";
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assigned-clocks = <&cru 321>;
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assigned-clock-rates = <150000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&can0m1_pins>;
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status = "okay";
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};
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&can1 {
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compatible = "rockchip,rk3568-can-2.0";
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assigned-clocks = <&cru 323>;
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assigned-clock-rates = <150000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&can1m1_pins>;
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status = "okay";
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};
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# 36 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
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# 82 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
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# 78 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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/{
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model = "dr4-rk3568";
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compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568";
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@@ -8934,7 +8916,7 @@ dsi1_panel: panel@0 {
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pinctrl-name = "default";
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pinctrl-0 = <&rp_power>;
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# 125 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 121 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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otg_mode {
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gpio_num = <&gpio1 4 1>;
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gpio_function = <0>;
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@@ -8943,13 +8925,13 @@ dsi1_panel: panel@0 {
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gpio_num = <&gpio0 5 0>;
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gpio_function = <4>;
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};
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# 173 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 169 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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};
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rp_gpio{
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status = "disabled";
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compatible = "rp_gpio";
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# 186 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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# 182 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
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gpio0a0 {
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gpio_num = <&gpio0 0 1>;
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gpio_function = <0>;
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@@ -9054,38 +9036,38 @@ dsi1_panel: panel@0 {
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};
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&uart3 {
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status = "disabled";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart3m1_xfer>;
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};
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&uart4 {
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status = "disabled";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart4m0_xfer>;
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};
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&uart5 {
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status = "disabled";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart5m0_xfer>;
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};
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&uart6 {
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status = "disabled";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart6m1_xfer>;
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};
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&uart7 {
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status = "disabled";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart7m1_xfer>;
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};
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&uart8 {
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status = "disabled";
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&uart8m0_xfer>;
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};
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@@ -9105,20 +9087,6 @@ dsi1_panel: panel@0 {
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};
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};
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&spi1 {
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status = "okay";
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pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
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pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
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spi_dev@0 {
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compatible = "rockchip,spidev";
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reg = <0>;
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spi-max-frequency = <12000000>;
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spi-lsb-first;
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};
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};
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&video_phy1 {
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status = "disabled";
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};
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@@ -9140,7 +9108,7 @@ dsi1_panel: panel@0 {
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|
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status = "disabled";
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};
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# 435 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
|
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# 417 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
|
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&rk_headset {
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pinctrl-0 = <&hp_det>;
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headset_gpio = <&gpio2 27 0>;
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@@ -9189,7 +9157,7 @@ dsi1_panel: panel@0 {
|
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BT,wake_host_irq = <&gpio0 28 0>;
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status = "disabled";
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||||
};
|
||||
# 533 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
|
||||
# 515 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
|
||||
&pinctrl {
|
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rp_pins {
|
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rp_power: rp-power {
|
||||
@@ -9229,7 +9197,7 @@ dsi1_panel: panel@0 {
|
||||
<3 2 0 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
# 587 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
|
||||
# 569 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
|
||||
};
|
||||
|
||||
|
||||
|
||||
Binary file not shown.
@@ -11,9 +11,6 @@
|
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#include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi"
|
||||
#include "../rk3568-linux.dtsi"
|
||||
|
||||
/**************************pcie***********************/
|
||||
#include "zkzg-pcie-rk3568.dtsi"
|
||||
|
||||
/*************************camera***********************/
|
||||
// #include "rp-camera-mipi-gc2093-single-2lane.dtsi"
|
||||
/***************************************************/
|
||||
@@ -24,7 +21,7 @@
|
||||
/***************************************************/
|
||||
|
||||
/*************************gmac***********************/
|
||||
// #include "rp-gmac1-m1-pro-rk3568.dtsi"
|
||||
#include "rp-gmac1-m1-pro-rk3568.dtsi"
|
||||
#include "rp-gmac0-pro-rk3568.dtsi"
|
||||
/***************************************************/
|
||||
|
||||
@@ -32,7 +29,6 @@
|
||||
// #include "rp-can0-m0-rk3568.dtsi"
|
||||
// #include "rp-can1-m1-rk3568.dtsi"
|
||||
// #include "rp-can2-m0-rk3568.dtsi"
|
||||
#include "zkzg-can-rk3568.dtsi"
|
||||
/**************************************************/
|
||||
|
||||
/*********************PCIE**************************/
|
||||
@@ -287,38 +283,38 @@
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3m1_xfer>;
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4m0_xfer>;
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5m0_xfer>;
|
||||
};
|
||||
|
||||
|
||||
&uart6 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart6m1_xfer>;
|
||||
};
|
||||
|
||||
&uart7 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart7m1_xfer>;
|
||||
};
|
||||
|
||||
&uart8 {
|
||||
status = "disabled";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart8m0_xfer>;
|
||||
};
|
||||
@@ -338,20 +334,6 @@
|
||||
};
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
/** redefine pins for cs1 used to be pwm5 */
|
||||
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
|
||||
pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
|
||||
|
||||
spi_dev@0 {
|
||||
compatible = "rockchip,spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <12000000>;
|
||||
spi-lsb-first;
|
||||
};
|
||||
};
|
||||
|
||||
&video_phy1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
&gmac0 {
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
|
||||
snps,reset-active-low;
|
||||
/* Reset time is 20ms, 100ms for rtl8211f */
|
||||
snps,reset-delays-us = <0 20000 100000>;
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
&can0 {
|
||||
compatible = "rockchip,rk3568-can-2.0";
|
||||
assigned-clocks = <&cru CLK_CAN0>;
|
||||
assigned-clock-rates = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can0m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can1 {
|
||||
compatible = "rockchip,rk3568-can-2.0";
|
||||
assigned-clocks = <&cru CLK_CAN1>;
|
||||
assigned-clock-rates = <150000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&can1m1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
@@ -1,8 +0,0 @@
|
||||
&pcie30phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie3x2 {
|
||||
compatible = "rockchip,rk3568-pcie-ep";
|
||||
status = "okay";
|
||||
};
|
||||
Reference in New Issue
Block a user