优化gmac配置

rk356x/.dr4-rk3568.dtb.dts.tmp

@@ -1,6 +1,6 @@
-# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 1 "<built-in>"
-# 1 "<command-line>"
+# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 0 "<built-in>"
+# 0 "<command-line>"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 
 
@@ -7868,7 +7868,7 @@
   };
  };
 };
-# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
+# 3892 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
 
 / {
@@ -8839,44 +8839,56 @@ dsi1_panel: panel@0 {
 
 
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
-&pcie30phy {
- status = "okay";
+/ {
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        pcie_dma: pcie-dma@40000000 {
+            reg = <0x0 0x40000000 0x0 0x10000000>;
+            no-map;
+        };
+    };
 };
 
 &pcie3x2 {
- compatible = "rockchip,rk3568-pcie-ep";
- status = "okay";
+    compatible = "rockchip,rk3568-pcie-ep";
+    reset-gpios = <&gpio0 22 0>;
+    vpcie3v3-supply = <&vcc3v3_sys>;
+    status = "okay";
+    memory-region = <&pcie_dma>;
 };
 # 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
 # 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
 
 &gmac0 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";
+        phy-mode = "rgmii";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio2 21 1>;
+        snps,reset-active-low;
 
-    snps,reset-gpio = <&gpio2 21 1>;
-    snps,reset-active-low;
+        snps,reset-delays-us = <0 20000 100000>;
 
-    snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru 389>, <&cru 386>;
+        assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
+        assigned-clock-rates = <0>, <125000000>;
 
-    assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
-    assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk_level2
+                    &gmac0_rgmii_bus
+                    &gmac0_clkinout>;
 
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac0_miim
-             &gmac0_tx_bus2
-             &gmac0_rx_bus2
-             &gmac0_rgmii_clk
-             &gmac0_rgmii_bus
-            &eth0_pins
-            &gmac0_clkinout>;
 
-    tx_delay = <0x2d>;
-    rx_delay = <0x2c>;
-    phy-handle = <&rgmii_phy0>;
-    status = "okay";
+        tx_delay = <0x3c>;
+        rx_delay = <0x2f>;
+
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
 };
 
 
@@ -8884,7 +8896,6 @@ dsi1_panel: panel@0 {
     rgmii_phy0: phy@0 {
         compatible = "ethernet-phy-ieee802.3-c22";
         reg = <0x0>;
-        clocks = <&cru 183>;
     };
 };
 # 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2

rk356x/dr4-rk3568.dts

@@ -582,3 +582,4 @@
                 BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
                 status = "disabled";
 };
+

rk356x/rp-gmac0-pro-rk3568.dtsi

@@ -1,30 +1,30 @@
 
 &gmac0 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";
+        phy-mode = "rgmii";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        /* Reset time is 20ms, 100ms for rtl8211f */
+        snps,reset-delays-us = <0 20000 100000>;
 
-    snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
-    snps,reset-active-low;
-    /* Reset time is 20ms, 100ms for rtl8211f */
-    snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+        assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
+        assigned-clock-rates = <0>, <125000000>;
 
-    assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
-    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk_level2
+                    &gmac0_rgmii_bus
+                    &gmac0_clkinout>;
 
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac0_miim
-             &gmac0_tx_bus2
-             &gmac0_rx_bus2
-             &gmac0_rgmii_clk
-             &gmac0_rgmii_bus
-            &eth0_pins
-            &gmac0_clkinout>;
 
-    tx_delay = <0x2d>;
-    rx_delay = <0x2c>;
-    phy-handle = <&rgmii_phy0>;
-    status = "okay";
+        tx_delay = <0x3c>;
+        rx_delay = <0x2f>;
+
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
 };
 
 
@@ -32,6 +32,5 @@
     rgmii_phy0: phy@0 {
         compatible = "ethernet-phy-ieee802.3-c22";
         reg = <0x0>;
-        clocks = <&cru CLK_MAC0_OUT>;
     };
 };

rk356x/zkzg-pcie-rk3568.dtsi

@@ -1,8 +1,20 @@
-&pcie30phy {
-	status = "okay";
+/ {
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        pcie_dma: pcie-dma@40000000 {
+            reg = <0x0 0x40000000 0x0 0x10000000>;
+            no-map;
+        };
+    };
 };
 
 &pcie3x2 {
-	compatible = "rockchip,rk3568-pcie-ep";
-	status = "okay";
+    compatible = "rockchip,rk3568-pcie-ep";
+    reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_sys>;
+    status = "okay";
+    memory-region = <&pcie_dma>;
 };