更改gmac配置

配置spi
2025-10-23 10:27:56 +08:00 · 2025-10-23 10:24:03 +08:00 · 2025-10-09 16:18:35 +08:00 · 2025-10-09 15:16:49 +08:00 · 2025-10-09 14:34:41 +08:00 · 2025-10-09 13:45:08 +08:00
9 changed files with 181 additions and 85 deletions
--- a/rk3568.dtsi
+++ b/rk3568.dtsi
@@ -227,6 +227,25 @@
 		};

 		/* RK3568J cpu OPPs */
+		opp-j-408000000 {
+			opp-supported-hw = <0xfb 0xffff>;
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <850000 850000 1150000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-j-600000000 {
+			opp-supported-hw = <0xfb 0xffff>;
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <850000 850000 1150000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-j-816000000 {
+			opp-supported-hw = <0xfb 0xffff>;
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <850000 850000 1150000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
 		opp-j-1008000000 {
 			opp-supported-hw = <0x04 0xffff>;
 			opp-hz = /bits/ 64 <1008000000>;
--- a/rk356x/.dr4-rk3568.dtb.cmd
+++ b/rk356x/.dr4-rk3568.dtb.cmd
@@ -27,8 +27,9 @@ deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb := \
  arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
-  arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
+  arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
+  arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi \

 arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb)

--- a/rk356x/.dr4-rk3568.dtb.d.pre.tmp
+++ b/rk356x/.dr4-rk3568.dtb.d.pre.tmp
@@ -23,5 +23,6 @@ dr4-rk3568.o: arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts \
 arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
 arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
 arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
- arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
- arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi
+ arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
+ arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
+ arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi
--- a/rk356x/.dr4-rk3568.dtb.dts.tmp
+++ b/rk356x/.dr4-rk3568.dtb.dts.tmp
@@ -1,6 +1,6 @@
-# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 0 "<built-in>"
-# 0 "<command-line>"
+# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 1 "<built-in>"
+# 1 "<command-line>"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"


@@ -682,6 +682,25 @@
  };


+  opp-j-408000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <408000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+  };
+  opp-j-600000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <600000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+  };
+  opp-j-816000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <816000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+   opp-suspend;
+  };
  opp-j-1008000000 {
   opp-supported-hw = <0x04 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
@@ -4166,7 +4185,7 @@
  rockchip,grf = <&grf>;
  status = "disabled";
 };
-# 3726 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
+# 3745 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
 csi2_dphy0: csi2-dphy0 {
  compatible = "rockchip,rk3568-csi2-dphy";
  rockchip,hw = <&csi2_dphy_hw>;
@@ -7849,7 +7868,7 @@
  };
 };
 };
-# 3873 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
+# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2

 / {
@@ -8817,72 +8836,45 @@ dsi1_panel: panel@0 {
 disable-win-move;
 };
 # 13 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
-# 24 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi" 1

-&gmac1 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";

-    snps,reset-gpio = <&gpio3 3 1>;
-    snps,reset-active-low;
-
-    snps,reset-delays-us = <0 20000 100000>;
-
-    assigned-clocks = <&cru 393>, <&cru 390>, <&cru 198>;
-    assigned-clock-parents = <&cru 391>,<&gmac1_clkin>, <&cru 197>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
-
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac1m1_miim
-             &gmac1m1_tx_bus2
-             &gmac1m1_rx_bus2
-             &gmac1m1_rgmii_clk
-             &gmac1m1_rgmii_bus
-            &eth1m0_pins
-            &gmac1m1_clkinout>;
-
-    tx_delay = <0x3a>;
-    rx_delay = <0x29>;
-    phy-handle = <&rgmii_phy1>;
+# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
+&pcie30phy {
 status = "okay";
 };

-
-&mdio1 {
-    rgmii_phy1: phy@0 {
-        compatible = "ethernet-phy-ieee802.3-c22";
-        reg = <0x0>;
-        clocks = <&cru 198>;
+&pcie3x2 {
+ compatible = "rockchip,rk3568-pcie-ep";
+ status = "okay";
 };
-};
-# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1

 &gmac0 {
    phy-mode = "rgmii";
    clock_in_out = "input";
-        snps,reset-gpio = <&gpio3 4 1>;
+
+    snps,reset-gpio = <&gpio2 21 1>;
    snps,reset-active-low;

    snps,reset-delays-us = <0 20000 100000>;

-        assigned-clocks = <&cru 389>, <&cru 386>;
-        assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
-        assigned-clock-rates = <0>, <125000000>;
+    assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
+    assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
+    assigned-clock-rates = <0>, <125000000>, <25000000>;

    pinctrl-names = "default";
    pinctrl-0 = <&gmac0_miim
             &gmac0_tx_bus2
             &gmac0_rx_bus2
-                    &gmac0_rgmii_clk_level2
+             &gmac0_rgmii_clk
             &gmac0_rgmii_bus
+            &eth0_pins
            &gmac0_clkinout>;

-
-        tx_delay = <0x3c>;
-        rx_delay = <0x2f>;
-
+    tx_delay = <0x2d>;
+    rx_delay = <0x2c>;
    phy-handle = <&rgmii_phy0>;
    status = "okay";
 };
@@ -8892,10 +8884,36 @@ dsi1_panel: panel@0 {
    rgmii_phy0: phy@0 {
        compatible = "ethernet-phy-ieee802.3-c22";
        reg = <0x0>;
+        clocks = <&cru 183>;
    };
 };
-# 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
-# 78 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+
+
+
+
+
+
+# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi" 1
+&can0 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru 321>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can0m1_pins>;
+    status = "okay";
+};
+
+&can1 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru 323>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can1m1_pins>;
+    status = "okay";
+};
+# 36 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 82 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 /{
        model = "dr4-rk3568";
        compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568";
@@ -8916,7 +8934,7 @@ dsi1_panel: panel@0 {

                pinctrl-name = "default";
                pinctrl-0 = <&rp_power>;
-# 121 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 125 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
                otg_mode {
                        gpio_num = <&gpio1 4 1>;
                        gpio_function = <0>;
@@ -8925,13 +8943,13 @@ dsi1_panel: panel@0 {
                        gpio_num = <&gpio0 5 0>;
                        gpio_function = <4>;
                };
-# 169 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 173 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
        };

        rp_gpio{
                status = "disabled";
                compatible = "rp_gpio";
-# 182 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 186 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
                gpio0a0 {
                        gpio_num = <&gpio0 0 1>;
                        gpio_function = <0>;
@@ -9036,38 +9054,38 @@ dsi1_panel: panel@0 {
 };

 &uart3 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart3m1_xfer>;
 };

 &uart4 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart4m0_xfer>;
 };

 &uart5 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart5m0_xfer>;
 };


 &uart6 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart6m1_xfer>;
 };

 &uart7 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart7m1_xfer>;
 };

 &uart8 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart8m0_xfer>;
 };
@@ -9087,6 +9105,20 @@ dsi1_panel: panel@0 {
    };
 };

+&spi1 {
+    status = "okay";
+
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
+
+    spi_dev@0 {
+        compatible = "rockchip,spidev";
+        reg = <0>;
+        spi-max-frequency = <12000000>;
+        spi-lsb-first;
+    };
+};
+
 &video_phy1 {
    status = "disabled";
 };
@@ -9108,7 +9140,7 @@ dsi1_panel: panel@0 {

    status = "disabled";
 };
-# 417 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 435 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &rk_headset {
    pinctrl-0 = <&hp_det>;
    headset_gpio = <&gpio2 27 0>;
@@ -9157,7 +9189,7 @@ dsi1_panel: panel@0 {
    BT,wake_host_irq = <&gpio0 28 0>;
    status = "disabled";
 };
-# 515 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 533 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &pinctrl {
    rp_pins {
        rp_power: rp-power {
@@ -9197,7 +9229,7 @@ dsi1_panel: panel@0 {
                <3 2 0 &pcfg_pull_none>;
        };
    };
-# 569 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 587 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 };


--- a/rk356x/dr4-rk3568.dtb
+++ b/rk356x/dr4-rk3568.dtb
--- a/rk356x/dr4-rk3568.dts
+++ b/rk356x/dr4-rk3568.dts
@@ -11,6 +11,9 @@
 #include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi"
 #include "../rk3568-linux.dtsi"

+/**************************pcie***********************/
+#include "zkzg-pcie-rk3568.dtsi"
+
 /*************************camera***********************/
 // #include "rp-camera-mipi-gc2093-single-2lane.dtsi"
 /***************************************************/
@@ -21,7 +24,7 @@
 /***************************************************/

 /*************************gmac***********************/
-#include "rp-gmac1-m1-pro-rk3568.dtsi"
+// #include "rp-gmac1-m1-pro-rk3568.dtsi"
 #include "rp-gmac0-pro-rk3568.dtsi"
 /***************************************************/

@@ -29,6 +32,7 @@
 // #include "rp-can0-m0-rk3568.dtsi"
 // #include "rp-can1-m1-rk3568.dtsi"
 // #include "rp-can2-m0-rk3568.dtsi"
+#include "zkzg-can-rk3568.dtsi"
 /**************************************************/

 /*********************PCIE**************************/
@@ -283,38 +287,38 @@
 };

 &uart3 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart3m1_xfer>;
 };

 &uart4 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart4m0_xfer>;
 };

 &uart5 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart5m0_xfer>;
 };


 &uart6 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart6m1_xfer>;
 };

 &uart7 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart7m1_xfer>;
 };

 &uart8 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart8m0_xfer>;
 };
@@ -334,6 +338,20 @@
    };
 };

+&spi1 {
+    status = "okay";
+    /** redefine pins for cs1 used to be pwm5 */
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+    pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>;
+
+    spi_dev@0 {
+        compatible = "rockchip,spidev";
+        reg = <0>;
+        spi-max-frequency = <12000000>;
+        spi-lsb-first;
+    };
+};
+
 &video_phy1 {
    status = "disabled";
 };
--- a/rk356x/rp-gmac0-pro-rk3568.dtsi
+++ b/rk356x/rp-gmac0-pro-rk3568.dtsi
@@ -2,7 +2,7 @@
 &gmac0 {
        phy-mode = "rgmii";
        clock_in_out = "input";
-        snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
+        snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
        snps,reset-active-low;
        /* Reset time is 20ms, 100ms for rtl8211f */
        snps,reset-delays-us = <0 20000 100000>;
--- a/rk356x/zkzg-can-rk3568.dtsi
+++ b/rk356x/zkzg-can-rk3568.dtsi
@@ -0,0 +1,17 @@
+&can0 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru CLK_CAN0>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can0m1_pins>;
+    status = "okay";
+};
+
+&can1 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru CLK_CAN1>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can1m1_pins>;
+    status = "okay";
+};
--- a/rk356x/zkzg-pcie-rk3568.dtsi
+++ b/rk356x/zkzg-pcie-rk3568.dtsi
@@ -0,0 +1,8 @@
+&pcie30phy {
+	status = "okay";
+};
+
+&pcie3x2 {
+	compatible = "rockchip,rk3568-pcie-ep";
+	status = "okay";
+};
Author	SHA1	Message	Date
zhangpeng	6ccbccafae	更改gmac配置	2025-10-23 10:27:56 +08:00
zhangpeng	128ab24eaa	更改gmac配置	2025-10-23 10:24:03 +08:00
zhangpeng	115e957b83	配置spi	2025-10-09 16:18:35 +08:00
zhangpeng	553f0a562e	禁用UART	2025-10-09 15:16:49 +08:00
zhangpeng	d92c0f85df	配置PCIE	2025-10-09 14:34:41 +08:00
zhangpeng	37cc8084fe	配置UART、CAN和网络	2025-10-09 13:45:08 +08:00
zhangpeng	85a0f6e6ea	增加CPU频率区间	2025-09-18 10:43:09 +08:00