优化gmac配置

修改GMAC复位引脚
更改网口gmac配置
2025-10-23 10:24:30 +08:00 · 2025-10-20 13:46:17 +08:00 · 2025-10-20 13:42:33 +08:00 · 2025-10-17 11:08:02 +08:00 · 2025-10-09 14:34:41 +08:00 · 2025-10-09 13:45:08 +08:00
9 changed files with 190 additions and 100 deletions
--- a/rk3568.dtsi
+++ b/rk3568.dtsi
@@ -227,6 +227,25 @@
 		};

 		/* RK3568J cpu OPPs */
+		opp-j-408000000 {
+			opp-supported-hw = <0xfb 0xffff>;
+			opp-hz = /bits/ 64 <408000000>;
+			opp-microvolt = <850000 850000 1150000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-j-600000000 {
+			opp-supported-hw = <0xfb 0xffff>;
+			opp-hz = /bits/ 64 <600000000>;
+			opp-microvolt = <850000 850000 1150000>;
+			clock-latency-ns = <40000>;
+		};
+		opp-j-816000000 {
+			opp-supported-hw = <0xfb 0xffff>;
+			opp-hz = /bits/ 64 <816000000>;
+			opp-microvolt = <850000 850000 1150000>;
+			clock-latency-ns = <40000>;
+			opp-suspend;
+		};
 		opp-j-1008000000 {
 			opp-supported-hw = <0x04 0xffff>;
 			opp-hz = /bits/ 64 <1008000000>;
--- a/rk356x/.dr4-rk3568.dtb.cmd
+++ b/rk356x/.dr4-rk3568.dtb.cmd
@@ -27,8 +27,9 @@ deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb := \
  arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
-  arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
+  arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
+  arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi \

 arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb)

--- a/rk356x/.dr4-rk3568.dtb.d.pre.tmp
+++ b/rk356x/.dr4-rk3568.dtb.d.pre.tmp
@@ -23,5 +23,6 @@ dr4-rk3568.o: arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts \
 arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
 arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
 arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
- arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
- arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi
+ arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi \
+ arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
+ arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi
--- a/rk356x/.dr4-rk3568.dtb.dts.tmp
+++ b/rk356x/.dr4-rk3568.dtb.dts.tmp
@@ -1,6 +1,6 @@
-# 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 1 "<built-in>"
-# 1 "<command-line>"
+# 0 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 0 "<built-in>"
+# 0 "<command-line>"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"


@@ -682,6 +682,25 @@
  };


+  opp-j-408000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <408000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+  };
+  opp-j-600000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <600000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+  };
+  opp-j-816000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <816000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+   opp-suspend;
+  };
  opp-j-1008000000 {
   opp-supported-hw = <0x04 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
@@ -4166,7 +4185,7 @@
  rockchip,grf = <&grf>;
  status = "disabled";
 };
-# 3726 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
+# 3745 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
 csi2_dphy0: csi2-dphy0 {
  compatible = "rockchip,rk3568-csi2-dphy";
  rockchip,hw = <&csi2_dphy_hw>;
@@ -7849,7 +7868,7 @@
  };
 };
 };
-# 3872 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
+# 3892 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2

 / {
@@ -8817,74 +8836,59 @@ dsi1_panel: panel@0 {
 disable-win-move;
 };
 # 13 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
-# 24 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi" 1
-
-&gmac1 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";
-
-    snps,reset-gpio = <&gpio3 3 1>;
-    snps,reset-active-low;
-
-    snps,reset-delays-us = <0 20000 100000>;
-
-    assigned-clocks = <&cru 393>, <&cru 390>, <&cru 198>;
-    assigned-clock-parents = <&cru 391>,<&gmac1_clkin>, <&cru 197>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
-
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac1m1_miim
-             &gmac1m1_tx_bus2
-             &gmac1m1_rx_bus2
-             &gmac1m1_rgmii_clk
-             &gmac1m1_rgmii_bus
-            &eth1m0_pins
-            &gmac1m1_clkinout>;
-
-    tx_delay = <0x3a>;
-    rx_delay = <0x29>;
-    phy-handle = <&rgmii_phy1>;
-    status = "okay";
-};


-&mdio1 {
-    rgmii_phy1: phy@0 {
-        compatible = "ethernet-phy-ieee802.3-c22";
-        reg = <0x0>;
-        clocks = <&cru 198>;
+# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-pcie-rk3568.dtsi" 1
+/ {
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        pcie_dma: pcie-dma@40000000 {
+            reg = <0x0 0x40000000 0x0 0x10000000>;
+            no-map;
+        };
    };
 };
-# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+
+&pcie3x2 {
+    compatible = "rockchip,rk3568-pcie-ep";
+    reset-gpios = <&gpio0 22 0>;
+    vpcie3v3-supply = <&vcc3v3_sys>;
+    status = "okay";
+    memory-region = <&pcie_dma>;
+};
+# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1

 &gmac0 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";
+        phy-mode = "rgmii";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio2 21 1>;
+        snps,reset-active-low;

-    snps,reset-gpio = <&gpio3 4 1>;
-    snps,reset-active-low;
+        snps,reset-delays-us = <0 20000 100000>;

-    snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru 389>, <&cru 386>;
+        assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
+        assigned-clock-rates = <0>, <125000000>;

-    assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>;
-    assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk_level2
+                    &gmac0_rgmii_bus
+                    &gmac0_clkinout>;

-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac0_miim
-             &gmac0_tx_bus2
-             &gmac0_rx_bus2
-             &gmac0_rgmii_clk
-             &gmac0_rgmii_bus
-            &eth0_pins
-            &gmac0_clkinout>;

-    tx_delay = <0x2d>;
-    rx_delay = <0x2c>;
-    phy-handle = <&rgmii_phy0>;
-    status = "okay";
+        tx_delay = <0x3c>;
+        rx_delay = <0x2f>;
+
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
 };


@@ -8892,11 +8896,35 @@ dsi1_panel: panel@0 {
    rgmii_phy0: phy@0 {
        compatible = "ethernet-phy-ieee802.3-c22";
        reg = <0x0>;
-        clocks = <&cru 183>;
    };
 };
-# 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
-# 78 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+
+
+
+
+
+
+# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi" 1
+&can0 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru 321>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can0m1_pins>;
+    status = "okay";
+};
+
+&can1 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru 323>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can1m1_pins>;
+    status = "okay";
+};
+# 36 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 82 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 /{
        model = "dr4-rk3568";
        compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568";
@@ -8917,7 +8945,7 @@ dsi1_panel: panel@0 {

                pinctrl-name = "default";
                pinctrl-0 = <&rp_power>;
-# 121 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 125 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
                otg_mode {
                        gpio_num = <&gpio1 4 1>;
                        gpio_function = <0>;
@@ -8926,13 +8954,13 @@ dsi1_panel: panel@0 {
                        gpio_num = <&gpio0 5 0>;
                        gpio_function = <4>;
                };
-# 169 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 173 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
        };

        rp_gpio{
                status = "disabled";
                compatible = "rp_gpio";
-# 182 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 186 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
                gpio0a0 {
                        gpio_num = <&gpio0 0 1>;
                        gpio_function = <0>;
@@ -9062,13 +9090,13 @@ dsi1_panel: panel@0 {
 };

 &uart7 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart7m1_xfer>;
 };

 &uart8 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart8m0_xfer>;
 };
@@ -9109,7 +9137,7 @@ dsi1_panel: panel@0 {

    status = "disabled";
 };
-# 417 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 421 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &rk_headset {
    pinctrl-0 = <&hp_det>;
    headset_gpio = <&gpio2 27 0>;
@@ -9158,7 +9186,7 @@ dsi1_panel: panel@0 {
    BT,wake_host_irq = <&gpio0 28 0>;
    status = "disabled";
 };
-# 515 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 519 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &pinctrl {
    rp_pins {
        rp_power: rp-power {
@@ -9198,7 +9226,7 @@ dsi1_panel: panel@0 {
                <3 2 0 &pcfg_pull_none>;
        };
    };
-# 569 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 573 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 };


--- a/rk356x/dr4-rk3568.dtb
+++ b/rk356x/dr4-rk3568.dtb
--- a/rk356x/dr4-rk3568.dts
+++ b/rk356x/dr4-rk3568.dts
@@ -11,6 +11,9 @@
 #include "rk3566-evb-rpdzkj-rk809-tcs4525.dtsi"
 #include "../rk3568-linux.dtsi"

+/**************************pcie***********************/
+#include "zkzg-pcie-rk3568.dtsi"
+
 /*************************camera***********************/
 // #include "rp-camera-mipi-gc2093-single-2lane.dtsi"
 /***************************************************/
@@ -21,7 +24,7 @@
 /***************************************************/

 /*************************gmac***********************/
-#include "rp-gmac1-m1-pro-rk3568.dtsi"
+// #include "rp-gmac1-m1-pro-rk3568.dtsi"
 #include "rp-gmac0-pro-rk3568.dtsi"
 /***************************************************/

@@ -29,6 +32,7 @@
 // #include "rp-can0-m0-rk3568.dtsi"
 // #include "rp-can1-m1-rk3568.dtsi"
 // #include "rp-can2-m0-rk3568.dtsi"
+#include "zkzg-can-rk3568.dtsi"
 /**************************************************/

 /*********************PCIE**************************/
@@ -308,13 +312,13 @@
 };

 &uart7 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart7m1_xfer>;
 };

 &uart8 {
-    status = "okay";
+    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&uart8m0_xfer>;
 };
@@ -578,3 +582,4 @@
                BT,wake_host_irq = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
                status = "disabled";
 };
+
--- a/rk356x/rp-gmac0-pro-rk3568.dtsi
+++ b/rk356x/rp-gmac0-pro-rk3568.dtsi
@@ -1,30 +1,30 @@

 &gmac0 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";
+        phy-mode = "rgmii";
+        clock_in_out = "input";
+        snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        /* Reset time is 20ms, 100ms for rtl8211f */
+        snps,reset-delays-us = <0 20000 100000>;

-    snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
-    snps,reset-active-low;
-    /* Reset time is 20ms, 100ms for rtl8211f */
-    snps,reset-delays-us = <0 20000 100000>;
+        assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+        assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
+        assigned-clock-rates = <0>, <125000000>;

-    assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
-    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac0_miim
+                    &gmac0_tx_bus2
+                    &gmac0_rx_bus2
+                    &gmac0_rgmii_clk_level2
+                    &gmac0_rgmii_bus
+                    &gmac0_clkinout>;

-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac0_miim
-             &gmac0_tx_bus2
-             &gmac0_rx_bus2
-             &gmac0_rgmii_clk
-             &gmac0_rgmii_bus
-            &eth0_pins
-            &gmac0_clkinout>;

-    tx_delay = <0x2d>;
-    rx_delay = <0x2c>;
-    phy-handle = <&rgmii_phy0>;
-    status = "okay";
+        tx_delay = <0x3c>;
+        rx_delay = <0x2f>;
+
+        phy-handle = <&rgmii_phy0>;
+        status = "okay";
 };


@@ -32,6 +32,5 @@
    rgmii_phy0: phy@0 {
        compatible = "ethernet-phy-ieee802.3-c22";
        reg = <0x0>;
-        clocks = <&cru CLK_MAC0_OUT>;
    };
 };
--- a/rk356x/zkzg-can-rk3568.dtsi
+++ b/rk356x/zkzg-can-rk3568.dtsi
@@ -0,0 +1,17 @@
+&can0 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru CLK_CAN0>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can0m1_pins>;
+    status = "okay";
+};
+
+&can1 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru CLK_CAN1>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can1m1_pins>;
+    status = "okay";
+};
--- a/rk356x/zkzg-pcie-rk3568.dtsi
+++ b/rk356x/zkzg-pcie-rk3568.dtsi
@@ -0,0 +1,20 @@
+/ {
+    reserved-memory {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+
+        pcie_dma: pcie-dma@40000000 {
+            reg = <0x0 0x40000000 0x0 0x10000000>;
+            no-map;
+        };
+    };
+};
+
+&pcie3x2 {
+    compatible = "rockchip,rk3568-pcie-ep";
+    reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_sys>;
+    status = "okay";
+    memory-region = <&pcie_dma>;
+};
Author	SHA1	Message	Date
zhangpeng	58da0ee3c8	优化gmac配置	2025-10-23 10:24:30 +08:00
zhangpeng	4b55c90c22	修改GMAC复位引脚	2025-10-20 13:46:17 +08:00
zhangpeng	d4232d0fe1	更改网口gmac配置	2025-10-20 13:42:33 +08:00
zhangpeng	dde492ee5f	增加地址分配	2025-10-17 11:08:02 +08:00
zhangpeng	d92c0f85df	配置PCIE	2025-10-09 14:34:41 +08:00
zhangpeng	37cc8084fe	配置UART、CAN和网络	2025-10-09 13:45:08 +08:00
zhangpeng	85a0f6e6ea	增加CPU频率区间	2025-09-18 10:43:09 +08:00