From c6977360c3cda5f6b26d88a0f3e9b80bcff705ea Mon Sep 17 00:00:00 2001 From: zhangpeng Date: Tue, 28 Oct 2025 19:08:22 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0MIPI=E7=9B=B8=E6=9C=BA?= =?UTF-8?q?=E6=8E=A7=E5=88=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- rk3588/dr4-rk3588.dts | 3 + rk3588/zkzg_mipi.dtsi | 178 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 rk3588/zkzg_mipi.dtsi diff --git a/rk3588/dr4-rk3588.dts b/rk3588/dr4-rk3588.dts index ea6aa7c..cd73f6d 100755 --- a/rk3588/dr4-rk3588.dts +++ b/rk3588/dr4-rk3588.dts @@ -11,6 +11,9 @@ // #include "rp-usb-typec-rk3588.dtsi" #include "rp-usb-host.dtsi" +/* mipi */ +#include "zkzg_mipi.dtsi" + /* ethernet */ // #include "rp-eth-pcie2gmac-rk3588.dtsi" #include "rp-eth-gmac0.dtsi" diff --git a/rk3588/zkzg_mipi.dtsi b/rk3588/zkzg_mipi.dtsi new file mode 100644 index 0000000..dc61210 --- /dev/null +++ b/rk3588/zkzg_mipi.dtsi @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 www.veye.cc + * + */ + +/ { + vcc_mipidphy0: vcc-mipidcphy0-regulator { + status = "disabled"; + compatible = "regulator-fixed"; + gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mipidphy0_pwr>; + regulator-name = "vcc_mipidphy0"; + enable-active-high; + }; +}; + +&csi2_dphy0 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipidphy0_in_ucam0: endpoint@1 { + reg = <1>; + remote-endpoint = <&mvcam_out0>; + data-lanes = <1 2 3 4>; + }; + }; + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + csidphy0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi2_csi2_input>; + }; + }; + }; +}; + +&csi2_dphy0_hw { + status = "okay"; +}; + +&i2c7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7m0_xfer>; + + mvcam: mvcam@3b{ + compatible = "veye,mvcam"; + reg = <0x3b>; + clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; + clock-names = "xvclk"; + pinctrl-names = "default"; + pinctrl-0 = <&mipim1_camera1_clk>; + power-domains = <&power RK3588_PD_VI>; + + //power-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; + + //avdd-supply = <&vcc_mipidcphy0>; + //firefly,clkout-enabled-index = <0>; + rockchip,camera-module-index = <0>; + rockchip,camera-module-facing = "back"; + rockchip,camera-module-name = "NC"; + rockchip,camera-module-lens-name = "NC"; + port { + mvcam_out0: endpoint { + remote-endpoint = <&mipidphy0_in_ucam0>; + data-lanes = <1 2 3 4>; + }; + }; + }; + +}; + +&mipi2_csi2 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_input: endpoint@1 { + reg = <1>; + remote-endpoint = <&csidphy0_out>; + }; + }; + + port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + mipi2_csi2_output: endpoint@0 { + reg = <0>; + remote-endpoint = <&cif_mipi2_in0>; + }; + }; + }; +}; + +&pinctrl { + cam { + mipidphy0_pwr: mipidphy0-pwr { + rockchip,pins = + /* camera power en */ + <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&rkcif { + status = "okay"; +// memory-region = <&cif_reserved>; +}; + +&rkcif_mipi_lvds2 { + status = "okay"; + //firefly,yuv_camera; + + port { + cif_mipi2_in0: endpoint { + remote-endpoint = <&mipi2_csi2_output>; + }; + }; +}; + +&rkcif_mipi_lvds2_sditf { + status = "disabled"; + + port { + mipi_lvds2_sditf: endpoint { + remote-endpoint = <&isp0_vir0>; + }; + }; +}; + +&rkcif_mmu { + status = "okay"; +}; + +&rkisp0 { + status = "disabled"; +}; + +&isp0_mmu { + status = "disabled"; +}; + +&rkisp0_vir0 { + status = "disabled"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + isp0_vir0: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds2_sditf>; + }; + }; +};