配置PCIE

rk3588/zkzg-pcie.dtsi

@@ -0,0 +1,62 @@
+/ {
+    vcc3v3_pcie30: vcc3v3-pcie30 {
+        compatible = "regulator-fixed";
+        regulator-name = "vcc3v3_pcie30";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        enable-active-high;
+        gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
+        startup-delay-us = <5000>;
+        vin-supply = <&vcc12v_dcin>;
+    };
+};
+
+&combphy0_ps {
+    status = "okay";
+};
+
+&combphy1_ps {
+    status = "okay";
+};
+
+&combphy2_psu {
+    status = "okay";
+};
+
+&pcie2x1l0 {
+    phys = <&combphy1_ps PHY_TYPE_PCIE>;
+    reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_pcie30>;
+    status = "okay";
+};
+
+&pcie2x1l1 {
+    phys = <&combphy2_psu PHY_TYPE_PCIE>;
+    reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_pcie30>;
+    status = "okay";
+};
+
+&pcie2x1l2 {
+    reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_pcie30>;
+    status = "okay";
+};
+
+&pcie30phy {
+    rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>;
+    status = "okay";
+};
+
+&pcie3x2 {
+    reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_pcie30>;
+    status = "okay";
+};
+
+&pcie3x4 {
+    num-lanes = <2>;
+    reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
+    vpcie3v3-supply = <&vcc3v3_pcie30>;
+    status = "okay";
+};