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优化gmac配置

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zhangpeng
2025-10-23 10:28:42 +08:00
parent 115e957b83
commit b64c4e9987
1 changed files with 21 additions and 22 deletions
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43
rk356x/rp-gmac0-pro-rk3568.dtsi
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@@ -1,30 +1,30 @@
&gmac0 { &gmac0 {
phy-mode = "rgmii"; phy-mode = "rgmii";
clock_in_out = "input"; clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>; assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
snps,reset-active-low; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
/* Reset time is 20ms, 100ms for rtl8211f */ assigned-clock-rates = <0>, <125000000>;
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>; pinctrl-names = "default";
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>; pinctrl-0 = <&gmac0_miim
assigned-clock-rates = <0>, <125000000>, <25000000>; &gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk_level2
&gmac0_rgmii_bus
&gmac0_clkinout>;
pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2
&gmac0_rx_bus2
&gmac0_rgmii_clk
&gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>;
tx_delay = <0x2d>; tx_delay = <0x3c>;
rx_delay = <0x2c>; rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>;
status = "okay"; phy-handle = <&rgmii_phy0>;
status = "okay";
}; };
@@ -32,6 +32,5 @@
rgmii_phy0: phy@0 { rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>; reg = <0x0>;
clocks = <&cru CLK_MAC0_OUT>;
}; };
}; };