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This commit is contained in:
zhangpeng
2025-11-01 14:21:48 +08:00
parent c6977360c3
commit 7a15762f4c
7 changed files with 202 additions and 198 deletions
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3
rk3588/.dr4-rk3588.dtb.cmd
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@@ -32,9 +32,8 @@ deps_arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dtb := \
scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h \
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/zkzg_mipi.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi \

3
rk3588/.dr4-rk3588.dtb.d.pre.tmp
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@@ -28,8 +28,7 @@ dr4-rk3588.o: arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts \
scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h \
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/zkzg_mipi.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac0.dtsi \
arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi

190
rk3588/.dr4-rk3588.dtb.dts.tmp
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@@ -14517,20 +14517,7 @@
/delete-node/ &backlight;
# 4 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-tp-i2c6-gt911.dtsi" 1
&i2c6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c6m0_xfer>;
goodix_ts:goodix_ts@5d {
status = "okay";
compatible = "goodix,gt9xx";
reg = <0x5d>;
};
};
# 6 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi" 1
@@ -14558,73 +14545,140 @@
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi" 1
&u2phy2 {
# 1 "arch/arm64/boot/dts/rockchip/rk3588/zkzg_mipi.dtsi" 1
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
mvcam: mvcam@1a {
compatible = "veye,mvcam";
status = "okay";
reg = <0x3b>;
clocks = <&cru 256>;
clock-names = "xvclk";
power-domains = <&power 27>;
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera2_clk>;
rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 3 0>;
pwdn-gpios = <&gpio1 5 0>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
mvcam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
data-lanes = <1 2 3 4>;
};
};
};
};
&csi2_dphy0_hw {
status = "okay";
};
&u2phy3 {
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam2: endpoint@1 {
reg = <1>;
remote-endpoint = <&mvcam_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&rkcif_mipi_lvds2 {
status = "okay";
port {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "okay";
port {
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp1_vir1>;
};
};
};
&u2phy2_host {
&rkisp1 {
status = "okay";
};
&u2phy3_host {
&isp1_mmu {
status = "okay";
};
&usb_host0_ehci {
&rkisp1_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp1_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_lvds_sditf>;
};
&usb_host0_ohci {
status = "okay";
};
&usb_host1_ehci {
status = "okay";
};
&usb_host1_ohci {
status = "okay";
};
&usbhost3_0 {
status = "okay";
};
&usbhost_dwc3_0 {
status = "okay";
};
&usbdrd_dwc3_0 {
extcon=<&u2phy0>;
status="okay";
};
&u2phy0 {
status = "okay";
};
&usbdrd_dwc3_1 {
extcon=<&u2phy1>;
status="okay";
};
&u2phy1 {
status = "okay";
};
# 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 16 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
@@ -14662,7 +14716,7 @@
phy-handle = <&rgmii_phy0>;
status = "okay";
};
# 17 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 20 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi" 1
&mdio1 {
@@ -14689,8 +14743,8 @@
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus
&gmac1_clkinout
&eth1_pins>;
&gmac1_clkinout>;
tx_delay = <0x44>;
@@ -14698,8 +14752,8 @@
phy-handle = <&rgmii_phy1>;
status = "okay";
};
# 18 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 90 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
# 21 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 93 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
/ {
model = "dr4-rk3588";
@@ -14735,7 +14789,7 @@
status = "okay";
compatible = "rp_power";
rp_not_deep_sleep = <1>;
# 142 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
# 145 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
usb-host-power {
gpio_num = <&gpio2 17 0>;
gpio_function = <4>;
@@ -14885,11 +14939,11 @@ clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
};
&hdptxphy_hdmi_clk0 {
status = "okay";
status = "disabled";
};
&hdptxphy_hdmi_clk1 {
status = "okay";
status = "disabled";
};
&pwm14 {

BIN
rk3588/dr4-rk3588.dtb
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Binary file not shown.

8
rk3588/dr4-rk3588.dts
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@@ -2,14 +2,14 @@
//#include "../rk3588-evb4-lp4-v10-linux.dts"
#include "rp-rk3588-board.dtsi"
#include "rp-tp-i2c6-gt911.dtsi"
// #include "rp-tp-i2c6-gt911.dtsi"
// #include "rd-rk3588-lcd-gpio.dtsi"
#include "rpdzkj_config.dtsi"
/* usb */
// #include "rp-usb-typec-rk3588.dtsi"
#include "rp-usb-host.dtsi"
// #include "rp-usb-host.dtsi"
/* mipi */
#include "zkzg_mipi.dtsi"
@@ -291,11 +291,11 @@ clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
};
&hdptxphy_hdmi_clk0 {
status = "okay";
status = "disabled";
};
&hdptxphy_hdmi_clk1 {
status = "okay";
status = "disabled";
};
&pwm14 {

4
rk3588/rp-eth-gmac1.dtsi
View File

@@ -23,8 +23,8 @@
&gmac1_rx_bus2
&gmac1_rgmii_clk
&gmac1_rgmii_bus
&gmac1_clkinout
&eth1_pins>;
&gmac1_clkinout>;
// &eth1_pins>;
tx_delay = <0x44>;
// rx_delay = <0x4f>;

172
rk3588/zkzg_mipi.dtsi
View File

@@ -1,48 +1,33 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 www.veye.cc
*
*/
/ {
vcc_mipidphy0: vcc-mipidcphy0-regulator {
status = "disabled";
compatible = "regulator-fixed";
gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipidphy0_pwr>;
regulator-name = "vcc_mipidphy0";
enable-active-high;
};
};
&csi2_dphy0 {
&i2c7 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipidphy0_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&mvcam_out0>;
mvcam: mvcam@1a {
compatible = "veye,mvcam";
status = "okay";
reg = <0x3b>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera2_clk>;
rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <2>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT2022-PX1";
rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20";
port {
mvcam_out0: endpoint {
remote-endpoint = <&mipi_in_ucam2>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
@@ -50,129 +35,96 @@
status = "okay";
};
&i2c7 {
&csi2_dphy0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c7m0_xfer>;
mvcam: mvcam@3b{
compatible = "veye,mvcam";
reg = <0x3b>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M1>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim1_camera1_clk>;
power-domains = <&power RK3588_PD_VI>;
//power-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>;
//avdd-supply = <&vcc_mipidcphy0>;
//firefly,clkout-enabled-index = <0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "NC";
rockchip,camera-module-lens-name = "NC";
port {
mvcam_out0: endpoint {
remote-endpoint = <&mipidphy0_in_ucam0>;
data-lanes = <1 2 3 4>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam2: endpoint@1 {
reg = <1>;
remote-endpoint = <&mvcam_out0>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&mipi2_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csidphy0_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi2_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi2_in0>;
remote-endpoint = <&cif_mipi_in2>;
};
};
};
};
&pinctrl {
cam {
mipidphy0_pwr: mipidphy0-pwr {
rockchip,pins =
/* camera power en */
<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&rkcif {
status = "okay";
// memory-region = <&cif_reserved>;
};
&rkcif_mipi_lvds2 {
status = "okay";
//firefly,yuv_camera;
port {
cif_mipi2_in0: endpoint {
cif_mipi_in2: endpoint {
remote-endpoint = <&mipi2_csi2_output>;
};
};
};
&rkcif_mipi_lvds2_sditf {
status = "disabled";
status = "okay";
port {
mipi_lvds2_sditf: endpoint {
remote-endpoint = <&isp0_vir0>;
mipi2_lvds_sditf: endpoint {
remote-endpoint = <&isp1_vir1>;
};
};
};
&rkcif_mmu {
&rkisp1 {
status = "okay";
};
&rkisp0 {
status = "disabled";
&isp1_mmu {
status = "okay";
};
&isp0_mmu {
status = "disabled";
};
&rkisp0_vir0 {
status = "disabled";
&rkisp1_vir1 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp0_vir0: endpoint@0 {
isp1_vir1: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds2_sditf>;
remote-endpoint = <&mipi2_lvds_sditf>;
};
};
};