From 591fa0c3f9480df0816cc191cb3015f332222f67 Mon Sep 17 00:00:00 2001
From: zhangpeng <philzhang1319@outlook.com>
Date: Thu, 16 Oct 2025 17:00:39 +0800
Subject: [PATCH] =?UTF-8?q?=E5=8F=AA=E4=BD=BF=E7=94=A8=E4=B8=B2=E5=8F=A3pc?=
 =?UTF-8?q?ie?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 rk3588/.dr4-rk3588.dtb.dts.tmp |  16 ++++++++--------
 rk3588/dr4-rk3588.dtb          | Bin 263477 -> 263493 bytes
 rk3588/zkzg-pcie.dtsi          |   8 ++++----
 3 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/rk3588/.dr4-rk3588.dtb.dts.tmp b/rk3588/.dr4-rk3588.dtb.dts.tmp
index 7763c8c..f88b648 100644
--- a/rk3588/.dr4-rk3588.dtb.dts.tmp
+++ b/rk3588/.dr4-rk3588.dtb.dts.tmp
@@ -1,6 +1,6 @@
-# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
-# 1 "<built-in>"
-# 1 "<command-line>"
+# 0 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
+# 0 "<built-in>"
+# 0 "<command-line>"
 # 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
 
 
@@ -10674,7 +10674,7 @@
   };
  };
 };
-# 6887 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
+# 6888 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
 # 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2
 # 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 1
 
@@ -14691,20 +14691,20 @@
     phys = <&combphy1_ps 2>;
     reset-gpios = <&gpio4 5 0>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 
 &pcie2x1l1 {
     phys = <&combphy2_psu 2>;
     reset-gpios = <&gpio4 2 0>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 
 &pcie2x1l2 {
     reset-gpios = <&gpio4 17 0>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 
 &pcie30phy {
@@ -14722,7 +14722,7 @@
     num-lanes = <2>;
     reset-gpios = <&gpio4 14 0>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 # 22 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
 # 68 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
diff --git a/rk3588/dr4-rk3588.dtb b/rk3588/dr4-rk3588.dtb
index 182b765b72e3a64a5f59ec93669dfaaff83359d6..fcd4c983481f3eff32face9fdb7dd2d1bd83e63e 100644
GIT binary patch
delta 83
zcmdnmC2+J$K;Q!Jzqbr5tgZ|U3>FN`8(&Nm5NF)bsIgUpadyRI^=ygl*DDw+SU{}y
g<XXn<$+b)YVPNs&mzhL3!Q$`lFl~Q-huKX70LU&LfdBvi

delta 87
zcmX@wC9t(iK;Q!Jzqbr5tfmYM3>FN`8*fY$5NBM_sIgUpadyS@=o?H5+n-l3=CFX7
h?d7$M+skX2T*4qS_b)SXa6)9b?=o%YzRPT-0RUJOA7=mn

diff --git a/rk3588/zkzg-pcie.dtsi b/rk3588/zkzg-pcie.dtsi
index b707bf1..b562f28 100755
--- a/rk3588/zkzg-pcie.dtsi
+++ b/rk3588/zkzg-pcie.dtsi
@@ -27,20 +27,20 @@
     phys = <&combphy1_ps PHY_TYPE_PCIE>;
     reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 
 &pcie2x1l1 {
     phys = <&combphy2_psu PHY_TYPE_PCIE>;
     reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 
 &pcie2x1l2 {
     reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
 
 &pcie30phy {
@@ -58,5 +58,5 @@
     num-lanes = <2>;
     reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
     vpcie3v3-supply = <&vcc3v3_pcie30>;
-    status = "okay";
+    status = "disabled";
 };
\ No newline at end of file