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优化gmac配置

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zhangpeng
2025-10-23 10:24:30 +08:00
parent 4b55c90c22
commit 58da0ee3c8
3 changed files with 37 additions and 37 deletions
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20
rk356x/.dr4-rk3568.dtb.dts.tmp
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@@ -8858,9 +8858,6 @@ dsi1_panel: panel@0 {
vpcie3v3-supply = <&vcc3v3_sys>; vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay"; status = "okay";
memory-region = <&pcie_dma>; memory-region = <&pcie_dma>;
}; };
# 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 # 16 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
# 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" # 28 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
@@ -8869,27 +8866,27 @@ dsi1_panel: panel@0 {
&gmac0 { &gmac0 {
phy-mode = "rgmii"; phy-mode = "rgmii";
clock_in_out = "input"; clock_in_out = "input";
snps,reset-gpio = <&gpio2 21 1>; snps,reset-gpio = <&gpio2 21 1>;
snps,reset-active-low; snps,reset-active-low;
snps,reset-delays-us = <0 20000 100000>; snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru 389>, <&cru 386>, <&cru 183>; assigned-clocks = <&cru 389>, <&cru 386>;
assigned-clock-parents = <&cru 387>, <&gmac0_clkin>, <&cru 182>; assigned-clock-parents = <&cru 387>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>, <25000000>; assigned-clock-rates = <0>, <125000000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2 &gmac0_tx_bus2
&gmac0_rx_bus2 &gmac0_rx_bus2
&gmac0_rgmii_clk &gmac0_rgmii_clk_level2
&gmac0_rgmii_bus &gmac0_rgmii_bus
&eth0_pins
&gmac0_clkinout>; &gmac0_clkinout>;
tx_delay = <0x2d>;
rx_delay = <0x2c>; tx_delay = <0x3c>;
rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>; phy-handle = <&rgmii_phy0>;
status = "okay"; status = "okay";
}; };
@@ -8899,7 +8896,6 @@ dsi1_panel: panel@0 {
rgmii_phy0: phy@0 { rgmii_phy0: phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>; reg = <0x0>;
clocks = <&cru 183>;
}; };
}; };
# 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2 # 29 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2

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rk356x/dr4-rk3568.dtb
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14
rk356x/rp-gmac0-pro-rk3568.dtsi
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@@ -2,23 +2,27 @@
&gmac0 { &gmac0 {
phy-mode = "rgmii"; phy-mode = "rgmii";
clock_in_out = "input"; clock_in_out = "input";
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>;
assigned-clock-rates = <0>, <125000000>; assigned-clock-rates = <0>, <125000000>;
snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
snps,reset-active-high;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&gmac0_miim pinctrl-0 = <&gmac0_miim
&gmac0_tx_bus2 &gmac0_tx_bus2
&gmac0_rx_bus2 &gmac0_rx_bus2
&gmac0_rgmii_clk &gmac0_rgmii_clk_level2
&gmac0_rgmii_bus &gmac0_rgmii_bus
&gmac0_clkinout>; &gmac0_clkinout>;
tx_delay = <0x3c>; tx_delay = <0x3c>;
rx_delay = <0x2f>; rx_delay = <0x2f>;
phy-handle = <&rgmii_phy0>; phy-handle = <&rgmii_phy0>;
status = "okay"; status = "okay";
}; };