串口、网口、USB3.0、HDMI调试成功

This commit is contained in:
zhangpeng 2025-05-26 18:18:57 +08:00
parent 92bc223ace
commit 3bbdf81bc5
4 changed files with 45 additions and 118 deletions

View File

@ -14600,11 +14600,29 @@
&usbhost3_0 { &usbhost3_0 {
status = "disabled"; status = "okay";
}; };
&usbhost_dwc3_0 { &usbhost_dwc3_0 {
status = "disabled"; status = "okay";
};
&usbdrd_dwc3_0 {
extcon=<&u2phy0>;
status="okay";
};
&u2phy0 {
status = "okay";
};
&usbdrd_dwc3_1 {
extcon=<&u2phy1>;
status="okay";
};
&u2phy1 {
status = "okay";
}; };
# 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2 # 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
@ -14810,24 +14828,10 @@
}; };
}; };
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
fifo-depth =<4096>;
rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>;
dma-names = "tx", "rx";
};
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart1m2_xfer>; pinctrl-0 = <&uart1m1_xfer>;
fifo-depth =<4096>; fifo-depth =<4096>;
rx-fifo-depth =<2048>; rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>; tx-fifo-depth =<2048>;
@ -14866,21 +14870,10 @@
}; };
&uart6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart6m2_xfer>;
fifo-depth =<4096>;
rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>;
dma-names = "tx", "rx";
};
&uart7 { &uart7 {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>; pinctrl-0 = <&uart7m0_xfer>;
fifo-depth =<4096>; fifo-depth =<4096>;
rx-fifo-depth =<2048>; rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>; tx-fifo-depth =<2048>;
@ -14897,27 +14890,6 @@
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9m2_xfer>;
fifo-depth =<4096>;
rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>;
dma-names = "tx", "rx";
};
&can0 {
assigned-clocks = <&cru 112>;
assigned-clock-rates = <200000000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&can0m0_pins>;
};
&can1 { &can1 {
assigned-clocks = <&cru 114>; assigned-clocks = <&cru 114>;
assigned-clock-rates = <200000000>; assigned-clock-rates = <200000000>;
@ -14926,14 +14898,6 @@
pinctrl-0 = <&can1m1_pins>; pinctrl-0 = <&can1m1_pins>;
}; };
&can2 {
assigned-clocks = <&cru 116>;
assigned-clock-rates = <200000000>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&can2m1_pins>;
};
&spi3 { &spi3 {
status = "okay"; status = "okay";
pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>; pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
@ -14968,7 +14932,7 @@
}; };
&sdmmc { &sdmmc {
status = "okay"; status = "disabled";
}; };
&fiq_debugger { &fiq_debugger {

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@ -161,24 +161,10 @@
}; };
}; };
&uart0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart0m0_xfer>;
fifo-depth =<4096>;
rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>;
dma-names = "tx", "rx";
};
&uart1 { &uart1 {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart1m2_xfer>; pinctrl-0 = <&uart1m1_xfer>;
fifo-depth =<4096>; fifo-depth =<4096>;
rx-fifo-depth =<2048>; rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>; tx-fifo-depth =<2048>;
@ -217,21 +203,10 @@
}; };
&uart6 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart6m2_xfer>;
fifo-depth =<4096>;
rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>;
dma-names = "tx", "rx";
};
&uart7 { &uart7 {
status = "okay"; status = "okay";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>; pinctrl-0 = <&uart7m0_xfer>;
fifo-depth =<4096>; fifo-depth =<4096>;
rx-fifo-depth =<2048>; rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>; tx-fifo-depth =<2048>;
@ -248,27 +223,6 @@
dma-names = "tx", "rx"; dma-names = "tx", "rx";
}; };
&uart9 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart9m2_xfer>;
fifo-depth =<4096>;
rx-fifo-depth =<2048>;
tx-fifo-depth =<2048>;
dma-names = "tx", "rx";
};
&can0 {
assigned-clocks = <&cru CLK_CAN0>;
assigned-clock-rates = <200000000>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&can0m0_pins>;
};
&can1 { &can1 {
assigned-clocks = <&cru CLK_CAN1>; assigned-clocks = <&cru CLK_CAN1>;
assigned-clock-rates = <200000000>; assigned-clock-rates = <200000000>;
@ -277,14 +231,6 @@
pinctrl-0 = <&can1m1_pins>; pinctrl-0 = <&can1m1_pins>;
}; };
&can2 {
assigned-clocks = <&cru CLK_CAN2>;
assigned-clock-rates = <200000000>;
status = "disabled";
pinctrl-names = "default";
pinctrl-0 = <&can2m1_pins>;
};
&spi3 { &spi3 {
status = "okay"; status = "okay";
pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>; pinctrl-0 = <&spi3m1_pins &spi3m1_cs1>;
@ -319,7 +265,7 @@
}; };
&sdmmc { &sdmmc {
status = "okay"; status = "disabled";
}; };
&fiq_debugger { &fiq_debugger {

View File

@ -39,10 +39,27 @@
&usbhost3_0 { &usbhost3_0 {
status = "disabled"; status = "okay";
}; };
&usbhost_dwc3_0 { &usbhost_dwc3_0 {
status = "disabled"; status = "okay";
}; };
&usbdrd_dwc3_0 {
extcon=<&u2phy0>;
status="okay";
};
&u2phy0 {
status = "okay";
};
&usbdrd_dwc3_1 {
extcon=<&u2phy1>;
status="okay";
};
&u2phy1 {
status = "okay";
};