From 37cc8084febd20a74e4f2a849a765a0fa596dae1 Mon Sep 17 00:00:00 2001
From: zhangpeng <philzhang1319@outlook.com>
Date: Thu, 9 Oct 2025 13:45:08 +0800
Subject: [PATCH] =?UTF-8?q?=E9=85=8D=E7=BD=AEUART=E3=80=81CAN=E5=92=8C?=
 =?UTF-8?q?=E7=BD=91=E7=BB=9C?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 rk356x/.dr4-rk3568.dtb.cmd       |   2 +-
 rk356x/.dr4-rk3568.dtb.d.pre.tmp |   4 +-
 rk356x/.dr4-rk3568.dtb.dts.tmp   | 109 ++++++++++++++++---------------
 rk356x/dr4-rk3568.dtb            | Bin 170951 -> 170960 bytes
 rk356x/dr4-rk3568.dts            |   7 +-
 rk356x/rp-gmac0-pro-rk3568.dtsi  |   2 +-
 rk356x/zkzg-can-rk3568.dtsi      |  17 +++++
 7 files changed, 82 insertions(+), 59 deletions(-)
 create mode 100644 rk356x/zkzg-can-rk3568.dtsi

diff --git a/rk356x/.dr4-rk3568.dtb.cmd b/rk356x/.dr4-rk3568.dtb.cmd
index 88ee0dd..980308d 100644
--- a/rk356x/.dr4-rk3568.dtb.cmd
+++ b/rk356x/.dr4-rk3568.dtb.cmd
@@ -27,8 +27,8 @@ deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb := \
   arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
   arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
   arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
-  arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
   arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
+  arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi \
 
 arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb: $(deps_arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dtb)
 
diff --git a/rk356x/.dr4-rk3568.dtb.d.pre.tmp b/rk356x/.dr4-rk3568.dtb.d.pre.tmp
index c5d9819..3f91f71 100644
--- a/rk356x/.dr4-rk3568.dtb.d.pre.tmp
+++ b/rk356x/.dr4-rk3568.dtb.d.pre.tmp
@@ -23,5 +23,5 @@ dr4-rk3568.o: arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts \
  arch/arm64/boot/dts/rockchip/rk356x/../rk3568-pinctrl.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/../rockchip-pinconf.dtsi \
  arch/arm64/boot/dts/rockchip/rk356x/../rk3568-linux.dtsi \
- arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi \
- arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi
+ arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi \
+ arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi
diff --git a/rk356x/.dr4-rk3568.dtb.dts.tmp b/rk356x/.dr4-rk3568.dtb.dts.tmp
index 2efe49c..12bfb23 100644
--- a/rk356x/.dr4-rk3568.dtb.dts.tmp
+++ b/rk356x/.dr4-rk3568.dtb.dts.tmp
@@ -682,6 +682,25 @@
   };
 
 
+  opp-j-408000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <408000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+  };
+  opp-j-600000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <600000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+  };
+  opp-j-816000000 {
+   opp-supported-hw = <0xfb 0xffff>;
+   opp-hz = /bits/ 64 <816000000>;
+   opp-microvolt = <850000 850000 1150000>;
+   clock-latency-ns = <40000>;
+   opp-suspend;
+  };
   opp-j-1008000000 {
    opp-supported-hw = <0x04 0xffff>;
    opp-hz = /bits/ 64 <1008000000>;
@@ -4166,7 +4185,7 @@
   rockchip,grf = <&grf>;
   status = "disabled";
  };
-# 3726 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
+# 3745 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi"
  csi2_dphy0: csi2-dphy0 {
   compatible = "rockchip,rk3568-csi2-dphy";
   rockchip,hw = <&csi2_dphy_hw>;
@@ -7849,7 +7868,7 @@
   };
  };
 };
-# 3872 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
+# 3891 "arch/arm64/boot/dts/rockchip/rk356x/../rk3568.dtsi" 2
 # 18 "arch/arm64/boot/dts/rockchip/rk356x/rk3566-evb-rpdzkj-rk809-tcs4525.dtsi" 2
 
 / {
@@ -8817,53 +8836,14 @@ dsi1_panel: panel@0 {
  disable-win-move;
 };
 # 13 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
-# 24 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
-# 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac1-m1-pro-rk3568.dtsi" 1
-
-&gmac1 {
-    phy-mode = "rgmii";
-    clock_in_out = "input";
-
-    snps,reset-gpio = <&gpio3 3 1>;
-    snps,reset-active-low;
-
-    snps,reset-delays-us = <0 20000 100000>;
-
-    assigned-clocks = <&cru 393>, <&cru 390>, <&cru 198>;
-    assigned-clock-parents = <&cru 391>,<&gmac1_clkin>, <&cru 197>;
-    assigned-clock-rates = <0>, <125000000>, <25000000>;
-
-    pinctrl-names = "default";
-    pinctrl-0 = <&gmac1m1_miim
-             &gmac1m1_tx_bus2
-             &gmac1m1_rx_bus2
-             &gmac1m1_rgmii_clk
-             &gmac1m1_rgmii_bus
-            &eth1m0_pins
-            &gmac1m1_clkinout>;
-
-    tx_delay = <0x3a>;
-    rx_delay = <0x29>;
-    phy-handle = <&rgmii_phy1>;
-    status = "okay";
-};
-
-
-&mdio1 {
-    rgmii_phy1: phy@0 {
-        compatible = "ethernet-phy-ieee802.3-c22";
-        reg = <0x0>;
-        clocks = <&cru 198>;
-    };
-};
-# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 25 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 # 1 "arch/arm64/boot/dts/rockchip/rk356x/rp-gmac0-pro-rk3568.dtsi" 1
 
 &gmac0 {
     phy-mode = "rgmii";
     clock_in_out = "input";
 
-    snps,reset-gpio = <&gpio3 4 1>;
+    snps,reset-gpio = <&gpio2 21 1>;
     snps,reset-active-low;
 
     snps,reset-delays-us = <0 20000 100000>;
@@ -8896,7 +8876,32 @@ dsi1_panel: panel@0 {
     };
 };
 # 26 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
-# 78 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+
+
+
+
+
+
+# 1 "arch/arm64/boot/dts/rockchip/rk356x/zkzg-can-rk3568.dtsi" 1
+&can0 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru 321>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can0m1_pins>;
+    status = "okay";
+};
+
+&can1 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru 323>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can1m1_pins>;
+    status = "okay";
+};
+# 33 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" 2
+# 79 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 /{
         model = "dr4-rk3568";
         compatible = "rpdzkj,dr4-rk3568", "rockchip,rk3568";
@@ -8917,7 +8922,7 @@ dsi1_panel: panel@0 {
 
                 pinctrl-name = "default";
                 pinctrl-0 = <&rp_power>;
-# 121 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 122 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
                 otg_mode {
                         gpio_num = <&gpio1 4 1>;
                         gpio_function = <0>;
@@ -8926,13 +8931,13 @@ dsi1_panel: panel@0 {
                         gpio_num = <&gpio0 5 0>;
                         gpio_function = <4>;
                 };
-# 169 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 170 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
         };
 
         rp_gpio{
                 status = "disabled";
                 compatible = "rp_gpio";
-# 182 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 183 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
                 gpio0a0 {
                         gpio_num = <&gpio0 0 1>;
                         gpio_function = <0>;
@@ -9062,13 +9067,13 @@ dsi1_panel: panel@0 {
 };
 
 &uart7 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart7m1_xfer>;
 };
 
 &uart8 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart8m0_xfer>;
 };
@@ -9109,7 +9114,7 @@ dsi1_panel: panel@0 {
 
     status = "disabled";
 };
-# 417 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 418 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &rk_headset {
     pinctrl-0 = <&hp_det>;
     headset_gpio = <&gpio2 27 0>;
@@ -9158,7 +9163,7 @@ dsi1_panel: panel@0 {
     BT,wake_host_irq = <&gpio0 28 0>;
     status = "disabled";
 };
-# 515 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 516 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 &pinctrl {
     rp_pins {
         rp_power: rp-power {
@@ -9198,7 +9203,7 @@ dsi1_panel: panel@0 {
                 <3 2 0 &pcfg_pull_none>;
         };
     };
-# 569 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
+# 570 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts"
 };
 
 
diff --git a/rk356x/dr4-rk3568.dtb b/rk356x/dr4-rk3568.dtb
index dad98565aeee70b7af7af226705ae4666a61c9c1..44a7af41ed515c9c303c31877bedc8b0df9e0c62 100644
GIT binary patch
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diff --git a/rk356x/dr4-rk3568.dts b/rk356x/dr4-rk3568.dts
index 0c6f90e..f8cb2ee 100755
--- a/rk356x/dr4-rk3568.dts
+++ b/rk356x/dr4-rk3568.dts
@@ -21,7 +21,7 @@
 /***************************************************/
 
 /*************************gmac***********************/
-#include "rp-gmac1-m1-pro-rk3568.dtsi"
+// #include "rp-gmac1-m1-pro-rk3568.dtsi"
 #include "rp-gmac0-pro-rk3568.dtsi"
 /***************************************************/
 
@@ -29,6 +29,7 @@
 // #include "rp-can0-m0-rk3568.dtsi"
 // #include "rp-can1-m1-rk3568.dtsi"
 // #include "rp-can2-m0-rk3568.dtsi"
+#include "zkzg-can-rk3568.dtsi"
 /**************************************************/
 
 /*********************PCIE**************************/
@@ -308,13 +309,13 @@
 };
 
 &uart7 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart7m1_xfer>;
 };
 
 &uart8 {
-    status = "okay";
+    status = "disabled";
     pinctrl-names = "default";
     pinctrl-0 = <&uart8m0_xfer>;
 };
diff --git a/rk356x/rp-gmac0-pro-rk3568.dtsi b/rk356x/rp-gmac0-pro-rk3568.dtsi
index a26a910..cf4da75 100755
--- a/rk356x/rp-gmac0-pro-rk3568.dtsi
+++ b/rk356x/rp-gmac0-pro-rk3568.dtsi
@@ -3,7 +3,7 @@
     phy-mode = "rgmii";
     clock_in_out = "input";
 
-    snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
+    snps,reset-gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_LOW>;
     snps,reset-active-low;
     /* Reset time is 20ms, 100ms for rtl8211f */
     snps,reset-delays-us = <0 20000 100000>;
diff --git a/rk356x/zkzg-can-rk3568.dtsi b/rk356x/zkzg-can-rk3568.dtsi
new file mode 100644
index 0000000..81e7e78
--- /dev/null
+++ b/rk356x/zkzg-can-rk3568.dtsi
@@ -0,0 +1,17 @@
+&can0 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru CLK_CAN0>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can0m1_pins>;
+    status = "okay";
+};
+
+&can1 {
+    compatible = "rockchip,rk3568-can-2.0";
+    assigned-clocks = <&cru CLK_CAN1>;
+    assigned-clock-rates = <150000000>;
+    pinctrl-names = "default";
+    pinctrl-0 = <&can1m1_pins>;
+    status = "okay";
+};