diff --git a/rk356x/.dr4-rk3568.dtb.dts.tmp b/rk356x/.dr4-rk3568.dtb.dts.tmp index d849176..c66c000 100644 --- a/rk356x/.dr4-rk3568.dtb.dts.tmp +++ b/rk356x/.dr4-rk3568.dtb.dts.tmp @@ -9054,26 +9054,26 @@ dsi1_panel: panel@0 { }; &uart3 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&uart3m1_xfer>; }; &uart4 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&uart4m0_xfer>; }; &uart5 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&uart5m0_xfer>; }; &uart6 { - status = "okay"; + status = "disabled"; pinctrl-names = "default"; pinctrl-0 = <&uart6m1_xfer>; }; @@ -9105,6 +9105,20 @@ dsi1_panel: panel@0 { }; }; +&spi1 { + status = "okay"; + + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>; + + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + &video_phy1 { status = "disabled"; }; @@ -9126,7 +9140,7 @@ dsi1_panel: panel@0 { status = "disabled"; }; -# 421 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" +# 435 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" &rk_headset { pinctrl-0 = <&hp_det>; headset_gpio = <&gpio2 27 0>; @@ -9175,7 +9189,7 @@ dsi1_panel: panel@0 { BT,wake_host_irq = <&gpio0 28 0>; status = "disabled"; }; -# 519 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" +# 533 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" &pinctrl { rp_pins { rp_power: rp-power { @@ -9215,7 +9229,7 @@ dsi1_panel: panel@0 { <3 2 0 &pcfg_pull_none>; }; }; -# 573 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" +# 587 "arch/arm64/boot/dts/rockchip/rk356x/dr4-rk3568.dts" }; diff --git a/rk356x/dr4-rk3568.dtb b/rk356x/dr4-rk3568.dtb index 010ccd9..750b0fe 100644 Binary files a/rk356x/dr4-rk3568.dtb and b/rk356x/dr4-rk3568.dtb differ diff --git a/rk356x/dr4-rk3568.dts b/rk356x/dr4-rk3568.dts index 0b84d44..dc509ee 100755 --- a/rk356x/dr4-rk3568.dts +++ b/rk356x/dr4-rk3568.dts @@ -338,6 +338,20 @@ }; }; +&spi1 { + status = "okay"; + /** redefine pins for cs1 used to be pwm5 */ + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>; + pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins_hs>; + + spi_dev@0 { + compatible = "rockchip,spidev"; + reg = <0>; + spi-max-frequency = <12000000>; + spi-lsb-first; + }; +}; + &video_phy1 { status = "disabled"; };