2025-04-28 03:36:59 +00:00
|
|
|
|
|
|
|
|
&gmac0 {
|
|
|
|
|
phy-mode = "rgmii";
|
|
|
|
|
clock_in_out = "input";
|
|
|
|
|
|
2025-05-12 06:54:18 +00:00
|
|
|
snps,reset-gpio = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>;
|
2025-04-28 03:36:59 +00:00
|
|
|
snps,reset-active-low;
|
|
|
|
|
/* Reset time is 20ms, 100ms for rtl8211f */
|
|
|
|
|
snps,reset-delays-us = <0 20000 100000>;
|
|
|
|
|
|
|
|
|
|
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>, <&cru CLK_MAC0_OUT>;
|
|
|
|
|
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&gmac0_clkin>, <&cru CLK_MAC0_2TOP>;
|
|
|
|
|
assigned-clock-rates = <0>, <125000000>, <25000000>;
|
|
|
|
|
|
|
|
|
|
pinctrl-names = "default";
|
|
|
|
|
pinctrl-0 = <&gmac0_miim
|
|
|
|
|
&gmac0_tx_bus2
|
|
|
|
|
&gmac0_rx_bus2
|
|
|
|
|
&gmac0_rgmii_clk
|
|
|
|
|
&gmac0_rgmii_bus
|
|
|
|
|
ð0_pins
|
|
|
|
|
&gmac0_clkinout>;
|
|
|
|
|
|
|
|
|
|
tx_delay = <0x2d>;
|
|
|
|
|
rx_delay = <0x2c>;
|
|
|
|
|
phy-handle = <&rgmii_phy0>;
|
|
|
|
|
status = "okay";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
&mdio0 {
|
|
|
|
|
rgmii_phy0: phy@0 {
|
|
|
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
|
|
|
reg = <0x0>;
|
|
|
|
|
clocks = <&cru CLK_MAC0_OUT>;
|
|
|
|
|
};
|
|
|
|
|
};
|
