rockchip/rk3588/rp-camera-dcphy1-mipi-xs9922b-rk3588s.dtsi

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2025-04-28 03:36:59 +00:00
/**
* mipi csi to xs9922b config
*/
#define RP_CAMERA_XS9922B
&i2c3 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&i2c3m1_xfer>;
xs9922_1: xs9922_1@30 {
compatible = "xs9922";
status = "okay";
reg = <0x30>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&xs9922_pwr_1>;
reset-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
// power-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
//avdd-supply = <&vcc_avdd>;
//dovdd-supply = <&vcc_dovdd>;
//dvdd-supply = <&vcc_dvdd>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "default";
rockchip,camera-module-lens-name = "default";
rockchip,default_rect= <1280 720>;
port {
xs9922_out1: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2 3 4>;
};
};
};
};
#ifndef RP_DOUBLE_XS9922B //rd-rk3588s-ahd share the same power-gpio
&xs9922_1 {
power-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
};
&pinctrl {
xs9922_1 {
xs9922_pwr_1: camera-pwr-1 {
rockchip,pins =
<4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
<4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
#else
&pinctrl {
xs9922_1 {
xs9922_pwr_1: camera-pwr-1 {
rockchip,pins =
<4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
#endif
&mipi_dcphy1 {
status = "okay";
};
// CIF
&csi2_dcphy1 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&xs9922_out1>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidcphy1_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi1_csi2_input>;
};
};
};
};
&mipi1_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_input: endpoint@0 {
reg = <0>;
remote-endpoint = <&csidcphy1_out>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi1_csi2_output: endpoint@1 {
reg = <1>;
remote-endpoint = <&cif_mipi_in1>;
};
};
};
};
&rkcif_mipi_lvds1 {
status = "okay";
port {
cif_mipi_in1: endpoint {
remote-endpoint = <&mipi1_csi2_output>;
};
};
};
&rkcif_mipi_lvds1_sditf {
status = "okay";
port {
mipi_lvds1_sditf: endpoint {
remote-endpoint = <&isp1_vir0>;
};
};
};
&rkcif {
status = "okay";
};
&rkcif_mmu {
status = "okay";
};
&rkisp1 {
status = "okay";
};
&isp1_mmu {
status = "okay";
};
&rkisp1_vir0 {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
isp1_vir0: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds1_sditf>;
};
};
};