559 lines
20 KiB
Plaintext
559 lines
20 KiB
Plaintext
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/ {
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backlight: backlight {
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status = "okay";
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compatible = "pwm-backlight";
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pwms = <&pwm0 0 25000 0>;
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brightness-levels = <
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0 1 2 3 4 5 6 7
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8 9 10 11 12 13 14 15
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16 17 18 19 20 21 22 23
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24 25 26 27 28 29 30 31
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32 33 34 35 36 37 38 39
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40 41 42 43 44 45 46 47
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48 49 50 51 52 53 54 55
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56 57 58 59 60 61 62 63
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64 65 66 67 68 69 70 71
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72 73 74 75 76 77 78 79
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80 81 82 83 84 85 86 87
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88 89 90 91 92 93 94 95
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96 97 98 99 100 101 102 103
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104 105 106 107 108 109 110 111
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112 113 114 115 116 117 118 119
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120 121 122 123 124 125 126 127
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128 129 130 131 132 133 134 135
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136 137 138 139 140 141 142 143
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144 145 146 147 148 149 150 151
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152 153 154 155 156 157 158 159
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160 161 162 163 164 165 166 167
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168 169 170 171 172 173 174 175
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176 177 178 179 180 181 182 183
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184 185 186 187 188 189 190 191
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192 193 194 195 196 197 198 199
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200 201 202 203 204 205 206 207
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208 209 210 211 212 213 214 215
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216 217 218 219 220 221 222 223
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224 225 226 227 228 229 230 231
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232 233 234 235 236 237 238 239
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240 241 242 243 244 245 246 247
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248 249 250 251 252 253 254 255>;
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default-brightness-level = <255>;
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};
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};
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&hdmi {
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#address-cells = <1>;
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#size-cells = <0>;
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#sound-dai-cells = <0>;
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ddc-i2c-scl-high-time-ns = <9625>;
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ddc-i2c-scl-low-time-ns = <10000>;
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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&display_subsystem {
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status = "okay";
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ports = <&vopb_out>, <&vopl_out>;
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logo-memory-region = <&drm_logo>;
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route {
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route_hdmi: route-hdmi {
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status = "okay";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_hdmi>;
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};
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route_dsi: route-dsi {
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status = "okay";
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//status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_dsi>;
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};
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route_dsi1: route-dsi1 {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopl_out_dsi1>;
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};
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route_edp: route-edp {
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status = "disabled";
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logo,uboot = "logo.bmp";
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logo,kernel = "logo_kernel.bmp";
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logo,mode = "center";
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charge_logo,mode = "center";
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connect = <&vopb_out_edp>;
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};
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};
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};
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&dsi {
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status = "okay";
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rockchip,lane-rate = <480>;
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panel {
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compatible ="simple-panel-dsi";
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status = "okay";
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reg = <0>;
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power-supply = <&vcc3v3_sys>;
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backlight = <&backlight>;
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cmd_later_reset = <0>;
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enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM|MIPI_DSI_MODE_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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// bus-format = <MEDIA_BUS_FMT_RGB666_1X24>;
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dsi,lanes = <4>;
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reset-delay-ms = <20>;
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init-delay-ms = <20>;
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enable-delay-ms = <120>;
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prepare-delay-ms = <120>;
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//for king/rp/rd board cannot enable boot logo
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pinctrl-names = "default";
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pinctrl-0 = <&pwr_en>;
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panel-init-sequence = [
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39 00 04 FF 98 81 03
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39 00 02 01 00
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39 00 02 02 00
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39 00 02 03 57 //54
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39 00 02 04 D3 //D4
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39 00 02 05 00
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39 00 02 06 11
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39 00 02 07 08 //09
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39 00 02 08 00
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39 00 02 09 00
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39 00 02 0a 3F //00
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39 00 02 0b 00
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39 00 02 0c 00
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39 00 02 0d 00
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39 00 02 0e 00
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39 00 02 0f 3F //00
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39 00 02 10 3F //00
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39 00 02 11 00
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39 00 02 12 00
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39 00 02 13 00
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39 00 02 14 00
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39 00 02 15 00
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39 00 02 16 00
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39 00 02 17 00
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39 00 02 18 00
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39 00 02 19 00
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39 00 02 1a 00
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39 00 02 1b 00
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39 00 02 1c 00
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39 00 02 1d 00
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39 00 02 1e 40
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39 00 02 1f 80
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39 00 02 20 06
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39 00 02 21 01
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39 00 02 22 00
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39 00 02 23 00
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39 00 02 24 00
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39 00 02 25 00
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39 00 02 26 00
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39 00 02 27 00
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39 00 02 28 33
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39 00 02 29 33
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39 00 02 2a 00
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39 00 02 2b 00
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39 00 02 2c 00
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39 00 02 2d 00
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39 00 02 2e 00
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39 00 02 2f 00
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39 00 02 30 00
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39 00 02 31 00
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39 00 02 32 00
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39 00 02 33 00
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39 00 02 34 00
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39 00 02 35 00
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39 00 02 36 00
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39 00 02 37 00
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39 00 02 38 78
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39 00 02 39 00
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39 00 02 3a 00
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39 00 02 3b 00
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39 00 02 3c 00
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39 00 02 3d 00
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39 00 02 3e 00
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39 00 02 3f 00
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39 00 02 40 00
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39 00 02 41 00
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39 00 02 42 00
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39 00 02 43 00 //GCH/L
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39 00 02 44 00
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39 00 02 50 00
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39 00 02 51 23
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39 00 02 52 45
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39 00 02 53 67
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39 00 02 54 89
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39 00 02 55 ab
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39 00 02 56 01
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39 00 02 57 23
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39 00 02 58 45
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39 00 02 59 67
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39 00 02 5a 89
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39 00 02 5b ab
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39 00 02 5c cd
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39 00 02 5d ef
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39 00 02 5e 00
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39 00 02 5f 0D //FW_CGOUT_L[1]
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39 00 02 60 0D //FW_CGOUT_L[2]
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39 00 02 61 0C //FW_CGOUT_L[3]
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39 00 02 62 0C //FW_CGOUT_L[4]
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39 00 02 63 0F //FW_CGOUT_L[5]
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39 00 02 64 0F //FW_CGOUT_L[6]
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39 00 02 65 0E //FW_CGOUT_L[7]
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39 00 02 66 0E //FW_CGOUT_L[8]
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39 00 02 67 08 //FW_CGOUT_L[9]
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39 00 02 68 02 //FW_CGOUT_L[10]
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39 00 02 69 02 //FW_CGOUT_L[11]
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39 00 02 6a 02 //FW_CGOUT_L[12]
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39 00 02 6b 02 //FW_CGOUT_L[13]
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39 00 02 6c 02 //FW_CGOUT_L[14]
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39 00 02 6d 02 //FW_CGOUT_L[15]
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39 00 02 6e 02 //FW_CGOUT_L[16]
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39 00 02 6f 02 //FW_CGOUT_L[17]
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39 00 02 70 14 //FW_CGOUT_L[18]
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39 00 02 71 15 //FW_CGOUT_L[19]
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39 00 02 72 06 //FW_CGOUT_L[20]
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39 00 02 73 02 //FW_CGOUT_L[21]
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39 00 02 74 02 //FW_CGOUT_L[22]
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39 00 02 75 0D //BW_CGOUT_L[1]
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39 00 02 76 0D //BW_CGOUT_L[2]
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39 00 02 77 0C //BW_CGOUT_L[3]
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39 00 02 78 0C //BW_CGOUT_L[4]
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39 00 02 79 0F //BW_CGOUT_L[5]
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39 00 02 7a 0F //BW_CGOUT_L[6]
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39 00 02 7b 0E //BW_CGOUT_L[7]
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39 00 02 7c 0E //BW_CGOUT_L[8]
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39 00 02 7d 08 //BW_CGOUT_L[9]
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39 00 02 7e 02 //BW_CGOUT_L[10]
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39 00 02 7f 02 //BW_CGOUT_L[11]
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39 00 02 80 02 //BW_CGOUT_L[12]
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39 00 02 81 02 //BW_CGOUT_L[13]
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39 00 02 82 02 //BW_CGOUT_L[14]
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39 00 02 83 02 //BW_CGOUT_L[15]
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39 00 02 84 02 //BW_CGOUT_L[16]
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39 00 02 85 02 //BW_CGOUT_L[17]
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39 00 02 86 14 //BW_CGOUT_L[18]
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39 00 02 87 15 //BW_CGOUT_L[19]
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39 00 02 88 06 //BW_CGOUT_L[20]
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39 00 02 89 02 //BW_CGOUT_L[21]
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39 00 02 8A 02 //BW_CGOUT_L[22]
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39 00 04 FF 98 81 04
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39 00 02 6E 3B
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39 00 02 6F 57
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39 00 02 3A 24
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39 00 02 8D 1F
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39 00 02 87 BA
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39 00 02 B2 D1
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39 00 02 88 0B
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39 00 02 38 01
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39 00 02 39 00
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39 00 02 B5 07
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39 00 02 31 75
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39 00 02 3B 98
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39 00 04 FF 98 81 01
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39 00 02 22 0A
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39 00 02 31 09
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39 00 02 35 07
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39 00 02 53 87
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39 00 02 55 84
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39 00 02 50 86
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39 00 02 51 82
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39 00 02 60 10
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39 00 02 62 00
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39 00 02 A0 00
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39 00 02 A1 12
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39 00 02 A2 1F
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39 00 02 A3 12
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39 00 02 A4 16
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39 00 02 A5 29
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39 00 02 A6 1E
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39 00 02 A7 1F
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39 00 02 A8 7E
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39 00 02 A9 1B
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39 00 02 AA 28
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39 00 02 AB 6D
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39 00 02 AC 19
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39 00 02 AD 18
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39 00 02 AE 4C
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39 00 02 AF 1E
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39 00 02 B0 23
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39 00 02 B1 52
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39 00 02 B2 6D
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39 00 02 B3 3F
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39 00 02 C0 00
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39 00 02 C1 12
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39 00 02 C2 20
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39 00 02 C3 10
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39 00 02 C4 13
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39 00 02 C5 27
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39 00 02 C6 1B
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39 00 02 C7 1D
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39 00 02 C8 75
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39 00 02 C9 1F
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39 00 02 CA 28
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39 00 02 CB 68
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39 00 02 CC 1A
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39 00 02 CD 18
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39 00 02 CE 4D
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39 00 02 CF 25
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39 00 02 D0 2E
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39 00 02 D1 53
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39 00 02 D2 60
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39 00 02 D3 3F
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39 00 04 FF 98 81 00
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39 00 02 35 00
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05 80 01 11
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05 20 01 29
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];
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panel-exit-sequence = [
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05 00 01 28
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05 78 01 10
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];
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display-timings {
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native-mode = <&timing0>;
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timing0: timing0 {
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clock-frequency = <76000000>;
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hactive = <800>;
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vactive = <1280>;
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hback-porch = <70>;
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hfront-porch = <70>;
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vback-porch = <22>;
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vfront-porch = <16>;
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hsync-len = <20>;
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vsync-len = <6>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <0>;
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};
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timing1: timing1 {
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clock-frequency = <148000000>;
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hactive = <1920>;
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vactive = <1080>;
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hback-porch = <100>;
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hfront-porch = <160>;
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vback-porch = <25>;
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vfront-porch = <10>;
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hsync-len = <20>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <0>;
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pixelclk-active = <1>;
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};
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};
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ports {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
port@0 {
|
||
|
|
reg = <0>;
|
||
|
|
panel_in_dsi: endpoint {
|
||
|
|
remote-endpoint = <&dsi_out_panel>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
ports {
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
port@1 {
|
||
|
|
reg = <1>;
|
||
|
|
dsi_out_panel: endpoint {
|
||
|
|
remote-endpoint = <&panel_in_dsi>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&vopb {
|
||
|
|
assigned-clocks = <&cru DCLK_VOP0_DIV>;
|
||
|
|
assigned-clock-parents = <&cru PLL_CPLL>;
|
||
|
|
//assigned-clock-parents = <&cru PLL_VPLL>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&vopb_mmu {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&vopl {
|
||
|
|
assigned-clocks = <&cru DCLK_VOP1_DIV>;
|
||
|
|
assigned-clock-parents = <&cru PLL_VPLL>;
|
||
|
|
//assigned-clock-parents = <&cru PLL_CPLL>;
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&vopl_mmu {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&dsi_in_vopl {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&dsi_in_vopb {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&hdmi_in_vopb {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&hdmi_in_vopl {
|
||
|
|
status = "okay";
|
||
|
|
};
|
||
|
|
|
||
|
|
&edp_in_vopb {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&edp_in_vopl {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&dsi1_in_vopb {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&dsi1_in_vopl {
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
&route_hdmi {
|
||
|
|
status = "okay";
|
||
|
|
connect = <&vopl_out_hdmi>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&route_dsi {
|
||
|
|
status = "okay";
|
||
|
|
connect = <&vopb_out_dsi>;
|
||
|
|
};
|
||
|
|
|
||
|
|
&i2c4 {
|
||
|
|
status = "okay";
|
||
|
|
goodix_ts@5d {
|
||
|
|
compatible = "goodix,gt9xx";
|
||
|
|
reg = <0x5d>;
|
||
|
|
|
||
|
|
gtp_resolution_x = <800>;
|
||
|
|
gtp_resolution_y = <1280>;
|
||
|
|
gtp_int_tarigger = <1>;
|
||
|
|
gtp_change_x2y = <0>;
|
||
|
|
gtp_overturn_x = <0>;
|
||
|
|
gtp_overturn_y = <0>;
|
||
|
|
gtp_send_cfg = <1>;
|
||
|
|
gtp_touch_wakeup = <1>;
|
||
|
|
|
||
|
|
goodix_rst_gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
|
||
|
|
goodix_irq_gpio = <&gpio1 22 IRQ_TYPE_EDGE_RISING>;
|
||
|
|
|
||
|
|
goodix,cfg-group0 = [
|
||
|
|
45 20 03 00 05 05 35 00 01 C8 1E 0F 50 32
|
||
|
|
03 05 00 00 00 00 00 00 04 18 1A 1E 14 8C
|
||
|
|
2E 0E 1E 20 EB 04 00 00 00 BA 02 2D 00 00
|
||
|
|
00 00 00 03 00 00 00 00 00 0F 2D 94 D5 02
|
||
|
|
07 00 00 04 E6 10 00 BB 14 00 92 1A 00 78
|
||
|
|
20 00 61 28 00 61 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 2A 29 28 26 24 22 21 20 1F 1E 1D 1C
|
||
|
|
18 16 00 02 04 06 08 0A 0C 0F 10 12 13 14
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 CB 01
|
||
|
|
];
|
||
|
|
|
||
|
|
/** jc */
|
||
|
|
goodix,cfg-group2 = [
|
||
|
|
00 20 03 00 05 0A 05 00 01 08 28
|
||
|
|
05 50 32 03 05 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 8C 2C 0E 17 15 31
|
||
|
|
0D 00 00 01 BA 03 1D 00 00 00 00
|
||
|
|
00 03 64 32 00 00 00 0F 41 94 C5
|
||
|
|
02 07 00 00 04 99 11 00 77 17 00
|
||
|
|
5F 1F 00 4C 2A 00 41 38 00 41 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 1C 1A 18 16 14 12 10 0E 0C
|
||
|
|
0A 08 06 04 02 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 28
|
||
|
|
26 24 22 21 20 1F 1E 1D 1C 18 16
|
||
|
|
00 02 04 06 08 0A 0C 0F 10 12 13
|
||
|
|
14 FF FF 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 FE 01
|
||
|
|
];
|
||
|
|
|
||
|
|
goodix,cfg-group5 = [
|
||
|
|
00 20 03 00 05 0A 05 00 01 08 28 08
|
||
|
|
50 32 03 05 00 00 00 00 00 00 00 18
|
||
|
|
1A 1E 14 8C 2C 0E 17 15 31 0D 00 00
|
||
|
|
02 9B 04 1D 00 00 00 00 00 03 64 32
|
||
|
|
00 00 00 11 25 94 C5 02 07 00 00 04
|
||
|
|
60 12 00 5D 15 00 57 19 00 54 1D 00
|
||
|
|
4F 22 00 4F 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 1C 1A 18 16 14 12 10 0E
|
||
|
|
0C 0A 08 06 04 02 00 00 00 00 00 00
|
||
|
|
00 00 00 00 00 00 00 00 00 00 28 26
|
||
|
|
24 22 21 20 1F 1E 1D 1C 18 16 14 13
|
||
|
|
00 02 04 06 08 0A 0C 0F 10 12 FF FF
|
||
|
|
00 00 00 00 00 00 00 00 00 00 00 00
|
||
|
|
00 00 00 00 2F 01];
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
&pinctrl{
|
||
|
|
pwr_5v {
|
||
|
|
pwr_en: pwr-en {
|
||
|
|
rockchip,pins = //<1 13 RK_FUNC_GPIO &pcfg_pull_up>,
|
||
|
|
<4 30 RK_FUNC_GPIO &pcfg_pull_up>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|