/**
 * mipi csi to xs9922b config
 */


&i2c5 {
        status = "okay";
        xs9922: xs9922@31 {
                compatible = "xs9922";
                status = "okay";
                reg = <0x31>;
                clocks = <&cru CLK_CAM0_OUT>;
                clock-names = "xvclk";
                power-domains = <&power RK3568_PD_VI>;
                //pinctrl-names = "default";
                // pinctrl-0 = <&cif_clk>;
        pinctrl-names = "default";
        pinctrl-0 = <&xs9922_pwr>;
                reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
    //    power-gpio = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
                //avdd-supply = <&vcc_avdd>;
                //dovdd-supply = <&vcc_dovdd>;
                //dvdd-supply = <&vcc_dvdd>;
                rockchip,camera-module-index = <0>;
                rockchip,camera-module-facing = "back";
                rockchip,camera-module-name = "default";
                rockchip,camera-module-lens-name = "default";
                rockchip,default_rect= <1920 1080>; 
                port {
                        ucam_out0: endpoint {
                                remote-endpoint = <&mipi_in_ucam0>;
                                data-lanes = <1 2 3 4>;
                        };
                };
        };
};

&csi2_dphy_hw {
        status = "okay";
};

&csi2_dphy0 {
        status = "okay";

        ports {
                #address-cells = <1>;
                #size-cells = <0>;
                port@0 {
                        reg = <0>;
                        #address-cells = <1>;
                        #size-cells = <0>;

                        mipi_in_ucam0: endpoint@1 {
                                reg = <1>;
                                remote-endpoint = <&ucam_out0>;
                                data-lanes = <1 2 3 4>;
                        };
                };
                port@1 {
                        reg = <1>;
                        #address-cells = <1>;
                        #size-cells = <0>;

                        csidphy_out: endpoint@1 {
                                reg = <1>;
                                remote-endpoint = <&mipi_csi2_input>;
                        };
                };
        };
};

&mipi_csi2 {
    status = "okay";
    
    ports {
        #address-cells = <1>;
        #size-cells = <0>;
        
        port@0 {
            reg = <0>;
            #address-cells = <1>;
            #size-cells = <0>;
            
            mipi_csi2_input: endpoint@1 {
                reg = <1>;
                remote-endpoint = <&csidphy_out>;
                data-lanes = <1 2 3 4>;
            };
        };

        port@1 {
            reg = <1>;
            #address-cells = <1>;
            #size-cells = <0>;
            
            mipi_csi2_output: endpoint@0 {
                reg = <0>;
                remote-endpoint = <&cif_mipi_in>;
                data-lanes = <1 2 3 4>;
            };
        };

    };
};

&rkcif_mipi_lvds {
    status = "okay";
    rockchip,cif-monitor = <3 2 5 1000 5>;
    
    port {
        cif_mipi_in: endpoint {
            remote-endpoint = <&mipi_csi2_output>;
            data-lanes = <1 2 3 4>;
        };
    };
};

&rkcif {
    status = "okay";
};

&rkcif_mmu {
        status = "okay";
};

&pinctrl {
        xs9922 {
                xs9922_pwr: camera-pwr {
                        rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
                 };
        };
};
