/*
 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <dt-bindings/display/drm_mipi_dsi.h>
#include "rk3399-vop-clk-set.dtsi"

/ {
    compatible = "rockchip,linux", "rockchip,rk3399";

    chosen {
        bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait coherent_pool=1m";
    };

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;

        drm_logo: drm-logo@00000000 {
            compatible = "rockchip,drm-logo";
            reg = <0x0 0x0 0x0 0x0>;
        };

        ramoops_mem: region@110000 {
            reg = <0x0 0x110000 0x0 0xf0000>;
            reg-names = "ramoops_mem";
        };
    };

    ramoops: ramoops {
        compatible = "ramoops";
        record-size = <0x0 0x40000>;
        console-size = <0x0 0x80000>;
        ftrace-size = <0x0 0x00000>;
        pmsg-size = <0x0 0x00000>;
        memory-region = <&ramoops_mem>;
    };

    cif_isp0: cif_isp@ff910000 {
        compatible = "rockchip,rk3399-cif-isp";
        rockchip,grf = <&grf>;
        reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
        reg-names = "register", "dsihost-register";
        clocks =
            <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
            <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
            <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>,
            <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
            <&cru SCLK_MIPIDPHY_REF>;
        clock-names =
            "aclk_isp0_noc", "aclk_isp0_wrapper",
            "hclk_isp0_noc", "hclk_isp0_wrapper",
            "clk_isp0", "pclk_dphyrx",
            "clk_cif_out", "clk_cif_pll",
            "pclk_dphy_ref";
        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
        interrupt-names = "cif_isp10_irq";
        power-domains = <&power RK3399_PD_ISP0>;
        rockchip,isp,iommu-enable = <1>;
        iommus = <&isp0_mmu>;
        status = "disabled";
    };

    cif_isp1: cif_isp@ff920000 {
        compatible = "rockchip,rk3399-cif-isp";
        rockchip,grf = <&grf>;
        reg = <0x0 0xff920000 0x0 0x4000>, <0x0 0xff968000 0x0 0x8000>;
        reg-names = "register", "dsihost-register";
        clocks =
            <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
            <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
            <&cru SCLK_ISP1>, <&cru PCLK_ISP1_WRAPPER>,
            <&cru SCLK_DPHY_TX1RX1_CFG>,
            <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>,
            <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
            <&cru SCLK_MIPIDPHY_REF>;
        clock-names =
            "aclk_isp1_noc", "aclk_isp1_wrapper",
            "hclk_isp1_noc", "hclk_isp1_wrapper",
            "clk_isp1", "pclkin_isp1",
            "pclk_dphytxrx",
            "pclk_mipi_dsi","mipi_dphy_cfg",
            "clk_cif_out", "clk_cif_pll",
            "pclk_dphy_ref";
        interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
        interrupt-names = "cif_isp10_irq";
        power-domains = <&power RK3399_PD_ISP1>;
        rockchip,isp,iommu-enable = <1>;
        iommus = <&isp1_mmu>;
        status = "disabled";
    };

    rga: rga@ff680000 {
        compatible = "rockchip,rga2";
        dev_mode = <1>;
        reg = <0x0 0xff680000 0x0 0x1000>;
        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
        clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
        clock-names = "aclk_rga", "hclk_rga", "clk_rga";
        power-domains = <&power RK3399_PD_RGA>;
        dma-coherent;
        status = "okay";
    };
};


/* HACK: keep MALI version on linux */
&gpu_power_model {
    // for DDK r14.
    voltage = <900>;
    frequency = <500>;
    static-power = <300>;
    dynamic-power = <396>;
};

&pvtm {
    status = "okay";
};

&pinctrl {
    isp {
        cif_clkout: cif-clkout {
            rockchip,pins =
                /* cif_clkout */
                <2 11 RK_FUNC_3 &pcfg_pull_none>;
        };

        isp_dvp_d0d7: isp-dvp-d0d7 {
            rockchip,pins =
                <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
                /* cif_clkout */
                <2 11 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data0 */
                <2 0 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data1 */
                <2 1 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data2 */
                <2 2 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data3 */
                <2 3 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data4 */
                <2 4 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data5 */
                <2 5 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data6 */
                <2 6 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_data7 */
                <2 7 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_sync */
                <2 8 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_href */
                <2 9 RK_FUNC_3 &pcfg_pull_none>,
                /* cif_clkin */
                <2 10 RK_FUNC_3 &pcfg_pull_none>;
        };

        isp_shutter: isp-shutter {
            rockchip,pins =
                /* SHUTTEREN */
                <1 1 RK_FUNC_1 &pcfg_pull_none>,
                /* SHUTTERTRIG */
                <1 0 RK_FUNC_1 &pcfg_pull_none>;
        };

        isp_flash_trigger: isp-flash-trigger {
            /* ISP_FLASHTRIGOU */
            rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
        };

        isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
            /* ISP_FLASHTRIGOU */
            rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
        };
    };

    cam_pins {
        cam0_default_pins: cam0-default-pins {
            rockchip,pins =
                <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
                <2 11 RK_FUNC_3 &pcfg_pull_none>;
        };
        cam0_sleep_pins: cam0-sleep-pins {
            rockchip,pins =
                <4 27 RK_FUNC_3 &pcfg_pull_none>,
                <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
        };
    };
};
