# 0 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
# 0 "<built-in>"
# 0 "<command-line>"
# 1 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"


# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 1






/dts-v1/;



# 1 "./scripts/dtc/include-prefixes/dt-bindings/usb/pd.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588j.dtsi" 1






# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy-snps-pcie3.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/rk3588-cru.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
# 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/phy/phy.h" 1
# 10 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/power/rk3588-power.h" 1
# 11 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip,boot-mode.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/soc/rockchip-system-status.h" 1
# 13 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/suspend/rockchip-rk3588.h" 1
# 14 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
# 15 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2

/ {
 compatible = "rockchip,rk3588";

 interrupt-parent = <&gic>;
 #address-cells = <2>;
 #size-cells = <2>;

 aliases {
  csi2dcphy0 = &csi2_dcphy0;
  csi2dcphy1 = &csi2_dcphy1;
  csi2dphy0 = &csi2_dphy0;
  csi2dphy1 = &csi2_dphy1;
  csi2dphy2 = &csi2_dphy2;
  csi2dphy3 = &csi2_dphy3;
  csi2dphy4 = &csi2_dphy4;
  csi2dphy5 = &csi2_dphy5;
  dsi0 = &dsi0;
  dsi1 = &dsi1;
  ethernet1 = &gmac1;
  gpio0 = &gpio0;
  gpio1 = &gpio1;
  gpio2 = &gpio2;
  gpio3 = &gpio3;
  gpio4 = &gpio4;
  i2c0 = &i2c0;
  i2c1 = &i2c1;
  i2c2 = &i2c2;
  i2c3 = &i2c3;
  i2c4 = &i2c4;
  i2c5 = &i2c5;
  i2c6 = &i2c6;
  i2c7 = &i2c7;
  i2c8 = &i2c8;
  rkcif_mipi_lvds0= &rkcif_mipi_lvds;
  rkcif_mipi_lvds1= &rkcif_mipi_lvds1;
  rkcif_mipi_lvds2= &rkcif_mipi_lvds2;
  rkcif_mipi_lvds3= &rkcif_mipi_lvds3;
  rkvdec0 = &rkvdec0;
  rkvdec1 = &rkvdec1;
  rkvenc0 = &rkvenc0;
  rkvenc1 = &rkvenc1;
  jpege0 = &jpege0;
  jpege1 = &jpege1;
  jpege2 = &jpege2;
  jpege3 = &jpege3;
  serial0 = &uart0;
  serial1 = &uart1;
  serial2 = &uart2;
  serial3 = &uart3;
  serial4 = &uart4;
  serial5 = &uart5;
  serial6 = &uart6;
  serial7 = &uart7;
  serial8 = &uart8;
  serial9 = &uart9;
  spi0 = &spi0;
  spi1 = &spi1;
  spi2 = &spi2;
  spi3 = &spi3;
  spi4 = &spi4;
  spi5 = &sfc;
  hdcp0 = &hdcp0;
  hdcp1 = &hdcp1;
 };

 clocks {
  compatible = "simple-bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  spll: spll {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <702000000>;
   clock-output-names = "spll";
  };

  xin32k: xin32k {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <32768>;
   clock-output-names = "xin32k";
  };

  xin24m: xin24m {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <24000000>;
   clock-output-names = "xin24m";
  };

  hclk_vo1: hclk_vo1@fd7c08ec {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08ec 0 0x10>;
   clock-names = "link";
   clocks = <&cru 612>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08b0 0 0x10>;
   clock-names = "link";
   clocks = <&cru 444>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_vo0: hclk_vo0@fd7c08dc {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08dc 0 0x10>;
   clock-names = "link";
   clocks = <&cru 621>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_usb: hclk_usb@fd7c08a8 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08a8 0 0x10>;
   clock-names = "link";
   clocks = <&cru 612>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_nvm: hclk_nvm@fd7c087c {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c087c 0 0x10>;
   clock-names = "link";
   clocks = <&cru 321>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_usb: aclk_usb@fd7c08a8 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08a8 0 0x10>;
   clock-names = "link";
   clocks = <&cru 611>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_isp1_pre: hclk_isp1_pre@fd7c0868 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c0868 0 0x10>;
   clock-names = "link";
   clocks = <&cru 481>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_isp1_pre: aclk_isp1_pre@fd7c0868 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c0868 0 0x10>;
   clock-names = "link";
   clocks = <&cru 480>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08a0 0 0x10>;
   clock-names = "link";
   clocks = <&cru 444>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08a0 0 0x10>;
   clock-names = "link";
   clocks = <&cru 446>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08a4 0 0x10>;
   clock-names = "link";
   clocks = <&cru 444>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08a4 0 0x10>;
   clock-names = "link";
   clocks = <&cru 446>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08b0 0 0x10>;
   clock-names = "link";
   clocks = <&cru 444>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08c0 0 0x10>;
   clock-names = "link";
   clocks = <&cru 453>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08c0 0 0x10>;
   clock-names = "link";
   clocks = <&cru 452>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08dc 0 0x10>;
   clock-names = "link";
   clocks = <&cru 620>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c08ec 0 0x10>;
   clock-names = "link";
   clocks = <&cru 611>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  pclk_av1_pre: pclk_av1_pre@fd7c0910 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c0910 0 0x10>;
   clock-names = "link";
   clocks = <&cru 446>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  aclk_av1_pre: aclk_av1_pre@fd7c0910 {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c0910 0 0x10>;
   clock-names = "link";
   clocks = <&cru 444>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  hclk_sdio_pre: hclk_sdio_pre@fd7c092c {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0 0xfd7c092c 0 0x10>;
   clock-names = "link";
   clocks = <&hclk_nvm>;
   #power-domain-cells = <1>;
   #clock-cells = <0>;
  };

  pclk_vo0_grf: pclk_vo0_grf@fd7c08dc {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0x0 0xfd7c08dc 0x0 0x4>;
   clocks = <&hclk_vo0>;
   clock-names = "link";
   #clock-cells = <0>;
  };

  pclk_vo1_grf: pclk_vo1_grf@fd7c08ec {
   compatible = "rockchip,rk3588-clock-gate-link";
   reg = <0x0 0xfd7c08ec 0x0 0x4>;
   clocks = <&hclk_vo1>;
   clock-names = "link";
   #clock-cells = <0>;
  };

  mclkin_i2s0: mclkin-i2s0 {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <0>;
   clock-output-names = "i2s0_mclkin";
  };

  mclkin_i2s1: mclkin-i2s1 {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <0>;
   clock-output-names = "i2s1_mclkin";
  };

  mclkin_i2s2: mclkin-i2s2 {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <0>;
   clock-output-names = "i2s2_mclkin";
  };

  mclkin_i2s3: mclkin-i2s3 {
   compatible = "fixed-clock";
   #clock-cells = <0>;
   clock-frequency = <0>;
   clock-output-names = "i2s3_mclkin";
  };

  mclkout_i2s0: mclkout-i2s0@fd58c318 {
   compatible = "rockchip,clk-out";
   reg = <0 0xfd58c318 0 0x4>;
   clocks = <&cru 57>;
                        assigned-clocks = <&cru 57>;
                        assigned-clock-rates = <22288000>;
                 #clock-cells = <0>;
   clock-output-names = "i2s0_mclkout_to_io";
   rockchip,bit-shift = <0>;
   rockchip,bit-set-to-disable;
   rockchip,clk-ignore-unused;
  };

  mclkout_i2s1: mclkout-i2s1@fd58c318 {
   compatible = "rockchip,clk-out";
   reg = <0 0xfd58c318 0 0x4>;
   clocks = <&cru 657>;
   #clock-cells = <0>;
   clock-output-names = "i2s1_mclkout_to_io";
   rockchip,bit-shift = <1>;
   rockchip,bit-set-to-disable;
   rockchip,clk-ignore-unused;
  };

  mclkout_i2s1m1: mclkout-i2s1@fd58a000 {
   compatible = "rockchip,clk-out";
   reg = <0 0xfd58a000 0 0x4>;
   clocks = <&cru 657>;
   #clock-cells = <0>;
   clock-output-names = "i2s1m1_mclkout_to_io";
   rockchip,bit-shift = <6>;
   rockchip,clk-ignore-unused;
  };

  mclkout_i2s2: mclkout-i2s2@fd58c318 {
   compatible = "rockchip,clk-out";
   reg = <0 0xfd58c318 0 0x4>;
   clocks = <&cru 40>;
   #clock-cells = <0>;
   clock-output-names = "i2s2_mclkout_to_io";
   rockchip,bit-shift = <2>;
   rockchip,bit-set-to-disable;
   rockchip,clk-ignore-unused;
  };

  mclkout_i2s3: mclkout-i2s3@fd58c318 {
   compatible = "rockchip,clk-out";
   reg = <0 0xfd58c318 0 0x4>;
   clocks = <&cru 46>;
   #clock-cells = <0>;
   clock-output-names = "i2s3_mclkout_to_io";
   rockchip,bit-shift = <7>;
   rockchip,bit-set-to-disable;
   rockchip,clk-ignore-unused;
  };
 };

 cpus {
  #address-cells = <1>;
  #size-cells = <0>;

  cpu-map {
   cluster0 {
    core0 {
     cpu = <&cpu_l0>;
    };
    core1 {
     cpu = <&cpu_l1>;
    };
    core2 {
     cpu = <&cpu_l2>;
    };
    core3 {
     cpu = <&cpu_l3>;
    };
   };
   cluster1 {
    core0 {
     cpu = <&cpu_b0>;
    };
    core1 {
     cpu = <&cpu_b1>;
    };
   };
   cluster2 {
    core0 {
     cpu = <&cpu_b2>;
    };
    core1 {
     cpu = <&cpu_b3>;
    };
   };
  };

  cpu_l0: cpu@0 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x0>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l0>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <100>;
  };

  cpu_l1: cpu@100 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x100>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l1>;
  };

  cpu_l2: cpu@200 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x200>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l2>;
  };

  cpu_l3: cpu@300 {
   device_type = "cpu";
   compatible = "arm,cortex-a55";
   reg = <0x300>;
   enable-method = "psci";
   capacity-dmips-mhz = <530>;
   clocks = <&scmi_clk 0>;
   operating-points-v2 = <&cluster0_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <32768>;
   i-cache-line-size = <64>;
   i-cache-sets = <128>;
   d-cache-size = <32768>;
   d-cache-line-size = <64>;
   d-cache-sets = <128>;
   next-level-cache = <&l2_cache_l3>;
  };

  cpu_b0: cpu@400 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x400>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 2>;
   operating-points-v2 = <&cluster1_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b0>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <300>;
  };

  cpu_b1: cpu@500 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x500>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 2>;
   operating-points-v2 = <&cluster1_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b1>;
  };

  cpu_b2: cpu@600 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x600>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 3>;
   operating-points-v2 = <&cluster2_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b2>;
   #cooling-cells = <2>;
   dynamic-power-coefficient = <300>;
  };

  cpu_b3: cpu@700 {
   device_type = "cpu";
   compatible = "arm,cortex-a76";
   reg = <0x700>;
   enable-method = "psci";
   capacity-dmips-mhz = <1024>;
   clocks = <&scmi_clk 3>;
   operating-points-v2 = <&cluster2_opp_table>;
   cpu-idle-states = <&CPU_SLEEP>;
   i-cache-size = <65536>;
   i-cache-line-size = <64>;
   i-cache-sets = <256>;
   d-cache-size = <65536>;
   d-cache-line-size = <64>;
   d-cache-sets = <256>;
   next-level-cache = <&l2_cache_b3>;
  };

  idle-states {
   entry-method = "psci";
   CPU_SLEEP: cpu-sleep {
    compatible = "arm,idle-state";
    local-timer-stop;
    arm,psci-suspend-param = <0x0010000>;
    entry-latency-us = <100>;
    exit-latency-us = <120>;
    min-residency-us = <1000>;
   };
  };

  l2_cache_l0: l2-cache-l0 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_l1: l2-cache-l1 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_l2: l2-cache-l2 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_l3: l2-cache-l3 {
   compatible = "cache";
   cache-size = <131072>;
   cache-line-size = <64>;
   cache-sets = <512>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b0: l2-cache-b0 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b1: l2-cache-b1 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b2: l2-cache-b2 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   next-level-cache = <&l3_cache>;
  };

  l2_cache_b3: l2-cache-b3 {
   compatible = "cache";
   cache-size = <524288>;
   cache-line-size = <64>;
   cache-sets = <1024>;
   next-level-cache = <&l3_cache>;
  };

  l3_cache: l3-cache {
   compatible = "cache";
   cache-size = <3145728>;
   cache-line-size = <64>;
   cache-sets = <4096>;
  };
 };

 cluster0_opp_table: cluster0-opp-table {
  compatible = "operating-points-v2";
  opp-shared;

  nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>;
  nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
  rockchip,supported-hw;
  rockchip,opp-shared-dsu;

  rockchip,pvtm-hw = <0x06>;
  rockchip,pvtm-voltage-sel-hw = <
   0 1365 0
   1366 1387 1
   1388 1409 2
   1410 1431 3
   1432 1453 4
   1454 1475 5
   1476 9999 6
  >;
  rockchip,pvtm-voltage-sel = <
   0 1410 0
   1411 1434 1
   1435 1458 2
   1459 1482 3
   1483 1506 4
   1507 1530 5
   1531 9999 6
  >;
  rockchip,pvtm-pvtpll;
  rockchip,pvtm-offset = <0x64>;
  rockchip,pvtm-sample-time = <1100>;
  rockchip,pvtm-freq = <1416000>;
  rockchip,pvtm-volt = <750000>;
  rockchip,pvtm-ref-temp = <25>;
  rockchip,pvtm-temp-prop = <244 244>;
  rockchip,pvtm-thermal-zone = "soc-thermal";

  rockchip,grf = <&litcore_grf>;
  rockchip,dsu-grf = <&dsu_grf>;
  volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;
  low-volt-mem-read-margin = <4>;
  intermediate-threshold-freq = <1008000>;
  rockchip,reboot-freq = <1416000>;

  rockchip,temp-hysteresis = <5000>;
  rockchip,low-temp = <10000>;
  rockchip,low-temp-min-volt = <750000>;
  rockchip,high-temp = <85000>;
  rockchip,high-temp-max-freq = <1608000>;


  opp-408000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <675000 675000 950000>,
     <675000 675000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-600000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <675000 675000 950000>,
     <675000 675000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <675000 675000 950000>,
     <675000 675000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1008000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <675000 675000 950000>,
     <675000 675000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <712500 712500 950000>,
     <712500 712500 950000>;
   opp-microvolt-L1 = <700000 700000 950000>,
        <700000 700000 950000>;
   opp-microvolt-L2 = <700000 700000 950000>,
        <700000 700000 950000>;
   opp-microvolt-L3 = <687500 687500 950000>,
        <687500 687500 950000>;
   opp-microvolt-L4 = <675000 675000 950000>,
        <675000 675000 950000>;
   opp-microvolt-L5 = <675000 675000 950000>,
        <675000 675000 950000>;
   opp-microvolt-L6 = <675000 675000 950000>,
        <675000 675000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <762500 762500 950000>,
     <762500 762500 950000>;
   opp-microvolt-L1 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L2 = <737500 737500 950000>,
        <737500 737500 950000>;
   opp-microvolt-L3 = <725000 725000 950000>,
        <725000 725000 950000>;
   opp-microvolt-L4 = <725000 725000 950000>,
        <725000 725000 950000>;
   opp-microvolt-L5 = <712500 712500 950000>,
        <712500 712500 950000>;
   opp-microvolt-L6 = <712500 712500 950000>,
        <712500 712500 950000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-1608000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <850000 850000 950000>,
     <850000 850000 950000>;
   opp-microvolt-L1 = <837500 837500 950000>,
        <837500 837500 950000>;
   opp-microvolt-L2 = <825000 825000 950000>,
        <825000 825000 950000>;
   opp-microvolt-L3 = <812500 812500 950000>,
        <812500 812500 950000>;
   opp-microvolt-L4 = <800000 800000 950000>,
        <800000 800000 950000>;
   opp-microvolt-L5 = <800000 800000 950000>,
        <800000 800000 950000>;
   opp-microvolt-L6 = <787500 787500 950000>,
        <787500 787500 950000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <950000 950000 950000>,
     <950000 950000 950000>;
   opp-microvolt-L1 = <937500 937500 950000>,
        <937500 937500 950000>;
   opp-microvolt-L2 = <925000 925000 950000>,
        <925000 925000 950000>;
   opp-microvolt-L3 = <912500 912500 950000>,
        <912500 912500 950000>;
   opp-microvolt-L4 = <900000 900000 950000>,
        <900000 900000 950000>;
   opp-microvolt-L5 = <887500 887500 950000>,
        <887500 887500 950000>;
   opp-microvolt-L6 = <875000 875000 950000>,
        <875000 875000 950000>;
   clock-latency-ns = <40000>;
  };


  opp-j-m-408000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-600000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-816000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1008000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1200000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-1296000000 {
   opp-supported-hw = <0x04 0xffff>;
   opp-hz = /bits/ 64 <1296000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   opp-microvolt-L0 = <775000 775000 950000>,
        <775000 775000 950000>;
   opp-microvolt-L1 = <762500 762500 950000>,
        <762500 762500 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1416000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   opp-microvolt-L0 = <787500 787500 950000>,
        <787500 787500 950000>;
   opp-microvolt-L1 = <775000 775000 950000>,
        <775000 775000 950000>;
   opp-microvolt-L2 = <762500 762500 950000>,
        <762500 762500 950000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-j-m-1608000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <887500 887500 950000>,
     <887500 887500 950000>;
   opp-microvolt-L1 = <875000 875000 950000>,
        <875000 875000 950000>;
   opp-microvolt-L2 = <862500 862500 950000>,
        <862500 862500 950000>;
   opp-microvolt-L3 = <850000 850000 950000>,
        <850000 850000 950000>;
   opp-microvolt-L4 = <837500 837500 950000>,
        <837500 837500 950000>;
   opp-microvolt-L5 = <825000 825000 950000>,
        <825000 825000 950000>;
   opp-microvolt-L6 = <812500 812500 950000>,
        <812500 812500 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1704000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1704000000>;
   opp-microvolt = <937500 937500 950000>,
     <937500 937500 950000>;
   opp-microvolt-L1 = <925000 925000 950000>,
        <925000 925000 950000>;
   opp-microvolt-L2 = <912500 912500 950000>,
        <912500 912500 950000>;
   opp-microvolt-L3 = <900000 900000 950000>,
        <900000 900000 950000>;
   opp-microvolt-L4 = <887500 887500 950000>,
        <887500 887500 950000>;
   opp-microvolt-L5 = <875000 875000 950000>,
        <875000 875000 950000>;
   opp-microvolt-L6 = <862500 862500 950000>,
        <862500 862500 950000>;
   clock-latency-ns = <40000>;
  };
 };

 cluster1_opp_table: cluster1-opp-table {
  compatible = "operating-points-v2";
  opp-shared;

  nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>;
  nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
  rockchip,supported-hw;

  rockchip,pvtm-hw = <0x06>;
  rockchip,pvtm-voltage-sel-hw = <
   0 1539 0
   1540 1564 1
   1565 1589 2
   1590 1614 3
   1615 1644 4
   1645 1674 5
   1675 1704 6
   1705 9999 7
  >;
  rockchip,pvtm-voltage-sel = <
   0 1595 0
   1596 1615 1
   1616 1640 2
   1641 1675 3
   1676 1710 4
   1711 1743 5
   1744 1776 6
   1777 9999 7
  >;
  rockchip,pvtm-pvtpll;
  rockchip,pvtm-offset = <0x18>;
  rockchip,pvtm-sample-time = <1100>;
  rockchip,pvtm-freq = <1608000>;
  rockchip,pvtm-volt = <750000>;
  rockchip,pvtm-ref-temp = <25>;
  rockchip,pvtm-temp-prop = <270 270>;
  rockchip,pvtm-thermal-zone = "soc-thermal";
  rockchip,pvtm-low-len-sel = <3>;

  rockchip,grf = <&bigcore0_grf>;
  volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;
  low-volt-mem-read-margin = <4>;
  intermediate-threshold-freq = <1008000>;
  rockchip,idle-threshold-freq = <2208000>;
  rockchip,reboot-freq = <1800000>;

  rockchip,temp-hysteresis = <5000>;
  rockchip,low-temp = <10000>;
  rockchip,low-temp-min-volt = <750000>;
  rockchip,high-temp = <85000>;
  rockchip,high-temp-max-freq = <2208000>;


  opp-408000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-600000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1008000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <725000 725000 1000000>,
     <725000 725000 1000000>;
   opp-microvolt-L2 = <712500 712500 1000000>,
        <712500 712500 1000000>;
   opp-microvolt-L3 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   opp-microvolt-L4 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   opp-microvolt-L5 = <687500 687500 1000000>,
        <687500 687500 1000000>;
   opp-microvolt-L6 = <675000 675000 1000000>,
        <675000 675000 1000000>;
   opp-microvolt-L7 = <675000 675000 1000000>,
        <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1608000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <762500 762500 1000000>,
     <762500 762500 1000000>;
   opp-microvolt-L2 = <750000 750000 1000000>,
        <750000 750000 1000000>;
   opp-microvolt-L3 = <737500 737500 1000000>,
        <737500 737500 1000000>;
   opp-microvolt-L4 = <725000 725000 1000000>,
        <725000 725000 1000000>;
   opp-microvolt-L5 = <712500 712500 1000000>,
        <712500 712500 1000000>;
   opp-microvolt-L6 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   opp-microvolt-L7 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <850000 850000 1000000>,
     <850000 850000 1000000>;
   opp-microvolt-L1 = <837500 837500 1000000>,
        <837500 837500 1000000>;
   opp-microvolt-L2 = <825000 825000 1000000>,
        <825000 825000 1000000>;
   opp-microvolt-L3 = <812500 812500 1000000>,
        <812500 812500 1000000>;
   opp-microvolt-L4 = <800000 800000 1000000>,
        <800000 800000 1000000>;
   opp-microvolt-L5 = <787500 787500 1000000>,
        <787500 787500 1000000>;
   opp-microvolt-L6 = <775000 775000 1000000>,
        <775000 775000 1000000>;
   opp-microvolt-L7 = <762500 762500 1000000>,
        <762500 762500 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2016000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <2016000000>;
   opp-microvolt = <925000 925000 1000000>,
     <925000 925000 1000000>;
   opp-microvolt-L1 = <912500 912500 1000000>,
        <912500 912500 1000000>;
   opp-microvolt-L2 = <900000 900000 1000000>,
        <900000 900000 1000000>;
   opp-microvolt-L3 = <887500 887500 1000000>,
        <887500 887500 1000000>;
   opp-microvolt-L4 = <875000 875000 1000000>,
        <875000 875000 1000000>;
   opp-microvolt-L5 = <862500 862500 1000000>,
        <862500 862500 1000000>;
   opp-microvolt-L6 = <850000 850000 1000000>,
        <850000 850000 1000000>;
   opp-microvolt-L7 = <837500 837500 1000000>,
        <837500 837500 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2208000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <2208000000>;
   opp-microvolt = <987500 987500 1000000>,
     <987500 987500 1000000>;
   opp-microvolt-L1 = <975000 975000 1000000>,
        <975000 975000 1000000>;
   opp-microvolt-L2 = <962500 962500 1000000>,
        <962500 962500 1000000>;
   opp-microvolt-L3 = <950000 950000 1000000>,
        <950000 950000 1000000>;
   opp-microvolt-L4 = <962500 962500 1000000>,
        <962500 962500 1000000>;
   opp-microvolt-L5 = <950000 950000 1000000>,
        <950000 950000 1000000>;
   opp-microvolt-L6 = <925000 925000 1000000>,
        <925000 925000 1000000>;
   opp-microvolt-L7 = <912500 912500 1000000>,
        <912500 912500 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2256000000 {
   opp-supported-hw = <0xf9 0x13>;
   opp-hz = /bits/ 64 <2256000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2304000000 {
   opp-supported-hw = <0xf9 0x24>;
   opp-hz = /bits/ 64 <2304000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2352000000 {
   opp-supported-hw = <0xf9 0x48>;
   opp-hz = /bits/ 64 <2352000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2400000000 {
   opp-supported-hw = <0xf9 0x80>;
   opp-hz = /bits/ 64 <2400000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };


  opp-j-m-408000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-600000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-816000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1008000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1200000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1416000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   opp-microvolt-L0 = <762500 762500 950000>,
     <762500 762500 950000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-j-m-1608000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <787500 787500 950000>,
     <787500 787500 950000>;
   opp-microvolt-L2 = <775000 775000 950000>,
        <775000 775000 950000>;
   opp-microvolt-L3 = <762500 762500 950000>,
        <762500 762500 950000>;
   opp-microvolt-L4 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L5 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L6 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L7 = <750000 750000 950000>,
        <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1800000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <875000 875000 950000>,
     <875000 875000 950000>;
   opp-microvolt-L1 = <862500 862500 950000>,
        <862500 862500 950000>;
   opp-microvolt-L2 = <850000 850000 950000>,
        <850000 850000 950000>;
   opp-microvolt-L3 = <837500 837500 950000>,
        <837500 837500 950000>;
   opp-microvolt-L4 = <825000 825000 950000>,
        <825000 825000 950000>;
   opp-microvolt-L5 = <812500 812500 950000>,
        <812500 812500 950000>;
   opp-microvolt-L6 = <800000 800000 950000>,
        <800000 800000 950000>;
   opp-microvolt-L7 = <787500 787500 950000>,
        <787500 787500 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-2016000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <2016000000>;
   opp-microvolt = <950000 950000 950000>,
     <950000 950000 950000>;
   opp-microvolt-L1 = <950000 950000 950000>,
        <950000 950000 950000>;
   opp-microvolt-L2 = <937500 937500 950000>,
        <937500 937500 950000>;
   opp-microvolt-L3 = <925000 925000 950000>,
        <925000 925000 950000>;
   opp-microvolt-L4 = <912500 912500 950000>,
        <912500 912500 950000>;
   opp-microvolt-L5 = <900000 900000 950000>,
        <900000 900000 950000>;
   opp-microvolt-L6 = <887500 887500 950000>,
        <887500 887500 950000>;
   opp-microvolt-L7 = <875000 875000 950000>,
        <875000 875000 950000>;
   clock-latency-ns = <40000>;
  };
 };

 cluster2_opp_table: cluster2-opp-table {
  compatible = "operating-points-v2";
  opp-shared;

  nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>;
  nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
  rockchip,supported-hw;

  rockchip,pvtm-hw = <0x06>;
  rockchip,pvtm-voltage-sel-hw = <
   0 1539 0
   1540 1564 1
   1565 1589 2
   1590 1614 3
   1615 1644 4
   1645 1674 5
   1675 1704 6
   1705 9999 7
  >;
  rockchip,pvtm-voltage-sel = <
   0 1595 0
   1596 1615 1
   1616 1640 2
   1641 1675 3
   1676 1710 4
   1711 1743 5
   1744 1776 6
   1777 9999 7
  >;
  rockchip,pvtm-pvtpll;
  rockchip,pvtm-offset = <0x18>;
  rockchip,pvtm-sample-time = <1100>;
  rockchip,pvtm-freq = <1608000>;
  rockchip,pvtm-volt = <750000>;
  rockchip,pvtm-ref-temp = <25>;
  rockchip,pvtm-temp-prop = <270 270>;
  rockchip,pvtm-thermal-zone = "soc-thermal";
  rockchip,pvtm-low-len-sel = <3>;

  rockchip,grf = <&bigcore1_grf>;
  volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;
  low-volt-mem-read-margin = <4>;
  intermediate-threshold-freq = <1008000>;
  rockchip,idle-threshold-freq = <2208000>;
  rockchip,reboot-freq = <1800000>;

  rockchip,temp-hysteresis = <5000>;
  rockchip,low-temp = <10000>;
  rockchip,low-temp-min-volt = <750000>;
  rockchip,high-temp = <85000>;
  rockchip,high-temp-max-freq = <2208000>;


  opp-408000000 {
   opp-supported-hw = <0xf9 0x0ffff>;
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-600000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-816000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1008000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1200000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <675000 675000 1000000>,
     <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1416000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <725000 725000 1000000>,
     <725000 725000 1000000>;
   opp-microvolt-L2 = <712500 712500 1000000>,
        <712500 712500 1000000>;
   opp-microvolt-L3 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   opp-microvolt-L4 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   opp-microvolt-L5 = <687500 687500 1000000>,
        <687500 687500 1000000>;
   opp-microvolt-L6 = <675000 675000 1000000>,
        <675000 675000 1000000>;
   opp-microvolt-L7 = <675000 675000 1000000>,
        <675000 675000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1608000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <762500 762500 1000000>,
     <762500 762500 1000000>;
   opp-microvolt-L2 = <750000 750000 1000000>,
        <750000 750000 1000000>;
   opp-microvolt-L3 = <737500 737500 1000000>,
        <737500 737500 1000000>;
   opp-microvolt-L4 = <725000 725000 1000000>,
        <725000 725000 1000000>;
   opp-microvolt-L5 = <712500 712500 1000000>,
        <712500 712500 1000000>;
   opp-microvolt-L6 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   opp-microvolt-L7 = <700000 700000 1000000>,
        <700000 700000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-1800000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <850000 850000 1000000>,
     <850000 850000 1000000>;
   opp-microvolt-L1 = <837500 837500 1000000>,
        <837500 837500 1000000>;
   opp-microvolt-L2 = <825000 825000 1000000>,
        <825000 825000 1000000>;
   opp-microvolt-L3 = <812500 812500 1000000>,
        <812500 812500 1000000>;
   opp-microvolt-L4 = <800000 800000 1000000>,
        <800000 800000 1000000>;
   opp-microvolt-L5 = <787500 787500 1000000>,
        <787500 787500 1000000>;
   opp-microvolt-L6 = <775000 775000 1000000>,
        <775000 775000 1000000>;
   opp-microvolt-L7 = <762500 762500 1000000>,
        <762500 762500 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2016000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <2016000000>;
   opp-microvolt = <925000 925000 1000000>,
     <925000 925000 1000000>;
   opp-microvolt-L1 = <912500 912500 1000000>,
        <912500 912500 1000000>;
   opp-microvolt-L2 = <900000 900000 1000000>,
        <900000 900000 1000000>;
   opp-microvolt-L3 = <887500 887500 1000000>,
        <887500 887500 1000000>;
   opp-microvolt-L4 = <875000 875000 1000000>,
        <875000 875000 1000000>;
   opp-microvolt-L5 = <862500 862500 1000000>,
        <862500 862500 1000000>;
   opp-microvolt-L6 = <850000 850000 1000000>,
        <850000 850000 1000000>;
   opp-microvolt-L7 = <837500 837500 1000000>,
        <837500 837500 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2208000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <2208000000>;
   opp-microvolt = <987500 987500 1000000>,
     <987500 987500 1000000>;
   opp-microvolt-L3 = <975000 975000 1000000>,
        <975000 975000 1000000>;
   opp-microvolt-L4 = <962500 962500 1000000>,
        <962500 962500 1000000>;
   opp-microvolt-L5 = <950000 950000 1000000>,
        <950000 950000 1000000>;
   opp-microvolt-L6 = <925000 925000 1000000>,
        <925000 925000 1000000>;
   opp-microvolt-L7 = <912500 912500 1000000>,
        <912500 912500 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2256000000 {
   opp-supported-hw = <0xf9 0x13>;
   opp-hz = /bits/ 64 <2256000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2304000000 {
   opp-supported-hw = <0xf9 0x24>;
   opp-hz = /bits/ 64 <2304000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2352000000 {
   opp-supported-hw = <0xf9 0x48>;
   opp-hz = /bits/ 64 <2352000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };
  opp-2400000000 {
   opp-supported-hw = <0xf9 0x80>;
   opp-hz = /bits/ 64 <2400000000>;
   opp-microvolt = <1000000 1000000 1000000>,
     <1000000 1000000 1000000>;
   clock-latency-ns = <40000>;
  };


  opp-j-m-408000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <408000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-600000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-816000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <816000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1008000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1008000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1200000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1200000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1416000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1416000000>;
   opp-microvolt = <750000 750000 950000>,
     <750000 750000 950000>;
   opp-microvolt-L0 = <762500 762500 950000>,
     <762500 762500 950000>;
   clock-latency-ns = <40000>;
   opp-suspend;
  };
  opp-j-m-1608000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1608000000>;
   opp-microvolt = <787500 787500 950000>,
     <787500 787500 950000>;
   opp-microvolt-L2 = <775000 775000 950000>,
        <775000 775000 950000>;
   opp-microvolt-L3 = <762500 762500 950000>,
        <762500 762500 950000>;
   opp-microvolt-L4 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L5 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L6 = <750000 750000 950000>,
        <750000 750000 950000>;
   opp-microvolt-L7 = <750000 750000 950000>,
        <750000 750000 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-1800000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1800000000>;
   opp-microvolt = <875000 875000 950000>,
     <875000 875000 950000>;
   opp-microvolt-L1 = <862500 862500 950000>,
        <862500 862500 950000>;
   opp-microvolt-L2 = <850000 850000 950000>,
        <850000 850000 950000>;
   opp-microvolt-L3 = <837500 837500 950000>,
        <837500 837500 950000>;
   opp-microvolt-L4 = <825000 825000 950000>,
        <825000 825000 950000>;
   opp-microvolt-L5 = <812500 812500 950000>,
        <812500 812500 950000>;
   opp-microvolt-L6 = <800000 800000 950000>,
        <800000 800000 950000>;
   opp-microvolt-L7 = <787500 787500 950000>,
        <787500 787500 950000>;
   clock-latency-ns = <40000>;
  };
  opp-j-m-2016000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <2016000000>;
   opp-microvolt = <950000 950000 950000>,
     <950000 950000 950000>;
   opp-microvolt-L1 = <950000 950000 950000>,
        <950000 950000 950000>;
   opp-microvolt-L2 = <937500 937500 950000>,
        <937500 937500 950000>;
   opp-microvolt-L3 = <925000 925000 950000>,
        <925000 925000 950000>;
   opp-microvolt-L4 = <912500 912500 950000>,
        <912500 912500 950000>;
   opp-microvolt-L5 = <900000 900000 950000>,
        <900000 900000 950000>;
   opp-microvolt-L6 = <887500 887500 950000>,
        <887500 887500 950000>;
   opp-microvolt-L7 = <875000 875000 950000>,
        <875000 875000 950000>;
   clock-latency-ns = <40000>;
  };
 };

 arm_pmu: arm-pmu {
  compatible = "arm,armv8-pmuv3";
  interrupts = <1 7 8>;
  interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>,
         <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>;
 };

 cpuinfo {
  compatible = "rockchip,cpuinfo";
  nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
  nvmem-cell-names = "id", "cpu-version", "cpu-code";
 };

 csi2_dcphy0: csi2-dcphy0 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dcphy1: csi2-dcphy1 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dphy0: csi2-dphy0 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dphy1: csi2-dphy1 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dphy2: csi2-dphy2 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dphy3: csi2-dphy3 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dphy4: csi2-dphy4 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 csi2_dphy5: csi2-dphy5 {
  compatible = "rockchip,rk3588-csi2-dphy";
  rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
  phys = <&mipidcphy0>, <&mipidcphy1>;
  phy-names = "dcphy0", "dcphy1";
  status = "disabled";
 };

 display_subsystem: display-subsystem {
  compatible = "rockchip,display-subsystem";
  ports = <&vop_out>;

  route {
   route_dp0: route-dp0 {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
    connect = <&vp1_out_dp0>;
   };

   route_dsi0: route-dsi0 {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
    connect = <&vp3_out_dsi0>;
   };

   route_dsi1: route-dsi1 {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
    connect = <&vp3_out_dsi1>;
   };

   route_edp0: route-edp0 {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
    connect = <&vp2_out_edp0>;
   };

   route_edp1: route-edp1 {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
   };

   route_hdmi0: route-hdmi0 {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
    connect = <&vp0_out_hdmi0>;
   };

   route_rgb: route-rgb {
    status = "disabled";
    logo,uboot = "logo.bmp";
    logo,kernel = "logo_kernel.bmp";
    logo,mode = "center";
    charge_logo,mode = "center";
    connect = <&vp3_out_rgb>;
   };
  };
 };

 dmc: dmc {
  compatible = "rockchip,rk3588-dmc";
  interrupts = <0 73 4>;
  interrupt-names = "complete";
  devfreq-events = <&dfi>;
  clocks = <&scmi_clk 4>;
  clock-names = "dmc_clk";
  operating-points-v2 = <&dmc_opp_table>;
  upthreshold = <40>;
  downdifferential = <20>;
  system-status-level = <

   (1 << 0) (0x1 << 2)
   (1 << 3) (0x1 << 3)
   (1 << 1) (0x1 << 0)
   (1 << 4) (0x1 << 2)
   (1 << 16) (0x1 << 2)
   (1 << 19) (0x1 << 2)
   (1 << 12) (0x1 << 3)
   (1 << 14) (0x1 << 3)
   (1 << 13) (0x1 << 3)
   ((1 << 10) | (1 << 11)) (0x1 << 3)
   (1 << 18) (0x1 << 3)
   (1 << 21) (0x1 << 3)
  >;
  auto-freq-en = <1>;
  status = "disabled";
 };

 dmc_opp_table: dmc-opp-table {
  compatible = "operating-points-v2";

  nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&specification_serial_number>;
  nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
  rockchip,supported-hw;

  rockchip,leakage-voltage-sel = <
   1 31 0
   32 44 1
   45 57 2
   58 254 3
  >;
  rockchip,temp-hysteresis = <5000>;
  rockchip,low-temp = <10000>;
  rockchip,low-temp-min-volt = <750000>;


  opp-528000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <528000000>;
   opp-microvolt = <675000 675000 875000>,
     <725000 725000 750000>;
   opp-microvolt-L1 = <675000 675000 875000>,
        <700000 700000 750000>;
   opp-microvolt-L2 = <675000 675000 875000>,
        <687500 687500 750000>;
   opp-microvolt-L3 = <675000 675000 875000>,
        <675000 675000 750000>;
  };
  opp-1068000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1068000000>;
   opp-microvolt = <725000 725000 875000>,
     <737500 737500 750000>;
   opp-microvolt-L1 = <700000 700000 875000>,
        <712500 712500 750000>;
   opp-microvolt-L2 = <675000 675000 875000>,
        <700000 700000 750000>;
   opp-microvolt-L3 = <675000 675000 875000>,
        <687500 687500 750000>;
  };
  opp-1560000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1560000000>;
   opp-microvolt = <800000 800000 875000>,
     <750000 750000 750000>;
   opp-microvolt-L1 = <775000 775000 875000>,
        <725000 725000 750000>;
   opp-microvolt-L2 = <750000 750000 875000>,
        <712500 712500 750000>;
   opp-microvolt-L3 = <725000 725000 875000>,
        <700000 700000 750000>;
  };
  opp-2750000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <2750000000>;
   opp-microvolt = <875000 875000 875000>,
     <750000 750000 750000>;
   opp-microvolt-L1 = <850000 850000 875000>,
        <750000 750000 750000>;
   opp-microvolt-L2 = <837500 837500 875000>,
        <725000 725000 750000>;
   opp-microvolt-L3 = <825000 820000 875000>,
        <700000 700000 750000>;
  };


  opp-j-m-528000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <528000000>;
   opp-microvolt = <750000 750000 875000>,
     <750000 750000 750000>;
  };
  opp-j-m-1068000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1068000000>;
   opp-microvolt = <750000 750000 875000>,
     <750000 750000 750000>;
  };
  opp-j-m-1560000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <1560000000>;
   opp-microvolt = <800000 800000 875000>,
     <750000 750000 750000>;
   opp-microvolt-L1 = <775000 775000 875000>,
        <750000 750000 750000>;
   opp-microvolt-L2 = <750000 750000 875000>,
        <750000 750000 750000>;
   opp-microvolt-L3 = <750000 750000 875000>,
        <750000 750000 750000>;
  };
  opp-j-m-2750000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <2750000000>;
   opp-microvolt = <875000 875000 875000>,
     <750000 750000 750000>;
   opp-microvolt-L1 = <850000 850000 875000>,
        <750000 750000 750000>;
   opp-microvolt-L2 = <837500 837500 875000>,
        <750000 750000 750000>;
   opp-microvolt-L3 = <825000 820000 875000>,
        <750000 750000 750000>;
  };
 };

 firmware {
  scmi: scmi {
   compatible = "arm,scmi-smc";
   shmem = <&scmi_shmem>;
   arm,smc-id = <0x82000010>;
   #address-cells = <1>;
   #size-cells = <0>;

   scmi_clk: protocol@14 {
    reg = <0x14>;
    #clock-cells = <1>;

    assigned-clocks = <&scmi_clk 0>,
        <&scmi_clk 2>,
        <&scmi_clk 3>;
    assigned-clock-rates = <816000000>,
             <816000000>,
             <816000000>;
   };

   scmi_reset: protocol@16 {
    reg = <0x16>;
    #reset-cells = <1>;
   };
  };

  sdei: sdei {
   compatible = "arm,sdei-1.0";
   method = "smc";
  };
 };

 jpege_ccu: jpege-ccu {
  compatible = "rockchip,vpu-jpege-ccu";
  status = "disabled";
 };

 /omit-if-no-ref/
 mipi_dcphy1: mipi_dcphy0: mipi-dcphy-dummy {
 };

 mipi0_csi2: mipi0-csi2 {
  compatible = "rockchip,rk3588-mipi-csi2";
  rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
         <&mipi2_csi2_hw>, <&mipi3_csi2_hw>,
         <&mipi4_csi2_hw>, <&mipi5_csi2_hw>;
  status = "disabled";
 };

 mipi1_csi2: mipi1-csi2 {
  compatible = "rockchip,rk3588-mipi-csi2";
  rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
         <&mipi2_csi2_hw>, <&mipi3_csi2_hw>,
         <&mipi4_csi2_hw>, <&mipi5_csi2_hw>;
  status = "disabled";
 };

 mipi2_csi2: mipi2-csi2 {
  compatible = "rockchip,rk3588-mipi-csi2";
  rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
         <&mipi2_csi2_hw>, <&mipi3_csi2_hw>,
         <&mipi4_csi2_hw>, <&mipi5_csi2_hw>;
  status = "disabled";
 };

 mipi3_csi2: mipi3-csi2 {
  compatible = "rockchip,rk3588-mipi-csi2";
  rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
         <&mipi2_csi2_hw>, <&mipi3_csi2_hw>,
         <&mipi4_csi2_hw>, <&mipi5_csi2_hw>;
  status = "disabled";
 };

 mipi4_csi2: mipi4-csi2 {
  compatible = "rockchip,rk3588-mipi-csi2";
  rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
         <&mipi2_csi2_hw>, <&mipi3_csi2_hw>,
         <&mipi4_csi2_hw>, <&mipi5_csi2_hw>;
  status = "disabled";
 };

 mipi5_csi2: mipi5-csi2 {
  compatible = "rockchip,rk3588-mipi-csi2";
  rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
         <&mipi2_csi2_hw>, <&mipi3_csi2_hw>,
         <&mipi4_csi2_hw>, <&mipi5_csi2_hw>;
  status = "disabled";
 };

 mpp_srv: mpp-srv {
  compatible = "rockchip,mpp-service";
  rockchip,taskqueue-count = <12>;
  rockchip,resetgroup-count = <1>;
  status = "disabled";
 };

 psci {
  compatible = "arm,psci-1.0";
  method = "smc";
 };

 rkcif_dvp: rkcif-dvp {
  compatible = "rockchip,rkcif-dvp";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_dvp_sditf: rkcif-dvp-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_dvp>;
  status = "disabled";
 };

 rkcif_mipi_lvds: rkcif-mipi-lvds {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds>;
  status = "disabled";
 };

 rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds1>;
  status = "disabled";
 };

 rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds2>;
  status = "disabled";
 };

 rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds3>;
  status = "disabled";
 };

 rkisp0_vir0: rkisp0-vir0 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;





  status = "disabled";
 };

 rkisp0_vir1: rkisp0-vir1 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;
  status = "disabled";
 };

 rkisp0_vir2: rkisp0-vir2 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;
  status = "disabled";
 };

 rkisp0_vir3: rkisp0-vir3 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp0>;
  status = "disabled";
 };

 rkisp1_vir0: rkisp1-vir0 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkisp1_vir1: rkisp1-vir1 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkisp1_vir2: rkisp1-vir2 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkisp1_vir3: rkisp1-vir3 {
  compatible = "rockchip,rkisp-vir";
  rockchip,hw = <&rkisp1>;
  status = "disabled";
 };

 rkispp0_vir0: rkispp0-vir0 {
  compatible = "rockchip,rk3588-rkispp-vir";
  rockchip,hw = <&rkispp0>;
  status = "disabled";
 };

 rkispp1_vir0: rkispp1-vir0 {
  compatible = "rockchip,rk3588-rkispp-vir";
  rockchip,hw = <&rkispp1>;
  status = "disabled";
 };

 rkvenc_ccu: rkvenc-ccu {
  compatible = "rockchip,rkv-encoder-v2-ccu";
  status = "disabled";
 };

 rkvtunnel: rkvtunnel {
  compatible = "rockchip,video-tunnel";
  status = "disabled";
 };

 rockchip_suspend: rockchip-suspend {
  compatible = "rockchip,pm-rk3588";
  status = "disabled";
  rockchip,sleep-debug-en = <0>;
  rockchip,sleep-mode-config = <
   (0
   | (1 << (3))
   | (1 << (9))
   | (1 << (10))
   | (1 << (24))
   )
  >;
  rockchip,wakeup-config = <
   (0
   | (1 << (8))
   )
  >;
 };

 rockchip_system_monitor: rockchip-system-monitor {
  compatible = "rockchip,system-monitor";

  rockchip,thermal-zone = "soc-thermal";
 };

 thermal_zones: thermal-zones {
  soc_thermal: soc-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   sustainable-power = <2100>;

   thermal-sensors = <&tsadc 0>;
   trips {
    threshold: trip-point-0 {
     temperature = <75000>;
     hysteresis = <2000>;
     type = "passive";
    };
    target: trip-point-1 {
     temperature = <85000>;
     hysteresis = <2000>;
     type = "passive";
    };
    soc_crit: soc-crit {

     temperature = <115000>;

     hysteresis = <2000>;
     type = "critical";
    };
   };
   cooling-maps {
    map0 {
     trip = <&target>;
     cooling-device = <&cpu_l0 (~0) (~0)>;
     contribution = <1024>;
    };
    map1 {
     trip = <&target>;
     cooling-device = <&cpu_b0 (~0) (~0)>;
     contribution = <1024>;
    };
    map2 {
     trip = <&target>;
     cooling-device = <&cpu_b2 (~0) (~0)>;
     contribution = <1024>;
    };
    map3 {
     trip = <&target>;
     cooling-device = <&gpu (~0) (~0)>;
     contribution = <1024>;
    };
   };
  };

  bigcore0_thermal: bigcore0-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 1>;
  };

  bigcore1_thermal: bigcore1-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 2>;
  };

  little_core_thermal: littlecore-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 3>;
  };

  center_thermal: center-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 4>;
  };

  gpu_thermal: gpu-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 5>;
  };

  npu_thermal: npu-thermal {
   polling-delay-passive = <20>;
   polling-delay = <1000>;
   thermal-sensors = <&tsadc 6>;
  };
 };

 timer {
  compatible = "arm,armv8-timer";
  interrupts = <1 13 ((((1 << (4)) - 1) << 8) | 4)>,
        <1 14 ((((1 << (4)) - 1) << 8) | 4)>,
        <1 11 ((((1 << (4)) - 1) << 8) | 4)>,
        <1 10 ((((1 << (4)) - 1) << 8) | 4)>;
 };

 sram@10f000 {
  compatible = "mmio-sram";
  reg = <0x0 0x0010f000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0 0x0 0x0010f000 0x100>;

  scmi_shmem: sram@0 {
   compatible = "arm,scmi-shmem";
   reg = <0x0 0x100>;
  };
 };

 gpu: gpu@fb000000 {
  compatible = "arm,mali-bifrost";
  reg = <0x0 0xfb000000 0x0 0x200000>;
  interrupts = <0 94 4>,
        <0 93 4>,
        <0 92 4>;
  interrupt-names = "GPU", "MMU", "JOB";

  clocks = <&scmi_clk 5>, <&cru 277>,
    <&cru 278>, <&cru 276>;
  clock-names = "clk_mali", "clk_gpu_coregroup",
         "clk_gpu_stacks", "clk_gpu";
  assigned-clocks = <&scmi_clk 5>;
  assigned-clock-rates = <200000000>;
  power-domains = <&power 12>;
  operating-points-v2 = <&gpu_opp_table>;
  #cooling-cells = <2>;
  dynamic-power-coefficient = <2982>;

  upthreshold = <30>;
  downdifferential = <10>;

  status = "disabled";
 };

 gpu_opp_table: gpu-opp-table {
  compatible = "operating-points-v2";

  nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>;
  nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
  rockchip,supported-hw;

  rockchip,pvtm-hw = <0x04>;
  rockchip,pvtm-voltage-sel-hw = <
   0 799 0
   800 819 1
   820 844 2
   845 869 3
   870 894 4
   895 9999 5
  >;
  rockchip,pvtm-voltage-sel = <
   0 815 0
   816 835 1
   836 860 2
   861 885 3
   886 910 4
   911 9999 5
  >;
  rockchip,pvtm-pvtpll;
  rockchip,pvtm-offset = <0x1c>;
  rockchip,pvtm-sample-time = <1100>;
  rockchip,pvtm-freq = <800000>;
  rockchip,pvtm-volt = <750000>;
  rockchip,pvtm-ref-temp = <25>;
  rockchip,pvtm-temp-prop = <(-135) (-135)>;
  rockchip,pvtm-thermal-zone = "gpu-thermal";

  rockchip,opp-clocks = <&cru 276>;
  rockchip,grf = <&gpu_grf>;
  volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;
  low-volt-mem-read-margin = <4>;
  intermediate-threshold-freq = <400000>;

  rockchip,temp-hysteresis = <5000>;
  rockchip,low-temp = <10000>;
  rockchip,low-temp-min-volt = <750000>;
  rockchip,high-temp = <85000>;
  rockchip,high-temp-max-freq = <800000>;


  opp-300000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <675000 675000 850000>,
     <675000 675000 850000>;
  };
  opp-400000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <675000 675000 850000>,
     <675000 675000 850000>;
  };
  opp-500000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <500000000>;
   opp-microvolt = <675000 675000 850000>,
     <675000 675000 850000>;
  };
  opp-600000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <675000 675000 850000>,
     <675000 675000 850000>;
  };
  opp-700000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <700000000>;
   opp-microvolt = <700000 700000 850000>,
     <700000 700000 850000>;
   opp-microvolt-L2 = <687500 687500 850000>,
        <687500 687500 850000>;
   opp-microvolt-L3 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L4 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L5 = <675000 675000 850000>,
        <675000 675000 850000>;
  };
  opp-800000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
   opp-microvolt-L1 = <737500 737500 850000>,
        <737500 737500 850000>;
   opp-microvolt-L2 = <725000 725000 850000>,
        <725000 725000 850000>;
   opp-microvolt-L3 = <712500 712500 850000>,
        <712500 712500 850000>;
   opp-microvolt-L4 = <700000 700000 850000>,
        <700000 700000 850000>;
   opp-microvolt-L5 = <700000 700000 850000>,
        <700000 700000 850000>;
  };
  opp-900000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <900000000>;
   opp-microvolt = <800000 800000 850000>,
     <800000 800000 850000>;
   opp-microvolt-L1 = <787500 787500 850000>,
        <787500 787500 850000>;
   opp-microvolt-L2 = <775000 775000 850000>,
        <775000 775000 850000>;
   opp-microvolt-L3 = <762500 762500 850000>,
        <762500 762500 850000>;
   opp-microvolt-L4 = <750000 750000 850000>,
        <750000 750000 850000>;
   opp-microvolt-L5 = <737500 737500 850000>,
        <737500 737500 850000>;
  };
  opp-1000000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <850000 850000 850000>,
     <850000 850000 850000>;
   opp-microvolt-L1 = <837500 837500 850000>,
        <837500 837500 850000>;
   opp-microvolt-L2 = <825000 825000 850000>,
        <825000 825000 850000>;
   opp-microvolt-L3 = <812500 812500 850000>,
        <812500 812500 850000>;
   opp-microvolt-L4 = <800000 800000 850000>,
        <800000 800000 850000>;
   opp-microvolt-L5 = <787500 787500 850000>,
        <787500 787500 850000>;
  };


  opp-j-m-300000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-400000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-500000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <500000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-600000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-700000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <700000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };

  opp-j-850000000 {
   opp-supported-hw = <0x04 0xffff>;
   opp-hz = /bits/ 64 <850000000>;
   opp-microvolt = <787500 787500 850000>,
     <787500 787500 850000>;
   opp-microvolt-L1 = <775000 775000 850000>,
        <775000 775000 850000>;
   opp-microvolt-L2 = <762500 762500 850000>,
        <762500 762500 850000>;
   opp-microvolt-L3 = <750000 750000 850000>,
        <750000 750000 850000>;
   opp-microvolt-L4 = <750000 750000 850000>,
        <750000 750000 850000>;
   opp-microvolt-L5 = <750000 750000 850000>,
        <750000 750000 850000>;
  };

  opp-m-800000000 {
   opp-supported-hw = <0x02 0xffff>;
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-m-900000000 {
   opp-supported-hw = <0x02 0xffff>;
   opp-hz = /bits/ 64 <900000000>;
   opp-microvolt = <800000 800000 850000>,
     <800000 800000 850000>;
   opp-microvolt-L1 = <787500 787500 850000>,
        <787500 787500 850000>;
   opp-microvolt-L2 = <775000 775000 850000>,
        <775000 775000 850000>;
   opp-microvolt-L3 = <762500 762500 850000>,
        <762500 762500 850000>;
   opp-microvolt-L4 = <750000 750000 850000>,
        <750000 750000 850000>;
   opp-microvolt-L5 = <750000 750000 850000>,
        <750000 750000 850000>;
  };
  opp-m-1000000000 {
   opp-supported-hw = <0x02 0xffff>;
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <850000 850000 850000>,
     <850000 850000 850000>;
   opp-microvolt-L1 = <837500 837500 850000>,
        <837500 837500 850000>;
   opp-microvolt-L2 = <825000 825000 850000>,
        <825000 825000 850000>;
   opp-microvolt-L3 = <812500 812500 850000>,
        <812500 812500 850000>;
   opp-microvolt-L4 = <800000 800000 850000>,
        <800000 800000 850000>;
   opp-microvolt-L5 = <787500 787500 850000>,
        <787500 787500 850000>;
  };
 };

 usbdrd3_0: usbdrd3_0 {
  compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
  clocks = <&cru 419>, <&cru 418>,
    <&cru 417>;
  clock-names = "ref", "suspend", "bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  status = "disabled";

  usbdrd_dwc3_0: usb@fc000000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfc000000 0x0 0x400000>;
   interrupts = <0 220 4>;
   power-domains = <&power 31>;
   resets = <&cru 676>;
   reset-names = "usb3-otg";
   dr_mode = "otg";
   phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
   phy-names = "usb2-phy", "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u1-entry-quirk;
   snps,dis-u2-entry-quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,dis-tx-ipgap-linecheck-quirk;
   snps,parkmode-disable-hs-quirk;
   snps,parkmode-disable-ss-quirk;
   quirk-skip-phy-init;
   status = "disabled";
  };
 };

 usb_host0_ehci: usb@fc800000 {
  compatible = "rockchip,rk3588-ehci", "generic-ehci";
  reg = <0x0 0xfc800000 0x0 0x40000>;
  interrupts = <0 215 4>;
  clocks = <&cru 413>, <&cru 414>, <&u2phy2>, <&aclk_usb>;
  clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
  companion = <&usb_host0_ohci>;
  phys = <&u2phy2_host>;
  phy-names = "usb2-phy";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host0_ohci: usb@fc840000 {
  compatible = "rockchip,rk3588-ohci", "generic-ohci";
  reg = <0x0 0xfc840000 0x0 0x40000>;
  interrupts = <0 216 4>;
  clocks = <&cru 413>, <&cru 414>, <&u2phy2>, <&aclk_usb>;
  clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
  phys = <&u2phy2_host>;
  phy-names = "usb2-phy";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host1_ehci: usb@fc880000 {
  compatible = "rockchip,rk3588-ehci", "generic-ehci";
  reg = <0x0 0xfc880000 0x0 0x40000>;
  interrupts = <0 218 4>;
  clocks = <&cru 415>, <&cru 416>, <&u2phy3>, <&aclk_usb>;
  clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
  companion = <&usb_host1_ohci>;
  phys = <&u2phy3_host>;
  phy-names = "usb2-phy";
  power-domains = <&power 31>;
  status = "disabled";
 };

 usb_host1_ohci: usb@fc8c0000 {
  compatible = "rockchip,rk3588-ohci", "generic-ohci";
  reg = <0x0 0xfc8c0000 0x0 0x40000>;
  interrupts = <0 219 4>;
  clocks = <&cru 415>, <&cru 416>, <&u2phy3>, <&aclk_usb>;
  clock-names = "usbhost", "arbiter", "utmi", "alk_usb";
  phys = <&u2phy3_host>;
  phy-names = "usb2-phy";
  power-domains = <&power 31>;
  status = "disabled";
 };

 mmu600_pcie: iommu@fc900000 {
  compatible = "arm,smmu-v3";
  reg = <0x0 0xfc900000 0x0 0x200000>;
  interrupts = <0 369 4>,
        <0 371 4>,
        <0 374 4>,
        <0 367 4>;
  interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
  #iommu-cells = <1>;
  status = "disabled";
 };

 mmu600_php: iommu@fcb00000 {
  compatible = "arm,smmu-v3";
  reg = <0x0 0xfcb00000 0x0 0x200000>;
  interrupts = <0 381 4>,
        <0 383 4>,
        <0 386 4>,
        <0 379 4>;
  interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
  #iommu-cells = <1>;
  status = "disabled";
 };

 usbhost3_0: usbhost3_0 {
  compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
  clocks = <&cru 377>, <&cru 376>,
    <&cru 375>, <&cru 378>,
    <&cru 358>, <&cru 385>;
  clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  status = "disabled";

  usbhost_dwc3_0: usb@fcd00000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfcd00000 0x0 0x400000>;
   interrupts = <0 222 4>;
   resets = <&cru 567>;
   reset-names = "usb3-host";
   dr_mode = "host";
   phys = <&combphy2_psu 4>;
   phy-names = "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,dis-tx-ipgap-linecheck-quirk;
   snps,dis_rxdet_inp3_quirk;
   snps,parkmode-disable-hs-quirk;
   snps,parkmode-disable-ss-quirk;
   status = "disabled";
  };
 };

 pmu0_grf: syscon@fd588000 {
  compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd";
  reg = <0x0 0xfd588000 0x0 0x2000>;

  reboot_mode: reboot-mode {
   compatible = "syscon-reboot-mode";
   offset = <0x80>;
   mode-bootloader = <(0x5242C300 + 1)>;
   mode-charge = <(0x5242C300 + 11)>;
   mode-fastboot = <(0x5242C300 + 9)>;
   mode-loader = <(0x5242C300 + 1)>;
   mode-normal = <(0x5242C300 + 0)>;
   mode-recovery = <(0x5242C300 + 3)>;
   mode-ums = <(0x5242C300 + 12)>;
   mode-panic = <(0x5242C300 + 7)>;
   mode-watchdog = <(0x5242C300 + 8)>;
   mode-quiescent = <(0x5242C300 + 14)>;

   mode-winusb = <(0x5242C300 + 15)>;
  };
 };

 pmu1_grf: syscon@fd58a000 {
  compatible = "rockchip,rk3588-pmu1-grf", "syscon";
  reg = <0x0 0xfd58a000 0x0 0x2000>;
 };

 sys_grf: syscon@fd58c000 {
  compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd";
  reg = <0x0 0xfd58c000 0x0 0x1000>;

  rgb: rgb {
   compatible = "rockchip,rk3588-rgb";
   pinctrl-names = "default";
   pinctrl-0 = <&bt1120_pins>;
   status = "disabled";

   ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@0 {
     reg = <0>;
     #address-cells = <1>;
     #size-cells = <0>;

     rgb_in_vp3: endpoint@2 {
      reg = <2>;
      remote-endpoint = <&vp3_out_rgb>;
      status = "disabled";
     };
    };
   };
  };
 };

 bigcore0_grf: syscon@fd590000 {
  compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
  reg = <0x0 0xfd590000 0x0 0x100>;
 };

 bigcore1_grf: syscon@fd592000 {
  compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
  reg = <0x0 0xfd592000 0x0 0x100>;
 };

 litcore_grf: syscon@fd594000 {
  compatible = "rockchip,rk3588-litcore-grf", "syscon";
  reg = <0x0 0xfd594000 0x0 0x100>;
 };

 dsu_grf: syscon@fd598000 {
  compatible = "rockchip,rk3588-dsu-grf", "syscon";
  reg = <0x0 0xfd598000 0x0 0x100>;
 };

 gpu_grf: syscon@fd5a0000 {
  compatible = "rockchip,rk3588-gpu-grf", "syscon";
  reg = <0x0 0xfd5a0000 0x0 0x100>;
 };

 npu_grf: syscon@fd5a2000 {
  compatible = "rockchip,rk3588-npu-grf", "syscon";
  reg = <0x0 0xfd5a2000 0x0 0x100>;
 };

 vop_grf: syscon@fd5a4000 {
  compatible = "rockchip,rk3588-vop-grf", "syscon";
  reg = <0x0 0xfd5a4000 0x0 0x2000>;
 };

 vo0_grf: syscon@fd5a6000 {
  compatible = "rockchip,rk3588-vo-grf", "syscon";
  reg = <0x0 0xfd5a6000 0x0 0x2000>;
  clocks = <&pclk_vo0_grf>;
 };

 vo1_grf: syscon@fd5a8000 {
  compatible = "rockchip,rk3588-vo-grf", "syscon";
  reg = <0x0 0xfd5a8000 0x0 0x100>;
  clocks = <&pclk_vo1_grf>;
 };

 usb_grf: syscon@fd5ac000 {
  compatible = "rockchip,rk3588-usb-grf", "syscon";
  reg = <0x0 0xfd5ac000 0x0 0x4000>;
 };

 php_grf: syscon@fd5b0000 {
  compatible = "rockchip,rk3588-php-grf", "syscon";
  reg = <0x0 0xfd5b0000 0x0 0x1000>;
 };

 mipidphy0_grf: syscon@fd5b4000 {
  compatible = "rockchip,mipi-dphy-grf", "syscon";
  reg = <0x0 0xfd5b4000 0x0 0x1000>;
 };

 mipidphy1_grf: syscon@fd5b5000 {
  compatible = "rockchip,mipi-dphy-grf", "syscon";
  reg = <0x0 0xfd5b5000 0x0 0x1000>;
 };

 pipe_phy0_grf: syscon@fd5bc000 {
  compatible = "rockchip,pipe-phy-grf", "syscon";
  reg = <0x0 0xfd5bc000 0x0 0x100>;
 };

 pipe_phy2_grf: syscon@fd5c4000 {
  compatible = "rockchip,pipe-phy-grf", "syscon";
  reg = <0x0 0xfd5c4000 0x0 0x100>;
 };

 usbdpphy0_grf: syscon@fd5c8000 {
  compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
  reg = <0x0 0xfd5c8000 0x0 0x4000>;
 };

 usb2phy0_grf: syscon@fd5d0000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
        "simple-mfd";
  reg = <0x0 0xfd5d0000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy0: usb2-phy@0 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0x0 0x10>;
   interrupts = <0 393 4>;
   resets = <&cru 786503>, <&cru 1160>;
   reset-names = "phy", "apb";
   clocks = <&cru 693>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy0";
   #clock-cells = <0>;
   rockchip,usbctrl-grf = <&usb_grf>;
   status = "disabled";

   u2phy0_otg: otg-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 usb2phy2_grf: syscon@fd5d8000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
        "simple-mfd";
  reg = <0x0 0xfd5d8000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy2: usb2-phy@8000 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0x8000 0x10>;
   interrupts = <0 391 4>;
   resets = <&cru 786505>, <&cru 1162>;
   reset-names = "phy", "apb";
   clocks = <&cru 693>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy2";
   #clock-cells = <0>;
   status = "disabled";

   u2phy2_host: host-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 usb2phy3_grf: syscon@fd5dc000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
        "simple-mfd";
  reg = <0x0 0xfd5dc000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy3: usb2-phy@c000 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0xc000 0x10>;
   interrupts = <0 392 4>;
   resets = <&cru 786506>, <&cru 1163>;
   reset-names = "phy", "apb";
   clocks = <&cru 693>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy3";
   #clock-cells = <0>;
   status = "disabled";

   u2phy3_host: host-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 hdptxphy0_grf: syscon@fd5e0000 {
  compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
  reg = <0x0 0xfd5e0000 0x0 0x100>;
 };

 mipidcphy0_grf: syscon@fd5e8000 {
  compatible = "rockchip,mipi-dcphy-grf", "syscon";
  reg = <0x0 0xfd5e8000 0x0 0x4000>;
 };

 mipidcphy1_grf: syscon@fd5ec000 {
  compatible = "rockchip,mipi-dcphy-grf", "syscon";
  reg = <0x0 0xfd5ec000 0x0 0x4000>;
 };

 ioc: syscon@fd5f0000 {
  compatible = "rockchip,rk3588-ioc", "syscon";
  reg = <0x0 0xfd5f0000 0x0 0x10000>;
 };

 cru: clock-controller@fd7c0000 {
  compatible = "rockchip,rk3588-cru";
  rockchip,grf = <&php_grf>;
  reg = <0x0 0xfd7c0000 0x0 0x5c000>;
  #clock-cells = <1>;
  #reset-cells = <1>;

  assigned-clocks =
   <&cru 9>, <&cru 5>,
   <&cru 8>, <&cru 7>,
   <&cru 216>,
   <&cru 218>, <&cru 217>,
   <&cru 270>, <&cru 271>,
   <&cru 272>, <&cru 665>,
   <&cru 666>,
   <&cru 123>, <&cru 236>,
   <&cru 276>, <&cru 520>,
   <&cru 526>, <&cru 543>,
   <&cru 119>;
  assigned-clock-rates =
   <1100000000>, <786432000>,
   <850000000>, <1188000000>,
   <702000000>,
   <400000000>, <500000000>,
   <750000000>, <100000000>,
   <400000000>, <100000000>,
   <200000000>,
   <375000000>, <150000000>,
   <200000000>, <12000000>,
   <12000000>, <99000000>,
   <20000000>;
 };

 i2c0: i2c@fd880000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfd880000 0x0 0x1000>;
  clocks = <&cru 647>, <&cru 646>;
  clock-names = "i2c", "pclk";
  interrupts = <0 317 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c0m0_xfer>;
  resets = <&cru 786466>, <&cru 786465>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 uart0: serial@fd890000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfd890000 0x0 0x100>;
  interrupts = <0 331 4>;
  clocks = <&cru 686>, <&cru 687>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac0 6>, <&dmac0 7>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart0m1_xfer>;
  status = "disabled";
 };

 pwm0: pwm@fd8b0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0000 0x0 0x10>;
  interrupts = <0 344 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm0m0_pins>;
  clocks = <&cru 677>, <&cru 676>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm1: pwm@fd8b0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0010 0x0 0x10>;
  interrupts = <0 344 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm1m0_pins>;
  clocks = <&cru 677>, <&cru 676>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm2: pwm@fd8b0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0020 0x0 0x10>;
  interrupts = <0 344 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm2m0_pins>;
  clocks = <&cru 677>, <&cru 676>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm3: pwm@fd8b0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfd8b0030 0x0 0x10>;
  interrupts = <0 344 4>,
        <0 345 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm3m0_pins>;
  clocks = <&cru 677>, <&cru 676>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pmu: power-management@fd8d8000 {
  compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
  reg = <0x0 0xfd8d8000 0x0 0x400>;

  power: power-controller {
   compatible = "rockchip,rk3588-power-controller";
   #power-domain-cells = <1>;
   #address-cells = <1>;
   #size-cells = <0>;
   status = "okay";


   power-domain@8 {
    reg = <8>;
    #address-cells = <1>;
    #size-cells = <0>;

    power-domain@9 {
     reg = <9>;
     #address-cells = <1>;
     #size-cells = <0>;
     clocks = <&cru 303>,
       <&cru 305>,
       <&cru 304>,
       <&cru 294>;
     pm_qos = <&qos_npu0_mwr>,
       <&qos_npu0_mro>,
       <&qos_mcu_npu>;

     power-domain@10 {
      reg = <10>;
      clocks = <&cru 303>,
        <&cru 305>,
        <&cru 304>;
      pm_qos = <&qos_npu1>;
     };
     power-domain@11 {
      reg = <11>;
      clocks = <&cru 303>,
        <&cru 305>,
        <&cru 304>;
      pm_qos = <&qos_npu2>;
     };
    };
   };

   power-domain@12 {
    reg = <12>;
    clocks = <&cru 276>,
      <&cru 277>,
      <&cru 278>;
    pm_qos = <&qos_gpu_m0>,
      <&qos_gpu_m1>,
      <&qos_gpu_m2>,
      <&qos_gpu_m3>;
   };

   power-domain@13 {
    reg = <13>;
    #address-cells = <1>;
    #size-cells = <0>;

    power-domain@14 {
     reg = <14>;
     clocks = <&cru 399>,
       <&cru 446>,
       <&cru 444>,
       <&cru 400>,
       <&cru 398>;
     pm_qos = <&qos_rkvdec0>;
    };
    power-domain@15 {
     reg = <15>;
     clocks = <&cru 404>,
       <&cru 446>,
       <&cru 444>,
       <&cru 405>;
     pm_qos = <&qos_rkvdec1>;
    };
    power-domain@16 {
     reg = <16>;
     #address-cells = <1>;
     #size-cells = <0>;
     clocks = <&cru 452>,
       <&cru 453>;
     pm_qos = <&qos_rkvenc0_m0ro>,
       <&qos_rkvenc0_m1ro>,
       <&qos_rkvenc0_m2wo>;

     power-domain@17 {
      reg = <17>;
      clocks = <&cru 457>,
        <&cru 452>,
        <&cru 453>,
        <&cru 458>;
      pm_qos = <&qos_rkvenc1_m0ro>,
        <&qos_rkvenc1_m1ro>,
        <&qos_rkvenc1_m2wo>;
     };
    };
   };

   power-domain@21 {
    reg = <21>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&cru 446>,
      <&cru 445>,
      <&cru 444>,
      <&cru 447>,
      <&cru 426>,
      <&cru 425>,
      <&cru 428>,
      <&cru 429>,
      <&cru 430>,
      <&cru 431>,
      <&cru 432>,
      <&cru 433>,
      <&cru 434>,
      <&cru 435>,
      <&cru 436>,
      <&cru 437>,
      <&cru 439>,
      <&cru 438>;
    pm_qos = <&qos_iep>,
      <&qos_jpeg_dec>,
      <&qos_jpeg_enc0>,
      <&qos_jpeg_enc1>,
      <&qos_jpeg_enc2>,
      <&qos_jpeg_enc3>,
      <&qos_rga2_mro>,
      <&qos_rga2_mwo>;

    power-domain@23 {
     reg = <23>;
     clocks = <&cru 75>,
       <&cru 73>,
       <&cru 446>;
     pm_qos = <&qos_av1>;
    };
    power-domain@14 {
     reg = <14>;
     clocks = <&cru 399>,
       <&cru 446>,
       <&cru 444>,
       <&cru 400>;
     pm_qos = <&qos_rkvdec0>;
    };
    power-domain@15 {
     reg = <15>;
     clocks = <&cru 404>,
       <&cru 446>,
       <&cru 444>;
     pm_qos = <&qos_rkvdec1>;
    };
    power-domain@22 {
     reg = <22>;
     clocks = <&cru 442>,
       <&cru 441>;
     pm_qos = <&qos_rga3_0>;
    };
   };
   power-domain@24 {
    reg = <24>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&cru 622>,
      <&cru 621>,
      <&cru 624>;
    pm_qos = <&qos_vop_m0>,
      <&qos_vop_m1>;

    power-domain@25 {
     reg = <25>;
     clocks = <&cru 502>,
       <&cru 503>,
       <&cru 501>,
       <&cru 499>,
       <&cru 494>,
       <&cru 493>,
       <&cru 621>;
     pm_qos = <&qos_hdcp0>;
    };
   };
   power-domain@26 {
    reg = <26>;
    clocks = <&cru 558>,
      <&cru 559>,
      <&cru 557>,
      <&cru 536>,
      <&cru 535>,
      <&cru 555>,
      <&cru 612>;
    pm_qos = <&qos_hdcp1>,
      <&qos_hdmirx>;
   };
   power-domain@27 {
    reg = <27>;
    #address-cells = <1>;
    #size-cells = <0>;
    clocks = <&cru 481>,
      <&cru 482>,
      <&cru 479>,
      <&cru 478>,
      <&cru 485>,
      <&cru 484>;
    pm_qos = <&qos_isp0_mro>,
      <&qos_isp0_mwo>,
      <&qos_vicap_m0>,
      <&qos_vicap_m1>;

    power-domain@28 {
     reg = <28>;
     clocks = <&cru 289>,
       <&cru 288>,
       <&cru 481>,
       <&cru 482>;
     pm_qos = <&qos_isp1_mwo>,
       <&qos_isp1_mro>;
    };
    power-domain@29 {
     reg = <29>;
     clocks = <&cru 470>,
       <&cru 469>,
       <&cru 473>,
       <&cru 472>,
       <&cru 482>;
     pm_qos = <&qos_fisheye0>,
       <&qos_fisheye1>;
    };
   };
   power-domain@30 {
    reg = <30>;
    clocks = <&cru 393>,
      <&cru 394>;
    pm_qos = <&qos_rga3_1>;
   };
   power-domain@31 {
    reg = <31>;
    clocks = <&cru 358>,
      <&cru 417>,
      <&cru 420>,
      <&cru 413>,
      <&cru 414>,
      <&cru 415>,
      <&cru 416>;
    pm_qos = <&qos_usb3_0>,
      <&qos_usb3_1>,
      <&qos_usb2host_0>,
      <&qos_usb2host_1>;
   };
   power-domain@33 {
    reg = <33>;
    clocks = <&cru 358>,
      <&cru 361>,
      <&cru 362>;
   };
   power-domain@34 {
    reg = <34>;
    clocks = <&cru 358>,
      <&cru 361>,
      <&cru 362>;
   };
   power-domain@37 {
    reg = <37>;
    clocks = <&cru 409>,
      <&cru 320>;
    pm_qos = <&qos_sdio>;
   };
   power-domain@38 {
    reg = <38>;
    clocks = <&cru 60>,
      <&cru 61>;
   };
   power-domain@40 {
    reg = <40>;
    pm_qos = <&qos_sdmmc>;
   };
  };
 };

 pvtm@fda40000 {
  compatible = "rockchip,rk3588-bigcore0-pvtm";
  reg = <0x0 0xfda40000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <0>;
  pvtm@0 {
   reg = <0>;
   clocks = <&cru 710>, <&cru 21>;
   clock-names = "clk", "pclk";
  };
 };

 pvtm@fda50000 {
  compatible = "rockchip,rk3588-bigcore1-pvtm";
  reg = <0x0 0xfda50000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <0>;
  pvtm@1 {
   reg = <1>;
   clocks = <&cru 712>, <&cru 23>;
   clock-names = "clk", "pclk";
  };
 };

 pvtm@fda60000 {
  compatible = "rockchip,rk3588-litcore-pvtm";
  reg = <0x0 0xfda60000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <0>;
  pvtm@2 {
   reg = <2>;
   clocks = <&cru 714>, <&cru 27>;
   clock-names = "clk", "pclk";
  };
 };

 pvtm@fdaf0000 {
  compatible = "rockchip,rk3588-npu-pvtm";
  reg = <0x0 0xfdaf0000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <0>;
  pvtm@3 {
   reg = <3>;
   clocks = <&cru 299>, <&cru 297>;
   clock-names = "clk", "pclk";
   resets = <&cru 478>, <&cru 476>;
   reset-names = "rts", "rst-p";
  };
 };

 pvtm@fdb30000 {
  compatible = "rockchip,rk3588-gpu-pvtm";
  reg = <0x0 0xfdb30000 0x0 0x100>;
  #address-cells = <1>;
  #size-cells = <0>;
  pvtm@4 {
   reg = <4>;
   clocks = <&cru 280>;
   clock-names = "clk";
   resets = <&cru 1072>, <&cru 1071>;
   reset-names = "rts", "rst-p";
  };
 };

 rknpu: npu@fdab0000 {
  compatible = "rockchip,rk3588-rknpu";
  reg = <0x0 0xfdab0000 0x0 0x10000>,
        <0x0 0xfdac0000 0x0 0x10000>,
        <0x0 0xfdad0000 0x0 0x10000>;
  interrupts = <0 110 4>,
        <0 111 4>,
        <0 112 4>;
  interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
  clocks = <&scmi_clk 6>, <&cru 301>,
    <&cru 290>, <&cru 292>,
    <&cru 302>, <&cru 291>,
    <&cru 293>, <&cru 305>;
  clock-names = "clk_npu", "aclk0",
         "aclk1", "aclk2",
         "hclk0", "hclk1",
         "hclk2", "pclk";
  assigned-clocks = <&scmi_clk 6>;
  assigned-clock-rates = <200000000>;
  resets = <&cru 486>, <&cru 432>, <&cru 448>,
    <&cru 488>, <&cru 434>, <&cru 450>;
  reset-names = "srst_a0", "srst_a1", "srst_a2",
         "srst_h0", "srst_h1", "srst_h2";
  power-domains = <&power 9>,
    <&power 10>,
    <&power 11>;
  power-domain-names = "npu0", "npu1", "npu2";
  operating-points-v2 = <&npu_opp_table>;
  iommus = <&rknpu_mmu>;
  status = "disabled";
 };

 npu_opp_table: npu-opp-table {
  compatible = "operating-points-v2";

  nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>;
  nvmem-cell-names = "leakage", "opp-info", "specification_serial_number";
  rockchip,supported-hw;

  rockchip,pvtm-hw = <0x06>;
  rockchip,pvtm-voltage-sel-hw = <
   0 799 0
   800 819 1
   820 844 2
   845 869 3
   870 894 4
   895 9999 5
  >;
  rockchip,pvtm-voltage-sel = <
   0 815 0
   816 835 1
   836 860 2
   861 885 3
   886 910 4
   911 9999 5
  >;
  rockchip,pvtm-pvtpll;
  rockchip,pvtm-offset = <0x50>;
  rockchip,pvtm-sample-time = <1100>;
  rockchip,pvtm-freq = <800000>;
  rockchip,pvtm-volt = <750000>;
  rockchip,pvtm-ref-temp = <25>;
  rockchip,pvtm-temp-prop = <(-113) (-113)>;
  rockchip,pvtm-thermal-zone = "npu-thermal";

  rockchip,opp-clocks = <&cru 298>, <&cru 303>;
  rockchip,grf = <&npu_grf>;
  volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;
  low-volt-mem-read-margin = <4>;
  intermediate-threshold-freq = <500000>;
  rockchip,init-freq = <1000000>;

  rockchip,temp-hysteresis = <5000>;
  rockchip,low-temp = <10000>;
  rockchip,low-temp-min-volt = <750000>;
  rockchip,high-temp = <85000>;
  rockchip,high-temp-max-freq = <800000>;


  opp-300000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <700000 700000 850000>,
     <700000 700000 850000>;
   opp-microvolt-L1 = <687500 687500 850000>,
        <687500 687500 850000>;
   opp-microvolt-L2 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L3 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L4 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L5 = <675000 675000 850000>,
        <675000 675000 850000>;
  };
  opp-400000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <700000 700000 850000>,
     <700000 700000 850000>;
   opp-microvolt-L1 = <687500 687500 850000>,
        <687500 687500 850000>;
   opp-microvolt-L2 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L3 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L4 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L5 = <675000 675000 850000>,
        <675000 675000 850000>;
  };
  opp-500000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <500000000>;
   opp-microvolt = <700000 700000 850000>,
     <700000 700000 850000>;
   opp-microvolt-L1 = <687500 687500 850000>,
        <687500 687500 850000>;
   opp-microvolt-L2 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L3 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L4 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L5 = <675000 675000 850000>,
        <675000 675000 850000>;
  };
  opp-600000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <700000 700000 850000>,
     <700000 700000 850000>;
   opp-microvolt-L1 = <687500 687500 850000>,
        <687500 687500 850000>;
   opp-microvolt-L2 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L3 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L4 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L5 = <675000 675000 850000>,
        <675000 675000 850000>;
  };
  opp-700000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <700000000>;
   opp-microvolt = <700000 700000 850000>,
     <700000 700000 850000>;
   opp-microvolt-L3 = <687500 687500 850000>,
        <687500 687500 850000>;
   opp-microvolt-L4 = <675000 675000 850000>,
        <675000 675000 850000>;
   opp-microvolt-L5 = <675000 675000 850000>,
        <675000 675000 850000>;
  };
  opp-800000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
   opp-microvolt-L2 = <737500 737500 850000>,
        <737500 737500 850000>;
   opp-microvolt-L3 = <725000 725000 850000>,
        <725000 725000 850000>;
   opp-microvolt-L4 = <712500 712500 850000>,
        <712500 712500 850000>;
   opp-microvolt-L5 = <700000 700000 850000>,
        <700000 700000 850000>;
  };
  opp-900000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <900000000>;
   opp-microvolt = <800000 800000 850000>,
     <800000 800000 850000>;
   opp-microvolt-L1 = <787500 787500 850000>,
        <787500 787500 850000>;
   opp-microvolt-L2 = <775000 775000 850000>,
        <775000 775000 850000>;
   opp-microvolt-L3 = <762500 762500 850000>,
        <762500 762500 850000>;
   opp-microvolt-L4 = <750000 750000 850000>,
        <750000 750000 850000>;
   opp-microvolt-L5 = <737500 737500 850000>,
        <737500 737500 850000>;
  };
  opp-1000000000 {
   opp-supported-hw = <0xf9 0xffff>;
   opp-hz = /bits/ 64 <1000000000>;
   opp-microvolt = <850000 850000 850000>,
     <850000 850000 850000>;
   opp-microvolt-L1 = <837500 837500 850000>,
        <837500 837500 850000>;
   opp-microvolt-L2 = <825000 825000 850000>,
        <825000 825000 850000>;
   opp-microvolt-L3 = <812500 812500 850000>,
        <812500 812500 850000>;
   opp-microvolt-L4 = <800000 800000 850000>,
        <800000 800000 850000>;
   opp-microvolt-L5 = <787500 787500 850000>,
        <787500 787500 850000>;
  };


  opp-j-m-300000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <300000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-400000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <400000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-500000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <500000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-600000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <600000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-700000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <700000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-800000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
  };
  opp-j-m-950000000 {
   opp-supported-hw = <0x06 0xffff>;
   opp-hz = /bits/ 64 <950000000>;
   opp-microvolt = <837500 837500 850000>,
     <837500 837500 850000>;
   opp-microvolt-L1 = <825000 825000 850000>,
        <825000 825000 850000>;
   opp-microvolt-L2 = <812500 812500 850000>,
        <812500 812500 850000>;
   opp-microvolt-L3 = <800000 800000 850000>,
        <800000 800000 850000>;
   opp-microvolt-L4 = <787500 787500 850000>,
        <787500 787500 850000>;
   opp-microvolt-L5 = <775000 775000 850000>,
        <775000 775000 850000>;
  };
 };

 rknpu_mmu: iommu@fdab9000 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdab9000 0x0 0x100>,
        <0x0 0xfdaba000 0x0 0x100>,
        <0x0 0xfdaca000 0x0 0x100>,
        <0x0 0xfdada000 0x0 0x100>;
  interrupts = <0 110 4>,
        <0 111 4>,
        <0 112 4>;
  interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
  clocks = <&cru 301>, <&cru 290>, <&cru 292>,
    <&cru 302>, <&cru 291>, <&cru 293>;
  clock-names = "aclk0", "aclk1", "aclk2",
         "iface0", "iface1", "iface2";
  #iommu-cells = <0>;
  status = "disabled";
 };

 vepu: vepu@fdb50000 {
  compatible = "rockchip,vpu-encoder-v2";
  reg = <0x0 0xfdb50000 0x0 0x400>;
  interrupts = <0 120 4>;
  interrupt-names = "irq_vepu";
  clocks = <&cru 448>, <&cru 449>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 448>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 712>, <&cru 713>;
  reset-names = "shared_video_a", "shared_video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&vdpu_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <0>;
  rockchip,resetgroup-node = <0>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 vdpu: vdpu@fdb50400 {
  compatible = "rockchip,vpu-decoder-v2";
  reg = <0x0 0xfdb50400 0x0 0x400>;
  interrupts = <0 119 4>;
  interrupt-names = "irq_vdpu";
  clocks = <&cru 448>, <&cru 449>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 448>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 712>, <&cru 713>;
  reset-names = "shared_video_a", "shared_video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&vdpu_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <0>;
  rockchip,resetgroup-node = <0>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 vdpu_mmu: iommu@fdb50800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdb50800 0x0 0x40>;
  interrupts = <0 118 4>;
  interrupt-names = "irq_vdpu_mmu";
  clocks = <&cru 448>, <&cru 449>;
  clock-names = "aclk", "iface";
  power-domains = <&power 21>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 avsd: avsd-plus@fdb51000 {
  compatible = "rockchip,avs-plus-decoder";
  reg = <0x0 0xfdb51000 0x0 0x200>;
  interrupts = <0 119 4>;
  interrupt-names = "irq_avsd";
  clocks = <&cru 448>, <&cru 449>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 448>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 712>, <&cru 713>;
  reset-names = "shared_video_a", "shared_video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&vdpu_mmu>;
  power-domains = <&power 21>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <0>;
  rockchip,resetgroup-node = <0>;
  status = "disabled";
 };

 rga3_core0: rga@fdb60000 {
  compatible = "rockchip,rga3_core0";
  reg = <0x0 0xfdb60000 0x0 0x1000>;
  interrupts = <0 114 4>;
  interrupt-names = "rga3_core0_irq";
  clocks = <&cru 442>, <&cru 441>, <&cru 443>;
  clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0";
  power-domains = <&power 22>;
  iommus = <&rga3_0_mmu>;
  status = "disabled";
 };

 rga3_0_mmu: iommu@fdb60f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdb60f00 0x0 0x100>;
  interrupts = <0 114 4>;
  interrupt-names = "rga3_0_mmu";
  clocks = <&cru 442>, <&cru 441>;
  clock-names = "aclk", "iface";
  power-domains = <&power 22>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 rga3_core1: rga@fdb70000 {
  compatible = "rockchip,rga3_core1";
  reg = <0x0 0xfdb70000 0x0 0x1000>;
  interrupts = <0 115 4>;
  interrupt-names = "rga3_core1_irq";
  clocks = <&cru 394>, <&cru 393>, <&cru 395>;
  clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1";
  power-domains = <&power 30>;
  iommus = <&rga3_1_mmu>;
  status = "disabled";
 };

 rga3_1_mmu: iommu@fdb70f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdb70f00 0x0 0x100>;
  interrupts = <0 115 4>;
  interrupt-names = "rga3_1_mmu";
  clocks = <&cru 394>, <&cru 393>;
  clock-names = "aclk", "iface";
  power-domains = <&power 30>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 rga2: rga@fdb80000 {
  compatible = "rockchip,rga2_core0";
  reg = <0x0 0xfdb80000 0x0 0x1000>;
  interrupts = <0 116 4>;
  interrupt-names = "rga2_irq";
  clocks = <&cru 439>, <&cru 438>, <&cru 440>;
  clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
  power-domains = <&power 21>;
  status = "disabled";
 };

 jpegd: jpegd@fdb90000 {
  compatible = "rockchip,rkv-jpeg-decoder-v1";
  reg = <0x0 0xfdb90000 0x0 0x400>;
  interrupts = <0 129 4>;
  interrupt-names = "irq_jpegd";
  clocks = <&cru 436>, <&cru 437>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <600000000>, <0>;
  assigned-clocks = <&cru 436>;
  assigned-clock-rates = <600000000>;
  resets = <&cru 722>, <&cru 723>;
  reset-names = "video_a", "video_h";
  rockchip,skip-pmu-idle-request;
  iommus = <&jpegd_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <1>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 jpegd_mmu: iommu@fdb90480 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdb90480 0x0 0x40>;
  interrupts = <0 130 4>;
  interrupt-names = "irq_jpegd_mmu";
  clocks = <&cru 436>, <&cru 437>;
  clock-names = "aclk", "iface";
  power-domains = <&power 21>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 jpege0: jpege-core@fdba0000 {
  compatible = "rockchip,vpu-jpege-core";
  reg = <0x0 0xfdba0000 0x0 0x400>;
  interrupts = <0 122 4>;
  interrupt-names = "irq_jpege0";
  clocks = <&cru 428>, <&cru 429>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 428>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 714>, <&cru 715>;
  reset-names = "video_a", "video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&jpege0_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <2>;
  rockchip,ccu = <&jpege_ccu>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 jpege0_mmu: iommu@fdba0800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdba0800 0x0 0x40>;
  interrupts = <0 121 4>;
  interrupt-names = "irq_jpege0_mmu";
  clocks = <&cru 428>, <&cru 429>;
  clock-names = "aclk", "iface";
  power-domains = <&power 21>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 jpege1: jpege-core@fdba4000 {
  compatible = "rockchip,vpu-jpege-core";
  reg = <0x0 0xfdba4000 0x0 0x400>;
  interrupts = <0 124 4>;
  interrupt-names = "irq_jpege1";
  clocks = <&cru 430>, <&cru 431>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 430>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 716>, <&cru 717>;
  reset-names = "video_a", "video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&jpege1_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <2>;
  rockchip,ccu = <&jpege_ccu>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 jpege1_mmu: iommu@fdba4800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdba4800 0x0 0x40>;
  interrupts = <0 123 4>;
  interrupt-names = "irq_jpege1_mmu";
  clocks = <&cru 430>, <&cru 431>;
  clock-names = "aclk", "iface";
  power-domains = <&power 21>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 jpege2: jpege-core@fdba8000 {
  compatible = "rockchip,vpu-jpege-core";
  reg = <0x0 0xfdba8000 0x0 0x400>;
  interrupts = <0 126 4>;
  interrupt-names = "irq_jpege2";
  clocks = <&cru 432>, <&cru 433>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 432>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 718>, <&cru 719>;
  reset-names = "video_a", "video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&jpege2_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <2>;
  rockchip,ccu = <&jpege_ccu>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 jpege2_mmu: iommu@fdba8800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdba8800 0x0 0x40>;
  interrupts = <0 125 4>;
  interrupt-names = "irq_jpege2_mmu";
  clocks = <&cru 432>, <&cru 433>;
  clock-names = "aclk", "iface";
  power-domains = <&power 21>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 jpege3: jpege-core@fdbac000 {
  compatible = "rockchip,vpu-jpege-core";
  reg = <0x0 0xfdbac000 0x0 0x400>;
  interrupts = <0 128 4>;
  interrupt-names = "irq_jpege3";
  clocks = <&cru 434>, <&cru 435>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 434>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 720>, <&cru 721>;
  reset-names = "video_a", "video_h";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  iommus = <&jpege3_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <2>;
  rockchip,ccu = <&jpege_ccu>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 jpege3_mmu: iommu@fdbac800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdbac800 0x0 0x40>;
  interrupts = <0 127 4>;
  interrupt-names = "irq_jpege3_mmu";
  clocks = <&cru 434>, <&cru 435>;
  clock-names = "aclk", "iface";
  power-domains = <&power 21>;
  #iommu-cells = <0>;
  status = "disabled";
 };

 iep: iep@fdbb0000 {
  compatible = "rockchip,iep-v2";
  reg = <0x0 0xfdbb0000 0x0 0x500>;
  interrupts = <0 117 4>;
  interrupt-names = "irq_iep";
  clocks = <&cru 426>, <&cru 425>, <&cru 427>;
  clock-names = "aclk", "hclk", "sclk";
  rockchip,normal-rates = <594000000>, <0>;
  assigned-clocks = <&cru 426>;
  assigned-clock-rates = <594000000>;
  resets = <&cru 725>, <&cru 724>, <&cru 726>;
  reset-names = "rst_a", "rst_h", "rst_s";
  rockchip,skip-pmu-idle-request;
  rockchip,disable-auto-freq;
  power-domains = <&power 21>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <6>;
  iommus = <&iep_mmu>;
  status = "disabled";
 };

 iep_mmu: iommu@fdbb0800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdbb0800 0x0 0x100>;
  interrupts = <0 117 4>;
  interrupt-names = "irq_iep_mmu";
  clocks = <&cru 426>, <&cru 425>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  power-domains = <&power 21>;
  status = "disabled";
 };

 rkvenc0: rkvenc-core@fdbd0000 {
  compatible = "rockchip,rkv-encoder-v2-core";
  reg = <0x0 0xfdbd0000 0x0 0x6000>;
  interrupts = <0 101 4>;
  interrupt-names = "irq_rkvenc0";
  clocks = <&cru 453>, <&cru 452>, <&cru 454>;
  clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
  rockchip,normal-rates = <500000000>, <0>, <800000000>;
  assigned-clocks = <&cru 453>, <&cru 454>;
  assigned-clock-rates = <500000000>, <800000000>;
  resets = <&cru 757>, <&cru 756>, <&cru 758>;
  reset-names = "video_a", "video_h", "video_core";
  rockchip,skip-pmu-idle-request;
  iommus = <&rkvenc0_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,ccu = <&rkvenc_ccu>;
  rockchip,taskqueue-node = <7>;
  rockchip,task-capacity = <8>;
  power-domains = <&power 16>;
  operating-points-v2 = <&venc_opp_table>;
  status = "disabled";
 };

 rkvenc0_mmu: iommu@fdbdf000 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>;
  interrupts = <0 99 4>,
        <0 100 4>;
  interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1";
  clocks = <&cru 453>, <&cru 452>;
  clock-names = "aclk", "iface";
  rockchip,disable-mmu-reset;
  rockchip,enable-cmd-retry;
  rockchip,shootdown-entire;
  #iommu-cells = <0>;
  power-domains = <&power 16>;
  status = "disabled";
 };

 rkvenc1: rkvenc-core@fdbe0000 {
  compatible = "rockchip,rkv-encoder-v2-core";
  reg = <0x0 0xfdbe0000 0x0 0x6000>;
  interrupts = <0 104 4>;
  interrupt-names = "irq_rkvenc1";
  clocks = <&cru 458>, <&cru 457>, <&cru 459>;
  clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
  rockchip,normal-rates = <500000000>, <0>, <800000000>;
  assigned-clocks = <&cru 458>, <&cru 459>;
  assigned-clock-rates = <500000000>, <800000000>;
  resets = <&cru 773>, <&cru 772>, <&cru 774>;
  reset-names = "video_a", "video_h", "video_core";
  rockchip,skip-pmu-idle-request;
  iommus = <&rkvenc1_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,ccu = <&rkvenc_ccu>;
  rockchip,taskqueue-node = <7>;
  rockchip,task-capacity = <8>;
  power-domains = <&power 17>;
  operating-points-v2 = <&venc_opp_table>;
  status = "disabled";
 };

 rkvenc1_mmu: iommu@fdbef000 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>;
  interrupts = <0 102 4>,
        <0 103 4>;
  interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1";
  clocks = <&cru 458>, <&cru 457>;
  lock-names = "aclk", "iface";
  rockchip,disable-mmu-reset;
  rockchip,enable-cmd-retry;
  rockchip,shootdown-entire;
  #iommu-cells = <0>;
  power-domains = <&power 17>;
  status = "disabled";
 };

 venc_opp_table: venc-opp-table {
  compatible = "operating-points-v2";

  nvmem-cells = <&codec_leakage>, <&venc_opp_info>;
  nvmem-cell-names = "leakage", "opp-info";
  rockchip,leakage-voltage-sel = <
   1 15 0
   16 25 1
   26 254 2
  >;

  rockchip,grf = <&sys_grf>;
  volt-mem-read-margin = <
   855000 1
   765000 2
   675000 3
   495000 4
  >;

  opp-800000000 {
   opp-hz = /bits/ 64 <800000000>;
   opp-microvolt = <750000 750000 850000>,
     <750000 750000 850000>;
   opp-microvolt-L0 = <800000 800000 850000>,
        <800000 800000 850000>;
   opp-microvolt-L1 = <775000 775000 850000>,
        <775000 775000 850000>;
   opp-microvolt-L2 = <750000 750000 850000>,
        <750000 750000 850000>;
  };
 };

 rkvdec_ccu: rkvdec-ccu@fdc30000 {
  compatible = "rockchip,rkv-decoder-v2-ccu";
  reg = <0x0 0xfdc30000 0x0 0x100>;
  reg-names = "ccu";
  clocks = <&cru 398>;
  clock-names = "aclk_ccu";
  assigned-clocks = <&cru 398>;
  assigned-clock-rates = <600000000>;
  resets = <&cru 642>;
  reset-names = "video_ccu";
  rockchip,skip-pmu-idle-request;

  rockchip,ccu-mode = <1>;
  power-domains = <&power 14>;
  status = "disabled";
 };

 rkvdec0: rkvdec-core@fdc38000 {
  compatible = "rockchip,rkv-decoder-v2";
  reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>;
  reg-names = "regs", "link";
  interrupts = <0 95 4>;
  interrupt-names = "irq_rkvdec0";
  clocks = <&cru 400>, <&cru 399>, <&cru 403>,
    <&cru 401>, <&cru 402>;
  clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
         "clk_cabac", "clk_hevc_cabac";
  rockchip,normal-rates = <800000000>, <0>, <600000000>,
     <600000000>, <1000000000>;
  assigned-clocks = <&cru 400>, <&cru 403>,
      <&cru 401>, <&cru 402>;
  assigned-clock-rates = <800000000>, <600000000>,
           <600000000>, <1000000000>;
  resets = <&cru 644>, <&cru 643>, <&cru 649>,
    <&cru 647>, <&cru 648>;
  reset-names = "video_a", "video_h", "video_core",
         "video_cabac", "video_hevc_cabac";
  rockchip,skip-pmu-idle-request;
  iommus = <&rkvdec0_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,ccu = <&rkvdec_ccu>;
  rockchip,core-mask = <0x00010001>;
  rockchip,task-capacity = <16>;
  rockchip,taskqueue-node = <9>;
  rockchip,sram = <&rkvdec0_sram>;

  rockchip,rcb-iova = <0xFFF00000 0x100000>;
  rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>,
        <139 180224>, <133 49152>, <134 8192>, <135 4352>,
        <138 13056>, <142 291584>;
  rockchip,rcb-min-width = <512>;
  power-domains = <&power 14>;
  status = "disabled";
 };

 rkvdec0_mmu: iommu@fdc38700 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
  interrupts = <0 96 4>;
  interrupt-names = "irq_rkvdec0_mmu";
  clocks = <&cru 400>, <&cru 399>;
  clock-names = "aclk", "iface";
  rockchip,disable-mmu-reset;
  rockchip,enable-cmd-retry;
  rockchip,shootdown-entire;
  rockchip,master-handle-irq;
  #iommu-cells = <0>;
  power-domains = <&power 14>;
  status = "disabled";
 };

 rkvdec1: rkvdec-core@fdc48000 {
  compatible = "rockchip,rkv-decoder-v2";
  reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>;
  reg-names = "regs", "link";
  interrupts = <0 97 4>;
  interrupt-names = "irq_rkvdec1";
  clocks = <&cru 405>, <&cru 404>, <&cru 408>,
    <&cru 406>, <&cru 407>;
  clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
         "clk_cabac", "clk_hevc_cabac";
  rockchip,normal-rates = <800000000>, <0>, <600000000>,
     <600000000>, <1000000000>;
  assigned-clocks = <&cru 405>, <&cru 408>,
      <&cru 406>, <&cru 407>;
  assigned-clock-rates = <800000000>, <600000000>,
           <600000000>, <1000000000>;
  resets = <&cru 659>, <&cru 658>, <&cru 664>,
    <&cru 662>, <&cru 663>;
  reset-names = "video_a", "video_h", "video_core",
         "video_cabac", "video_hevc_cabac";
  rockchip,skip-pmu-idle-request;
  iommus = <&rkvdec1_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,ccu = <&rkvdec_ccu>;
  rockchip,core-mask = <0x00020002>;
  rockchip,task-capacity = <16>;
  rockchip,taskqueue-node = <9>;
  rockchip,sram = <&rkvdec1_sram>;

  rockchip,rcb-iova = <0xFFE00000 0x100000>;
  rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>,
        <139 180224>, <133 49152>, <134 8192>, <135 4352>,
        <138 13056>, <142 291584>;
  rockchip,rcb-min-width = <512>;
  power-domains = <&power 15>;
  status = "disabled";
 };

 rkvdec1_mmu: iommu@fdc48700 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>;
  interrupts = <0 98 4>;
  interrupt-names = "irq_rkvdec1_mmu";
  clocks = <&cru 405>, <&cru 404>;
  clock-names = "aclk", "iface";
  rockchip,disable-mmu-reset;
  rockchip,enable-cmd-retry;
  rockchip,shootdown-entire;
  rockchip,master-handle-irq;
  #iommu-cells = <0>;
  power-domains = <&power 15>;
  status = "disabled";
 };

 av1d: av1d@fdc70000 {
  compatible = "rockchip,av1-decoder";
  reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>,
        <0x0 0xfdc90000 0x0 0x400>;
  reg-names = "vcd", "cache", "afbc";
  interrupts = <0 108 4>, <0 107 4>,
        <0 106 4>;
  interrupt-names = "irq_av1d", "irq_cache", "irq_afbc";
  clocks = <&cru 73>, <&cru 75>;
  clock-names = "aclk_vcodec", "hclk_vcodec";
  rockchip,normal-rates = <400000000>, <400000000>;
  assigned-clocks = <&cru 73>, <&cru 75>;
  assigned-clock-rates = <400000000>, <400000000>;
  resets = <&cru 1090>, <&cru 1093>;
  reset-names = "video_a", "video_h";
  iommus = <&av1d_mmu>;
  rockchip,srv = <&mpp_srv>;
  rockchip,taskqueue-node = <11>;
  power-domains = <&power 23>;
  status = "disabled";
 };

 av1d_mmu: iommu@fdca0000 {
  compatible = "rockchip,iommu-av1";
  reg = <0x0 0xfdca0000 0x0 0x600>;
  interrupts = <0 109 4>;
  interrupt-names = "irq_av1d_mmu";
  clocks = <&cru 73>, <&cru 75>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  power-domains = <&power 23>;
  status = "disabled";
 };

 rkisp_unite: rkisp-unite@fdcb0000 {
  compatible = "rockchip,rk3588-rkisp-unite";
  reg = <0x0 0xfdcb0000 0x0 0x10000>,
        <0x0 0xfdcc0000 0x0 0x10000>;
  interrupts = <0 135 4>,
        <0 137 4>,
        <0 138 4>;
  interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
  clocks = <&cru 478>, <&cru 479>,
    <&cru 475>, <&cru 476>,
    <&cru 477>, <&cru 288>,
    <&cru 289>, <&cru 285>,
    <&cru 286>, <&cru 287>;
  clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0",
         "clk_isp_core_marvin0", "clk_isp_core_vicap0",
         "aclk_isp1", "hclk_isp1", "clk_isp_core1",
         "clk_isp_core_marvin1", "clk_isp_core_vicap1";
  power-domains = <&power 28>;
  iommus = <&rkisp_unite_mmu>;
  status = "disabled";
 };

 rkisp0: rkisp@fdcb0000 {
  compatible = "rockchip,rk3588-rkisp";
  reg = <0x0 0xfdcb0000 0x0 0x7f00>;
  interrupts = <0 131 4>,
        <0 133 4>,
        <0 134 4>;
  interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
  clocks = <&cru 478>, <&cru 479>,
    <&cru 475>, <&cru 476>,
    <&cru 477>;
  clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
         "clk_isp_core_marvin", "clk_isp_core_vicap";
  power-domains = <&power 27>;
  iommus = <&isp0_mmu>;
  status = "disabled";
 };

 rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>;
  interrupts = <0 132 4>,
        <0 136 4>;
  interrupt-names = "isp0_mmu", "isp1_mmu";
  clocks = <&cru 478>, <&cru 479>,
    <&cru 288>, <&cru 289>;
  clock-names = "aclk0", "iface0", "aclk1", "iface1";
  power-domains = <&power 28>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 isp0_mmu: iommu@fdcb7f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcb7f00 0x0 0x100>;
  interrupts = <0 132 4>;
  interrupt-names = "isp0_mmu";
  clocks = <&cru 478>, <&cru 479>;
  clock-names = "aclk", "iface";
  power-domains = <&power 27>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 rkisp1: rkisp@fdcc0000 {
  compatible = "rockchip,rk3588-rkisp";
  reg = <0x0 0xfdcc0000 0x0 0x7f00>;
  interrupts = <0 135 4>,
        <0 137 4>,
        <0 138 4>;
  interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
  clocks = <&cru 288>, <&cru 289>,
    <&cru 285>, <&cru 286>,
    <&cru 287>;
  clock-names = "aclk_isp", "hclk_isp", "clk_isp_core",
         "clk_isp_core_marvin", "clk_isp_core_vicap";
  power-domains = <&power 28>;
  iommus = <&isp1_mmu>;
  status = "disabled";
 };

 isp1_mmu: iommu@fdcc7f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcc7f00 0x0 0x100>;
  interrupts = <0 136 4>;
  interrupt-names = "isp1_mmu";
  clocks = <&cru 288>, <&cru 289>;
  clock-names = "aclk", "iface";
  power-domains = <&power 28>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 rkispp0: rkispp@fdcd0000 {
  compatible = "rockchip,rk3588-rkispp";
  reg = <0x0 0xfdcd0000 0x0 0x0f00>;
  interrupts = <0 139 4>;
  interrupt-names = "fec_irq";
  clocks = <&cru 469>, <&cru 470>,
    <&cru 471>;
  clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
  assigned-clocks = <&cru 470>;
  assigned-clock-rates = <100000000>;
  power-domains = <&power 29>;
  iommus = <&fec0_mmu>;
  status = "disabled";
 };

 fec0_mmu: iommu@fdcd0f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcd0f00 0x0 0x100>;
  interrupts = <0 140 4>;
  interrupt-names = "fec0_mmu";
  clocks = <&cru 469>, <&cru 470>, <&cru 471>;
  clock-names = "aclk", "iface", "pclk";
  power-domains = <&power 29>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 rkispp1: rkispp@fdcd8000 {
  compatible = "rockchip,rk3588-rkispp";
  reg = <0x0 0xfdcd8000 0x0 0x0f00>;
  interrupts = <0 141 4>;
  interrupt-names = "fec_irq";
  clocks = <&cru 472>, <&cru 473>,
    <&cru 474>;
  clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp";
  assigned-clocks = <&cru 473>;
  assigned-clock-rates = <100000000>;
  power-domains = <&power 29>;
  iommus = <&fec1_mmu>;
  status = "disabled";
 };

 fec1_mmu: iommu@fdcd8f00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdcd8f00 0x0 0x100>;
  interrupts = <0 142 4>;
  interrupt-names = "fec1_mmu";
  clocks = <&cru 472>, <&cru 473>, <&cru 474>;
  clock-names = "aclk", "iface", "pclk";
  power-domains = <&power 29>;
  #iommu-cells = <0>;
  rockchip,disable-mmu-reset;
  status = "disabled";
 };

 rkcif: rkcif@fdce0000 {
  compatible = "rockchip,rk3588-cif";
  reg = <0x0 0xfdce0000 0x0 0x800>;
  reg-names = "cif_regs";
  interrupts = <0 155 4>;
  interrupt-names = "cif-intr";
  clocks = <&cru 484>, <&cru 485>, <&cru 483>,
    <&cru 461>, <&cru 462>;
  clock-names = "aclk_cif", "hclk_cif", "dclk_cif",
         "iclk_host0", "iclk_host1";
  resets = <&cru 791>, <&cru 792>, <&cru 790>,
    <&cru 820>, <&cru 821>,
    <&cru 822>, <&cru 823>,
    <&cru 824>, <&cru 825>;
  reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d",
         "rst_cif_host0", "rst_cif_host1", "rst_cif_host2",
         "rst_cif_host3", "rst_cif_host4", "rst_cif_host5";
  assigned-clocks = <&cru 483>;
  assigned-clock-rates = <600000000>;
  power-domains = <&power 27>;
  rockchip,grf = <&sys_grf>;
  iommus = <&rkcif_mmu>;
  nvmem-cells = <&specification_serial_number>,
         <&package_serial_number_low>,
         <&package_serial_number_high>;
  nvmem-cell-names = "specification",
       "package_low",
       "package_high";
  status = "disabled";
 };

 rkcif_mmu: iommu@fdce0800 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdce0800 0x0 0x100>,
        <0x0 0xfdce0900 0x0 0x100>;
  interrupts = <0 113 4>;
  interrupt-names = "cif_mmu";
  clocks = <&cru 484>, <&cru 485>;
  clock-names = "aclk", "iface";
  power-domains = <&power 27>;
  rockchip,disable-mmu-reset;
  #iommu-cells = <0>;
  status = "disabled";
 };

 mipi0_csi2_hw: mipi0-csi2-hw@fdd10000 {
  compatible = "rockchip,rk3588-mipi-csi2-hw";
  reg = <0x0 0xfdd10000 0x0 0x10000>;
  reg-names = "csihost_regs";
  interrupts = <0 143 4>,
        <0 144 4>;
  interrupt-names = "csi-intr1", "csi-intr2";
  clocks = <&cru 463>;
  clock-names = "pclk_csi2host";
  resets = <&cru 804>;
  reset-names = "srst_csihost_p";
  status = "okay";
 };

 mipi1_csi2_hw: mipi1-csi2-hw@fdd20000 {
  compatible = "rockchip,rk3588-mipi-csi2-hw";
  reg = <0x0 0xfdd20000 0x0 0x10000>;
  reg-names = "csihost_regs";
  interrupts = <0 145 4>,
        <0 146 4>;
  interrupt-names = "csi-intr1", "csi-intr2";
  clocks = <&cru 464>;
  clock-names = "pclk_csi2host";
  resets = <&cru 805>;
  reset-names = "srst_csihost_p";
  status = "okay";
 };

 mipi2_csi2_hw: mipi2-csi2-hw@fdd30000 {
  compatible = "rockchip,rk3588-mipi-csi2-hw";
  reg = <0x0 0xfdd30000 0x0 0x10000>;
  reg-names = "csihost_regs";
  interrupts = <0 147 4>,
        <0 148 4>;
  interrupt-names = "csi-intr1", "csi-intr2";
  clocks = <&cru 465>;
  clock-names = "pclk_csi2host";
  resets = <&cru 806>;
  reset-names = "srst_csihost_p";
  status = "okay";
 };

 mipi3_csi2_hw: mipi3-csi2-hw@fdd40000 {
  compatible = "rockchip,rk3588-mipi-csi2-hw";
  reg = <0x0 0xfdd40000 0x0 0x10000>;
  reg-names = "csihost_regs";
  interrupts = <0 149 4>,
        <0 150 4>;
  interrupt-names = "csi-intr1", "csi-intr2";
  clocks = <&cru 466>;
  clock-names = "pclk_csi2host";
  resets = <&cru 807>;
  reset-names = "srst_csihost_p";
  status = "okay";
 };

 mipi4_csi2_hw: mipi4-csi2-hw@fdd50000 {
  compatible = "rockchip,rk3588-mipi-csi2-hw";
  reg = <0x0 0xfdd50000 0x0 0x10000>;
  reg-names = "csihost_regs";
  interrupts = <0 151 4>,
        <0 152 4>;
  interrupt-names = "csi-intr1", "csi-intr2";
  clocks = <&cru 467>;
  clock-names = "pclk_csi2host";
  resets = <&cru 808>;
  reset-names = "srst_csihost_p";
  status = "okay";
 };

 mipi5_csi2_hw: mipi5-csi2-hw@fdd60000 {
  compatible = "rockchip,rk3588-mipi-csi2-hw";
  reg = <0x0 0xfdd60000 0x0 0x10000>;
  reg-names = "csihost_regs";
  interrupts = <0 153 4>,
        <0 154 4>;
  interrupt-names = "csi-intr1", "csi-intr2";
  clocks = <&cru 468>;
  clock-names = "pclk_csi2host";
  resets = <&cru 809>;
  reset-names = "srst_csihost_p";
  status = "okay";
 };

 vop: vop@fdd90000 {
  compatible = "rockchip,rk3588-vop";
  reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>;
  reg-names = "regs", "gamma_lut";
  interrupts = <0 156 4>;
  clocks = <&cru 624>,
    <&cru 623>,
    <&cru 628>,
    <&cru 629>,
    <&cru 630>,
    <&cru 631>,
    <&cru 622>,
    <&cru 625>,
    <&cru 626>,
    <&cru 627>;
  clock-names = "aclk_vop",
         "hclk_vop",
         "dclk_vp0",
         "dclk_vp1",
         "dclk_vp2",
         "dclk_vp3",
         "pclk_vop",
         "dclk_src_vp0",
         "dclk_src_vp1",
         "dclk_src_vp2";
  assigned-clocks = <&cru 624>;
  assigned-clock-rates = <750000000>;
  resets = <&cru 841>,
    <&cru 840>,
    <&cru 845>,
    <&cru 848>,
    <&cru 849>,
    <&cru 850>;
  reset-names = "axi",
         "ahb",
         "dclk_vp0",
         "dclk_vp1",
         "dclk_vp2",
         "dclk_vp3";
  iommus = <&vop_mmu>;
  power-domains = <&power 24>;
  rockchip,grf = <&sys_grf>;
  rockchip,vop-grf = <&vop_grf>;
  rockchip,vo1-grf = <&vo1_grf>;
  rockchip,pmu = <&pmu>;

  status = "disabled";

  vop_out: ports {
   #address-cells = <1>;
   #size-cells = <0>;

   vp0: port@0 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <0>;

    vp0_out_dp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&dp0_in_vp0>;
    };

    vp0_out_edp0: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&edp0_in_vp0>;
    };

    vp0_out_hdmi0: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&hdmi0_in_vp0>;
    };
   };

   vp1: port@1 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <1>;

    vp1_out_dp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&dp0_in_vp1>;
    };

    vp1_out_edp0: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&edp0_in_vp1>;
    };

    vp1_out_hdmi0: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&hdmi0_in_vp1>;
    };
   };

   vp2: port@2 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <2>;

    assigned-clocks = <&cru 627>;
    assigned-clock-parents = <&cru 4>;

    vp2_out_dp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&dp0_in_vp2>;
    };

    vp2_out_edp0: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&edp0_in_vp2>;
    };

    vp2_out_hdmi0: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&hdmi0_in_vp2>;
    };

    vp2_out_dsi0: endpoint@3 {
     reg = <3>;
     remote-endpoint = <&dsi0_in_vp2>;
    };

    vp2_out_dsi1: endpoint@4 {
     reg = <4>;
     remote-endpoint = <&dsi1_in_vp2>;
    };
   };

   vp3: port@3 {
    #address-cells = <1>;
    #size-cells = <0>;
    reg = <3>;

    vp3_out_dsi0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&dsi0_in_vp3>;
    };

    vp3_out_dsi1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&dsi1_in_vp3>;
    };

    vp3_out_rgb: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&rgb_in_vp3>;
    };
   };
  };
 };

 vop_mmu: iommu@fdd97e00 {
  compatible = "rockchip,iommu-v2";
  reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>;
  interrupts = <0 156 4>;
  interrupt-names = "vop_mmu";
  clocks = <&cru 624>, <&cru 623>;
  clock-names = "aclk", "iface";
  #iommu-cells = <0>;
  rockchip,disable-device-link-resume;
  rockchip,shootdown-entire;
  status = "disabled";
 };

 spdif_tx2: spdif-tx@fddb0000 {
  compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
  reg = <0x0 0xfddb0000 0x0 0x1000>;
  interrupts = <0 195 4>;
  dmas = <&dmac1 6>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 521>, <&cru 516>;
  assigned-clocks = <&cru 517>;
  assigned-clock-parents = <&cru 5>;
  power-domains = <&power 25>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s4_8ch: i2s@fddc0000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddc0000 0x0 0x1000>;
  interrupts = <0 184 4>;
  clocks = <&cru 507>, <&cru 507>, <&cru 496>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 505>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac2 0>;
  dma-names = "tx";
  power-domains = <&power 25>;
  resets = <&cru 909>;
  reset-names = "tx-m";
  rockchip,playback-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_tx3: spdif-tx@fdde0000 {
  compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
  reg = <0x0 0xfdde0000 0x0 0x1000>;
  interrupts = <0 196 4>;
  dmas = <&dmac1 7>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 599>, <&cru 595>;
  assigned-clocks = <&cru 596>;
  assigned-clock-parents = <&cru 5>;
  power-domains = <&power 26>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s5_8ch: i2s@fddf0000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddf0000 0x0 0x1000>;
  interrupts = <0 185 4>;
  clocks = <&cru 582>, <&cru 582>, <&cru 584>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 579>;
  assigned-clock-parents = <&cru 7>;
  dmas = <&dmac2 2>;
  dma-names = "tx";
  power-domains = <&power 26>;
  resets = <&cru 1000>;
  reset-names = "tx-m";
  rockchip,always-on;
  rockchip,hdmi-path;
  rockchip,playback-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s9_8ch: i2s@fddfc000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddfc000 0x0 0x1000>;
  interrupts = <0 189 4>;
  clocks = <&cru 578>, <&cru 578>, <&cru 574>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 575>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac2 23>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 1043>;
  reset-names = "rx-m";
  rockchip,capture-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_rx0: spdif-rx@fde08000 {
  compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
  reg = <0x0 0xfde08000 0x0 0x1000>;
  interrupts = <0 199 4>;
  clocks = <&cru 606>, <&cru 605>;
  clock-names = "mclk", "hclk";
  assigned-clocks = <&cru 606>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac0 21>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 1021>;
  reset-names = "spdifrx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 dsi0: dsi@fde20000 {
  compatible = "rockchip,rk3588-mipi-dsi2";
  reg = <0x0 0xfde20000 0x0 0x10000>;
  interrupts = <0 167 4>;
  clocks = <&cru 632>, <&cru 634>;
  clock-names = "pclk", "sys_clk";
  resets = <&cru 852>;
  reset-names = "apb";
  power-domains = <&power 24>;
  phys = <&mipidcphy0>;
  phy-names = "dcphy";
  rockchip,grf = <&vop_grf>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   dsi0_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    dsi0_in_vp2: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp2_out_dsi0>;
     status = "disabled";
    };

    dsi0_in_vp3: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp3_out_dsi0>;
     status = "disabled";
    };
   };
  };
 };

 dsi1: dsi@fde30000 {
  compatible = "rockchip,rk3588-mipi-dsi2";
  reg = <0x0 0xfde30000 0x0 0x10000>;
  interrupts = <0 168 4>;
  clocks = <&cru 633>, <&cru 635>;
  clock-names = "pclk", "sys_clk";
  resets = <&cru 853>;
  reset-names = "apb";
  power-domains = <&power 24>;
  phys = <&mipidcphy1>;
  phy-names = "dcphy";
  rockchip,grf = <&vop_grf>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   dsi1_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    dsi1_in_vp2: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp2_out_dsi1>;
     status = "disabled";
    };

    dsi1_in_vp3: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp3_out_dsi1>;
     status = "disabled";
    };
   };
  };
 };

 hdcp0: hdcp@fde40000 {
  compatible = "rockchip,rk3588-hdcp";
  reg = <0x0 0xfde40000 0x0 0x80>;
  interrupts = <0 159 4>;
  clocks = <&cru 493>, <&cru 495>,
    <&cru 494>, <&cru 492>,
    <&cru 497>, <&cru 498>;
  clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
  resets = <&cru 895>, <&cru 893>,
    <&cru 892>, <&cru 891>,
    <&cru 897>;
  reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
  power-domains = <&power 25>;
  rockchip,vo-grf = <&vo0_grf>;
  status = "disabled";
 };

 dp0: dp@fde50000 {
  compatible = "rockchip,rk3588-dp";
  reg = <0x0 0xfde50000 0x0 0x4000>;
  interrupts = <0 161 4>;
  clocks = <&cru 486>, <&cru 716>,
    <&cru 507>, <&cru 519>,
    <&hclk_vo0>, <&cru 490>;
  clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp";
  assigned-clocks = <&cru 716>;
  assigned-clock-rates = <16000000>;
  resets = <&cru 904>;
  phys = <&usbdp_phy0_dp>;
  power-domains = <&power 25>;
  #sound-dai-cells = <1>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    dp0_in_vp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp0_out_dp0>;
     status = "disabled";
    };

    dp0_in_vp1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp1_out_dp0>;
     status = "disabled";
    };

    dp0_in_vp2: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&vp2_out_dp0>;
     status = "disabled";
    };
   };

   port@1 {
    reg = <1>;

    dp0_out: endpoint { };
   };
  };
 };

 hdcp1: hdcp@fde70000 {
  compatible = "rockchip,rk3588-hdcp";
  reg = <0x0 0xfde70000 0x0 0x80>;
  interrupts = <0 160 4>;
  clocks = <&cru 535>, <&cru 537>,
    <&cru 536>, <&cru 534>,
    <&cru 552>, <&cru 553>;
  clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng";
  resets = <&cru 968>, <&cru 966>,
    <&cru 965>, <&cru 964>,
    <&cru 970>;
  reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng";
  power-domains = <&power 26>;
  rockchip,vo-grf = <&vo1_grf>;
  status = "disabled";
 };

 hdmi0: hdmi@fde80000 {
  compatible = "rockchip,rk3588-dw-hdmi";
  reg = <0x0 0xfde80000 0x0 0x10000>, <0x0 0xfde90000 0x0 0x10000>;
  interrupts = <0 169 4>,
        <0 170 4>,
        <0 171 4>,
        <0 172 4>,
        <0 360 4>;
  clocks = <&cru 545>,
    <&cru 613>,
    <&cru 546>,
    <&cru 547>,
    <&cru 582>,
    <&cru 628>,
    <&cru 629>,
    <&cru 630>,
    <&cru 631>,
    <&hclk_vo1>,
    <&hdptxphy_hdmi_clk0>;
  clock-names = "pclk",
         "hpd",
         "earc",
         "hdmitx_ref",
         "aud",
         "dclk_vp0",
         "dclk_vp1",
         "dclk_vp2",
         "dclk_vp3",
         "hclk_vo1",
         "link_clk";
  resets = <&cru 976>, <&cru 1180>;
  reset-names = "ref", "hdp";
  power-domains = <&power 26>;
  pinctrl-names = "default";
  pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>;
  reg-io-width = <4>;
  rockchip,grf = <&sys_grf>;
  rockchip,vo1_grf = <&vo1_grf>;
  phys = <&hdptxphy_hdmi0>;
  phy-names = "hdmi";
  #sound-dai-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   hdmi0_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    hdmi0_in_vp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp0_out_hdmi0>;
     status = "disabled";
    };

    hdmi0_in_vp1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp1_out_hdmi0>;
     status = "disabled";
    };

    hdmi0_in_vp2: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&vp2_out_hdmi0>;
     status = "disabled";
    };
   };
  };
 };

 edp0: edp@fdec0000 {
  compatible = "rockchip,rk3588-edp";
  reg = <0x0 0xfdec0000 0x0 0x1000>;
  interrupts = <0 163 4>;
  clocks = <&cru 529>, <&cru 528>,
    <&cru 530>, <&hclk_vo1>;
  clock-names = "dp", "pclk", "spdif", "hclk";
  resets = <&cru 993>, <&cru 992>;
  reset-names = "dp", "apb";
  phys = <&hdptxphy0>;
  phy-names = "dp";
  power-domains = <&power 26>;
  rockchip,grf = <&vo1_grf>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    edp0_in_vp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp0_out_edp0>;
     status = "disabled";
    };

    edp0_in_vp1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp1_out_edp0>;
     status = "disabled";
    };

    edp0_in_vp2: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&vp2_out_edp0>;
     status = "disabled";
    };
   };

   port@1 {
    reg = <1>;

    edp0_out: endpoint { };
   };
  };
 };

 qos_gpu_m0: qos@fdf35000 {
  compatible = "syscon";
  reg = <0x0 0xfdf35000 0x0 0x20>;
 };

 qos_gpu_m1: qos@fdf35200 {
  compatible = "syscon";
  reg = <0x0 0xfdf35200 0x0 0x20>;
 };

 qos_gpu_m2: qos@fdf35400 {
  compatible = "syscon";
  reg = <0x0 0xfdf35400 0x0 0x20>;
 };

 qos_gpu_m3: qos@fdf35600 {
  compatible = "syscon";
  reg = <0x0 0xfdf35600 0x0 0x20>;
 };

 qos_rga3_1: qos@fdf36000 {
  compatible = "syscon";
  reg = <0x0 0xfdf36000 0x0 0x20>;
 };

 qos_sdio: qos@fdf39000 {
  compatible = "syscon";
  reg = <0x0 0xfdf39000 0x0 0x20>;
 };

 qos_sdmmc: qos@fdf3d800 {
  compatible = "syscon";
  reg = <0x0 0xfdf3d800 0x0 0x20>;
 };

 qos_usb3_1: qos@fdf3e000 {
  compatible = "syscon";
  reg = <0x0 0xfdf3e000 0x0 0x20>;
 };

 qos_usb3_0: qos@fdf3e200 {
  compatible = "syscon";
  reg = <0x0 0xfdf3e200 0x0 0x20>;
 };

 qos_usb2host_0: qos@fdf3e400 {
  compatible = "syscon";
  reg = <0x0 0xfdf3e400 0x0 0x20>;
 };

 qos_usb2host_1: qos@fdf3e600 {
  compatible = "syscon";
  reg = <0x0 0xfdf3e600 0x0 0x20>;
 };

 qos_fisheye0: qos@fdf40000 {
  compatible = "syscon";
  reg = <0x0 0xfdf40000 0x0 0x20>;
 };

 qos_fisheye1: qos@fdf40200 {
  compatible = "syscon";
  reg = <0x0 0xfdf40200 0x0 0x20>;
 };

 qos_isp0_mro: qos@fdf40400 {
  compatible = "syscon";
  reg = <0x0 0xfdf40400 0x0 0x20>;
 };

 qos_isp0_mwo: qos@fdf40500 {
  compatible = "syscon";
  reg = <0x0 0xfdf40500 0x0 0x20>;
 };

 qos_vicap_m0: qos@fdf40600 {
  compatible = "syscon";
  reg = <0x0 0xfdf40600 0x0 0x20>;
 };

 qos_vicap_m1: qos@fdf40800 {
  compatible = "syscon";
  reg = <0x0 0xfdf40800 0x0 0x20>;
 };

 qos_isp1_mwo: qos@fdf41000 {
  compatible = "syscon";
  reg = <0x0 0xfdf41000 0x0 0x20>;
 };

 qos_isp1_mro: qos@fdf41100 {
  compatible = "syscon";
  reg = <0x0 0xfdf41100 0x0 0x20>;
 };

 qos_rkvenc0_m0ro: qos@fdf60000 {
  compatible = "syscon";
  reg = <0x0 0xfdf60000 0x0 0x20>;
 };

 qos_rkvenc0_m1ro: qos@fdf60200 {
  compatible = "syscon";
  reg = <0x0 0xfdf60200 0x0 0x20>;
 };

 qos_rkvenc0_m2wo: qos@fdf60400 {
  compatible = "syscon";
  reg = <0x0 0xfdf60400 0x0 0x20>;
 };

 qos_rkvenc1_m0ro: qos@fdf61000 {
  compatible = "syscon";
  reg = <0x0 0xfdf61000 0x0 0x20>;
 };

 qos_rkvenc1_m1ro: qos@fdf61200 {
  compatible = "syscon";
  reg = <0x0 0xfdf61200 0x0 0x20>;
 };

 qos_rkvenc1_m2wo: qos@fdf61400 {
  compatible = "syscon";
  reg = <0x0 0xfdf61400 0x0 0x20>;
 };

 qos_rkvdec0: qos@fdf62000 {
  compatible = "syscon";
  reg = <0x0 0xfdf62000 0x0 0x20>;
 };

 qos_rkvdec1: qos@fdf63000 {
  compatible = "syscon";
  reg = <0x0 0xfdf63000 0x0 0x20>;
 };

 qos_av1: qos@fdf64000 {
  compatible = "syscon";
  reg = <0x0 0xfdf64000 0x0 0x20>;
 };

 qos_iep: qos@fdf66000 {
  compatible = "syscon";
  reg = <0x0 0xfdf66000 0x0 0x20>;
 };

 qos_jpeg_dec: qos@fdf66200 {
  compatible = "syscon";
  reg = <0x0 0xfdf66200 0x0 0x20>;
 };

 qos_jpeg_enc0: qos@fdf66400 {
  compatible = "syscon";
  reg = <0x0 0xfdf66400 0x0 0x20>;
 };

 qos_jpeg_enc1: qos@fdf66600 {
  compatible = "syscon";
  reg = <0x0 0xfdf66600 0x0 0x20>;
 };

 qos_jpeg_enc2: qos@fdf66800 {
  compatible = "syscon";
  reg = <0x0 0xfdf66800 0x0 0x20>;
 };

 qos_jpeg_enc3: qos@fdf66a00 {
  compatible = "syscon";
  reg = <0x0 0xfdf66a00 0x0 0x20>;
 };

 qos_rga2_mro: qos@fdf66c00 {
  compatible = "syscon";
  reg = <0x0 0xfdf66c00 0x0 0x20>;
 };

 qos_rga2_mwo: qos@fdf66e00 {
  compatible = "syscon";
  reg = <0x0 0xfdf66e00 0x0 0x20>;
 };

 qos_rga3_0: qos@fdf67000 {
  compatible = "syscon";
  reg = <0x0 0xfdf67000 0x0 0x20>;
 };

 qos_vdpu: qos@fdf67200 {
  compatible = "syscon";
  reg = <0x0 0xfdf67200 0x0 0x20>;
 };

 qos_npu1: qos@fdf70000 {
  compatible = "syscon";
  reg = <0x0 0xfdf70000 0x0 0x20>;
 };

 qos_npu2: qos@fdf71000 {
  compatible = "syscon";
  reg = <0x0 0xfdf71000 0x0 0x20>;
 };

 qos_npu0_mwr: qos@fdf72000 {
  compatible = "syscon";
  reg = <0x0 0xfdf72000 0x0 0x20>;
 };

 qos_npu0_mro: qos@fdf72200 {
  compatible = "syscon";
  reg = <0x0 0xfdf72200 0x0 0x20>;
 };

 qos_mcu_npu: qos@fdf72400 {
  compatible = "syscon";
  reg = <0x0 0xfdf72400 0x0 0x20>;
 };

 qos_hdcp0: qos@fdf80000 {
  compatible = "syscon";
  reg = <0x0 0xfdf80000 0x0 0x20>;
 };

 qos_hdcp1: qos@fdf81000 {
  compatible = "syscon";
  reg = <0x0 0xfdf81000 0x0 0x20>;
 };

 qos_hdmirx: qos@fdf81200 {
  compatible = "syscon";
  reg = <0x0 0xfdf81200 0x0 0x20>;
 };

 qos_vop_m0: qos@fdf82000 {
  compatible = "syscon";
  reg = <0x0 0xfdf82000 0x0 0x20>;
 };

 qos_vop_m1: qos@fdf82200 {
  compatible = "syscon";
  reg = <0x0 0xfdf82200 0x0 0x20>;
 };

 dfi: dfi@fe060000 {
  compatible = "rockchip,rk3588-dfi";
  reg = <0x00 0xfe060000 0x00 0x10000>;
  rockchip,pmu_grf = <&pmu1_grf>;
  status = "disabled";
 };

 pcie2x1l1: pcie@fe180000 {
  compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x30 0x3f>;
  clocks = <&cru 337>, <&cru 342>,
    <&cru 332>, <&cru 348>,
    <&cru 353>, <&cru 709>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 248 4>,
        <0 247 4>,
        <0 246 4>,
        <0 245 4>,
        <0 244 4>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
    <0 0 0 2 &pcie2x1l1_intc 1>,
    <0 0 0 3 &pcie2x1l1_intc 2>,
    <0 0 0 4 &pcie2x1l1_intc 3>;
  linux,pci-domain = <3>;
  num-ib-windows = <8>;
  num-ob-windows = <8>;
  num-viewport = <4>;
  max-link-speed = <2>;
  msi-map = <0x3000 &its0 0x3000 0x1000>;
  num-lanes = <1>;
  phys = <&combphy2_psu 2>;
  phy-names = "pcie-phy";
  ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000
     0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000
     0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000
     0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
  reg = <0x0 0xfe180000 0x0 0x10000>,
        <0xa 0x40c00000 0x0 0x400000>;
  reg-names = "pcie-apb", "pcie-dbi";
  resets = <&cru 528>, <&cru 543>;
  reset-names = "pcie", "periph";
  rockchip,pipe-grf = <&php_grf>;
  status = "disabled";

  pcie2x1l1_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 245 1>;
  };
 };

 pcie2x1l2: pcie@fe190000 {
  compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x40 0x4f>;
  clocks = <&cru 338>, <&cru 343>,
    <&cru 333>, <&cru 349>,
    <&cru 354>, <&cru 386>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 253 4>,
        <0 252 4>,
        <0 251 4>,
        <0 250 4>,
        <0 249 4>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
    <0 0 0 2 &pcie2x1l2_intc 1>,
    <0 0 0 3 &pcie2x1l2_intc 2>,
    <0 0 0 4 &pcie2x1l2_intc 3>;
  linux,pci-domain = <4>;
  num-ib-windows = <8>;
  num-ob-windows = <8>;
  num-viewport = <4>;
  max-link-speed = <2>;
  msi-map = <0x4000 &its0 0x4000 0x1000>;
  num-lanes = <1>;
  phys = <&combphy0_ps 2>;
  phy-names = "pcie-phy";
  ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000
     0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000
     0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000
     0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
  reg = <0x0 0xfe190000 0x0 0x10000>,
        <0xa 0x41000000 0x0 0x400000>;
  reg-names = "pcie-apb", "pcie-dbi";
  resets = <&cru 529>, <&cru 544>;
  reset-names = "pcie", "periph";
  rockchip,pipe-grf = <&php_grf>;
  status = "disabled";

  pcie2x1l2_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 250 1>;
  };
 };

 gmac_uio1: uio@fe1c0000 {
  compatible = "rockchip,uio-gmac";
  reg = <0x0 0xfe1c0000 0x0 0x10000>;
  rockchip,ethernet = <&gmac1>;
  status = "disabled";
 };

 gmac1: ethernet@fe1c0000 {
  compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe1c0000 0x0 0x10000>;
  interrupts = <0 234 4>,
        <0 233 4>;
  interrupt-names = "macirq", "eth_wake_irq";
  rockchip,grf = <&sys_grf>;
  rockchip,php_grf = <&php_grf>;
  clocks = <&cru 324>, <&cru 325>,
    <&cru 360>, <&cru 365>,
    <&cru 323>;
  clock-names = "stmmaceth", "clk_mac_ref",
         "pclk_mac", "aclk_mac",
         "ptp_ref";
  resets = <&cru 523>;
  reset-names = "stmmaceth";
  power-domains = <&power 33>;

  snps,mixed-burst;
  snps,tso;

  snps,axi-config = <&gmac1_stmmac_axi_setup>;
  snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
  status = "disabled";

  mdio1: mdio {
   compatible = "snps,dwmac-mdio";
   #address-cells = <0x1>;
   #size-cells = <0x0>;
  };

  gmac1_stmmac_axi_setup: stmmac-axi-config {
   snps,wr_osr_lmt = <4>;
   snps,rd_osr_lmt = <8>;
   snps,blen = <0 0 0 0 16 8 4>;
  };

  gmac1_mtl_rx_setup: rx-queues-config {
   snps,rx-queues-to-use = <1>;
   queue0 {};
  };

  gmac1_mtl_tx_setup: tx-queues-config {
   snps,tx-queues-to-use = <1>;
   queue0 {};
  };
 };

 sata0: sata@fe210000 {
  compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
  reg = <0 0xfe210000 0 0x1000>;
  clocks = <&cru 369>, <&cru 366>,
    <&cru 372>, <&cru 355>,
    <&cru 382>;
  clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  interrupts = <0 273 4>;
  interrupt-names = "hostc";
  phys = <&combphy0_ps 1>;
  phy-names = "sata-phy";
  ports-implemented = <0x1>;
  status = "disabled";
 };

 sata2: sata@fe230000 {
  compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
  reg = <0 0xfe230000 0 0x1000>;
  clocks = <&cru 371>, <&cru 368>,
    <&cru 374>, <&cru 357>,
    <&cru 384>;
  clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  interrupts = <0 275 4>;
  interrupt-names = "hostc";
  phys = <&combphy2_psu 1>;
  phy-names = "sata-phy";
  ports-implemented = <0x1>;
  status = "disabled";
 };

 sfc: spi@fe2b0000 {
  compatible = "rockchip,sfc";
  reg = <0x0 0xfe2b0000 0x0 0x4000>;
  interrupts = <0 206 4>;
  clocks = <&cru 317>, <&cru 318>;
  clock-names = "clk_sfc", "hclk_sfc";
  assigned-clocks = <&cru 317>;
  assigned-clock-rates = <100000000>;
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 sdmmc: mmc@fe2c0000 {
  compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe2c0000 0x0 0x4000>;
  interrupts = <0 203 4>;
  clocks = <&scmi_clk 23>, <&scmi_clk 9>,
    <&cru 706>, <&cru 707>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <200000000>;
  pinctrl-names = "default";
  pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
  power-domains = <&power 40>;
  status = "disabled";
 };

 sdio: mmc@fe2d0000 {
  compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
  reg = <0x0 0xfe2d0000 0x0 0x4000>;
  interrupts = <0 204 4>;
  clocks = <&cru 409>, <&cru 410>,
    <&cru 704>, <&cru 705>;
  clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
  fifo-depth = <0x100>;
  max-frequency = <200000000>;
  pinctrl-names = "default";
  pinctrl-0 = <&sdiom1_pins>;
  power-domains = <&power 37>;
  status = "disabled";
 };

 sdhci: mmc@fe2e0000 {
  compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci";
  reg = <0x0 0xfe2e0000 0x0 0x10000>;
  interrupts = <0 205 4>;
  assigned-clocks = <&cru 315>, <&cru 316>, <&cru 314>;
  assigned-clock-rates = <200000000>, <24000000>, <200000000>;
  clocks = <&cru 314>, <&cru 312>,
    <&cru 313>, <&cru 315>,
    <&cru 316>;
  clock-names = "core", "bus", "axi", "block", "timer";
  resets = <&cru 502>, <&cru 500>,
    <&cru 501>, <&cru 503>,
    <&cru 504>;
  reset-names = "core", "bus", "axi", "block", "timer";
  max-frequency = <200000000>;
  status = "disabled";
 };

 crypto: crypto@fe370000 {
  compatible = "rockchip,rk3588-crypto";
  reg = <0x0 0xfe370000 0x0 0x2000>;
  interrupts = <0 209 4>;
  clocks = <&scmi_clk 11>, <&scmi_clk 12>,
    <&scmi_clk 20>, <&scmi_clk 21>;
  clock-names = "aclk", "hclk", "sclk", "pka";
  resets = <&scmi_reset 15>;
  reset-names = "crypto-rst";
  status = "disabled";
 };

 rng: rng@fe378000 {
  compatible = "rockchip,trngv1";
  reg = <0x0 0xfe378000 0x0 0x200>;
  interrupts = <0 400 4>;
  clocks = <&scmi_clk 12>;
  clock-names = "hclk_trng";
  resets = <&scmi_reset 48>;
  reset-names = "reset";
  status = "disabled";
 };

 i2s0_8ch: i2s@fe470000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfe470000 0x0 0x1000>;
  interrupts = <0 180 4>;
  clocks = <&cru 51>, <&cru 55>, <&cru 48>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 49>, <&cru 53>;
  assigned-clock-parents = <&cru 5>, <&cru 5>;
  dmas = <&dmac0 0>, <&dmac0 1>;
  dma-names = "tx", "rx";
  power-domains = <&power 38>;
  resets = <&cru 119>, <&cru 122>;
  reset-names = "tx-m", "rx-m";
  rockchip,clk-trcm = <1>;
  pinctrl-names = "default", "idle", "clk";
  pinctrl-0 = <&i2s0_sdi0
        &i2s0_sdi1
        &i2s0_sdi2
        &i2s0_sdi3
        &i2s0_sdo0
        &i2s0_sdo1>;
  pinctrl-1 = <&i2s0_idle>;
  pinctrl-2 = <&i2s0_lrck
        &i2s0_sclk>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s1_8ch: i2s@fe480000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfe480000 0x0 0x1000>;
  interrupts = <0 181 4>;
  clocks = <&cru 652>, <&cru 656>, <&cru 648>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  dmas = <&dmac0 2>, <&dmac0 3>;
  dma-names = "tx", "rx";
  resets = <&cru 786474>, <&cru 786477>;
  reset-names = "tx-m", "rx-m";
  rockchip,clk-trcm = <1>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2s1m0_lrck
        &i2s1m0_sclk
        &i2s1m0_sdi0
        &i2s1m0_sdi1
        &i2s1m0_sdi2
        &i2s1m0_sdi3
        &i2s1m0_sdo0
        &i2s1m0_sdo1
        &i2s1m0_sdo2
        &i2s1m0_sdo3>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s2_2ch: i2s@fe490000 {
  compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xfe490000 0x0 0x1000>;
  interrupts = <0 182 4>;
  clocks = <&cru 39>, <&cru 34>;
  clock-names = "i2s_clk", "i2s_hclk";
  assigned-clocks = <&cru 36>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac1 0>, <&dmac1 1>;
  dma-names = "tx", "rx";
  power-domains = <&power 38>;
  rockchip,clk-trcm = <1>;
  pinctrl-names = "default", "idle", "clk";
  pinctrl-0 = <&i2s2m1_sdi
        &i2s2m1_sdo>;
  pinctrl-1 = <&i2s2m1_idle>;
  pinctrl-2 = <&i2s2m1_lrck
        &i2s2m1_sclk>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s3_2ch: i2s@fe4a0000 {
  compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
  reg = <0x0 0xfe4a0000 0x0 0x1000>;
  interrupts = <0 183 4>;
  clocks = <&cru 45>, <&cru 35>;
  clock-names = "i2s_clk", "i2s_hclk";
  assigned-clocks = <&cru 42>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac1 2>, <&dmac1 3>;
  dma-names = "tx", "rx";
  power-domains = <&power 38>;
  rockchip,clk-trcm = <1>;
  pinctrl-names = "default", "idle", "clk";
  pinctrl-0 = <&i2s3_sdi
        &i2s3_sdo>;
  pinctrl-1 = <&i2s3_idle>;
  pinctrl-2 = <&i2s3_lrck
        &i2s3_sclk>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 pdm0: pdm@fe4b0000 {
  compatible = "rockchip,rk3588-pdm";
  reg = <0x0 0xfe4b0000 0x0 0x1000>;
  clocks = <&cru 671>, <&cru 670>;
  clock-names = "pdm_clk", "pdm_hclk";
  dmas = <&dmac0 4>;
  dma-names = "rx";
  pinctrl-names = "default", "idle", "clk";
  pinctrl-0 = <&pdm0m0_sdi0
        &pdm0m0_sdi1
        &pdm0m0_sdi2
        &pdm0m0_sdi3>;
  pinctrl-1 = <&pdm0m0_idle>;
  pinctrl-2 = <&pdm0m0_clk
        &pdm0m0_clk1>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 pdm1: pdm@fe4c0000 {
  compatible = "rockchip,rk3588-pdm";
  reg = <0x0 0xfe4c0000 0x0 0x1000>;
  clocks = <&cru 59>, <&cru 58>;
  clock-names = "pdm_clk", "pdm_hclk";
  assigned-clocks = <&cru 59>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac1 4>;
  dma-names = "rx";
  power-domains = <&power 38>;
  pinctrl-names = "default", "idle", "clk";
  pinctrl-0 = <&pdm1m0_sdi0
        &pdm1m0_sdi1
        &pdm1m0_sdi2
        &pdm1m0_sdi3>;
  pinctrl-1 = <&pdm1m0_idle>;
  pinctrl-2 = <&pdm1m0_clk
        &pdm1m0_clk1>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 vad: vad@fe4d0000 {
  compatible = "rockchip,rk3588-vad";
  reg = <0x0 0xfe4d0000 0x0 0x1000>;
  reg-names = "vad";
  clocks = <&cru 672>;
  clock-names = "hclk";
  interrupts = <0 202 4>;
  rockchip,audio-src = <0>;
  rockchip,det-channel = <0>;
  rockchip,mode = <0>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_tx0: spdif-tx@fe4e0000 {
  compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
  reg = <0x0 0xfe4e0000 0x0 0x1000>;
  interrupts = <0 193 4>;
  dmas = <&dmac0 5>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 65>, <&cru 62>;
  assigned-clocks = <&cru 63>;
  assigned-clock-parents = <&cru 5>;
  power-domains = <&power 38>;
  pinctrl-names = "default";
  pinctrl-0 = <&spdif0m0_tx>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_tx1: spdif-tx@fe4f0000 {
  compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
  reg = <0x0 0xfe4f0000 0x0 0x1000>;
  interrupts = <0 194 4>;
  dmas = <&dmac1 5>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 71>, <&cru 68>;
  assigned-clocks = <&cru 69>;
  assigned-clock-parents = <&cru 5>;
  power-domains = <&power 38>;
  pinctrl-names = "default";
  pinctrl-0 = <&spdif1m0_tx>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 acdcdig_dsm: codec-digital@fe500000 {
  compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1";
  reg = <0x0 0xfe500000 0x0 0x1000>;
  clocks = <&cru 41>, <&cru 47>;
  clock-names = "dac", "pclk";
  power-domains = <&power 38>;
  resets = <&cru 132>;
  reset-names = "reset" ;
  rockchip,grf = <&sys_grf>;
  rockchip,pwm-output-mode;
  pinctrl-names = "default";
  pinctrl-0 = <&auddsm_pins>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 hwlock: hwspinlock@fe5a0000 {
  compatible = "rockchip,hwspinlock";
  reg = <0 0xfe5a0000 0 0x100>;
  #hwlock-cells = <1>;
 };

 gic: interrupt-controller@fe600000 {
  compatible = "arm,gic-v3";
  #interrupt-cells = <3>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  interrupt-controller;

  reg = <0x0 0xfe600000 0 0x10000>,
        <0x0 0xfe680000 0 0x100000>;
  interrupts = <1 9 4>;
  its0: msi-controller@fe640000 {
   compatible = "arm,gic-v3-its";
   msi-controller;
   #msi-cells = <1>;
   reg = <0x0 0xfe640000 0x0 0x20000>;
  };
  its1: msi-controller@fe660000 {
   compatible = "arm,gic-v3-its";
   msi-controller;
   #msi-cells = <1>;
   reg = <0x0 0xfe660000 0x0 0x20000>;
  };
 };

 dmac0: dma-controller@fea10000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfea10000 0x0 0x4000>;
  interrupts = <0 86 4>,
        <0 87 4>;
  clocks = <&cru 120>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
  arm,pl330-periph-burst;
 };

 dmac1: dma-controller@fea30000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfea30000 0x0 0x4000>;
  interrupts = <0 88 4>,
        <0 89 4>;
  clocks = <&cru 121>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
  arm,pl330-periph-burst;
 };

 can0: can@fea50000 {
  compatible = "rockchip,can-2.0";
  reg = <0x0 0xfea50000 0x0 0x1000>;
  interrupts = <0 341 4>;
  clocks = <&cru 112>, <&cru 111>;
  clock-names = "baudclk", "apb_pclk";
  resets = <&cru 185>, <&cru 184>;
  reset-names = "can", "can-apb";
  pinctrl-names = "default";
  pinctrl-0 = <&can0m0_pins>;
  tx-fifo-depth = <1>;
  rx-fifo-depth = <6>;
  status = "disabled";
 };

 can1: can@fea60000 {
  compatible = "rockchip,can-2.0";
  reg = <0x0 0xfea60000 0x0 0x1000>;
  interrupts = <0 342 4>;
  clocks = <&cru 114>, <&cru 113>;
  clock-names = "baudclk", "apb_pclk";
  resets = <&cru 187>, <&cru 186>;
  reset-names = "can", "can-apb";
  pinctrl-names = "default";
  pinctrl-0 = <&can1m0_pins>;
  tx-fifo-depth = <1>;
  rx-fifo-depth = <6>;
  status = "disabled";
 };

 can2: can@fea70000 {
  compatible = "rockchip,can-2.0";
  reg = <0x0 0xfea70000 0x0 0x1000>;
  interrupts = <0 343 4>;
  clocks = <&cru 116>, <&cru 115>;
  clock-names = "baudclk", "apb_pclk";
  resets = <&cru 189>, <&cru 188>;
  reset-names = "can", "can-apb";
  pinctrl-names = "default";
  pinctrl-0 = <&can2m0_pins>;
  tx-fifo-depth = <1>;
  rx-fifo-depth = <6>;
  status = "disabled";
 };

 hw_decompress: decompress@fea80000 {
  compatible = "rockchip,hw-decompress";
  reg = <0x0 0xfea80000 0x0 0x1000>;
  interrupts = <0 85 4>;
  clocks = <&cru 117>, <&cru 119>, <&cru 118>;
  clock-names = "aclk", "dclk", "pclk";
  resets = <&cru 280>;
  reset-names = "dresetn";
  status = "disabled";
 };

 i2c1: i2c@fea90000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfea90000 0x0 0x1000>;
  clocks = <&cru 141>, <&cru 133>;
  clock-names = "i2c", "pclk";
  interrupts = <0 318 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c1m0_xfer>;
  resets = <&cru 176>, <&cru 168>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c2: i2c@feaa0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeaa0000 0x0 0x1000>;
  clocks = <&cru 142>, <&cru 134>;
  clock-names = "i2c", "pclk";
  interrupts = <0 319 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c2m0_xfer>;
  resets = <&cru 177>, <&cru 169>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c3: i2c@feab0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeab0000 0x0 0x1000>;
  clocks = <&cru 143>, <&cru 135>;
  clock-names = "i2c", "pclk";
  interrupts = <0 320 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c3m0_xfer>;
  resets = <&cru 178>, <&cru 170>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c4: i2c@feac0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeac0000 0x0 0x1000>;
  clocks = <&cru 144>, <&cru 136>;
  clock-names = "i2c", "pclk";
  interrupts = <0 321 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c4m0_xfer>;
  resets = <&cru 179>, <&cru 171>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c5: i2c@fead0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfead0000 0x0 0x1000>;
  clocks = <&cru 145>, <&cru 137>;
  clock-names = "i2c", "pclk";
  interrupts = <0 322 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c5m0_xfer>;
  resets = <&cru 180>, <&cru 172>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 rktimer: timer@feae0000 {
  compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
  reg = <0x0 0xfeae0000 0x0 0x20>;
  interrupts = <0 289 4>;
  clocks = <&cru 92>, <&cru 95>;
  clock-names = "pclk", "timer";
 };

 wdt: watchdog@feaf0000 {
  compatible = "snps,dw-wdt";
  reg = <0x0 0xfeaf0000 0x0 0x100>;
  clocks = <&cru 108>, <&cru 107>;
  clock-names = "tclk", "pclk";
  interrupts = <0 315 4>;
  status = "disabled";
 };

 spi0: spi@feb00000 {
  compatible = "rockchip,rk3066-spi";
  reg = <0x0 0xfeb00000 0x0 0x1000>;
  interrupts = <0 326 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clocks = <&cru 163>, <&cru 158>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 14>, <&dmac0 15>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
  num-cs = <2>;
  status = "disabled";
 };

 spi1: spi@feb10000 {
  compatible = "rockchip,rk3066-spi";
  reg = <0x0 0xfeb10000 0x0 0x1000>;
  interrupts = <0 327 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clocks = <&cru 164>, <&cru 159>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac0 16>, <&dmac0 17>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
  num-cs = <2>;
  status = "disabled";
 };

 spi2: spi@feb20000 {
  compatible = "rockchip,rk3066-spi";
  reg = <0x0 0xfeb20000 0x0 0x1000>;
  interrupts = <0 328 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clocks = <&cru 165>, <&cru 160>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac1 15>, <&dmac1 16>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
  num-cs = <2>;
  status = "disabled";
 };

 spi3: spi@feb30000 {
  compatible = "rockchip,rk3066-spi";
  reg = <0x0 0xfeb30000 0x0 0x1000>;
  interrupts = <0 329 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clocks = <&cru 166>, <&cru 161>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac1 17>, <&dmac1 18>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
  num-cs = <2>;
  status = "disabled";
 };

 uart1: serial@feb40000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb40000 0x0 0x100>;
  interrupts = <0 332 4>;
  clocks = <&cru 183>, <&cru 171>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac0 8>, <&dmac0 9>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart1m1_xfer>;
  status = "disabled";
 };

 uart2: serial@feb50000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb50000 0x0 0x100>;
  interrupts = <0 333 4>;
  clocks = <&cru 187>, <&cru 172>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac0 10>, <&dmac0 11>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart2m1_xfer>;
  status = "disabled";
 };

 uart3: serial@feb60000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb60000 0x0 0x100>;
  interrupts = <0 334 4>;
  clocks = <&cru 191>, <&cru 173>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac0 12>, <&dmac0 13>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart3m1_xfer>;
  status = "disabled";
 };

 uart4: serial@feb70000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb70000 0x0 0x100>;
  interrupts = <0 335 4>;
  clocks = <&cru 195>, <&cru 174>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac1 9>, <&dmac1 10>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart4m1_xfer>;
  status = "disabled";
 };

 uart5: serial@feb80000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb80000 0x0 0x100>;
  interrupts = <0 336 4>;
  clocks = <&cru 199>, <&cru 175>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac1 11>, <&dmac1 12>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart5m1_xfer>;
  status = "disabled";
 };

 uart6: serial@feb90000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeb90000 0x0 0x100>;
  interrupts = <0 337 4>;
  clocks = <&cru 203>, <&cru 176>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac1 13>, <&dmac1 14>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart6m1_xfer>;
  status = "disabled";
 };

 uart7: serial@feba0000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfeba0000 0x0 0x100>;
  interrupts = <0 338 4>;
  clocks = <&cru 207>, <&cru 177>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac2 7>, <&dmac2 8>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart7m1_xfer>;
  status = "disabled";
 };

 uart8: serial@febb0000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfebb0000 0x0 0x100>;
  interrupts = <0 339 4>;
  clocks = <&cru 211>, <&cru 178>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac2 9>, <&dmac2 10>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart8m1_xfer>;
  status = "disabled";
 };

 uart9: serial@febc0000 {
  compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
  reg = <0x0 0xfebc0000 0x0 0x100>;
  interrupts = <0 340 4>;
  clocks = <&cru 215>, <&cru 179>;
  clock-names = "baudclk", "apb_pclk";
  reg-shift = <2>;
  reg-io-width = <4>;
  dmas = <&dmac2 11>, <&dmac2 12>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart9m1_xfer>;
  status = "disabled";
 };

 pwm4: pwm@febd0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0000 0x0 0x10>;
  interrupts = <0 346 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm4m0_pins>;
  clocks = <&cru 84>, <&cru 83>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm5: pwm@febd0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0010 0x0 0x10>;
  interrupts = <0 346 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm5m0_pins>;
  clocks = <&cru 84>, <&cru 83>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm6: pwm@febd0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0020 0x0 0x10>;
  interrupts = <0 346 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm6m0_pins>;
  clocks = <&cru 84>, <&cru 83>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm7: pwm@febd0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebd0030 0x0 0x10>;
  interrupts = <0 346 4>,
        <0 347 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm7m0_pins>;
  clocks = <&cru 84>, <&cru 83>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm8: pwm@febe0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0000 0x0 0x10>;
  interrupts = <0 348 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm8m0_pins>;
  clocks = <&cru 87>, <&cru 86>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm9: pwm@febe0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0010 0x0 0x10>;
  interrupts = <0 348 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm9m0_pins>;
  clocks = <&cru 87>, <&cru 86>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm10: pwm@febe0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0020 0x0 0x10>;
  interrupts = <0 348 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm10m0_pins>;
  clocks = <&cru 87>, <&cru 86>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm11: pwm@febe0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebe0030 0x0 0x10>;
  interrupts = <0 348 4>,
        <0 349 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm11m0_pins>;
  clocks = <&cru 87>, <&cru 86>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm12: pwm@febf0000 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0000 0x0 0x10>;
  interrupts = <0 350 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm12m0_pins>;
  clocks = <&cru 90>, <&cru 89>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm13: pwm@febf0010 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0010 0x0 0x10>;
  interrupts = <0 350 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm13m0_pins>;
  clocks = <&cru 90>, <&cru 89>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm14: pwm@febf0020 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0020 0x0 0x10>;
  interrupts = <0 350 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm14m0_pins>;
  clocks = <&cru 90>, <&cru 89>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 pwm15: pwm@febf0030 {
  compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
  reg = <0x0 0xfebf0030 0x0 0x10>;
  interrupts = <0 350 4>,
        <0 351 4>;
  #pwm-cells = <3>;
  pinctrl-names = "active";
  pinctrl-0 = <&pwm15m0_pins>;
  clocks = <&cru 90>, <&cru 89>;
  clock-names = "pwm", "pclk";
  status = "disabled";
 };

 tsadc: tsadc@fec00000 {
  compatible = "rockchip,rk3588-tsadc";
  reg = <0x0 0xfec00000 0x0 0x400>;
  interrupts = <0 397 4>;
  clocks = <&cru 170>, <&cru 169>;
  clock-names = "tsadc", "apb_pclk";
  assigned-clocks = <&cru 170>;
  assigned-clock-rates = <2000000>;
  resets = <&cru 193>, <&cru 192>;
  reset-names = "tsadc", "tsadc-apb";
  #thermal-sensor-cells = <1>;
  rockchip,hw-tshut-temp = <120000>;
  rockchip,hw-tshut-mode = <0>;
  rockchip,hw-tshut-polarity = <0>;
  pinctrl-names = "gpio", "otpout";
  pinctrl-0 = <&tsadc_gpio_func>;
  pinctrl-1 = <&tsadc_shut>;
  status = "disabled";
 };

 saradc: saradc@fec10000 {
  compatible = "rockchip,rk3588-saradc";
  reg = <0x0 0xfec10000 0x0 0x10000>;
  interrupts = <0 398 4>;
  #io-channel-cells = <1>;
  clocks = <&cru 157>, <&cru 156>;
  clock-names = "saradc", "apb_pclk";
  resets = <&cru 190>;
  reset-names = "saradc-apb";
  status = "disabled";
 };

 mailbox0: mailbox@fec60000 {
  compatible = "rockchip,rk3588-mailbox",
        "rockchip,rk3368-mailbox";
  reg = <0x0 0xfec60000 0x0 0x200>;
  interrupts = <0 61 4>,
        <0 62 4>,
        <0 63 4>,
        <0 64 4>;
  clocks = <&cru 76>;
  clock-names = "pclk_mailbox";
  #mbox-cells = <1>;
  status = "disabled";
 };

 mailbox1: mailbox@fec70000 {
  compatible = "rockchip,rk3588-mailbox",
        "rockchip,rk3368-mailbox";
  reg = <0x0 0xfec70000 0x0 0x200>;
  interrupts = <0 69 4>,
        <0 70 4>,
        <0 71 4>,
        <0 72 4>;
  clocks = <&cru 77>;
  clock-names = "pclk_mailbox";
  #mbox-cells = <1>;
  status = "disabled";
 };

 i2c6: i2c@fec80000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfec80000 0x0 0x1000>;
  clocks = <&cru 146>, <&cru 138>;
  clock-names = "i2c", "pclk";
  interrupts = <0 323 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c6m0_xfer>;
  resets = <&cru 181>, <&cru 173>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c7: i2c@fec90000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfec90000 0x0 0x1000>;
  clocks = <&cru 147>, <&cru 139>;
  clock-names = "i2c", "pclk";
  interrupts = <0 324 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c7m0_xfer>;
  resets = <&cru 182>, <&cru 174>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 i2c8: i2c@feca0000 {
  compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
  reg = <0x0 0xfeca0000 0x0 0x1000>;
  clocks = <&cru 148>, <&cru 140>;
  clock-names = "i2c", "pclk";
  interrupts = <0 325 4>;
  pinctrl-names = "default";
  pinctrl-0 = <&i2c8m0_xfer>;
  resets = <&cru 183>, <&cru 175>;
  reset-names = "i2c", "apb";
  #address-cells = <1>;
  #size-cells = <0>;
  status = "disabled";
 };

 spi4: spi@fecb0000 {
  compatible = "rockchip,rk3066-spi";
  reg = <0x0 0xfecb0000 0x0 0x1000>;
  interrupts = <0 330 4>;
  #address-cells = <1>;
  #size-cells = <0>;
  clocks = <&cru 167>, <&cru 162>;
  clock-names = "spiclk", "apb_pclk";
  dmas = <&dmac2 13>, <&dmac2 14>;
  dma-names = "tx", "rx";
  pinctrl-names = "default";
  pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
  num-cs = <2>;
  status = "disabled";
 };

 otp: otp@fecc0000 {
  compatible = "rockchip,rk3588-otp";
  reg = <0x0 0xfecc0000 0x0 0x400>;
  #address-cells = <1>;
  #size-cells = <1>;
  clocks = <&cru 150>, <&cru 149>,
    <&cru 151>, <&cru 153>;
  clock-names = "otpc", "apb", "arb", "phy";
  resets = <&cru 298>, <&cru 297>,
    <&cru 299>;
  reset-names = "otpc", "apb", "arb";


  cpu_code: cpu-code@2 {
   reg = <0x02 0x2>;
  };
  package_serial_number_high: package-serial-number-high@5 {
   reg = <0x05 0x1>;
   bits = <0 1>;
  };
  package_serial_number_low: package-serial-number-low@6 {
   reg = <0x06 0x1>;
   bits = <5 3>;
  };
  specification_serial_number: specification-serial-number@6 {
   reg = <0x06 0x1>;
   bits = <0 5>;
  };
  otp_id: id@7 {
   reg = <0x07 0x10>;
  };
  otp_cpu_version: cpu-version@1c {
   reg = <0x1c 0x1>;
   bits = <3 3>;
  };
  cpub0_leakage: cpub0-leakage@17 {
   reg = <0x17 0x1>;
  };
  cpub1_leakage: cpub1-leakage@18 {
   reg = <0x18 0x1>;
  };
  cpul_leakage: cpul-leakage@19 {
   reg = <0x19 0x1>;
  };
  log_leakage: log-leakage@1a {
   reg = <0x1a 0x1>;
  };
  gpu_leakage: gpu-leakage@1b {
   reg = <0x1b 0x1>;
  };
  npu_leakage: npu-leakage@28 {
   reg = <0x28 0x1>;
  };
  codec_leakage: codec-leakage@29 {
   reg = <0x29 0x1>;
  };
  cpul_opp_info: cpul-opp-info@3d {
   reg = <0x3d 0x6>;
  };
  cpub01_opp_info: cpub01-opp-info@43 {
   reg = <0x43 0x6>;
  };
  cpub23_opp_info: cpub23-opp-info@49 {
   reg = <0x49 0x6>;
  };
  gpu_opp_info: gpu-opp-info@4f {
   reg = <0x4f 0x6>;
  };
  npu_opp_info: npu-opp-info@55 {
   reg = <0x55 0x6>;
  };
  dmc_opp_info: dmc-opp-info@5b {
   reg = <0x5b 0x6>;
  };
  vop_opp_info: vop-opp-info@61 {
   reg = <0x61 0x6>;
  };
  venc_opp_info: venc-opp-info@67 {
   reg = <0x67 0x6>;
  };
 };

 mailbox2: mailbox@fece0000 {
  compatible = "rockchip,rk3588-mailbox",
        "rockchip,rk3368-mailbox";
  reg = <0x0 0xfece0000 0x0 0x200>;
  interrupts = <0 77 4>,
        <0 78 4>,
        <0 79 4>,
        <0 80 4>;
  clocks = <&cru 78>;
  clock-names = "pclk_mailbox";
  #mbox-cells = <1>;
  status = "disabled";
 };

 dmac2: dma-controller@fed10000 {
  compatible = "arm,pl330", "arm,primecell";
  reg = <0x0 0xfed10000 0x0 0x4000>;
  interrupts = <0 90 4>,
        <0 91 4>;
  clocks = <&cru 122>;
  clock-names = "apb_pclk";
  #dma-cells = <1>;
  arm,pl330-periph-burst;
 };

 hdptxphy0: phy@fed60000 {
  compatible = "rockchip,rk3588-hdptx-phy";
  reg = <0x0 0xfed60000 0x0 0x2000>;
  clocks = <&cru 693>, <&cru 615>;
  clock-names = "ref", "apb";
  resets = <&cru 1157>, <&cru 786491>,
    <&cru 786492>, <&cru 786493>;
  reset-names = "apb", "init", "cmn", "lane";
  rockchip,grf = <&hdptxphy0_grf>;
  #phy-cells = <0>;
  status = "disabled";
 };

 hdptxphy_hdmi0: hdmiphy@fed60000 {
  compatible = "rockchip,rk3588-hdptx-phy-hdmi";
  reg = <0x0 0xfed60000 0x0 0x2000>;
  clocks = <&cru 693>, <&cru 615>;
  clock-names = "ref", "apb";
  resets = <&cru 1166>, <&cru 1157>,
    <&cru 786491>, <&cru 786492>,
    <&cru 786493>, <&cru 1164>,
    <&cru 1165>;
  reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
         "lcpll";
  rockchip,grf = <&hdptxphy0_grf>;
  #phy-cells = <0>;
  status = "disabled";

  hdptxphy_hdmi_clk0: clk-port {
   #clock-cells = <0>;
   status = "okay";
  };
 };

  hdptxphy_hdmi1: hdmiphy@fed70000 {
        compatible = "rockchip,rk3588-hdptx-phy-hdmi";
        reg = <0x0 0xfed70000 0x0 0x2000>;
        clocks = <&cru 693>, <&cru 616>;
        clock-names = "ref", "apb";
        resets = <&cru 1169>, <&cru 1158>,
             <&cru 786495>, <&cru 786496>,
             <&cru 786497>, <&cru 1167>,
             <&cru 1168>;
        reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
                  "lcpll";
        rockchip,grf = <&hdptxphy1_grf>;
        #phy-cells = <0>;
        status = "disabled";

        hdptxphy_hdmi_clk1: clk-port {
            #clock-cells = <0>;
            status = "okay";
        };
    };

    hdptxphy1_grf: syscon@fd5e4000 {
        compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
        reg = <0x0 0xfd5e4000 0x0 0x100>;
    };

 usbdp_phy0: phy@fed80000 {
  compatible = "rockchip,rk3588-usbdp-phy";
  reg = <0x0 0xfed80000 0x0 0x10000>;
  rockchip,u2phy-grf = <&usb2phy0_grf>;
  rockchip,usb-grf = <&usb_grf>;
  rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
  rockchip,vo-grf = <&vo0_grf>;
  clocks = <&cru 694>,
    <&cru 639>,
    <&cru 617>,
    <&u2phy0>;
  clock-names = "refclk", "immortal", "pclk", "utmi";
  resets = <&cru 40>,
    <&cru 41>,
    <&cru 42>,
    <&cru 43>,
    <&cru 1154>;
  reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
  status = "disabled";

  usbdp_phy0_dp: dp-port {
   #phy-cells = <0>;
   status = "disabled";
  };

  usbdp_phy0_u3: u3-port {
   #phy-cells = <0>;
   status = "disabled";
  };
 };

 mipidcphy0: phy@feda0000 {
  compatible = "rockchip,rk3588-mipi-dcphy";
  reg = <0x0 0xfeda0000 0x0 0x10000>;
  rockchip,grf = <&mipidcphy0_grf>;
  clocks = <&cru 264>,
    <&cru 694>;
  clock-names = "pclk", "ref";
  resets = <&cru 786499>,
    <&cru 62>,
    <&cru 63>,
    <&cru 786500>;
  reset-names = "m_phy", "apb", "grf", "s_phy";
  #phy-cells = <0>;
  status = "okay";
 };

 mipidcphy1: phy@fedb0000 {
  compatible = "rockchip,rk3588-mipi-dcphy";
  reg = <0x0 0xfedb0000 0x0 0x10000>;
  rockchip,grf = <&mipidcphy1_grf>;
  clocks = <&cru 265>,
    <&cru 694>;
  clock-names = "pclk", "ref";
  resets = <&cru 786501>,
    <&cru 67>,
    <&cru 68>,
    <&cru 786502>;
  reset-names = "m_phy", "apb", "grf", "s_phy";
  #phy-cells = <0>;
  status = "okay";
 };

 csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 {
  compatible = "rockchip,rk3588-csi2-dphy-hw";
  reg = <0x0 0xfedc0000 0x0 0x8000>;
  clocks = <&cru 268>;
  clock-names = "pclk";
  resets = <&cru 23>, <&cru 22>;
  reset-names = "srst_csiphy0", "srst_p_csiphy0";
  rockchip,grf = <&mipidphy0_grf>;
  rockchip,sys_grf = <&sys_grf>;
  status = "okay";
 };

 csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 {
  compatible = "rockchip,rk3588-csi2-dphy-hw";
  reg = <0x0 0xfedc8000 0x0 0x8000>;
  clocks = <&cru 269>;
  clock-names = "pclk";
  resets = <&cru 25>, <&cru 24>;
  reset-names = "srst_csiphy1", "srst_p_csiphy1";
  rockchip,grf = <&mipidphy1_grf>;
  rockchip,sys_grf = <&sys_grf>;
  status = "okay";
 };

 combphy0_ps: phy@fee00000 {
  compatible = "rockchip,rk3588-naneng-combphy";
  reg = <0x0 0xfee00000 0x0 0x100>;
  #phy-cells = <1>;
  clocks = <&cru 701>, <&cru 389>,
    <&cru 358>;
  clock-names = "refclk", "apbclk", "phpclk";
  assigned-clocks = <&cru 701>;
  assigned-clock-rates = <100000000>;
  resets = <&cru 131077>, <&cru 1238>;
  reset-names = "combphy-apb", "combphy";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
  status = "disabled";
 };

 combphy2_psu: phy@fee20000 {
  compatible = "rockchip,rk3588-naneng-combphy";
  reg = <0x0 0xfee20000 0x0 0x100>;
  #phy-cells = <1>;
  clocks = <&cru 703>, <&cru 391>,
    <&cru 358>;
  clock-names = "refclk", "apbclk", "phpclk";
  assigned-clocks = <&cru 703>;
  assigned-clock-rates = <100000000>;
  resets = <&cru 131079>, <&cru 1240>;
  reset-names = "combphy-apb", "combphy";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
  rockchip,pcie1ln-sel-bits = <0x100 1 1 0>;
  status = "disabled";
 };

 syssram: sram@ff001000 {
  compatible = "mmio-sram";
  reg = <0x0 0xff001000 0x0 0xef000>;

  #address-cells = <1>;
  #size-cells = <1>;
  ranges = <0x0 0x0 0xff001000 0xef000>;

  rkvdec0_sram: rkvdec-sram@0 {
   reg = <0x0 0x78000>;
  };
  rkvdec1_sram: rkvdec-sram@78000 {
   reg = <0x78000 0x77000>;
  };
 };

 pinctrl: pinctrl {
  compatible = "rockchip,rk3588-pinctrl";
  rockchip,grf = <&ioc>;
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  gpio0: gpio@fd8a0000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfd8a0000 0x0 0x100>;
   interrupts = <0 277 4>;
   clocks = <&cru 644>, <&cru 645>;

   gpio-controller;
   #gpio-cells = <2>;
   gpio-ranges = <&pinctrl 0 0 32>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio1: gpio@fec20000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec20000 0x0 0x100>;
   interrupts = <0 278 4>;
   clocks = <&cru 125>, <&cru 126>;

   gpio-controller;
   #gpio-cells = <2>;
   gpio-ranges = <&pinctrl 0 32 32>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio2: gpio@fec30000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec30000 0x0 0x100>;
   interrupts = <0 279 4>;
   clocks = <&cru 127>, <&cru 128>;

   gpio-controller;
   #gpio-cells = <2>;
   gpio-ranges = <&pinctrl 0 64 32>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio3: gpio@fec40000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec40000 0x0 0x100>;
   interrupts = <0 280 4>;
   clocks = <&cru 129>, <&cru 130>;

   gpio-controller;
   #gpio-cells = <2>;
   gpio-ranges = <&pinctrl 0 96 32>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };

  gpio4: gpio@fec50000 {
   compatible = "rockchip,gpio-bank";
   reg = <0x0 0xfec50000 0x0 0x100>;
   interrupts = <0 281 4>;
   clocks = <&cru 131>, <&cru 132>;

   gpio-controller;
   #gpio-cells = <2>;
   gpio-ranges = <&pinctrl 0 128 32>;
   interrupt-controller;
   #interrupt-cells = <2>;
  };
 };
};

# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi" 1





# 1 "./scripts/dtc/include-prefixes/dt-bindings/pinctrl/rockchip.h" 1
# 7 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinconf.dtsi" 1





&pinctrl {
 /omit-if-no-ref/
 pcfg_pull_up: pcfg-pull-up {
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_pull_down: pcfg-pull-down {
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_pull_none: pcfg-pull-none {
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
  bias-disable;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
  bias-disable;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
  bias-disable;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
  bias-disable;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
  bias-disable;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
  bias-disable;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
  bias-disable;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
  bias-pull-up;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
  bias-pull-up;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
  bias-pull-up;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
  bias-pull-up;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
  bias-pull-up;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
  bias-pull-up;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
  bias-pull-up;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
  bias-pull-down;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
  bias-pull-down;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
  bias-pull-down;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
  bias-pull-down;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
  bias-pull-down;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
  bias-pull-down;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
  bias-pull-down;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_smt: pcfg-pull-up-smt {
  bias-pull-up;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_down_smt: pcfg-pull-down-smt {
  bias-pull-down;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_smt: pcfg-pull-none-smt {
  bias-disable;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
  bias-disable;
  drive-strength = <0>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
  bias-disable;
  drive-strength = <1>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
  bias-disable;
  drive-strength = <2>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
  bias-disable;
  drive-strength = <3>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
  bias-disable;
  drive-strength = <4>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
  bias-disable;
  drive-strength = <5>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_6_smt: pcfg-pull-none-drv-level-6-smt {
  bias-disable;
  drive-strength = <6>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_output_high: pcfg-output-high {
  output-high;
 };

 /omit-if-no-ref/
 pcfg_output_high_pull_up: pcfg-output-high-pull-up {
  output-high;
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_output_high_pull_down: pcfg-output-high-pull-down {
  output-high;
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_output_high_pull_none: pcfg-output-high-pull-none {
  output-high;
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_output_low: pcfg-output-low {
  output-low;
 };

 /omit-if-no-ref/
 pcfg_output_low_pull_up: pcfg-output-low-pull-up {
  output-low;
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_output_low_pull_down: pcfg-output-low-pull-down {
  output-low;
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_output_low_pull_none: pcfg-output-low-pull-none {
  output-low;
  bias-disable;
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s-pinctrl.dtsi" 2





&pinctrl {
 auddsm {
  /omit-if-no-ref/
  auddsm_pins: auddsm-pins {
   rockchip,pins =

    <3 1 4 &pcfg_pull_none>,

    <3 2 4 &pcfg_pull_none>,

    <3 3 4 &pcfg_pull_none>,

    <3 4 4 &pcfg_pull_none>;
  };
 };

 bt1120 {
  /omit-if-no-ref/
  bt1120_pins: bt1120-pins {
   rockchip,pins =

    <4 8 2 &pcfg_pull_none>,

    <4 0 2 &pcfg_pull_none>,

    <4 1 2 &pcfg_pull_none>,

    <4 2 2 &pcfg_pull_none>,

    <4 3 2 &pcfg_pull_none>,

    <4 4 2 &pcfg_pull_none>,

    <4 5 2 &pcfg_pull_none>,

    <4 6 2 &pcfg_pull_none>,

    <4 7 2 &pcfg_pull_none>,

    <4 10 2 &pcfg_pull_none>,

    <4 11 2 &pcfg_pull_none>,

    <4 12 2 &pcfg_pull_none>,

    <4 13 2 &pcfg_pull_none>,

    <4 14 2 &pcfg_pull_none>,

    <4 15 2 &pcfg_pull_none>,

    <4 16 2 &pcfg_pull_none>,

    <4 17 2 &pcfg_pull_none>;
  };
 };

 can0 {
  /omit-if-no-ref/
  can0m0_pins: can0m0-pins {
   rockchip,pins =

    <0 16 11 &pcfg_pull_none>,

    <0 15 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can0m1_pins: can0m1-pins {
   rockchip,pins =

    <4 29 9 &pcfg_pull_none>,

    <4 28 9 &pcfg_pull_none>;
  };
 };

 can1 {
  /omit-if-no-ref/
  can1m0_pins: can1m0-pins {
   rockchip,pins =

    <3 13 9 &pcfg_pull_none>,

    <3 14 9 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can1m1_pins: can1m1-pins {
   rockchip,pins =

    <4 10 12 &pcfg_pull_none>,

    <4 11 12 &pcfg_pull_none>;
  };
 };

 can2 {
  /omit-if-no-ref/
  can2m0_pins: can2m0-pins {
   rockchip,pins =

    <3 20 9 &pcfg_pull_none>,

    <3 21 9 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  can2m1_pins: can2m1-pins {
   rockchip,pins =

    <0 28 10 &pcfg_pull_none>,

    <0 29 10 &pcfg_pull_none>;
  };
 };

 cif {
  /omit-if-no-ref/
  cif_clk: cif-clk {
   rockchip,pins =

    <4 12 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_clk: cif-dvp-clk {
   rockchip,pins =

    <4 8 1 &pcfg_pull_none>,

    <4 10 1 &pcfg_pull_none>,

    <4 11 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_bus16: cif-dvp-bus16 {
   rockchip,pins =

    <3 20 1 &pcfg_pull_none>,

    <3 21 1 &pcfg_pull_none>,

    <3 22 1 &pcfg_pull_none>,

    <3 23 1 &pcfg_pull_none>,

    <3 24 1 &pcfg_pull_none>,

    <3 25 1 &pcfg_pull_none>,

    <3 26 1 &pcfg_pull_none>,

    <3 27 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  cif_dvp_bus8: cif-dvp-bus8 {
   rockchip,pins =

    <4 0 1 &pcfg_pull_none>,

    <4 1 1 &pcfg_pull_none>,

    <4 2 1 &pcfg_pull_none>,

    <4 3 1 &pcfg_pull_none>,

    <4 4 1 &pcfg_pull_none>,

    <4 5 1 &pcfg_pull_none>,

    <4 6 1 &pcfg_pull_none>,

    <4 7 1 &pcfg_pull_none>;
  };
 };

 clk32k {
  /omit-if-no-ref/
  clk32k_in: clk32k-in {
   rockchip,pins =

    <0 10 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  clk32k_out0: clk32k-out0 {
   rockchip,pins =

    <0 10 2 &pcfg_pull_none>;
  };
 };

 cpu {
  /omit-if-no-ref/
  cpu_pins: cpu-pins {
   rockchip,pins =

    <0 25 2 &pcfg_pull_none>,

    <0 29 2 &pcfg_pull_none>;
  };
 };

 ddrphych0 {
  /omit-if-no-ref/
  ddrphych0_pins: ddrphych0-pins {
   rockchip,pins =

    <4 0 7 &pcfg_pull_none>,

    <4 1 7 &pcfg_pull_none>,

    <4 2 7 &pcfg_pull_none>,

    <4 3 7 &pcfg_pull_none>;
  };
 };

 ddrphych1 {
  /omit-if-no-ref/
  ddrphych1_pins: ddrphych1-pins {
   rockchip,pins =

    <4 4 7 &pcfg_pull_none>,

    <4 5 7 &pcfg_pull_none>,

    <4 6 7 &pcfg_pull_none>,

    <4 7 7 &pcfg_pull_none>;
  };
 };

 ddrphych2 {
  /omit-if-no-ref/
  ddrphych2_pins: ddrphych2-pins {
   rockchip,pins =

    <4 8 7 &pcfg_pull_none>,

    <4 9 7 &pcfg_pull_none>,

    <4 10 7 &pcfg_pull_none>,

    <4 11 7 &pcfg_pull_none>;
  };
 };

 ddrphych3 {
  /omit-if-no-ref/
  ddrphych3_pins: ddrphych3-pins {
   rockchip,pins =

    <4 12 7 &pcfg_pull_none>,

    <4 13 7 &pcfg_pull_none>,

    <4 14 7 &pcfg_pull_none>,

    <4 15 7 &pcfg_pull_none>;
  };
 };

 dp0 {
  /omit-if-no-ref/
  dp0m0_pins: dp0m0-pins {
   rockchip,pins =

    <4 12 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp0m1_pins: dp0m1-pins {
   rockchip,pins =

    <0 20 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp0m2_pins: dp0m2-pins {
   rockchip,pins =

    <1 0 5 &pcfg_pull_none>;
  };
 };

 dp1 {
  /omit-if-no-ref/
  dp1m0_pins: dp1m0-pins {
   rockchip,pins =

    <3 29 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp1m1_pins: dp1m1-pins {
   rockchip,pins =

    <0 21 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  dp1m2_pins: dp1m2-pins {
   rockchip,pins =

    <1 1 5 &pcfg_pull_none>;
  };
 };

 emmc {
  /omit-if-no-ref/
  emmc_rstnout: emmc-rstnout {
   rockchip,pins =

    <2 3 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  emmc_bus8: emmc-bus8 {
   rockchip,pins =

    <2 24 1 &pcfg_pull_up_drv_level_2>,

    <2 25 1 &pcfg_pull_up_drv_level_2>,

    <2 26 1 &pcfg_pull_up_drv_level_2>,

    <2 27 1 &pcfg_pull_up_drv_level_2>,

    <2 28 1 &pcfg_pull_up_drv_level_2>,

    <2 29 1 &pcfg_pull_up_drv_level_2>,

    <2 30 1 &pcfg_pull_up_drv_level_2>,

    <2 31 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_clk: emmc-clk {
   rockchip,pins =

    <2 1 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_cmd: emmc-cmd {
   rockchip,pins =

    <2 0 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  emmc_data_strobe: emmc-data-strobe {
   rockchip,pins =

    <2 2 1 &pcfg_pull_none>;
  };
 };

 eth1 {
  /omit-if-no-ref/
  eth1_pins: eth1-pins {
   rockchip,pins =

    <3 6 1 &pcfg_pull_none>;
  };
 };

 fspi {
  /omit-if-no-ref/
  fspim0_pins: fspim0-pins {
   rockchip,pins =

    <2 0 2 &pcfg_pull_up_drv_level_2>,

    <2 30 2 &pcfg_pull_up_drv_level_2>,

    <2 24 2 &pcfg_pull_up_drv_level_2>,

    <2 25 2 &pcfg_pull_up_drv_level_2>,

    <2 26 2 &pcfg_pull_up_drv_level_2>,

    <2 27 2 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim0_cs1: fspim0-cs1 {
   rockchip,pins =

    <2 31 2 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim2_pins: fspim2-pins {
   rockchip,pins =

    <3 5 5 &pcfg_pull_up_drv_level_2>,

    <3 20 2 &pcfg_pull_up_drv_level_2>,

    <3 0 5 &pcfg_pull_up_drv_level_2>,

    <3 1 5 &pcfg_pull_up_drv_level_2>,

    <3 2 5 &pcfg_pull_up_drv_level_2>,

    <3 3 5 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim2_cs1: fspim2-cs1 {
   rockchip,pins =

    <3 21 2 &pcfg_pull_up_drv_level_2>;
  };
 };

 gmac1 {
  /omit-if-no-ref/
  gmac1_miim: gmac1-miim {
   rockchip,pins =

    <3 18 1 &pcfg_pull_none>,

    <3 19 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_clkinout: gmac1-clkinout {
   rockchip,pins =

    <3 14 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_rx_bus2: gmac1-rx-bus2 {
   rockchip,pins =

    <3 7 1 &pcfg_pull_none>,

    <3 8 1 &pcfg_pull_none>,

    <3 9 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_tx_bus2: gmac1-tx-bus2 {
   rockchip,pins =

    <3 11 1 &pcfg_pull_none>,

    <3 12 1 &pcfg_pull_none>,

    <3 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_rgmii_clk: gmac1-rgmii-clk {
   rockchip,pins =

    <3 5 1 &pcfg_pull_none>,

    <3 4 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_rgmii_bus: gmac1-rgmii-bus {
   rockchip,pins =

    <3 2 1 &pcfg_pull_none>,

    <3 3 1 &pcfg_pull_none>,

    <3 0 1 &pcfg_pull_none>,

    <3 1 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_ppsclk: gmac1-ppsclk {
   rockchip,pins =

    <3 17 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_ppstrig: gmac1-ppstrig {
   rockchip,pins =

    <3 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
   rockchip,pins =

    <3 15 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac1_txer: gmac1-txer {
   rockchip,pins =

    <3 10 1 &pcfg_pull_none>;
  };
 };

 gpu {
  /omit-if-no-ref/
  gpu_pins: gpu-pins {
   rockchip,pins =

    <0 21 2 &pcfg_pull_none>;
  };
 };

 hdmi {
  /omit-if-no-ref/
  hdmim0_rx_cec: hdmim0-rx-cec {
   rockchip,pins =

    <4 13 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_rx_hpdin: hdmim0-rx-hpdin {
   rockchip,pins =

    <4 14 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_rx_scl: hdmim0-rx-scl {
   rockchip,pins =

    <0 26 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_rx_sda: hdmim0-rx-sda {
   rockchip,pins =

    <0 25 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_cec: hdmim0-tx0-cec {
   rockchip,pins =

    <4 17 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_hpd: hdmim0-tx0-hpd {
   rockchip,pins =

    <1 5 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_scl: hdmim0-tx0-scl {
   rockchip,pins =

    <4 15 5 &pcfg_pull_none_drv_level_5_smt>;
  };

  /omit-if-no-ref/
  hdmim0_tx0_sda: hdmim0-tx0-sda {
   rockchip,pins =

    <4 16 5 &pcfg_pull_none_drv_level_1_smt>;
  };

  /omit-if-no-ref/
  hdmim0_tx1_hpd: hdmim0-tx1-hpd {
   rockchip,pins =

    <1 6 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx: hdmim1-rx {
   rockchip,pins =

    <3 25 5 &pcfg_pull_none>,

    <3 26 5 &pcfg_pull_none_smt>,

    <3 27 5 &pcfg_pull_none_smt>,

    <3 28 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx_cec: hdmim1-rx-cec {
   rockchip,pins =

    <3 25 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx_hpdin: hdmim1-rx-hpdin {
   rockchip,pins =

    <3 28 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_rx_scl: hdmim1-rx-scl {
   rockchip,pins =

    <3 26 5 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  hdmim1_rx_sda: hdmim1-rx-sda {
   rockchip,pins =

    <3 27 5 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_cec: hdmim1-tx0-cec {
   rockchip,pins =

    <0 25 13 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_hpd: hdmim1-tx0-hpd {
   rockchip,pins =

    <3 28 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_scl: hdmim1-tx0-scl {
   rockchip,pins =

    <0 29 11 &pcfg_pull_none_drv_level_5_smt>;
  };

  /omit-if-no-ref/
  hdmim1_tx0_sda: hdmim1-tx0-sda {
   rockchip,pins =

    <0 28 11 &pcfg_pull_none_drv_level_1_smt>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_cec: hdmim1-tx1-cec {
   rockchip,pins =

    <0 26 13 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_hpd: hdmim1-tx1-hpd {
   rockchip,pins =

    <3 15 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_scl: hdmim1-tx1-scl {
   rockchip,pins =

    <3 22 5 &pcfg_pull_none_drv_level_5_smt>;
  };

  /omit-if-no-ref/
  hdmim1_tx1_sda: hdmim1-tx1-sda {
   rockchip,pins =

    <3 21 5 &pcfg_pull_none_drv_level_1_smt>;
  };
  /omit-if-no-ref/
  hdmim2_rx_cec: hdmim2-rx-cec {
   rockchip,pins =

    <1 15 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_rx_hpdin: hdmim2-rx-hpdin {
   rockchip,pins =

    <1 14 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_rx_scl: hdmim2-rx-scl {
   rockchip,pins =

    <1 30 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_rx_sda: hdmim2-rx-sda {
   rockchip,pins =

    <1 31 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx0_scl: hdmim2-tx0-scl {
   rockchip,pins =

    <3 23 5 &pcfg_pull_none_drv_level_5_smt>;
  };

  /omit-if-no-ref/
  hdmim2_tx0_sda: hdmim2-tx0-sda {
   rockchip,pins =

    <3 24 5 &pcfg_pull_none_drv_level_1_smt>;
  };

  /omit-if-no-ref/
  hdmim2_tx1_cec: hdmim2-tx1-cec {
   rockchip,pins =

    <3 20 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim2_tx1_scl: hdmim2-tx1-scl {
   rockchip,pins =

    <1 4 5 &pcfg_pull_none_drv_level_5_smt>;
  };

  /omit-if-no-ref/
  hdmim2_tx1_sda: hdmim2-tx1-sda {
   rockchip,pins =

    <1 3 5 &pcfg_pull_none_drv_level_1_smt>;
  };

  /omit-if-no-ref/
  hdmi_debug0: hdmi-debug0 {
   rockchip,pins =

    <1 7 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug1: hdmi-debug1 {
   rockchip,pins =

    <1 8 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug2: hdmi-debug2 {
   rockchip,pins =

    <1 9 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug3: hdmi-debug3 {
   rockchip,pins =

    <1 10 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug4: hdmi-debug4 {
   rockchip,pins =

    <1 11 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug5: hdmi-debug5 {
   rockchip,pins =

    <1 12 7 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmi_debug6: hdmi-debug6 {
   rockchip,pins =

    <1 0 7 &pcfg_pull_none>;
  };
 };

 i2c0 {
  /omit-if-no-ref/
  i2c0m0_xfer: i2c0m0-xfer {
   rockchip,pins =

    <0 11 2 &pcfg_pull_none_smt>,

    <0 6 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c0m2_xfer: i2c0m2-xfer {
   rockchip,pins =

    <0 25 3 &pcfg_pull_none_smt>,

    <0 26 3 &pcfg_pull_none_smt>;
  };
 };

 i2c1 {
  /omit-if-no-ref/
  i2c1m0_xfer: i2c1m0-xfer {
   rockchip,pins =

    <0 13 9 &pcfg_pull_none_smt>,

    <0 14 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m1_xfer: i2c1m1-xfer {
   rockchip,pins =

    <0 8 2 &pcfg_pull_none_smt>,

    <0 9 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m2_xfer: i2c1m2-xfer {
   rockchip,pins =

    <0 28 9 &pcfg_pull_none_smt>,

    <0 29 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m3_xfer: i2c1m3-xfer {
   rockchip,pins =

    <2 28 9 &pcfg_pull_none_smt>,

    <2 29 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c1m4_xfer: i2c1m4-xfer {
   rockchip,pins =

    <1 26 9 &pcfg_pull_none_smt>,

    <1 27 9 &pcfg_pull_none_smt>;
  };
 };

 i2c2 {
  /omit-if-no-ref/
  i2c2m0_xfer: i2c2m0-xfer {
   rockchip,pins =

    <0 15 9 &pcfg_pull_none_smt>,

    <0 16 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m2_xfer: i2c2m2-xfer {
   rockchip,pins =

    <2 3 9 &pcfg_pull_none_smt>,

    <2 2 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m3_xfer: i2c2m3-xfer {
   rockchip,pins =

    <1 21 9 &pcfg_pull_none_smt>,

    <1 20 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c2m4_xfer: i2c2m4-xfer {
   rockchip,pins =

    <1 1 9 &pcfg_pull_none_smt>,

    <1 0 9 &pcfg_pull_none_smt>;
  };
 };

 i2c3 {
  /omit-if-no-ref/
  i2c3m0_xfer: i2c3m0-xfer {
   rockchip,pins =

    <1 17 9 &pcfg_pull_none_smt>,

    <1 16 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m1_xfer: i2c3m1-xfer {
   rockchip,pins =

    <3 15 9 &pcfg_pull_none_smt>,

    <3 16 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m2_xfer: i2c3m2-xfer {
   rockchip,pins =

    <4 4 9 &pcfg_pull_none_smt>,

    <4 5 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c3m4_xfer: i2c3m4-xfer {
   rockchip,pins =

    <4 24 9 &pcfg_pull_none_smt>,

    <4 25 9 &pcfg_pull_none_smt>;
  };
 };

 i2c4 {
  /omit-if-no-ref/
  i2c4m0_xfer: i2c4m0-xfer {
   rockchip,pins =

    <3 6 9 &pcfg_pull_none_smt>,

    <3 5 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m2_xfer: i2c4m2-xfer {
   rockchip,pins =

    <0 21 9 &pcfg_pull_none_smt>,

    <0 20 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m3_xfer: i2c4m3-xfer {
   rockchip,pins =

    <1 3 9 &pcfg_pull_none_smt>,

    <1 2 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c4m4_xfer: i2c4m4-xfer {
   rockchip,pins =

    <1 23 9 &pcfg_pull_none_smt>,

    <1 22 9 &pcfg_pull_none_smt>;
  };
 };

 i2c5 {
  /omit-if-no-ref/
  i2c5m0_xfer: i2c5m0-xfer {
   rockchip,pins =

    <3 23 9 &pcfg_pull_none_smt>,

    <3 24 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m1_xfer: i2c5m1-xfer {
   rockchip,pins =

    <4 14 9 &pcfg_pull_none_smt>,

    <4 15 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m2_xfer: i2c5m2-xfer {
   rockchip,pins =

    <4 6 9 &pcfg_pull_none_smt>,

    <4 7 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c5m3_xfer: i2c5m3-xfer {
   rockchip,pins =

    <1 14 9 &pcfg_pull_none_smt>,

    <1 15 9 &pcfg_pull_none_smt>;
  };
 };

 i2c6 {
  /omit-if-no-ref/
  i2c6m0_xfer: i2c6m0-xfer {
   rockchip,pins =

    <0 24 9 &pcfg_pull_none_smt>,

    <0 23 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c6m1_xfer: i2c6m1-xfer {
   rockchip,pins =

    <1 19 9 &pcfg_pull_none_smt>,

    <1 18 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c6m3_xfer: i2c6m3-xfer {
   rockchip,pins =

    <4 9 9 &pcfg_pull_none_smt>,

    <4 8 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c6m4_xfer: i2c6m4-xfer {
   rockchip,pins =

    <3 1 9 &pcfg_pull_none_smt>,

    <3 0 9 &pcfg_pull_none_smt>;
  };
 };

 i2c7 {
  /omit-if-no-ref/
  i2c7m0_xfer: i2c7m0-xfer {
   rockchip,pins =

    <1 24 9 &pcfg_pull_none_smt>,

    <1 25 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c7m2_xfer: i2c7m2-xfer {
   rockchip,pins =

    <3 26 9 &pcfg_pull_none_smt>,

    <3 27 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c7m3_xfer: i2c7m3-xfer {
   rockchip,pins =

    <4 10 9 &pcfg_pull_none_smt>,

    <4 11 9 &pcfg_pull_none_smt>;
  };
 };

 i2c8 {
  /omit-if-no-ref/
  i2c8m0_xfer: i2c8m0-xfer {
   rockchip,pins =

    <4 26 9 &pcfg_pull_none_smt>,

    <4 27 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c8m2_xfer: i2c8m2-xfer {
   rockchip,pins =

    <1 30 9 &pcfg_pull_none_smt>,

    <1 31 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c8m3_xfer: i2c8m3-xfer {
   rockchip,pins =

    <4 16 9 &pcfg_pull_none_smt>,

    <4 17 9 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2c8m4_xfer: i2c8m4-xfer {
   rockchip,pins =

    <3 18 9 &pcfg_pull_none_smt>,

    <3 19 9 &pcfg_pull_none_smt>;
  };
 };

 i2s0 {
  /omit-if-no-ref/
  i2s0_idle: i2s0-idle {
   rockchip,pins =

    <1 21 0 &pcfg_pull_none>,

    <1 19 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_lrck: i2s0-lrck {
   rockchip,pins =

    <1 21 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s0_mclk: i2s0-mclk {
   rockchip,pins =

    <1 18 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s0_sclk: i2s0-sclk {
   rockchip,pins =

    <1 19 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s0_sdi0: i2s0-sdi0 {
   rockchip,pins =

    <1 28 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi1: i2s0-sdi1 {
   rockchip,pins =

    <1 27 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi2: i2s0-sdi2 {
   rockchip,pins =

    <1 26 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdi3: i2s0-sdi3 {
   rockchip,pins =

    <1 25 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo0: i2s0-sdo0 {
   rockchip,pins =

    <1 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo1: i2s0-sdo1 {
   rockchip,pins =

    <1 24 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo2: i2s0-sdo2 {
   rockchip,pins =

    <1 25 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s0_sdo3: i2s0-sdo3 {
   rockchip,pins =

    <1 26 1 &pcfg_pull_none>;
  };
 };

 i2s1 {
  /omit-if-no-ref/
  i2s1m0_lrck: i2s1m0-lrck {
   rockchip,pins =

    <4 2 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s1m0_mclk: i2s1m0-mclk {
   rockchip,pins =

    <4 0 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s1m0_sclk: i2s1m0-sclk {
   rockchip,pins =

    <4 1 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi0: i2s1m0-sdi0 {
   rockchip,pins =

    <4 5 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi1: i2s1m0-sdi1 {
   rockchip,pins =

    <4 6 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi2: i2s1m0-sdi2 {
   rockchip,pins =

    <4 7 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdi3: i2s1m0-sdi3 {
   rockchip,pins =

    <4 8 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo0: i2s1m0-sdo0 {
   rockchip,pins =

    <4 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo1: i2s1m0-sdo1 {
   rockchip,pins =

    <4 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo2: i2s1m0-sdo2 {
   rockchip,pins =

    <4 11 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m0_sdo3: i2s1m0-sdo3 {
   rockchip,pins =

    <4 12 3 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  i2s1m1_lrck: i2s1m1-lrck {
   rockchip,pins =

    <0 15 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s1m1_mclk: i2s1m1-mclk {
   rockchip,pins =

    <0 13 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s1m1_sclk: i2s1m1-sclk {
   rockchip,pins =

    <0 14 1 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi0: i2s1m1-sdi0 {
   rockchip,pins =

    <0 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi1: i2s1m1-sdi1 {
   rockchip,pins =

    <0 22 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi2: i2s1m1-sdi2 {
   rockchip,pins =

    <0 23 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdi3: i2s1m1-sdi3 {
   rockchip,pins =

    <0 24 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo0: i2s1m1-sdo0 {
   rockchip,pins =

    <0 25 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo1: i2s1m1-sdo1 {
   rockchip,pins =

    <0 26 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo2: i2s1m1-sdo2 {
   rockchip,pins =

    <0 28 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s1m1_sdo3: i2s1m1-sdo3 {
   rockchip,pins =

    <0 29 1 &pcfg_pull_none>;
  };
 };

 i2s2 {
  /omit-if-no-ref/
  i2s2m1_idle: i2s2m1-idle {
   rockchip,pins =

    <3 14 0 &pcfg_pull_none>,

    <3 13 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_lrck: i2s2m1-lrck {
   rockchip,pins =

    <3 14 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s2m1_mclk: i2s2m1-mclk {
   rockchip,pins =

    <3 12 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s2m1_sclk: i2s2m1-sclk {
   rockchip,pins =

    <3 13 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s2m1_sdi: i2s2m1-sdi {
   rockchip,pins =

    <3 10 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m1_sdo: i2s2m1-sdo {
   rockchip,pins =

    <3 11 3 &pcfg_pull_none>;
  };
 };

 i2s3 {
  /omit-if-no-ref/
  i2s3_idle: i2s3-idle {
   rockchip,pins =

    <3 2 0 &pcfg_pull_none>,

    <3 1 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3_lrck: i2s3-lrck {
   rockchip,pins =

    <3 2 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s3_mclk: i2s3-mclk {
   rockchip,pins =

    <3 0 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s3_sclk: i2s3-sclk {
   rockchip,pins =

    <3 1 3 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s3_sdi: i2s3-sdi {
   rockchip,pins =

    <3 4 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s3_sdo: i2s3-sdo {
   rockchip,pins =

    <3 3 3 &pcfg_pull_none>;
  };
 };

 jtag {
  /omit-if-no-ref/
  jtagm0_pins: jtagm0-pins {
   rockchip,pins =

    <4 26 5 &pcfg_pull_none>,

    <4 27 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  jtagm1_pins: jtagm1-pins {
   rockchip,pins =

    <4 24 5 &pcfg_pull_none>,

    <4 25 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  jtagm2_pins: jtagm2-pins {
   rockchip,pins =

    <0 13 2 &pcfg_pull_none>,

    <0 14 2 &pcfg_pull_none>;
  };
 };

 litcpu {
  /omit-if-no-ref/
  litcpu_pins: litcpu-pins {
   rockchip,pins =

    <0 27 1 &pcfg_pull_none>;
  };
 };

 mcu {
  /omit-if-no-ref/
  mcum0_pins: mcum0-pins {
   rockchip,pins =

    <4 28 5 &pcfg_pull_none>,

    <4 29 5 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mcum1_pins: mcum1-pins {
   rockchip,pins =

    <3 28 6 &pcfg_pull_none>,

    <3 29 6 &pcfg_pull_none>;
  };
 };

 mipi {
  /omit-if-no-ref/
  mipim0_camera0_clk: mipim0-camera0-clk {
   rockchip,pins =

    <4 9 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera1_clk: mipim0-camera1-clk {
   rockchip,pins =

    <1 14 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera2_clk: mipim0-camera2-clk {
   rockchip,pins =

    <1 15 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera3_clk: mipim0-camera3-clk {
   rockchip,pins =

    <1 30 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim0_camera4_clk: mipim0-camera4-clk {
   rockchip,pins =

    <1 31 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera0_clk: mipim1-camera0-clk {
   rockchip,pins =

    <3 5 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera1_clk: mipim1-camera1-clk {
   rockchip,pins =

    <3 6 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera2_clk: mipim1-camera2-clk {
   rockchip,pins =

    <3 7 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera3_clk: mipim1-camera3-clk {
   rockchip,pins =

    <3 8 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipim1_camera4_clk: mipim1-camera4-clk {
   rockchip,pins =

    <3 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipi_te0: mipi-te0 {
   rockchip,pins =

    <3 18 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  mipi_te1: mipi-te1 {
   rockchip,pins =

    <3 19 2 &pcfg_pull_none>;
  };
 };

 npu {
  /omit-if-no-ref/
  npu_pins: npu-pins {
   rockchip,pins =

    <0 22 2 &pcfg_pull_none>;
  };
 };

 pcie20x1 {
  /omit-if-no-ref/
  pcie20x1m0_pins: pcie20x1m0-pins {
   rockchip,pins =

    <3 23 4 &pcfg_pull_none>,

    <3 25 4 &pcfg_pull_none>,

    <3 24 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20x1m1_pins: pcie20x1m1-pins {
   rockchip,pins =

    <4 15 4 &pcfg_pull_none>,

    <4 17 4 &pcfg_pull_none>,

    <4 16 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
   rockchip,pins =

    <4 11 4 &pcfg_pull_none>;
  };
 };

 pcie30phy {
  /omit-if-no-ref/
  pcie30phy_pins: pcie30phy-pins {
   rockchip,pins =

    <1 20 4 &pcfg_pull_none>,

    <1 25 4 &pcfg_pull_none>;
  };
 };

 pcie30x1 {
  /omit-if-no-ref/
  pcie30x1m0_pins: pcie30x1m0-pins {
   rockchip,pins =

    <0 16 12 &pcfg_pull_none>,

    <0 21 12 &pcfg_pull_none>,

    <0 20 12 &pcfg_pull_none>,

    <0 13 12 &pcfg_pull_none>,

    <0 15 12 &pcfg_pull_none>,

    <0 14 12 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1m1_pins: pcie30x1m1-pins {
   rockchip,pins =

    <4 3 4 &pcfg_pull_none>,

    <4 5 4 &pcfg_pull_none>,

    <4 4 4 &pcfg_pull_none>,

    <4 0 4 &pcfg_pull_none>,

    <4 2 4 &pcfg_pull_none>,

    <4 1 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1m2_pins: pcie30x1m2-pins {
   rockchip,pins =

    <1 13 4 &pcfg_pull_none>,

    <1 12 4 &pcfg_pull_none>,

    <1 11 4 &pcfg_pull_none>,

    <1 0 4 &pcfg_pull_none>,

    <1 7 4 &pcfg_pull_none>,

    <1 1 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
   rockchip,pins =

    <4 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
   rockchip,pins =

    <4 10 4 &pcfg_pull_none>;
  };
 };

 pcie30x2 {
  /omit-if-no-ref/
  pcie30x2m0_pins: pcie30x2m0-pins {
   rockchip,pins =

    <0 25 12 &pcfg_pull_none>,

    <0 28 12 &pcfg_pull_none>,

    <0 26 12 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m1_pins: pcie30x2m1-pins {
   rockchip,pins =

    <4 6 4 &pcfg_pull_none>,

    <4 8 4 &pcfg_pull_none>,

    <4 7 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m2_pins: pcie30x2m2-pins {
   rockchip,pins =

    <3 26 4 &pcfg_pull_none>,

    <3 28 4 &pcfg_pull_none>,

    <3 27 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2m3_pins: pcie30x2m3-pins {
   rockchip,pins =

    <1 31 4 &pcfg_pull_none>,

    <1 15 4 &pcfg_pull_none>,

    <1 14 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x2_button_rstn: pcie30x2-button-rstn {
   rockchip,pins =

    <3 17 4 &pcfg_pull_none>;
  };
 };

 pcie30x4 {
  /omit-if-no-ref/
  pcie30x4m0_pins: pcie30x4m0-pins {
   rockchip,pins =

    <0 22 12 &pcfg_pull_none>,

    <0 24 12 &pcfg_pull_none>,

    <0 23 12 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4m1_pins: pcie30x4m1-pins {
   rockchip,pins =

    <4 12 4 &pcfg_pull_none>,

    <4 14 4 &pcfg_pull_none>,

    <4 13 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4m2_pins: pcie30x4m2-pins {
   rockchip,pins =

    <3 20 4 &pcfg_pull_none>,

    <3 22 4 &pcfg_pull_none>,

    <3 21 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4m3_pins: pcie30x4m3-pins {
   rockchip,pins =

    <1 8 4 &pcfg_pull_none>,

    <1 10 4 &pcfg_pull_none>,

    <1 9 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pcie30x4_button_rstn: pcie30x4-button-rstn {
   rockchip,pins =

    <3 29 4 &pcfg_pull_none>;
  };
 };

 pdm0 {
  /omit-if-no-ref/
  pdm0m0_clk: pdm0m0-clk {
   rockchip,pins =

    <1 22 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_clk1: pdm0m0-clk1 {
   rockchip,pins =

    <1 20 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_idle: pdm0m0-idle {
   rockchip,pins =

    <1 22 0 &pcfg_pull_none>,

    <1 20 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi0: pdm0m0-sdi0 {
   rockchip,pins =

    <1 29 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi1: pdm0m0-sdi1 {
   rockchip,pins =

    <1 25 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi2: pdm0m0-sdi2 {
   rockchip,pins =

    <1 26 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m0_sdi3: pdm0m0-sdi3 {
   rockchip,pins =

    <1 27 3 &pcfg_pull_none>;
  };
  /omit-if-no-ref/
  pdm0m1_clk: pdm0m1-clk {
   rockchip,pins =

    <0 16 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_clk1: pdm0m1-clk1 {
   rockchip,pins =

    <0 20 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_idle: pdm0m1-idle {
   rockchip,pins =

    <0 16 0 &pcfg_pull_none>,

    <0 20 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi0: pdm0m1-sdi0 {
   rockchip,pins =

    <0 23 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi1: pdm0m1-sdi1 {
   rockchip,pins =

    <0 24 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi2: pdm0m1-sdi2 {
   rockchip,pins =

    <0 28 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm0m1_sdi3: pdm0m1-sdi3 {
   rockchip,pins =

    <0 30 2 &pcfg_pull_none>;
  };
 };

 pdm1 {
  /omit-if-no-ref/
  pdm1m0_clk: pdm1m0-clk {
   rockchip,pins =

    <4 29 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_clk1: pdm1m0-clk1 {
   rockchip,pins =

    <4 28 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_idle: pdm1m0-idle {
   rockchip,pins =

    <4 29 0 &pcfg_pull_none>,

    <4 28 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi0: pdm1m0-sdi0 {
   rockchip,pins =

    <4 27 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi1: pdm1m0-sdi1 {
   rockchip,pins =

    <4 26 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi2: pdm1m0-sdi2 {
   rockchip,pins =

    <4 25 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m0_sdi3: pdm1m0-sdi3 {
   rockchip,pins =

    <4 24 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_clk: pdm1m1-clk {
   rockchip,pins =

    <1 12 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_clk1: pdm1m1-clk1 {
   rockchip,pins =

    <1 11 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_idle: pdm1m1-idle {
   rockchip,pins =

    <1 12 0 &pcfg_pull_none>,

    <1 11 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi0: pdm1m1-sdi0 {
   rockchip,pins =

    <1 7 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi1: pdm1m1-sdi1 {
   rockchip,pins =

    <1 8 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi2: pdm1m1-sdi2 {
   rockchip,pins =

    <1 9 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pdm1m1_sdi3: pdm1m1-sdi3 {
   rockchip,pins =

    <1 10 2 &pcfg_pull_none>;
  };
 };

 pmic {
  /omit-if-no-ref/
  pmic_pins: pmic-pins {
   rockchip,pins =

    <0 7 0 &pcfg_pull_up>,

    <0 2 1 &pcfg_pull_none>,

    <0 3 1 &pcfg_pull_none>,

    <0 17 1 &pcfg_pull_none>,

    <0 18 1 &pcfg_pull_none>,

    <0 19 1 &pcfg_pull_none>,

    <0 30 1 &pcfg_pull_none>;
  };
 };

 pmu {
  /omit-if-no-ref/
  pmu_pins: pmu-pins {
   rockchip,pins =

    <0 5 3 &pcfg_pull_none>;
  };
 };

 pwm0 {
  /omit-if-no-ref/
  pwm0m0_pins: pwm0m0-pins {
   rockchip,pins =

    <0 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm0m1_pins: pwm0m1-pins {
   rockchip,pins =

    <1 26 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm0m2_pins: pwm0m2-pins {
   rockchip,pins =

    <1 2 11 &pcfg_pull_none>;
  };
 };

 pwm1 {
  /omit-if-no-ref/
  pwm1m0_pins: pwm1m0-pins {
   rockchip,pins =

    <0 16 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm1m1_pins: pwm1m1-pins {
   rockchip,pins =

    <1 27 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm1m2_pins: pwm1m2-pins {
   rockchip,pins =

    <1 3 11 &pcfg_pull_none>;
  };
 };

 pwm2 {
  /omit-if-no-ref/
  pwm2m0_pins: pwm2m0-pins {
   rockchip,pins =

    <0 20 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm2m1_pins: pwm2m1-pins {
   rockchip,pins =

    <3 9 11 &pcfg_pull_none>;
  };
 };

 pwm3 {
  /omit-if-no-ref/
  pwm3m0_pins: pwm3m0-pins {
   rockchip,pins =

    <0 28 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm3m1_pins: pwm3m1-pins {
   rockchip,pins =

    <3 10 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm3m2_pins: pwm3m2-pins {
   rockchip,pins =

    <1 18 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm3m3_pins: pwm3m3-pins {
   rockchip,pins =

    <1 7 11 &pcfg_pull_none>;
  };
 };

 pwm4 {
  /omit-if-no-ref/
  pwm4m0_pins: pwm4m0-pins {
   rockchip,pins =

    <0 21 11 &pcfg_pull_none>;
  };
 };

 pwm5 {
  /omit-if-no-ref/
  pwm5m0_pins: pwm5m0-pins {
   rockchip,pins =

    <0 9 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm5m1_pins: pwm5m1-pins {
   rockchip,pins =

    <0 22 11 &pcfg_pull_none>;
  };
 };

 pwm6 {
  /omit-if-no-ref/
  pwm6m0_pins: pwm6m0-pins {
   rockchip,pins =

    <0 23 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm6m1_pins: pwm6m1-pins {
   rockchip,pins =

    <4 17 11 &pcfg_pull_none>;
  };
 };

 pwm7 {
  /omit-if-no-ref/
  pwm7m0_pins: pwm7m0-pins {
   rockchip,pins =

    <0 24 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm7m1_pins: pwm7m1-pins {
   rockchip,pins =

    <4 28 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm7m2_pins: pwm7m2-pins {
   rockchip,pins =

    <1 19 11 &pcfg_pull_none>;
  };
 };

 pwm8 {
  /omit-if-no-ref/
  pwm8m0_pins: pwm8m0-pins {
   rockchip,pins =

    <3 7 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm8m1_pins: pwm8m1-pins {
   rockchip,pins =

    <4 24 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm8m2_pins: pwm8m2-pins {
   rockchip,pins =

    <3 24 11 &pcfg_pull_none>;
  };
 };

 pwm9 {
  /omit-if-no-ref/
  pwm9m0_pins: pwm9m0-pins {
   rockchip,pins =

    <3 8 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm9m1_pins: pwm9m1-pins {
   rockchip,pins =

    <4 25 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm9m2_pins: pwm9m2-pins {
   rockchip,pins =

    <3 25 11 &pcfg_pull_none>;
  };
 };

 pwm10 {
  /omit-if-no-ref/
  pwm10m0_pins: pwm10m0-pins {
   rockchip,pins =

    <3 0 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm10m1_pins: pwm10m1-pins {
   rockchip,pins =

    <4 27 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm10m2_pins: pwm10m2-pins {
   rockchip,pins =

    <3 27 11 &pcfg_pull_none>;
  };
 };

 pwm11 {
  /omit-if-no-ref/
  pwm11m0_pins: pwm11m0-pins {
   rockchip,pins =

    <3 1 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m1_pins: pwm11m1-pins {
   rockchip,pins =

    <4 12 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m2_pins: pwm11m2-pins {
   rockchip,pins =

    <1 20 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm11m3_pins: pwm11m3-pins {
   rockchip,pins =

    <3 29 11 &pcfg_pull_none>;
  };
 };

 pwm12 {
  /omit-if-no-ref/
  pwm12m0_pins: pwm12m0-pins {
   rockchip,pins =

    <3 13 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm12m1_pins: pwm12m1-pins {
   rockchip,pins =

    <4 13 11 &pcfg_pull_none>;
  };
 };

 pwm13 {
  /omit-if-no-ref/
  pwm13m0_pins: pwm13m0-pins {
   rockchip,pins =

    <3 14 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm13m1_pins: pwm13m1-pins {
   rockchip,pins =

    <4 14 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm13m2_pins: pwm13m2-pins {
   rockchip,pins =

    <1 15 11 &pcfg_pull_none>;
  };
 };

 pwm14 {
  /omit-if-no-ref/
  pwm14m0_pins: pwm14m0-pins {
   rockchip,pins =

    <3 18 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm14m1_pins: pwm14m1-pins {
   rockchip,pins =

    <4 10 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm14m2_pins: pwm14m2-pins {
   rockchip,pins =

    <1 30 11 &pcfg_pull_none>;
  };
 };

 pwm15 {
  /omit-if-no-ref/
  pwm15m0_pins: pwm15m0-pins {
   rockchip,pins =

    <3 19 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m1_pins: pwm15m1-pins {
   rockchip,pins =

    <4 11 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m2_pins: pwm15m2-pins {
   rockchip,pins =

    <1 22 11 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  pwm15m3_pins: pwm15m3-pins {
   rockchip,pins =

    <1 31 11 &pcfg_pull_none>;
  };
 };

 refclk {
  /omit-if-no-ref/
  refclk_pins: refclk-pins {
   rockchip,pins =

    <0 0 1 &pcfg_pull_none>;
  };
 };

 sata {
  /omit-if-no-ref/
  sata_pins: sata-pins {
   rockchip,pins =

    <0 22 13 &pcfg_pull_none>,

    <0 28 13 &pcfg_pull_none>,

    <0 29 13 &pcfg_pull_none>;
  };
 };

 sata0 {
  /omit-if-no-ref/
  sata0m0_pins: sata0m0-pins {
   rockchip,pins =

    <4 14 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sata0m1_pins: sata0m1-pins {
   rockchip,pins =

    <1 11 6 &pcfg_pull_none>;
  };
 };

 sata1 {
  /omit-if-no-ref/
  sata1m0_pins: sata1m0-pins {
   rockchip,pins =

    <4 13 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sata1m1_pins: sata1m1-pins {
   rockchip,pins =

    <1 1 6 &pcfg_pull_none>;
  };
 };

 sata2 {
  /omit-if-no-ref/
  sata2m0_pins: sata2m0-pins {
   rockchip,pins =

    <4 9 6 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  sata2m1_pins: sata2m1-pins {
   rockchip,pins =

    <1 15 6 &pcfg_pull_none>;
  };
 };

 sdio {
  /omit-if-no-ref/
  sdiom1_pins: sdiom1-pins {
   rockchip,pins =

    <3 5 2 &pcfg_pull_none>,

    <3 4 2 &pcfg_pull_up>,

    <3 0 2 &pcfg_pull_up>,

    <3 1 2 &pcfg_pull_up>,

    <3 2 2 &pcfg_pull_up>,

    <3 3 2 &pcfg_pull_up>;
  };
 };

 sdmmc {
  /omit-if-no-ref/
  sdmmc_bus4: sdmmc-bus4 {
   rockchip,pins =

    <4 24 1 &pcfg_pull_up_drv_level_2>,

    <4 25 1 &pcfg_pull_up_drv_level_2>,

    <4 26 1 &pcfg_pull_up_drv_level_2>,

    <4 27 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc_clk: sdmmc-clk {
   rockchip,pins =

    <4 29 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc_cmd: sdmmc-cmd {
   rockchip,pins =

    <4 28 1 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  sdmmc_det: sdmmc-det {
   rockchip,pins =

    <0 4 1 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  sdmmc_pwren: sdmmc-pwren {
   rockchip,pins =

    <0 5 2 &pcfg_pull_none>;
  };
 };

 spdif0 {
  /omit-if-no-ref/
  spdif0m0_tx: spdif0m0-tx {
   rockchip,pins =

    <1 14 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdif0m1_tx: spdif0m1-tx {
   rockchip,pins =

    <4 12 6 &pcfg_pull_none>;
  };
 };

 spdif1 {
  /omit-if-no-ref/
  spdif1m0_tx: spdif1m0-tx {
   rockchip,pins =

    <1 15 3 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdif1m1_tx: spdif1m1-tx {
   rockchip,pins =

    <4 9 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  spdif1m2_tx: spdif1m2-tx {
   rockchip,pins =

    <4 17 3 &pcfg_pull_none>;
  };
 };

 spi0 {
  /omit-if-no-ref/
  spi0m0_pins: spi0m0-pins {
   rockchip,pins =

    <0 22 8 &pcfg_pull_up_drv_level_6>,

    <0 23 8 &pcfg_pull_up_drv_level_6>,

    <0 16 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m0_cs0: spi0m0-cs0 {
   rockchip,pins =

    <0 25 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m0_cs1: spi0m0-cs1 {
   rockchip,pins =

    <0 15 8 &pcfg_pull_up_drv_level_6>;
  };
  /omit-if-no-ref/
  spi0m1_pins: spi0m1-pins {
   rockchip,pins =

    <4 2 8 &pcfg_pull_up_drv_level_6>,

    <4 0 8 &pcfg_pull_up_drv_level_6>,

    <4 1 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m1_cs0: spi0m1-cs0 {
   rockchip,pins =

    <4 10 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m1_cs1: spi0m1-cs1 {
   rockchip,pins =

    <4 9 8 &pcfg_pull_up_drv_level_6>;
  };
  /omit-if-no-ref/
  spi0m2_pins: spi0m2-pins {
   rockchip,pins =

    <1 11 8 &pcfg_pull_up_drv_level_6>,

    <1 9 8 &pcfg_pull_up_drv_level_6>,

    <1 10 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m2_cs0: spi0m2-cs0 {
   rockchip,pins =

    <1 12 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m2_cs1: spi0m2-cs1 {
   rockchip,pins =

    <1 13 8 &pcfg_pull_up_drv_level_6>;
  };
  /omit-if-no-ref/
  spi0m3_pins: spi0m3-pins {
   rockchip,pins =

    <3 27 8 &pcfg_pull_up_drv_level_6>,

    <3 25 8 &pcfg_pull_up_drv_level_6>,

    <3 26 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m3_cs0: spi0m3-cs0 {
   rockchip,pins =

    <3 28 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi0m3_cs1: spi0m3-cs1 {
   rockchip,pins =

    <3 29 8 &pcfg_pull_up_drv_level_6>;
  };
 };

 spi1 {
  /omit-if-no-ref/
  spi1m1_pins: spi1m1-pins {
   rockchip,pins =

    <3 17 8 &pcfg_pull_up_drv_level_6>,

    <3 16 8 &pcfg_pull_up_drv_level_6>,

    <3 15 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi1m1_cs0: spi1m1-cs0 {
   rockchip,pins =

    <3 18 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi1m1_cs1: spi1m1-cs1 {
   rockchip,pins =

    <3 19 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi1m2_pins: spi1m2-pins {
   rockchip,pins =

    <1 26 8 &pcfg_pull_up_drv_level_6>,

    <1 24 8 &pcfg_pull_up_drv_level_6>,

    <1 25 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi1m2_cs0: spi1m2-cs0 {
   rockchip,pins =

    <1 27 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi1m2_cs1: spi1m2-cs1 {
   rockchip,pins =

    <1 29 8 &pcfg_pull_up_drv_level_6>;
  };
 };

 spi2 {
  /omit-if-no-ref/
  spi2m0_pins: spi2m0-pins {
   rockchip,pins =

    <1 6 8 &pcfg_pull_up_drv_level_6>,

    <1 4 8 &pcfg_pull_up_drv_level_6>,

    <1 5 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi2m0_cs0: spi2m0-cs0 {
   rockchip,pins =

    <1 7 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi2m0_cs1: spi2m0-cs1 {
   rockchip,pins =

    <1 8 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi2m1_pins: spi2m1-pins {
   rockchip,pins =

    <4 6 8 &pcfg_pull_up_drv_level_6>,

    <4 4 8 &pcfg_pull_up_drv_level_6>,

    <4 5 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi2m1_cs0: spi2m1-cs0 {
   rockchip,pins =

    <4 7 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi2m1_cs1: spi2m1-cs1 {
   rockchip,pins =

    <4 8 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi2m2_pins: spi2m2-pins {
   rockchip,pins =

    <0 5 1 &pcfg_pull_up_drv_level_1>,

    <0 11 1 &pcfg_pull_up_drv_level_1>,

    <0 6 1 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m2_cs0: spi2m2-cs0 {
   rockchip,pins =

    <0 9 1 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi2m2_cs1: spi2m2-cs1 {
   rockchip,pins =

    <0 8 1 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi3 {
  /omit-if-no-ref/
  spi3m1_pins: spi3m1-pins {
   rockchip,pins =

    <4 15 8 &pcfg_pull_up_drv_level_6>,

    <4 13 8 &pcfg_pull_up_drv_level_6>,

    <4 14 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m1_cs0: spi3m1-cs0 {
   rockchip,pins =

    <4 16 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m1_cs1: spi3m1-cs1 {
   rockchip,pins =

    <4 17 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m2_pins: spi3m2-pins {
   rockchip,pins =

    <0 27 8 &pcfg_pull_up_drv_level_6>,

    <0 24 8 &pcfg_pull_up_drv_level_6>,

    <0 26 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m2_cs0: spi3m2-cs0 {
   rockchip,pins =

    <0 28 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m2_cs1: spi3m2-cs1 {
   rockchip,pins =

    <0 29 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m3_pins: spi3m3-pins {
   rockchip,pins =

    <3 24 8 &pcfg_pull_up_drv_level_6>,

    <3 22 8 &pcfg_pull_up_drv_level_6>,

    <3 23 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m3_cs0: spi3m3-cs0 {
   rockchip,pins =

    <3 20 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi3m3_cs1: spi3m3-cs1 {
   rockchip,pins =

    <3 21 8 &pcfg_pull_up_drv_level_6>;
  };
 };

 spi4 {
  /omit-if-no-ref/
  spi4m0_pins: spi4m0-pins {
   rockchip,pins =

    <1 18 8 &pcfg_pull_up_drv_level_6>,

    <1 16 8 &pcfg_pull_up_drv_level_6>,

    <1 17 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m0_cs0: spi4m0-cs0 {
   rockchip,pins =

    <1 19 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m0_cs1: spi4m0-cs1 {
   rockchip,pins =

    <1 20 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m1_pins: spi4m1-pins {
   rockchip,pins =

    <3 2 8 &pcfg_pull_up_drv_level_6>,

    <3 0 8 &pcfg_pull_up_drv_level_6>,

    <3 1 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m1_cs0: spi4m1-cs0 {
   rockchip,pins =

    <3 3 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m1_cs1: spi4m1-cs1 {
   rockchip,pins =

    <3 4 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m2_pins: spi4m2-pins {
   rockchip,pins =

    <1 2 8 &pcfg_pull_up_drv_level_6>,

    <1 0 8 &pcfg_pull_up_drv_level_6>,

    <1 1 8 &pcfg_pull_up_drv_level_6>;
  };

  /omit-if-no-ref/
  spi4m2_cs0: spi4m2-cs0 {
   rockchip,pins =

    <1 3 8 &pcfg_pull_up_drv_level_6>;
  };
 };

 tsadc {
  /omit-if-no-ref/
  tsadcm1_shut: tsadcm1-shut {
   rockchip,pins =

    <0 2 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  tsadc_shut: tsadc-shut {
   rockchip,pins =

    <0 1 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  tsadc_shut_org: tsadc-shut-org {
   rockchip,pins =

    <0 1 1 &pcfg_pull_none>;
  };
 };

 uart0 {
  /omit-if-no-ref/
  uart0m0_xfer: uart0m0-xfer {
   rockchip,pins =

    <0 20 4 &pcfg_pull_up>,

    <0 21 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0m1_xfer: uart0m1-xfer {
   rockchip,pins =

    <0 8 4 &pcfg_pull_up>,

    <0 9 4 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0m2_xfer: uart0m2-xfer {
   rockchip,pins =

    <4 4 10 &pcfg_pull_up>,

    <4 3 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart0_ctsn: uart0-ctsn {
   rockchip,pins =

    <0 25 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart0_rtsn: uart0-rtsn {
   rockchip,pins =

    <0 22 4 &pcfg_pull_none>;
  };
 };

 uart1 {
  /omit-if-no-ref/
  uart1m1_xfer: uart1m1-xfer {
   rockchip,pins =

    <1 15 10 &pcfg_pull_up>,

    <1 14 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m1_ctsn: uart1m1-ctsn {
   rockchip,pins =

    <1 31 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m1_rtsn: uart1m1-rtsn {
   rockchip,pins =

    <1 30 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m2_xfer: uart1m2-xfer {
   rockchip,pins =

    <0 26 10 &pcfg_pull_up>,

    <0 25 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m2_ctsn: uart1m2-ctsn {
   rockchip,pins =

    <0 24 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m2_rtsn: uart1m2-rtsn {
   rockchip,pins =

    <0 23 10 &pcfg_pull_none>;
  };
 };

 uart2 {
  /omit-if-no-ref/
  uart2m0_xfer: uart2m0-xfer {
   rockchip,pins =

    <0 14 10 &pcfg_pull_up>,

    <0 13 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2m1_xfer: uart2m1-xfer {
   rockchip,pins =

    <4 25 10 &pcfg_pull_up>,

    <4 24 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2m2_xfer: uart2m2-xfer {
   rockchip,pins =

    <3 10 10 &pcfg_pull_up>,

    <3 9 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart2_ctsn: uart2-ctsn {
   rockchip,pins =

    <3 12 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart2_rtsn: uart2-rtsn {
   rockchip,pins =

    <3 11 10 &pcfg_pull_none>;
  };
 };

 uart3 {
  /omit-if-no-ref/
  uart3m0_xfer: uart3m0-xfer {
   rockchip,pins =

    <1 16 10 &pcfg_pull_up>,

    <1 17 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3m1_xfer: uart3m1-xfer {
   rockchip,pins =

    <3 14 10 &pcfg_pull_up>,

    <3 13 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3m2_xfer: uart3m2-xfer {
   rockchip,pins =

    <4 6 10 &pcfg_pull_up>,

    <4 5 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart3_ctsn: uart3-ctsn {
   rockchip,pins =

    <1 19 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart3_rtsn: uart3-rtsn {
   rockchip,pins =

    <1 18 10 &pcfg_pull_none>;
  };
 };

 uart4 {
  /omit-if-no-ref/
  uart4m0_xfer: uart4m0-xfer {
   rockchip,pins =

    <1 27 10 &pcfg_pull_up>,

    <1 26 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4m1_xfer: uart4m1-xfer {
   rockchip,pins =

    <3 24 10 &pcfg_pull_up>,

    <3 25 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4m2_xfer: uart4m2-xfer {
   rockchip,pins =

    <1 10 10 &pcfg_pull_up>,

    <1 11 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart4_ctsn: uart4-ctsn {
   rockchip,pins =

    <1 23 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart4_rtsn: uart4-rtsn {
   rockchip,pins =

    <1 21 10 &pcfg_pull_none>;
  };
 };

 uart5 {
  /omit-if-no-ref/
  uart5m0_xfer: uart5m0-xfer {
   rockchip,pins =

    <4 28 10 &pcfg_pull_up>,

    <4 29 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart5m0_ctsn: uart5m0-ctsn {
   rockchip,pins =

    <4 26 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m0_rtsn: uart5m0-rtsn {
   rockchip,pins =

    <4 27 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m1_xfer: uart5m1-xfer {
   rockchip,pins =

    <3 21 10 &pcfg_pull_up>,

    <3 20 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart5m1_ctsn: uart5m1-ctsn {
   rockchip,pins =

    <2 2 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m1_rtsn: uart5m1-rtsn {
   rockchip,pins =

    <2 3 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart5m2_xfer: uart5m2-xfer {
   rockchip,pins =

    <2 28 10 &pcfg_pull_up>,

    <2 29 10 &pcfg_pull_up>;
  };
 };

 uart6 {
  /omit-if-no-ref/
  uart6m1_xfer: uart6m1-xfer {
   rockchip,pins =

    <1 0 10 &pcfg_pull_up>,

    <1 1 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart6m1_ctsn: uart6m1-ctsn {
   rockchip,pins =

    <1 3 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m1_rtsn: uart6m1-rtsn {
   rockchip,pins =

    <1 2 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m2_xfer: uart6m2-xfer {
   rockchip,pins =

    <1 25 10 &pcfg_pull_up>,

    <1 24 10 &pcfg_pull_up>;
  };
 };

 uart7 {
  /omit-if-no-ref/
  uart7m1_xfer: uart7m1-xfer {
   rockchip,pins =

    <3 17 10 &pcfg_pull_up>,

    <3 16 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart7m1_ctsn: uart7m1-ctsn {
   rockchip,pins =

    <3 19 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m1_rtsn: uart7m1-rtsn {
   rockchip,pins =

    <3 18 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m2_xfer: uart7m2-xfer {
   rockchip,pins =

    <1 12 10 &pcfg_pull_up>,

    <1 13 10 &pcfg_pull_up>;
  };
 };

 uart8 {
  /omit-if-no-ref/
  uart8m0_xfer: uart8m0-xfer {
   rockchip,pins =

    <4 9 10 &pcfg_pull_up>,

    <4 8 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart8m0_ctsn: uart8m0-ctsn {
   rockchip,pins =

    <4 11 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m0_rtsn: uart8m0-rtsn {
   rockchip,pins =

    <4 10 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m1_xfer: uart8m1-xfer {
   rockchip,pins =

    <3 3 10 &pcfg_pull_up>,

    <3 2 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart8m1_ctsn: uart8m1-ctsn {
   rockchip,pins =

    <3 5 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8m1_rtsn: uart8m1-rtsn {
   rockchip,pins =

    <3 4 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart8_xfer: uart8-xfer {
   rockchip,pins =

    <4 9 10 &pcfg_pull_up>;
  };
 };

 uart9 {
  /omit-if-no-ref/
  uart9m1_xfer: uart9m1-xfer {
   rockchip,pins =

    <4 13 10 &pcfg_pull_up>,

    <4 12 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m1_ctsn: uart9m1-ctsn {
   rockchip,pins =

    <4 1 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m1_rtsn: uart9m1-rtsn {
   rockchip,pins =

    <4 0 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m2_xfer: uart9m2-xfer {
   rockchip,pins =

    <3 28 10 &pcfg_pull_up>,

    <3 29 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m2_ctsn: uart9m2-ctsn {
   rockchip,pins =

    <3 27 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m2_rtsn: uart9m2-rtsn {
   rockchip,pins =

    <3 26 10 &pcfg_pull_none>;
  };
 };

 vop {
  /omit-if-no-ref/
  vop_pins: vop-pins {
   rockchip,pins =

    <1 2 1 &pcfg_pull_none>;
  };
 };
};




&pinctrl {
 bt656 {
  /omit-if-no-ref/
  bt656_pins: bt656-pins {
   rockchip,pins =

    <4 8 2 &pcfg_pull_none_drv_level_2>,

    <4 0 2 &pcfg_pull_none_drv_level_2>,

    <4 1 2 &pcfg_pull_none_drv_level_2>,

    <4 2 2 &pcfg_pull_none_drv_level_2>,

    <4 3 2 &pcfg_pull_none_drv_level_2>,

    <4 4 2 &pcfg_pull_none_drv_level_2>,

    <4 5 2 &pcfg_pull_none_drv_level_2>,

    <4 6 2 &pcfg_pull_none_drv_level_2>,

    <4 7 2 &pcfg_pull_none_drv_level_2>;
  };
 };

 gpio-func {
  /omit-if-no-ref/
  tsadc_gpio_func: tsadc-gpio-func {
   rockchip,pins =
    <0 1 0 &pcfg_pull_none>;
  };
 };
};
# 6888 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588s.dtsi" 2
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 1






# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rockchip-pinconf.dtsi" 1





&pinctrl {
 /omit-if-no-ref/
 pcfg_pull_up: pcfg-pull-up {
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_pull_down: pcfg-pull-down {
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_pull_none: pcfg-pull-none {
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
  bias-disable;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
  bias-disable;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
  bias-disable;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
  bias-disable;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
  bias-disable;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
  bias-disable;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
  bias-disable;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
  bias-disable;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
  bias-disable;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
  bias-disable;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
  bias-disable;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
  bias-disable;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
  bias-disable;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
  bias-disable;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
  bias-disable;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
  bias-disable;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
  bias-pull-up;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
  bias-pull-up;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
  bias-pull-up;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
  bias-pull-up;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
  bias-pull-up;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
  bias-pull-up;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
  bias-pull-up;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_7: pcfg-pull-up-drv-level-7 {
  bias-pull-up;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_8: pcfg-pull-up-drv-level-8 {
  bias-pull-up;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_9: pcfg-pull-up-drv-level-9 {
  bias-pull-up;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_10: pcfg-pull-up-drv-level-10 {
  bias-pull-up;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_11: pcfg-pull-up-drv-level-11 {
  bias-pull-up;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_12: pcfg-pull-up-drv-level-12 {
  bias-pull-up;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_13: pcfg-pull-up-drv-level-13 {
  bias-pull-up;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_14: pcfg-pull-up-drv-level-14 {
  bias-pull-up;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_drv_level_15: pcfg-pull-up-drv-level-15 {
  bias-pull-up;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_0: pcfg-pull-down-drv-level-0 {
  bias-pull-down;
  drive-strength = <0>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_1: pcfg-pull-down-drv-level-1 {
  bias-pull-down;
  drive-strength = <1>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_2: pcfg-pull-down-drv-level-2 {
  bias-pull-down;
  drive-strength = <2>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_3: pcfg-pull-down-drv-level-3 {
  bias-pull-down;
  drive-strength = <3>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_4: pcfg-pull-down-drv-level-4 {
  bias-pull-down;
  drive-strength = <4>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_5: pcfg-pull-down-drv-level-5 {
  bias-pull-down;
  drive-strength = <5>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_6: pcfg-pull-down-drv-level-6 {
  bias-pull-down;
  drive-strength = <6>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_7: pcfg-pull-down-drv-level-7 {
  bias-pull-down;
  drive-strength = <7>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_8: pcfg-pull-down-drv-level-8 {
  bias-pull-down;
  drive-strength = <8>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_9: pcfg-pull-down-drv-level-9 {
  bias-pull-down;
  drive-strength = <9>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_10: pcfg-pull-down-drv-level-10 {
  bias-pull-down;
  drive-strength = <10>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_11: pcfg-pull-down-drv-level-11 {
  bias-pull-down;
  drive-strength = <11>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_12: pcfg-pull-down-drv-level-12 {
  bias-pull-down;
  drive-strength = <12>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_13: pcfg-pull-down-drv-level-13 {
  bias-pull-down;
  drive-strength = <13>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_14: pcfg-pull-down-drv-level-14 {
  bias-pull-down;
  drive-strength = <14>;
 };

 /omit-if-no-ref/
 pcfg_pull_down_drv_level_15: pcfg-pull-down-drv-level-15 {
  bias-pull-down;
  drive-strength = <15>;
 };

 /omit-if-no-ref/
 pcfg_pull_up_smt: pcfg-pull-up-smt {
  bias-pull-up;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_down_smt: pcfg-pull-down-smt {
  bias-pull-down;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_smt: pcfg-pull-none-smt {
  bias-disable;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_0_smt: pcfg-pull-none-drv-level-0-smt {
  bias-disable;
  drive-strength = <0>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_1_smt: pcfg-pull-none-drv-level-1-smt {
  bias-disable;
  drive-strength = <1>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_2_smt: pcfg-pull-none-drv-level-2-smt {
  bias-disable;
  drive-strength = <2>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_3_smt: pcfg-pull-none-drv-level-3-smt {
  bias-disable;
  drive-strength = <3>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_4_smt: pcfg-pull-none-drv-level-4-smt {
  bias-disable;
  drive-strength = <4>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_pull_none_drv_level_5_smt: pcfg-pull-none-drv-level-5-smt {
  bias-disable;
  drive-strength = <5>;
  input-schmitt-enable;
 };

 /omit-if-no-ref/
 pcfg_output_high: pcfg-output-high {
  output-high;
 };

 /omit-if-no-ref/
 pcfg_output_high_pull_up: pcfg-output-high-pull-up {
  output-high;
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_output_high_pull_down: pcfg-output-high-pull-down {
  output-high;
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_output_high_pull_none: pcfg-output-high-pull-none {
  output-high;
  bias-disable;
 };

 /omit-if-no-ref/
 pcfg_output_low: pcfg-output-low {
  output-low;
 };

 /omit-if-no-ref/
 pcfg_output_low_pull_up: pcfg-output-low-pull-up {
  output-low;
  bias-pull-up;
 };

 /omit-if-no-ref/
 pcfg_output_low_pull_down: pcfg-output-low-pull-down {
  output-low;
  bias-pull-down;
 };

 /omit-if-no-ref/
 pcfg_output_low_pull_none: pcfg-output-low-pull-none {
  output-low;
  bias-disable;
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-vccio3-pinctrl.dtsi" 2





&pinctrl {
 clk32k {
  /omit-if-no-ref/
  clk32k_out1: clk32k-out1 {
   rockchip,pins =

    <2 21 1 &pcfg_pull_none>;
  };

 };

 eth0 {
  /omit-if-no-ref/
  eth0_pins: eth0-pins {
   rockchip,pins =

    <2 19 1 &pcfg_pull_none>;
  };

 };

 fspi {
  /omit-if-no-ref/
  fspim1_pins: fspim1-pins {
   rockchip,pins =

    <2 11 3 &pcfg_pull_up_drv_level_2>,

    <2 12 3 &pcfg_pull_up_drv_level_2>,

    <2 6 3 &pcfg_pull_up_drv_level_2>,

    <2 7 3 &pcfg_pull_up_drv_level_2>,

    <2 8 3 &pcfg_pull_up_drv_level_2>,

    <2 9 3 &pcfg_pull_up_drv_level_2>;
  };

  /omit-if-no-ref/
  fspim1_cs1: fspim1-cs1 {
   rockchip,pins =

    <2 13 3 &pcfg_pull_up_drv_level_2>;
  };
 };

 gmac0 {
  /omit-if-no-ref/
  gmac0_miim: gmac0-miim {
   rockchip,pins =

    <4 20 1 &pcfg_pull_none>,

    <4 21 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_clkinout: gmac0-clkinout {
   rockchip,pins =

    <4 19 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rx_bus2: gmac0-rx-bus2 {
   rockchip,pins =

    <2 17 1 &pcfg_pull_none>,

    <2 18 1 &pcfg_pull_none>,

    <4 18 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_tx_bus2: gmac0-tx-bus2 {
   rockchip,pins =

    <2 14 1 &pcfg_pull_none>,

    <2 15 1 &pcfg_pull_none>,

    <2 16 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_clk: gmac0-rgmii-clk {
   rockchip,pins =

    <2 8 1 &pcfg_pull_none>,

    <2 11 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_rgmii_bus: gmac0-rgmii-bus {
   rockchip,pins =

    <2 6 1 &pcfg_pull_none>,

    <2 7 1 &pcfg_pull_none>,

    <2 9 1 &pcfg_pull_none>,

    <2 10 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_ppsclk: gmac0-ppsclk {
   rockchip,pins =

    <2 20 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_ppstring: gmac0-ppstring {
   rockchip,pins =

    <2 13 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_ptp_refclk: gmac0-ptp-refclk {
   rockchip,pins =

    <2 12 1 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  gmac0_txer: gmac0-txer {
   rockchip,pins =

    <4 22 1 &pcfg_pull_none>;
  };

 };

 hdmi {
  /omit-if-no-ref/
  hdmim0_tx1_cec: hdmim0-tx1-cec {
   rockchip,pins =

    <2 20 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx1_scl: hdmim0-tx1-scl {
   rockchip,pins =

    <2 13 4 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  hdmim0_tx1_sda: hdmim0-tx1-sda {
   rockchip,pins =

    <2 12 4 &pcfg_pull_none>;
  };
 };

 i2c0 {
  /omit-if-no-ref/
  i2c0m1_xfer: i2c0m1-xfer {
   rockchip,pins =

    <4 21 9 &pcfg_pull_none_smt>,

    <4 22 9 &pcfg_pull_none_smt>;
  };
 };

 i2c2 {
  /omit-if-no-ref/
  i2c2m1_xfer: i2c2m1-xfer {
   rockchip,pins =

    <2 17 9 &pcfg_pull_none_smt>,

    <2 16 9 &pcfg_pull_none_smt>;
  };
 };

 i2c3 {
  /omit-if-no-ref/
  i2c3m3_xfer: i2c3m3-xfer {
   rockchip,pins =

    <2 10 9 &pcfg_pull_none_smt>,

    <2 11 9 &pcfg_pull_none_smt>;
  };
 };

 i2c4 {
  /omit-if-no-ref/
  i2c4m1_xfer: i2c4m1-xfer {
   rockchip,pins =

    <2 13 9 &pcfg_pull_none_smt>,

    <2 12 9 &pcfg_pull_none_smt>;
  };
 };

 i2c5 {
  /omit-if-no-ref/
  i2c5m4_xfer: i2c5m4-xfer {
   rockchip,pins =

    <2 14 9 &pcfg_pull_none_smt>,

    <2 15 9 &pcfg_pull_none_smt>;
  };
 };

 i2c6 {
  /omit-if-no-ref/
  i2c6m2_xfer: i2c6m2-xfer {
   rockchip,pins =

    <2 19 9 &pcfg_pull_none_smt>,

    <2 18 9 &pcfg_pull_none_smt>;
  };
 };

 i2c7 {
  /omit-if-no-ref/
  i2c7m1_xfer: i2c7m1-xfer {
   rockchip,pins =

    <4 19 9 &pcfg_pull_none_smt>,

    <4 20 9 &pcfg_pull_none_smt>;
  };
 };

 i2c8 {
  /omit-if-no-ref/
  i2c8m1_xfer: i2c8m1-xfer {
   rockchip,pins =

    <2 8 9 &pcfg_pull_none_smt>,

    <2 9 9 &pcfg_pull_none_smt>;
  };
 };

 i2s2 {
  /omit-if-no-ref/
  i2s2m0_idle: i2s2m0-idle {
   rockchip,pins =

    <2 16 0 &pcfg_pull_none>,

    <2 15 0 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_lrck: i2s2m0-lrck {
   rockchip,pins =

    <2 16 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s2m0_mclk: i2s2m0-mclk {
   rockchip,pins =

    <2 14 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s2m0_sclk: i2s2m0-sclk {
   rockchip,pins =

    <2 15 2 &pcfg_pull_none_smt>;
  };

  /omit-if-no-ref/
  i2s2m0_sdi: i2s2m0-sdi {
   rockchip,pins =

    <2 19 2 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  i2s2m0_sdo: i2s2m0-sdo {
   rockchip,pins =

    <4 19 2 &pcfg_pull_none>;
  };
 };

 pwm2 {
  /omit-if-no-ref/
  pwm2m2_pins: pwm2m2-pins {
   rockchip,pins =

    <4 18 11 &pcfg_pull_none>;
  };
 };

 pwm4 {
  /omit-if-no-ref/
  pwm4m1_pins: pwm4m1-pins {
   rockchip,pins =

    <4 19 11 &pcfg_pull_none>;
  };
 };

 pwm5 {
  /omit-if-no-ref/
  pwm5m2_pins: pwm5m2-pins {
   rockchip,pins =

    <4 20 11 &pcfg_pull_none>;
  };
 };

 pwm6 {
  /omit-if-no-ref/
  pwm6m2_pins: pwm6m2-pins {
   rockchip,pins =

    <4 21 11 &pcfg_pull_none>;
  };
 };

 pwm7 {
  /omit-if-no-ref/
  pwm7m3_pins: pwm7m3-pins {
   rockchip,pins =

    <4 22 11 &pcfg_pull_none>;
  };
 };

 sdio {
  /omit-if-no-ref/
  sdiom0_pins: sdiom0-pins {
   rockchip,pins =

    <2 11 2 &pcfg_pull_none>,

    <2 10 2 &pcfg_pull_up>,

    <2 6 2 &pcfg_pull_up>,

    <2 7 2 &pcfg_pull_up>,

    <2 8 2 &pcfg_pull_up>,

    <2 9 2 &pcfg_pull_up>;
  };
 };

 spi1 {
  /omit-if-no-ref/
  spi1m0_pins: spi1m0-pins {
   rockchip,pins =

    <2 16 8 &pcfg_pull_up_drv_level_1>,

    <2 17 8 &pcfg_pull_up_drv_level_1>,

    <2 18 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m0_cs0: spi1m0-cs0 {
   rockchip,pins =

    <2 19 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi1m0_cs1: spi1m0-cs1 {
   rockchip,pins =

    <2 20 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 spi3 {
  /omit-if-no-ref/
  spi3m0_pins: spi3m0-pins {
   rockchip,pins =

    <4 22 8 &pcfg_pull_up_drv_level_1>,

    <4 20 8 &pcfg_pull_up_drv_level_1>,

    <4 21 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m0_cs0: spi3m0-cs0 {
   rockchip,pins =

    <4 18 8 &pcfg_pull_up_drv_level_1>;
  };

  /omit-if-no-ref/
  spi3m0_cs1: spi3m0-cs1 {
   rockchip,pins =

    <4 19 8 &pcfg_pull_up_drv_level_1>;
  };
 };

 uart1 {
  /omit-if-no-ref/
  uart1m0_xfer: uart1m0-xfer {
   rockchip,pins =

    <2 14 10 &pcfg_pull_up>,

    <2 15 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart1m0_ctsn: uart1m0-ctsn {
   rockchip,pins =

    <2 17 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart1m0_rtsn: uart1m0-rtsn {
   rockchip,pins =

    <2 16 10 &pcfg_pull_none>;
  };
 };

 uart6 {
  /omit-if-no-ref/
  uart6m0_xfer: uart6m0-xfer {
   rockchip,pins =

    <2 6 10 &pcfg_pull_up>,

    <2 7 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart6m0_ctsn: uart6m0-ctsn {
   rockchip,pins =

    <2 9 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart6m0_rtsn: uart6m0-rtsn {
   rockchip,pins =

    <2 8 10 &pcfg_pull_none>;
  };
 };

 uart7 {
  /omit-if-no-ref/
  uart7m0_xfer: uart7m0-xfer {
   rockchip,pins =

    <2 12 10 &pcfg_pull_up>,

    <2 13 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart7m0_ctsn: uart7m0-ctsn {
   rockchip,pins =

    <4 22 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart7m0_rtsn: uart7m0-rtsn {
   rockchip,pins =

    <4 18 10 &pcfg_pull_none>;
  };
 };

 uart9 {
  /omit-if-no-ref/
  uart9m0_xfer: uart9m0-xfer {
   rockchip,pins =

    <2 20 10 &pcfg_pull_up>,

    <2 18 10 &pcfg_pull_up>;
  };

  /omit-if-no-ref/
  uart9m0_ctsn: uart9m0-ctsn {
   rockchip,pins =

    <4 21 10 &pcfg_pull_none>;
  };

  /omit-if-no-ref/
  uart9m0_rtsn: uart9m0-rtsn {
   rockchip,pins =

    <4 20 10 &pcfg_pull_none>;
  };
 };
};
# 9 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588.dtsi" 2

/ {
 aliases {
  dp0 = &dp0;
  dp1 = &dp1;
  edp0 = &edp0;
  edp1 = &edp1;
  ethernet0 = &gmac0;
  hdptx0 = &hdptxphy0;
  hdptx1 = &hdptxphy1;
  hdptxhdmi0 = &hdptxphy_hdmi0;
  hdptxhdmi1 = &hdptxphy_hdmi1;
  hdmi0 = &hdmi0;
  hdmi1 = &hdmi1;
  hdmirx0 = &hdmirx_ctrler;
  rkcif_mipi_lvds4= &rkcif_mipi_lvds4;
  rkcif_mipi_lvds5= &rkcif_mipi_lvds5;
  usbdp0 = &usbdp_phy0;
  usbdp1 = &usbdp_phy1;
 };

 rkcif_mipi_lvds4: rkcif-mipi-lvds4 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds4>;
  status = "disabled";
 };

 rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds4>;
  status = "disabled";
 };

 rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds4>;
  status = "disabled";
 };

 rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds4>;
  status = "disabled";
 };

 rkcif_mipi_lvds5: rkcif-mipi-lvds5 {
  compatible = "rockchip,rkcif-mipi-lvds";
  rockchip,hw = <&rkcif>;
  iommus = <&rkcif_mmu>;
  status = "disabled";
 };

 rkcif_mipi_lvds5_sditf: rkcif-mipi-lvds5-sditf {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds5>;
  status = "disabled";
 };

 rkcif_mipi_lvds5_sditf_vir1: rkcif-mipi-lvds5-sditf-vir1 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds5>;
  status = "disabled";
 };

 rkcif_mipi_lvds5_sditf_vir2: rkcif-mipi-lvds5-sditf-vir2 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds5>;
  status = "disabled";
 };

 rkcif_mipi_lvds5_sditf_vir3: rkcif-mipi-lvds5-sditf-vir3 {
  compatible = "rockchip,rkcif-sditf";
  rockchip,cif = <&rkcif_mipi_lvds5>;
  status = "disabled";
 };

 usbdrd3_1: usbdrd3_1 {
  compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
  clocks = <&cru 422>, <&cru 421>,
    <&cru 420>;
  clock-names = "ref", "suspend", "bus";
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;
  status = "disabled";

  usbdrd_dwc3_1: usb@fc400000 {
   compatible = "snps,dwc3";
   reg = <0x0 0xfc400000 0x0 0x400000>;
   interrupts = <0 221 4>;
   power-domains = <&power 31>;
   resets = <&cru 679>;
   reset-names = "usb3-otg";
   dr_mode = "host";
   phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
   phy-names = "usb2-phy", "usb3-phy";
   phy_type = "utmi_wide";
   snps,dis_enblslpm_quirk;
   snps,dis-u1-entry-quirk;
   snps,dis-u2-entry-quirk;
   snps,dis-u2-freeclk-exists-quirk;
   snps,dis-del-phy-power-chg-quirk;
   snps,dis-tx-ipgap-linecheck-quirk;
   snps,parkmode-disable-hs-quirk;
   snps,parkmode-disable-ss-quirk;
   status = "disabled";
  };
 };

 pcie30_phy_grf: syscon@fd5b8000 {
  compatible = "rockchip,pcie30-phy-grf", "syscon";
  reg = <0x0 0xfd5b8000 0x0 0x10000>;
 };

 pipe_phy1_grf: syscon@fd5c0000 {
  compatible = "rockchip,pipe-phy-grf", "syscon";
  reg = <0x0 0xfd5c0000 0x0 0x100>;
 };

 usbdpphy1_grf: syscon@fd5cc000 {
  compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
  reg = <0x0 0xfd5cc000 0x0 0x4000>;
 };

 usb2phy1_grf: syscon@fd5d4000 {
  compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
        "simple-mfd";
  reg = <0x0 0xfd5d4000 0x0 0x4000>;
  #address-cells = <1>;
  #size-cells = <1>;

  u2phy1: usb2-phy@4000 {
   compatible = "rockchip,rk3588-usb2phy";
   reg = <0x4000 0x10>;
   interrupts = <0 394 4>;
   resets = <&cru 786504>, <&cru 1161>;
   reset-names = "phy", "apb";
   clocks = <&cru 693>;
   clock-names = "phyclk";
   clock-output-names = "usb480m_phy1";
   #clock-cells = <0>;
   rockchip,usbctrl-grf = <&usb_grf>;
   status = "disabled";

   u2phy1_otg: otg-port {
    #phy-cells = <0>;
    status = "disabled";
   };
  };
 };

 hdptxphy1_grf: syscon@fd5e4000 {
  compatible = "rockchip,rk3588-hdptxphy-grf", "syscon";
  reg = <0x0 0xfd5e4000 0x0 0x100>;
 };

 spdif_tx5: spdif-tx@fddb8000 {
  compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
  reg = <0x0 0xfddb8000 0x0 0x1000>;
  interrupts = <0 198 4>;
  dmas = <&dmac1 22>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 527>, <&cru 522>;
  assigned-clocks = <&cru 523>;
  assigned-clock-parents = <&cru 5>;
  power-domains = <&power 25>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s8_8ch: i2s@fddc8000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddc8000 0x0 0x1000>;
  interrupts = <0 188 4>;
  clocks = <&cru 513>, <&cru 510>;
  clock-names = "mclk_tx", "hclk";
  assigned-clocks = <&cru 511>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac2 22>;
  dma-names = "tx";
  power-domains = <&power 25>;
  resets = <&cru 913>;
  reset-names = "tx-m";
  rockchip,playback-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_tx4: spdif-tx@fdde8000 {
  compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif";
  reg = <0x0 0xfdde8000 0x0 0x1000>;
  interrupts = <0 197 4>;
  dmas = <&dmac1 8>;
  dma-names = "tx";
  clock-names = "mclk", "hclk";
  clocks = <&cru 604>, <&cru 600>;
  assigned-clocks = <&cru 601>;
  assigned-clock-parents = <&cru 5>;
  power-domains = <&power 26>;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s6_8ch: i2s@fddf4000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddf4000 0x0 0x1000>;
  interrupts = <0 186 4>;
  clocks = <&cru 588>, <&cru 588>, <&cru 594>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 585>;
  assigned-clock-parents = <&cru 7>;
  dmas = <&dmac2 4>;
  dma-names = "tx";
  power-domains = <&power 26>;
  resets = <&cru 1007>;
  reset-names = "tx-m";
  rockchip,always-on;
  rockchip,hdmi-path;
  rockchip,playback-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s7_8ch: i2s@fddf8000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfddf8000 0x0 0x1000>;
  interrupts = <0 187 4>;
  clocks = <&cru 572>, <&cru 572>, <&cru 568>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 569>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac2 21>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 963>;
  reset-names = "rx-m";
  rockchip,capture-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 i2s10_8ch: i2s@fde00000 {
  compatible = "rockchip,rk3588-i2s-tdm";
  reg = <0x0 0xfde00000 0x0 0x1000>;
  interrupts = <0 190 4>;
  clocks = <&cru 567>, <&cru 567>, <&cru 563>;
  clock-names = "mclk_tx", "mclk_rx", "hclk";
  assigned-clocks = <&cru 564>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac2 24>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 1047>;
  reset-names = "rx-m";
  rockchip,capture-only;
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_rx1: spdif-rx@fde10000 {
  compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
  reg = <0x0 0xfde10000 0x0 0x1000>;
  interrupts = <0 200 4>;
  clocks = <&cru 608>, <&cru 607>;
  clock-names = "mclk", "hclk";
  assigned-clocks = <&cru 608>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac0 22>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 1023>;
  reset-names = "spdifrx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 spdif_rx2: spdif-rx@fde18000 {
  compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx";
  reg = <0x0 0xfde18000 0x0 0x1000>;
  interrupts = <0 201 4>;
  clocks = <&cru 610>, <&cru 609>;
  clock-names = "mclk", "hclk";
  assigned-clocks = <&cru 610>;
  assigned-clock-parents = <&cru 5>;
  dmas = <&dmac0 23>;
  dma-names = "rx";
  power-domains = <&power 26>;
  resets = <&cru 1025>;
  reset-names = "spdifrx-m";
  #sound-dai-cells = <0>;
  status = "disabled";
 };

 dp1: dp@fde60000 {
  compatible = "rockchip,rk3588-dp";
  reg = <0x0 0xfde60000 0x0 0x4000>;
  interrupts = <0 162 4>;
  clocks = <&cru 487>, <&cru 717>,
    <&cru 513>, <&cru 525>,
    <&hclk_vo0>, <&cru 491>;
  clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp";
  assigned-clocks = <&cru 717>;
  assigned-clock-rates = <16000000>;
  resets = <&cru 905>;
  phys = <&usbdp_phy1_dp>;
  power-domains = <&power 25>;
  #sound-dai-cells = <1>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    dp1_in_vp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp0_out_dp1>;
     status = "disabled";
    };

    dp1_in_vp1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp1_out_dp1>;
     status = "disabled";
    };

    dp1_in_vp2: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&vp2_out_dp1>;
     status = "disabled";
    };
   };

   port@1 {
    reg = <1>;

    dp1_out: endpoint { };
   };
  };
 };

 hdmi1: hdmi@fdea0000 {
  compatible = "rockchip,rk3588-dw-hdmi";
  reg = <0x0 0xfdea0000 0x0 0x10000>, <0x0 0xfdeb0000 0x0 0x10000>;
  interrupts = <0 173 4>,
        <0 174 4>,
        <0 175 4>,
        <0 176 4>,
        <0 361 4>;
  clocks = <&cru 548>,
    <&cru 614>,
    <&cru 549>,
    <&cru 550>,
    <&cru 588>,
    <&cru 628>,
    <&cru 629>,
    <&cru 630>,
    <&cru 631>,
    <&hclk_vo1>,
    <&hdptxphy_hdmi_clk1>;
  clock-names = "pclk",
         "hpd",
         "earc",
         "hdmitx_ref",
         "aud",
         "dclk_vp0",
         "dclk_vp1",
         "dclk_vp2",
         "dclk_vp3",
         "hclk_vo1",
         "link_clk";
  resets = <&cru 983>, <&cru 1181>;
  reset-names = "ref", "hdp";
  power-domains = <&power 26>;
  pinctrl-names = "default";
  pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>;
  reg-io-width = <4>;
  rockchip,grf = <&sys_grf>;
  rockchip,vo1_grf = <&vo1_grf>;
  phys = <&hdptxphy_hdmi1>;
  phy-names = "hdmi";
  #sound-dai-cells = <0>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   hdmi1_in: port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    hdmi1_in_vp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp0_out_hdmi1>;
     status = "disabled";
    };

    hdmi1_in_vp1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp1_out_hdmi1>;
     status = "disabled";
    };

    hdmi1_in_vp2: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&vp2_out_hdmi1>;
     status = "disabled";
    };
   };
  };
 };

 edp1: edp@fded0000 {
  compatible = "rockchip,rk3588-edp";
  reg = <0x0 0xfded0000 0x0 0x1000>;
  interrupts = <0 164 4>;
  clocks = <&cru 532>, <&cru 531>,
    <&cru 533>, <&hclk_vo1>;
  clock-names = "dp", "pclk", "spdif", "hclk";
  resets = <&cru 996>, <&cru 995>;
  reset-names = "dp", "apb";
  phys = <&hdptxphy1>;
  phy-names = "dp";
  power-domains = <&power 26>;
  rockchip,grf = <&vo1_grf>;
  status = "disabled";

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    edp1_in_vp0: endpoint@0 {
     reg = <0>;
     remote-endpoint = <&vp0_out_edp1>;
     status = "disabled";
    };

    edp1_in_vp1: endpoint@1 {
     reg = <1>;
     remote-endpoint = <&vp1_out_edp1>;
     status = "disabled";
    };

    edp1_in_vp2: endpoint@2 {
     reg = <2>;
     remote-endpoint = <&vp2_out_edp1>;
     status = "disabled";
    };
   };

   port@1 {
    reg = <1>;

    edp1_out: endpoint { };
   };
  };
 };

 hdmirx_ctrler: hdmirx-controller@fdee0000 {
  compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler";
  reg = <0x0 0xfdee0000 0x0 0x6000>;
  reg-names = "hdmirx_regs";
  power-domains = <&power 26>;
  rockchip,grf = <&sys_grf>;
  rockchip,vo1_grf = <&vo1_grf>;
  interrupts = <0 177 4>,
        <0 436 4>,
        <0 179 4>;
  interrupt-names = "cec", "hdmi", "dma";
  clocks = <&cru 538>,
    <&cru 543>,
    <&cru 690>,
    <&cru 539>,
    <&cru 540>,
    <&cru 562>,
    <&hclk_vo1>;
  clock-names = "aclk",
         "audio",
         "cr_para",
         "pclk",
         "ref",
         "hclk_s_hdmirx",
         "hclk_vo1";
  resets = <&cru 985>, <&cru 986>,
    <&cru 987>, <&cru 951>;
  reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu";
  pinctrl-0 = <&hdmim1_rx>;
  pinctrl-names = "default";
  status = "disabled";
 };

 pcie3x4: pcie@fe150000 {
  compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x00 0x0f>;
  clocks = <&cru 334>, <&cru 339>,
    <&cru 329>, <&cru 344>,
    <&cru 350>, <&cru 387>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 263 4>,
        <0 262 4>,
        <0 261 4>,
        <0 260 4>,
        <0 259 4>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
    <0 0 0 2 &pcie3x4_intc 1>,
    <0 0 0 3 &pcie3x4_intc 2>,
    <0 0 0 4 &pcie3x4_intc 3>;
  linux,pci-domain = <0>;
  num-ib-windows = <16>;
  num-ob-windows = <16>;
  num-viewport = <8>;
  max-link-speed = <3>;
  msi-map = <0x0000 &its1 0x0000 0x1000>;
  num-lanes = <4>;
  phys = <&pcie30phy>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000
     0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000
     0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000
     0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
  reg = <0x0 0xfe150000 0x0 0x10000>,
        <0xa 0x40000000 0x0 0x400000>;
  reg-names = "pcie-apb", "pcie-dbi";
  resets = <&cru 525>, <&cru 540>;
  reset-names = "pcie", "periph";
  rockchip,pipe-grf = <&php_grf>;
  status = "disabled";

  pcie3x4_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 260 1>;
  };
 };

 pcie3x2: pcie@fe160000 {
  compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x10 0x1f>;
  clocks = <&cru 335>, <&cru 340>,
    <&cru 330>, <&cru 345>,
    <&cru 351>, <&cru 388>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 258 4>,
        <0 257 4>,
        <0 256 4>,
        <0 255 4>,
        <0 254 4>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
    <0 0 0 2 &pcie3x2_intc 1>,
    <0 0 0 3 &pcie3x2_intc 2>,
    <0 0 0 4 &pcie3x2_intc 3>;
  linux,pci-domain = <1>;
  num-ib-windows = <16>;
  num-ob-windows = <16>;
  num-viewport = <8>;
  max-link-speed = <3>;
  msi-map = <0x1000 &its1 0x1000 0x1000>;
  num-lanes = <2>;
  phys = <&pcie30phy>;
  phy-names = "pcie-phy";
  power-domains = <&power 34>;
  ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000
     0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000
     0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000
     0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;
  reg = <0x0 0xfe160000 0x0 0x10000>,
        <0xa 0x40400000 0x0 0x400000>;
  reg-names = "pcie-apb", "pcie-dbi";
  resets = <&cru 526>, <&cru 541>;
  reset-names = "pcie", "periph";
  rockchip,pipe-grf = <&php_grf>;
  status = "disabled";

  pcie3x2_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 255 1>;
  };
 };

 pcie2x1l0: pcie@fe170000 {
  compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
  #address-cells = <3>;
  #size-cells = <2>;
  bus-range = <0x20 0x2f>;
  clocks = <&cru 336>, <&cru 341>,
    <&cru 331>, <&cru 347>,
    <&cru 352>, <&cru 708>;
  clock-names = "aclk_mst", "aclk_slv",
         "aclk_dbi", "pclk",
         "aux", "pipe";
  device_type = "pci";
  interrupts = <0 243 4>,
        <0 242 4>,
        <0 241 4>,
        <0 240 4>,
        <0 239 4>;
  interrupt-names = "sys", "pmc", "msg", "legacy", "err";
  #interrupt-cells = <1>;
  interrupt-map-mask = <0 0 0 7>;
  interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
    <0 0 0 2 &pcie2x1l0_intc 1>,
    <0 0 0 3 &pcie2x1l0_intc 2>,
    <0 0 0 4 &pcie2x1l0_intc 3>;
  linux,pci-domain = <2>;
  num-ib-windows = <8>;
  num-ob-windows = <8>;
  num-viewport = <4>;
  max-link-speed = <2>;
  msi-map = <0x2000 &its0 0x2000 0x1000>;
  num-lanes = <1>;
  phys = <&combphy1_ps 2>;
  phy-names = "pcie-phy";
  ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000
     0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000
     0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000
     0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
  reg = <0x0 0xfe170000 0x0 0x10000>,
        <0xa 0x40800000 0x0 0x400000>;
  reg-names = "pcie-apb", "pcie-dbi";
  resets = <&cru 527>, <&cru 542>;
  reset-names = "pcie", "periph";
  rockchip,pipe-grf = <&php_grf>;
  status = "disabled";

  pcie2x1l0_intc: legacy-interrupt-controller {
   interrupt-controller;
   #address-cells = <0>;
   #interrupt-cells = <1>;
   interrupt-parent = <&gic>;
   interrupts = <0 240 1>;
  };
 };

 gmac_uio0: uio@fe1b0000 {
  compatible = "rockchip,uio-gmac";
  reg = <0x0 0xfe1b0000 0x0 0x10000>;
  rockchip,ethernet = <&gmac0>;
  status = "disabled";
 };

 gmac0: ethernet@fe1b0000 {
  compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
  reg = <0x0 0xfe1b0000 0x0 0x10000>;
  interrupts = <0 227 4>,
        <0 226 4>;
  interrupt-names = "macirq", "eth_wake_irq";
  rockchip,grf = <&sys_grf>;
  rockchip,php_grf = <&php_grf>;
  clocks = <&cru 324>, <&cru 325>,
    <&cru 359>, <&cru 364>,
    <&cru 322>;
  clock-names = "stmmaceth", "clk_mac_ref",
         "pclk_mac", "aclk_mac",
         "ptp_ref";
  resets = <&cru 522>;
  reset-names = "stmmaceth";
  power-domains = <&power 33>;

  snps,mixed-burst;
  snps,tso;

  snps,axi-config = <&gmac0_stmmac_axi_setup>;
  snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
  snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
  status = "disabled";

  mdio0: mdio {
   compatible = "snps,dwmac-mdio";
   #address-cells = <0x1>;
   #size-cells = <0x0>;
  };

  gmac0_stmmac_axi_setup: stmmac-axi-config {
   snps,wr_osr_lmt = <4>;
   snps,rd_osr_lmt = <8>;
   snps,blen = <0 0 0 0 16 8 4>;
  };

  gmac0_mtl_rx_setup: rx-queues-config {
   snps,rx-queues-to-use = <1>;
   queue0 {};
  };

  gmac0_mtl_tx_setup: tx-queues-config {
   snps,tx-queues-to-use = <1>;
   queue0 {};
  };
 };

 sata1: sata@fe220000 {
  compatible = "rockchip,rk-ahci", "snps,dwc-ahci";
  reg = <0 0xfe220000 0 0x1000>;
  clocks = <&cru 370>, <&cru 367>,
    <&cru 373>, <&cru 356>,
    <&cru 383>;
  clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
  interrupts = <0 274 4>;
  interrupt-names = "hostc";
  phys = <&combphy1_ps 1>;
  phy-names = "sata-phy";
  ports-implemented = <0x1>;
  status = "disabled";
 };

 hdptxphy1: phy@fed70000 {
  compatible = "rockchip,rk3588-hdptx-phy";
  reg = <0x0 0xfed70000 0x0 0x2000>;
  clocks = <&cru 693>, <&cru 616>;
  clock-names = "ref", "apb";
  resets = <&cru 1158>, <&cru 786495>,
    <&cru 786496>, <&cru 786497>;
  reset-names = "apb", "init", "cmn", "lane";
  rockchip,grf = <&hdptxphy1_grf>;
  #phy-cells = <0>;
  status = "disabled";
 };

 hdptxphy_hdmi1: hdmiphy@fed70000 {
  compatible = "rockchip,rk3588-hdptx-phy-hdmi";
  reg = <0x0 0xfed70000 0x0 0x2000>;
  clocks = <&cru 693>, <&cru 616>;
  clock-names = "ref", "apb";
  resets = <&cru 1169>, <&cru 1158>,
    <&cru 786495>, <&cru 786496>,
    <&cru 786497>, <&cru 1167>,
    <&cru 1168>;
  reset-names = "phy", "apb", "init", "cmn", "lane", "ropll",
         "lcpll";
  rockchip,grf = <&hdptxphy1_grf>;
  #phy-cells = <0>;
  status = "disabled";

  hdptxphy_hdmi_clk1: clk-port {
   #clock-cells = <0>;
   status = "okay";
  };
 };


 usbdp_phy1: phy@fed90000 {
  compatible = "rockchip,rk3588-usbdp-phy";
  reg = <0x0 0xfed90000 0x0 0x10000>;
  rockchip,u2phy-grf = <&usb2phy1_grf>;
  rockchip,usb-grf = <&usb_grf>;
  rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
  rockchip,vo-grf = <&vo0_grf>;
  clocks = <&cru 694>,
    <&cru 640>,
    <&cru 618>,
    <&u2phy1>;
  clock-names = "refclk", "immortal", "pclk", "utmi";
  resets = <&cru 47>,
    <&cru 48>,
    <&cru 49>,
    <&cru 50>,
    <&cru 1156>;
  reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
  status = "disabled";

  usbdp_phy1_dp: dp-port {
   #phy-cells = <0>;
   status = "disabled";
  };

  usbdp_phy1_u3: u3-port {
   #phy-cells = <0>;
   status = "disabled";
  };
 };

 combphy1_ps: phy@fee10000 {
  compatible = "rockchip,rk3588-naneng-combphy";
  reg = <0x0 0xfee10000 0x0 0x100>;
  #phy-cells = <1>;
  clocks = <&cru 702>, <&cru 390>,
    <&cru 358>;
  clock-names = "refclk", "apbclk", "phpclk";
  assigned-clocks = <&cru 702>;
  assigned-clock-rates = <100000000>;
  resets = <&cru 131078>, <&cru 1239>;
  reset-names = "combphy-apb", "combphy";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
  rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
  status = "disabled";
 };

 pcie30phy: phy@fee80000 {
  compatible = "rockchip,rk3588-pcie3-phy";
  reg = <0x0 0xfee80000 0x0 0x20000>;
  #phy-cells = <0>;
  clocks = <&cru 392>;
  clock-names = "pclk";
  resets = <&cru 131082>;
  reset-names = "phy";
  rockchip,pipe-grf = <&php_grf>;
  rockchip,phy-grf = <&pcie30_phy_grf>;
  status = "disabled";
 };

};

&display_subsystem {
 route {
  route_dp1: route-dp1 {
   status = "disabled";
   logo,uboot = "logo.bmp";
   logo,kernel = "logo_kernel.bmp";
   logo,mode = "center";
   charge_logo,mode = "center";
   connect = <&vp1_out_dp1>;
  };

  route_hdmi1: route-hdmi1 {
   status = "disabled";
   logo,uboot = "logo.bmp";
   logo,kernel = "logo_kernel.bmp";
   logo,mode = "center";
   charge_logo,mode = "center";
   connect = <&vp1_out_hdmi1>;
  };
 };
};

&vp0 {
 vp0_out_dp1: endpoint@3 {
  reg = <3>;
  remote-endpoint = <&dp1_in_vp0>;
 };

 vp0_out_edp1: endpoint@4 {
  reg = <4>;
  remote-endpoint = <&edp1_in_vp0>;
 };

 vp0_out_hdmi1: endpoint@5 {
  reg = <5>;
  remote-endpoint = <&hdmi1_in_vp0>;
 };
};

&vp1 {
 vp1_out_dp1: endpoint@3 {
  reg = <3>;
  remote-endpoint = <&dp1_in_vp1>;
 };

 vp1_out_edp1: endpoint@4 {
  reg = <4>;
  remote-endpoint = <&edp1_in_vp1>;
 };

 vp1_out_hdmi1: endpoint@5 {
  reg = <5>;
  remote-endpoint = <&hdmi1_in_vp1>;
 };
};

&vp2 {
 vp2_out_dp1: endpoint@5 {
  reg = <5>;
  remote-endpoint = <&dp1_in_vp2>;
 };

 vp2_out_edp1: endpoint@6 {
  reg = <6>;
  remote-endpoint = <&edp1_in_vp2>;
 };

 vp2_out_hdmi1: endpoint@7 {
  reg = <7>;
  remote-endpoint = <&hdmi1_in_vp2>;
 };
};
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588j.dtsi" 2

&cluster0_opp_table {







 /delete-node/ opp-j-m-1416000000;
 /delete-node/ opp-j-m-1608000000;
 /delete-node/ opp-j-m-1704000000;
};

&cluster1_opp_table {







 /delete-node/ opp-j-m-1800000000;
 /delete-node/ opp-j-m-2016000000;
};

&cluster2_opp_table {







 /delete-node/ opp-j-m-1800000000;
 /delete-node/ opp-j-m-2016000000;
};

&gpu_opp_table {







 /delete-node/ opp-j-850000000;
};

&npu_opp_table {







 /delete-node/ opp-j-m-950000000;
};
# 13 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 1






# 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
# 8 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/pwm/pwm.h" 1
# 9 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2

# 1 "./scripts/dtc/include-prefixes/dt-bindings/input/rk-input.h" 1
# 11 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/display/drm_mipi_dsi.h" 1
# 12 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/display/rockchip_vop.h" 1
# 13 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2
# 1 "./scripts/dtc/include-prefixes/dt-bindings/sensor-dev.h" 1
# 14 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-evb.dtsi" 2

/ {
 adc_keys: adc-keys {
  compatible = "adc-keys";
  io-channels = <&saradc 1>;
  io-channel-names = "buttons";
  keyup-threshold-microvolt = <1800000>;
  poll-interval = <100>;

  vol-up-key {
   label = "volume up";
   linux,code = <115>;
   press-threshold-microvolt = <17000>;
  };

  vol-down-key {
   label = "volume down";
   linux,code = <114>;
   press-threshold-microvolt = <417000>;
  };

  menu-key {
   label = "menu";
   linux,code = <139>;
   press-threshold-microvolt = <890000>;
  };

  back-key {
   label = "back";
   linux,code = <158>;
   press-threshold-microvolt = <1235000>;
  };
 };

 backlight: backlight {
  compatible = "pwm-backlight";
  brightness-levels = <
     0 20 20 21 21 22 22 23
    23 24 24 25 25 26 26 27
    27 28 28 29 29 30 30 31
    31 32 32 33 33 34 34 35
    35 36 36 37 37 38 38 39
    40 41 42 43 44 45 46 47
    48 49 50 51 52 53 54 55
    56 57 58 59 60 61 62 63
    64 65 66 67 68 69 70 71
    72 73 74 75 76 77 78 79
    80 81 82 83 84 85 86 87
    88 89 90 91 92 93 94 95
    96 97 98 99 100 101 102 103
   104 105 106 107 108 109 110 111
   112 113 114 115 116 117 118 119
   120 121 122 123 124 125 126 127
   128 129 130 131 132 133 134 135
   136 137 138 139 140 141 142 143
   144 145 146 147 148 149 150 151
   152 153 154 155 156 157 158 159
   160 161 162 163 164 165 166 167
   168 169 170 171 172 173 174 175
   176 177 178 179 180 181 182 183
   184 185 186 187 188 189 190 191
   192 193 194 195 196 197 198 199
   200 201 202 203 204 205 206 207
   208 209 210 211 212 213 214 215
   216 217 218 219 220 221 222 223
   224 225 226 227 228 229 230 231
   232 233 234 235 236 237 238 239
   240 241 242 243 244 245 246 247
   248 249 250 251 252 253 254 255
  >;
  default-brightness-level = <200>;
 };

 bt_sco: bt-sco {
  status = "disabled";
  compatible = "delta,dfbmcs320";
  #sound-dai-cells = <1>;
 };

 bt_sound: bt-sound {
  status = "disabled";
  compatible = "simple-audio-card";
  simple-audio-card,format = "dsp_a";
  simple-audio-card,bitclock-inversion;
  simple-audio-card,mclk-fs = <256>;
  simple-audio-card,name = "rockchip,bt";
  simple-audio-card,cpu {
   sound-dai = <&i2s2_2ch>;
  };
  simple-audio-card,codec {
   sound-dai = <&bt_sco 1>;
  };
 };

 hdmi0_sound: hdmi0-sound {
  status = "disabled";
  compatible = "rockchip,hdmi";
  rockchip,mclk-fs = <128>;
  rockchip,card-name = "rockchip-hdmi0";
  rockchip,cpu = <&i2s5_8ch>;
  rockchip,codec = <&hdmi0>;
  rockchip,jack-det;
 };

 hdmi1_sound: hdmi1-sound {
  status = "disabled";
  compatible = "rockchip,hdmi";
  rockchip,mclk-fs = <128>;
  rockchip,card-name = "rockchip-hdmi1";
  rockchip,cpu = <&i2s6_8ch>;
  rockchip,codec = <&hdmi1>;
  rockchip,jack-det;
 };

 dp0_sound: dp0-sound {
  status = "disabled";
  compatible = "rockchip,hdmi";
  rockchip,card-name= "rockchip-dp0";
  rockchip,mclk-fs = <512>;
  rockchip,cpu = <&spdif_tx2>;
  rockchip,codec = <&dp0 1>;
  rockchip,jack-det;
 };

 dp1_sound: dp1-sound {
  status = "disabled";
  compatible = "rockchip,hdmi";
  rockchip,card-name= "rockchip-dp1";
  rockchip,mclk-fs = <512>;
  rockchip,cpu = <&spdif_tx5>;
  rockchip,codec = <&dp1 1>;
  rockchip,jack-det;
 };

 leds: leds {
  compatible = "gpio-leds";
  work_led: work {
   gpios = <&gpio3 15 0>;
   linux,default-trigger = "heartbeat";
  };
 };

 spdif_tx0_dc: spdif-tx0-dc {
  status = "disabled";
  compatible = "linux,spdif-dit";
  #sound-dai-cells = <0>;
 };

 spdif_tx0_sound: spdif-tx0-sound {
  status = "disabled";
  compatible = "simple-audio-card";
  simple-audio-card,mclk-fs = <128>;
  simple-audio-card,name = "rockchip,spdif-tx0";
  simple-audio-card,cpu {
   sound-dai = <&spdif_tx0>;
  };
  simple-audio-card,codec {
   sound-dai = <&spdif_tx0_dc>;
  };
 };

 spdif_tx1_dc: spdif-tx1-dc {
  status = "disabled";
  compatible = "linux,spdif-dit";
  #sound-dai-cells = <0>;
 };

 spdif_tx1_sound: spdif-tx1-sound {
  status = "disabled";
  compatible = "simple-audio-card";
  simple-audio-card,mclk-fs = <128>;
  simple-audio-card,name = "rockchip,spdif-tx1";
  simple-audio-card,cpu {
   sound-dai = <&spdif_tx1>;
  };
  simple-audio-card,codec {
   sound-dai = <&spdif_tx1_dc>;
  };
 };

 test-power {
  status = "okay";
 };

 vcc12v_dcin: vcc12v-dcin {
  compatible = "regulator-fixed";
  regulator-name = "vcc12v_dcin";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <12000000>;
  regulator-max-microvolt = <12000000>;
 };

 vcc5v0_sys: vcc5v0-sys {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_sys";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&vcc12v_dcin>;
 };

 vcc5v0_usbdcin: vcc5v0-usbdcin {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_usbdcin";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&vcc12v_dcin>;
 };

 vcc5v0_usb: vcc5v0-usb {
  compatible = "regulator-fixed";
  regulator-name = "vcc5v0_usb";
  regulator-always-on;
  regulator-boot-on;
  regulator-min-microvolt = <5000000>;
  regulator-max-microvolt = <5000000>;
  vin-supply = <&vcc5v0_usbdcin>;
 };
};

&av1d_mmu {
 status = "okay";
};

&avsd {
 status = "okay";
};

&cpu_l0 {
 cpu-supply = <&vdd_cpu_lit_s0>;
 mem-supply = <&vdd_cpu_lit_mem_s0>;
};

&cpu_b0 {
 cpu-supply = <&vdd_cpu_big0_s0>;
 mem-supply = <&vdd_cpu_big0_mem_s0>;
};

&cpu_b2 {
 cpu-supply = <&vdd_cpu_big1_s0>;
 mem-supply = <&vdd_cpu_big1_mem_s0>;
};

&dsi0 {
 status = "disabled";

 dsi0_panel: panel@0 {
  status = "okay";
  compatible = "simple-panel-dsi";
  reg = <0>;
  backlight = <&backlight>;
  reset-delay-ms = <10>;
  enable-delay-ms = <10>;
  prepare-delay-ms = <10>;
  unprepare-delay-ms = <10>;
  disable-delay-ms = <60>;
  width-mm = <68>;
  height-mm = <121>;
  dsi,flags = <((1 << 0) | (1 << 1) |
   (1 << 11) | (1 << 9))>;
  dsi,format = <0>;
  dsi,lanes = <4>;
  panel-init-sequence = [
   23 00 02 FE 21
   23 00 02 04 00
   23 00 02 00 64
   23 00 02 2A 00
   23 00 02 26 64
   23 00 02 54 00
   23 00 02 50 64
   23 00 02 7B 00
   23 00 02 77 64
   23 00 02 A2 00
   23 00 02 9D 64
   23 00 02 C9 00
   23 00 02 C5 64
   23 00 02 01 71
   23 00 02 27 71
   23 00 02 51 71
   23 00 02 78 71
   23 00 02 9E 71
   23 00 02 C6 71
   23 00 02 02 89
   23 00 02 28 89
   23 00 02 52 89
   23 00 02 79 89
   23 00 02 9F 89
   23 00 02 C7 89
   23 00 02 03 9E
   23 00 02 29 9E
   23 00 02 53 9E
   23 00 02 7A 9E
   23 00 02 A0 9E
   23 00 02 C8 9E
   23 00 02 09 00
   23 00 02 05 B0
   23 00 02 31 00
   23 00 02 2B B0
   23 00 02 5A 00
   23 00 02 55 B0
   23 00 02 80 00
   23 00 02 7C B0
   23 00 02 A7 00
   23 00 02 A3 B0
   23 00 02 CE 00
   23 00 02 CA B0
   23 00 02 06 C0
   23 00 02 2D C0
   23 00 02 56 C0
   23 00 02 7D C0
   23 00 02 A4 C0
   23 00 02 CB C0
   23 00 02 07 CF
   23 00 02 2F CF
   23 00 02 58 CF
   23 00 02 7E CF
   23 00 02 A5 CF
   23 00 02 CC CF
   23 00 02 08 DD
   23 00 02 30 DD
   23 00 02 59 DD
   23 00 02 7F DD
   23 00 02 A6 DD
   23 00 02 CD DD
   23 00 02 0E 15
   23 00 02 0A E9
   23 00 02 36 15
   23 00 02 32 E9
   23 00 02 5F 15
   23 00 02 5B E9
   23 00 02 85 15
   23 00 02 81 E9
   23 00 02 AD 15
   23 00 02 A9 E9
   23 00 02 D3 15
   23 00 02 CF E9
   23 00 02 0B 14
   23 00 02 33 14
   23 00 02 5C 14
   23 00 02 82 14
   23 00 02 AA 14
   23 00 02 D0 14
   23 00 02 0C 36
   23 00 02 34 36
   23 00 02 5D 36
   23 00 02 83 36
   23 00 02 AB 36
   23 00 02 D1 36
   23 00 02 0D 6B
   23 00 02 35 6B
   23 00 02 5E 6B
   23 00 02 84 6B
   23 00 02 AC 6B
   23 00 02 D2 6B
   23 00 02 13 5A
   23 00 02 0F 94
   23 00 02 3B 5A
   23 00 02 37 94
   23 00 02 64 5A
   23 00 02 60 94
   23 00 02 8A 5A
   23 00 02 86 94
   23 00 02 B2 5A
   23 00 02 AE 94
   23 00 02 D8 5A
   23 00 02 D4 94
   23 00 02 10 D1
   23 00 02 38 D1
   23 00 02 61 D1
   23 00 02 87 D1
   23 00 02 AF D1
   23 00 02 D5 D1
   23 00 02 11 04
   23 00 02 39 04
   23 00 02 62 04
   23 00 02 88 04
   23 00 02 B0 04
   23 00 02 D6 04
   23 00 02 12 05
   23 00 02 3A 05
   23 00 02 63 05
   23 00 02 89 05
   23 00 02 B1 05
   23 00 02 D7 05
   23 00 02 18 AA
   23 00 02 14 36
   23 00 02 42 AA
   23 00 02 3D 36
   23 00 02 69 AA
   23 00 02 65 36
   23 00 02 8F AA
   23 00 02 8B 36
   23 00 02 B7 AA
   23 00 02 B3 36
   23 00 02 DD AA
   23 00 02 D9 36
   23 00 02 15 74
   23 00 02 3F 74
   23 00 02 66 74
   23 00 02 8C 74
   23 00 02 B4 74
   23 00 02 DA 74
   23 00 02 16 9F
   23 00 02 40 9F
   23 00 02 67 9F
   23 00 02 8D 9F
   23 00 02 B5 9F
   23 00 02 DB 9F
   23 00 02 17 DC
   23 00 02 41 DC
   23 00 02 68 DC
   23 00 02 8E DC
   23 00 02 B6 DC
   23 00 02 DC DC
   23 00 02 1D FF
   23 00 02 19 03
   23 00 02 47 FF
   23 00 02 43 03
   23 00 02 6E FF
   23 00 02 6A 03
   23 00 02 94 FF
   23 00 02 90 03
   23 00 02 BC FF
   23 00 02 B8 03
   23 00 02 E2 FF
   23 00 02 DE 03
   23 00 02 1A 35
   23 00 02 44 35
   23 00 02 6B 35
   23 00 02 91 35
   23 00 02 B9 35
   23 00 02 DF 35
   23 00 02 1B 45
   23 00 02 45 45
   23 00 02 6C 45
   23 00 02 92 45
   23 00 02 BA 45
   23 00 02 E0 45
   23 00 02 1C 55
   23 00 02 46 55
   23 00 02 6D 55
   23 00 02 93 55
   23 00 02 BB 55
   23 00 02 E1 55
   23 00 02 22 FF
   23 00 02 1E 68
   23 00 02 4C FF
   23 00 02 48 68
   23 00 02 73 FF
   23 00 02 6F 68
   23 00 02 99 FF
   23 00 02 95 68
   23 00 02 C1 FF
   23 00 02 BD 68
   23 00 02 E7 FF
   23 00 02 E3 68
   23 00 02 1F 7E
   23 00 02 49 7E
   23 00 02 70 7E
   23 00 02 96 7E
   23 00 02 BE 7E
   23 00 02 E4 7E
   23 00 02 20 97
   23 00 02 4A 97
   23 00 02 71 97
   23 00 02 97 97
   23 00 02 BF 97
   23 00 02 E5 97
   23 00 02 21 B5
   23 00 02 4B B5
   23 00 02 72 B5
   23 00 02 98 B5
   23 00 02 C0 B5
   23 00 02 E6 B5
   23 00 02 25 F0
   23 00 02 23 E8
   23 00 02 4F F0
   23 00 02 4D E8
   23 00 02 76 F0
   23 00 02 74 E8
   23 00 02 9C F0
   23 00 02 9A E8
   23 00 02 C4 F0
   23 00 02 C2 E8
   23 00 02 EA F0
   23 00 02 E8 E8
   23 00 02 24 FF
   23 00 02 4E FF
   23 00 02 75 FF
   23 00 02 9B FF
   23 00 02 C3 FF
   23 00 02 E9 FF
   23 00 02 FE 3D
   23 00 02 00 04
   23 00 02 FE 23
   23 00 02 08 82
   23 00 02 0A 00
   23 00 02 0B 00
   23 00 02 0C 01
   23 00 02 16 00
   23 00 02 18 02
   23 00 02 1B 04
   23 00 02 19 04
   23 00 02 1C 81
   23 00 02 1F 00
   23 00 02 20 03
   23 00 02 23 04
   23 00 02 21 01
   23 00 02 54 63
   23 00 02 55 54
   23 00 02 6E 45
   23 00 02 6D 36
   23 00 02 FE 3D
   23 00 02 55 78
   23 00 02 FE 20
   23 00 02 26 30
   23 00 02 FE 3D
   23 00 02 20 71
   23 00 02 50 8F
   23 00 02 51 8F
   23 00 02 FE 00
   23 00 02 35 00
   05 78 01 11
   05 00 01 29
  ];

  panel-exit-sequence = [
   05 00 01 28
   05 00 01 10
  ];

  disp_timings0: display-timings {
   native-mode = <&dsi0_timing0>;
   dsi0_timing0: timing0 {
    clock-frequency = <132000000>;
    hactive = <1080>;
    vactive = <1920>;
    hfront-porch = <15>;
    hsync-len = <4>;
    hback-porch = <30>;
    vfront-porch = <15>;
    vsync-len = <2>;
    vback-porch = <15>;
    hsync-active = <0>;
    vsync-active = <0>;
    de-active = <0>;
    pixelclk-active = <0>;
   };
  };

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    panel_in_dsi: endpoint {
     remote-endpoint = <&dsi_out_panel>;
    };
   };
  };
 };

 ports {
  #address-cells = <1>;
  #size-cells = <0>;

  port@1 {
   reg = <1>;
   dsi_out_panel: endpoint {
    remote-endpoint = <&panel_in_dsi>;
   };
  };
 };

};

&dsi1 {
 status = "disabled";

 dsi1_panel: panel@0 {
  status = "okay";
  compatible = "simple-panel-dsi";
  reg = <0>;
  backlight = <&backlight>;
  reset-delay-ms = <10>;
  enable-delay-ms = <10>;
  prepare-delay-ms = <10>;
  unprepare-delay-ms = <10>;
  disable-delay-ms = <10>;
  width-mm = <68>;
  height-mm = <121>;
  dsi,flags = <((1 << 0) | (1 << 1) |
   (1 << 11) | (1 << 9))>;
  dsi,format = <0>;
  dsi,lanes = <4>;
  panel-init-sequence = [
   23 00 02 FE 21
   23 00 02 04 00
   23 00 02 00 64
   23 00 02 2A 00
   23 00 02 26 64
   23 00 02 54 00
   23 00 02 50 64
   23 00 02 7B 00
   23 00 02 77 64
   23 00 02 A2 00
   23 00 02 9D 64
   23 00 02 C9 00
   23 00 02 C5 64
   23 00 02 01 71
   23 00 02 27 71
   23 00 02 51 71
   23 00 02 78 71
   23 00 02 9E 71
   23 00 02 C6 71
   23 00 02 02 89
   23 00 02 28 89
   23 00 02 52 89
   23 00 02 79 89
   23 00 02 9F 89
   23 00 02 C7 89
   23 00 02 03 9E
   23 00 02 29 9E
   23 00 02 53 9E
   23 00 02 7A 9E
   23 00 02 A0 9E
   23 00 02 C8 9E
   23 00 02 09 00
   23 00 02 05 B0
   23 00 02 31 00
   23 00 02 2B B0
   23 00 02 5A 00
   23 00 02 55 B0
   23 00 02 80 00
   23 00 02 7C B0
   23 00 02 A7 00
   23 00 02 A3 B0
   23 00 02 CE 00
   23 00 02 CA B0
   23 00 02 06 C0
   23 00 02 2D C0
   23 00 02 56 C0
   23 00 02 7D C0
   23 00 02 A4 C0
   23 00 02 CB C0
   23 00 02 07 CF
   23 00 02 2F CF
   23 00 02 58 CF
   23 00 02 7E CF
   23 00 02 A5 CF
   23 00 02 CC CF
   23 00 02 08 DD
   23 00 02 30 DD
   23 00 02 59 DD
   23 00 02 7F DD
   23 00 02 A6 DD
   23 00 02 CD DD
   23 00 02 0E 15
   23 00 02 0A E9
   23 00 02 36 15
   23 00 02 32 E9
   23 00 02 5F 15
   23 00 02 5B E9
   23 00 02 85 15
   23 00 02 81 E9
   23 00 02 AD 15
   23 00 02 A9 E9
   23 00 02 D3 15
   23 00 02 CF E9
   23 00 02 0B 14
   23 00 02 33 14
   23 00 02 5C 14
   23 00 02 82 14
   23 00 02 AA 14
   23 00 02 D0 14
   23 00 02 0C 36
   23 00 02 34 36
   23 00 02 5D 36
   23 00 02 83 36
   23 00 02 AB 36
   23 00 02 D1 36
   23 00 02 0D 6B
   23 00 02 35 6B
   23 00 02 5E 6B
   23 00 02 84 6B
   23 00 02 AC 6B
   23 00 02 D2 6B
   23 00 02 13 5A
   23 00 02 0F 94
   23 00 02 3B 5A
   23 00 02 37 94
   23 00 02 64 5A
   23 00 02 60 94
   23 00 02 8A 5A
   23 00 02 86 94
   23 00 02 B2 5A
   23 00 02 AE 94
   23 00 02 D8 5A
   23 00 02 D4 94
   23 00 02 10 D1
   23 00 02 38 D1
   23 00 02 61 D1
   23 00 02 87 D1
   23 00 02 AF D1
   23 00 02 D5 D1
   23 00 02 11 04
   23 00 02 39 04
   23 00 02 62 04
   23 00 02 88 04
   23 00 02 B0 04
   23 00 02 D6 04
   23 00 02 12 05
   23 00 02 3A 05
   23 00 02 63 05
   23 00 02 89 05
   23 00 02 B1 05
   23 00 02 D7 05
   23 00 02 18 AA
   23 00 02 14 36
   23 00 02 42 AA
   23 00 02 3D 36
   23 00 02 69 AA
   23 00 02 65 36
   23 00 02 8F AA
   23 00 02 8B 36
   23 00 02 B7 AA
   23 00 02 B3 36
   23 00 02 DD AA
   23 00 02 D9 36
   23 00 02 15 74
   23 00 02 3F 74
   23 00 02 66 74
   23 00 02 8C 74
   23 00 02 B4 74
   23 00 02 DA 74
   23 00 02 16 9F
   23 00 02 40 9F
   23 00 02 67 9F
   23 00 02 8D 9F
   23 00 02 B5 9F
   23 00 02 DB 9F
   23 00 02 17 DC
   23 00 02 41 DC
   23 00 02 68 DC
   23 00 02 8E DC
   23 00 02 B6 DC
   23 00 02 DC DC
   23 00 02 1D FF
   23 00 02 19 03
   23 00 02 47 FF
   23 00 02 43 03
   23 00 02 6E FF
   23 00 02 6A 03
   23 00 02 94 FF
   23 00 02 90 03
   23 00 02 BC FF
   23 00 02 B8 03
   23 00 02 E2 FF
   23 00 02 DE 03
   23 00 02 1A 35
   23 00 02 44 35
   23 00 02 6B 35
   23 00 02 91 35
   23 00 02 B9 35
   23 00 02 DF 35
   23 00 02 1B 45
   23 00 02 45 45
   23 00 02 6C 45
   23 00 02 92 45
   23 00 02 BA 45
   23 00 02 E0 45
   23 00 02 1C 55
   23 00 02 46 55
   23 00 02 6D 55
   23 00 02 93 55
   23 00 02 BB 55
   23 00 02 E1 55
   23 00 02 22 FF
   23 00 02 1E 68
   23 00 02 4C FF
   23 00 02 48 68
   23 00 02 73 FF
   23 00 02 6F 68
   23 00 02 99 FF
   23 00 02 95 68
   23 00 02 C1 FF
   23 00 02 BD 68
   23 00 02 E7 FF
   23 00 02 E3 68
   23 00 02 1F 7E
   23 00 02 49 7E
   23 00 02 70 7E
   23 00 02 96 7E
   23 00 02 BE 7E
   23 00 02 E4 7E
   23 00 02 20 97
   23 00 02 4A 97
   23 00 02 71 97
   23 00 02 97 97
   23 00 02 BF 97
   23 00 02 E5 97
   23 00 02 21 B5
   23 00 02 4B B5
   23 00 02 72 B5
   23 00 02 98 B5
   23 00 02 C0 B5
   23 00 02 E6 B5
   23 00 02 25 F0
   23 00 02 23 E8
   23 00 02 4F F0
   23 00 02 4D E8
   23 00 02 76 F0
   23 00 02 74 E8
   23 00 02 9C F0
   23 00 02 9A E8
   23 00 02 C4 F0
   23 00 02 C2 E8
   23 00 02 EA F0
   23 00 02 E8 E8
   23 00 02 24 FF
   23 00 02 4E FF
   23 00 02 75 FF
   23 00 02 9B FF
   23 00 02 C3 FF
   23 00 02 E9 FF
   23 00 02 FE 3D
   23 00 02 00 04
   23 00 02 FE 23
   23 00 02 08 82
   23 00 02 0A 00
   23 00 02 0B 00
   23 00 02 0C 01
   23 00 02 16 00
   23 00 02 18 02
   23 00 02 1B 04
   23 00 02 19 04
   23 00 02 1C 81
   23 00 02 1F 00
   23 00 02 20 03
   23 00 02 23 04
   23 00 02 21 01
   23 00 02 54 63
   23 00 02 55 54
   23 00 02 6E 45
   23 00 02 6D 36
   23 00 02 FE 3D
   23 00 02 55 78
   23 00 02 FE 20
   23 00 02 26 30
   23 00 02 FE 3D
   23 00 02 20 71
   23 00 02 50 8F
   23 00 02 51 8F
   23 00 02 FE 00
   23 00 02 35 00
   05 78 01 11
   05 00 01 29
  ];

  panel-exit-sequence = [
   05 00 01 28
   05 00 01 10
  ];

  disp_timings1: display-timings {
   native-mode = <&dsi1_timing0>;
   dsi1_timing0: timing0 {
    clock-frequency = <132000000>;
    hactive = <1080>;
    vactive = <1920>;
    hfront-porch = <15>;
    hsync-len = <4>;
    hback-porch = <30>;
    vfront-porch = <15>;
    vsync-len = <2>;
    vback-porch = <15>;
    hsync-active = <0>;
    vsync-active = <0>;
    de-active = <0>;
    pixelclk-active = <0>;
   };
  };

  ports {
   #address-cells = <1>;
   #size-cells = <0>;

   port@0 {
    reg = <0>;
    panel_in_dsi1: endpoint {
     remote-endpoint = <&dsi1_out_panel>;
    };
   };
  };
 };

 ports {
  #address-cells = <1>;
  #size-cells = <0>;

  port@1 {
   reg = <1>;
   dsi1_out_panel: endpoint {
    remote-endpoint = <&panel_in_dsi1>;
   };
  };
 };

};

&gpu {
 mali-supply = <&vdd_gpu_s0>;
 mem-supply = <&vdd_gpu_mem_s0>;
 status = "okay";
};

&i2s0_8ch {
 status = "okay";
 pinctrl-0 = <&i2s0_lrck
       &i2s0_sclk
       &i2s0_sdi0
       &i2s0_sdo0>;
};

&i2s2_2ch {
 pinctrl-0 = <&i2s2m1_lrck &i2s2m1_sclk &i2s2m1_sdi &i2s2m1_sdo>;
 rockchip,bclk-fs = <32>;
 status = "disabled";
};

&iep {
 status = "okay";
};

&iep_mmu {
 status = "okay";
};

&jpegd {
 status = "okay";
};

&jpegd_mmu {
 status = "okay";
};

&jpege_ccu {
 status = "okay";
};

&jpege0 {
 status = "okay";
};

&jpege0_mmu {
 status = "okay";
};

&jpege1 {
 status = "okay";
};

&jpege1_mmu {
 status = "okay";
};

&jpege2 {
 status = "okay";
};

&jpege2_mmu {
 status = "okay";
};

&jpege3 {
 status = "okay";
};

&jpege3_mmu {
 status = "okay";
};

&mpp_srv {
 status = "okay";
};

&rga3_core0 {
 status = "okay";
};

&rga3_0_mmu {
 status = "okay";
};

&rga3_core1 {
 status = "okay";
};

&rga3_1_mmu {
 status = "okay";
};

&rga2 {
 status = "okay";
};

&rknpu {
 rknpu-supply = <&vdd_npu_s0>;
 mem-supply = <&vdd_npu_mem_s0>;
 status = "okay";
};

&rknpu_mmu {
 status = "okay";
};

&rkvdec_ccu {
 status = "okay";
};

&rkvdec0 {
 status = "okay";
};

&rkvdec0_mmu {
 status = "okay";
};

&rkvdec1 {
 status = "okay";
};

&rkvdec1_mmu {
 status = "okay";
};

&rkvenc_ccu {
 status = "okay";
};

&rkvenc0 {
 venc-supply = <&vdd_vdenc_s0>;
 mem-supply = <&vdd_vdenc_mem_s0>;
 status = "okay";
};

&rkvenc0_mmu {
 status = "okay";
};

&rkvenc1 {
 venc-supply = <&vdd_vdenc_s0>;
 mem-supply = <&vdd_vdenc_mem_s0>;
 status = "okay";
};

&rkvenc1_mmu {
 status = "okay";
};

&rkvtunnel {
 status = "okay";
};

&rockchip_suspend {
 status = "okay";
 rockchip,sleep-debug-en = <1>;
};

&saradc {
 status = "okay";
 vref-supply = <&vcc_1v8_s0>;
};

&sdhci {
 bus-width = <8>;
 no-sdio;
 no-sd;
 non-removable;
 max-frequency = <200000000>;
 mmc-hs400-1_8v;
 mmc-hs400-enhanced-strobe;
 full-pwr-cycle-in-suspend;
 status = "okay";
};

&sdmmc {
 max-frequency = <200000000>;
 no-sdio;
 no-mmc;
 bus-width = <4>;
 cap-mmc-highspeed;
 cap-sd-highspeed;
 disable-wp;
 sd-uhs-sdr104;
 vqmmc-supply = <&vccio_sd_s0>;
 status = "disabled";
};

&tsadc {
 status = "okay";
};

&u2phy0 {
 status = "okay";
};

&u2phy1 {
 status = "okay";
};

&u2phy2 {
 status = "okay";
};

&u2phy3 {
 status = "okay";
};

&u2phy0_otg {
 status = "okay";
};

&u2phy1_otg {
 status = "okay";
};

&u2phy2_host {
 status = "okay";
};

&u2phy3_host {
 status = "okay";
};

&usb_host0_ehci {
 status = "okay";
};

&usb_host0_ohci {
 status = "okay";
};

&usb_host1_ehci {
 status = "okay";
};

&usb_host1_ohci {
 status = "okay";
};

&usbdp_phy0 {
 status = "okay";
};

&usbdp_phy0_dp {
 status = "okay";
};

&usbdp_phy0_u3 {
 status = "okay";
};

&usbdp_phy1 {
 status = "okay";
};

&usbdp_phy1_dp {
 status = "okay";
};

&usbdp_phy1_u3 {
 status = "okay";
};

&usbdrd3_0 {
 status = "okay";
};

&usbdrd_dwc3_0 {
 dr_mode = "otg";
 status = "okay";
};

&usbhost3_0 {
 status = "okay";
};

&usbhost_dwc3_0 {
 status = "okay";
};

&usbdrd3_1 {
 status = "okay";
};

&usbdrd_dwc3_1 {
 status = "okay";
};

&vdpu {
 status = "okay";
};

&vdpu_mmu {
 status = "okay";
};

&vepu {
 status = "okay";
};

&vop {
 status = "okay";
};

&vop_mmu {
 status = "okay";
};


&vp0 {
 rockchip,plane-mask = <(1 << 0 | 1 << 2)>;
 rockchip,primary-plane = <2>;
};

&vp1 {
 rockchip,plane-mask = <(1 << 1 | 1 << 3)>;
 rockchip,primary-plane = <3>;
};

&vp2 {
 rockchip,plane-mask = <(1 << 6 | 1 << 8)>;
 rockchip,primary-plane = <8>;
};

&vp3 {
 rockchip,plane-mask = <(1 << 7 | 1 << 9)>;
 rockchip,primary-plane = <9>;
};
# 14 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi" 1
# 10 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi"
&spi2 {
 status = "okay";
 assigned-clocks = <&cru 165>;
 assigned-clock-rates = <200000000>;
 pinctrl-names = "default";
 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
 num-cs = <1>;

 rk806single: rk806single@0 {
  compatible = "rockchip,rk806";
  spi-max-frequency = <1000000>;
  reg = <0x0>;

  interrupt-parent = <&gpio0>;
  interrupts = <7 8>;

  pinctrl-names = "default", "pmic-power-off";
  pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
  pinctrl-1 = <&rk806_dvs1_pwrdn>;


  low_voltage_threshold = <3000>;

  shutdown_voltage_threshold = <2700>;

  shutdown_temperture_threshold = <160>;
  hotdie_temperture_threshold = <115>;
# 45 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-rk806-single.dtsi"
  pmic-reset-func = <1>;

  vcc1-supply = <&vcc5v0_sys>;
  vcc2-supply = <&vcc5v0_sys>;
  vcc3-supply = <&vcc5v0_sys>;
  vcc4-supply = <&vcc5v0_sys>;
  vcc5-supply = <&vcc5v0_sys>;
  vcc6-supply = <&vcc5v0_sys>;
  vcc7-supply = <&vcc5v0_sys>;
  vcc8-supply = <&vcc5v0_sys>;
  vcc9-supply = <&vcc5v0_sys>;
  vcc10-supply = <&vcc5v0_sys>;
  vcc11-supply = <&vcc_2v0_pldo_s3>;
  vcc12-supply = <&vcc5v0_sys>;
  vcc13-supply = <&vcc_1v1_nldo_s3>;
  vcc14-supply = <&vcc_1v1_nldo_s3>;
  vcca-supply = <&vcc5v0_sys>;

  pwrkey {
   status = "okay";
  };

  pinctrl_rk806: pinctrl_rk806 {
   gpio-controller;
   #gpio-cells = <2>;

   rk806_dvs1_null: rk806_dvs1_null {
    pins = "gpio_pwrctrl2";
    function = "pin_fun0";
   };

   rk806_dvs1_slp: rk806_dvs1_slp {
    pins = "gpio_pwrctrl1";
    function = "pin_fun1";
   };

   rk806_dvs1_pwrdn: rk806_dvs1_pwrdn {
    pins = "gpio_pwrctrl1";
    function = "pin_fun2";
   };

   rk806_dvs1_rst: rk806_dvs1_rst {
    pins = "gpio_pwrctrl1";
    function = "pin_fun3";
   };

   rk806_dvs2_null: rk806_dvs2_null {
    pins = "gpio_pwrctrl2";
    function = "pin_fun0";
   };

   rk806_dvs2_slp: rk806_dvs2_slp {
    pins = "gpio_pwrctrl2";
    function = "pin_fun1";
   };

   rk806_dvs2_pwrdn: rk806_dvs2_pwrdn {
    pins = "gpio_pwrctrl2";
    function = "pin_fun2";
   };

   rk806_dvs2_rst: rk806_dvs2_rst {
    pins = "gpio_pwrctrl2";
    function = "pin_fun3";
   };

   rk806_dvs2_dvs: rk806_dvs2_dvs {
    pins = "gpio_pwrctrl2";
    function = "pin_fun4";
   };

   rk806_dvs2_gpio: rk806_dvs2_gpio {
    pins = "gpio_pwrctrl2";
    function = "pin_fun5";
   };

   rk806_dvs3_null: rk806_dvs3_null {
    pins = "gpio_pwrctrl3";
    function = "pin_fun0";
   };

   rk806_dvs3_slp: rk806_dvs3_slp {
    pins = "gpio_pwrctrl3";
    function = "pin_fun1";
   };

   rk806_dvs3_pwrdn: rk806_dvs3_pwrdn {
    pins = "gpio_pwrctrl3";
    function = "pin_fun2";
   };

   rk806_dvs3_rst: rk806_dvs3_rst {
    pins = "gpio_pwrctrl3";
    function = "pin_fun3";
   };

   rk806_dvs3_dvs: rk806_dvs3_dvs {
    pins = "gpio_pwrctrl3";
    function = "pin_fun4";
   };

   rk806_dvs3_gpio: rk806_dvs3_gpio {
    pins = "gpio_pwrctrl3";
    function = "pin_fun5";
   };
  };

  regulators {
   vdd_gpu_s0: vdd_gpu_mem_s0: DCDC_REG1 {
    regulator-boot-on;
    regulator-min-microvolt = <550000>;
    regulator-max-microvolt = <950000>;
    regulator-ramp-delay = <12500>;
    regulator-name = "vdd_gpu_s0";
    regulator-enable-ramp-delay = <400>;
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: DCDC_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <550000>;
    regulator-max-microvolt = <950000>;
    regulator-ramp-delay = <12500>;
    regulator-name = "vdd_cpu_lit_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vdd_log_s0: DCDC_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <675000>;
    regulator-max-microvolt = <750000>;
    regulator-ramp-delay = <12500>;
    regulator-name = "vdd_log_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
     regulator-suspend-microvolt = <750000>;
    };
   };

   vdd_vdenc_s0: vdd_vdenc_mem_s0: DCDC_REG4 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <550000>;
    regulator-max-microvolt = <950000>;
    regulator-init-microvolt = <750000>;
    regulator-ramp-delay = <12500>;
    regulator-name = "vdd_vdenc_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vdd_ddr_s0: DCDC_REG5 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <675000>;
    regulator-max-microvolt = <900000>;
    regulator-ramp-delay = <12500>;
    regulator-name = "vdd_ddr_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
     regulator-suspend-microvolt = <850000>;
    };
   };

   vdd2_ddr_s3: DCDC_REG6 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vdd2_ddr_s3";
    regulator-state-mem {
     regulator-on-in-suspend;
    };
   };

   vcc_2v0_pldo_s3: DCDC_REG7 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <2000000>;
    regulator-max-microvolt = <2000000>;
    regulator-name = "vdd_2v0_pldo_s3";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <2000000>;
    };
   };

   vcc_3v3_s3: DCDC_REG8 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vcc_3v3_s3";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <3300000>;
    };
   };

   vddq_ddr_s0: DCDC_REG9 {
    regulator-always-on;
    regulator-boot-on;
    regulator-name = "vddq_ddr_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_1v8_s3: DCDC_REG10 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc_1v8_s3";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   avcc_1v8_s0: PLDO_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "avcc_1v8_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_1v8_s0: PLDO_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "vcc_1v8_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   avdd_1v2_s0: PLDO_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1200000>;
    regulator-max-microvolt = <1200000>;
    regulator-name = "avdd_1v2_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vcc_3v3_s0: PLDO_REG4 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <3300000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vcc_3v3_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vccio_sd_s0: PLDO_REG5 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <3300000>;
    regulator-name = "vccio_sd_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   pldo6_s3: PLDO_REG6 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <1800000>;
    regulator-max-microvolt = <1800000>;
    regulator-name = "pldo6_s3";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <1800000>;
    };
   };

   vdd_0v75_s3: NLDO_REG1 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <750000>;
    regulator-name = "vdd_0v75_s3";
    regulator-state-mem {
     regulator-on-in-suspend;
     regulator-suspend-microvolt = <750000>;
    };
   };

   vdd_ddr_pll_s0: NLDO_REG2 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <850000>;
    regulator-max-microvolt = <850000>;
    regulator-name = "vdd_ddr_pll_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
     regulator-suspend-microvolt = <850000>;
    };
   };

   avdd_0v75_s0: NLDO_REG3 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <837500>;
    regulator-max-microvolt = <837500>;
    regulator-name = "avdd_0v75_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vdd_0v85_s0: NLDO_REG4 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <850000>;
    regulator-max-microvolt = <850000>;
    regulator-name = "vdd_0v85_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };

   vdd_0v75_s0: NLDO_REG5 {
    regulator-always-on;
    regulator-boot-on;
    regulator-min-microvolt = <750000>;
    regulator-max-microvolt = <750000>;
    regulator-name = "vdd_0v75_s0";
    regulator-state-mem {
     regulator-off-in-suspend;
    };
   };
  };
 };
};
# 15 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/../rk3588-linux.dtsi" 1






/ {
 aliases {
  mmc0 = &sdhci;
  mmc1 = &sdmmc;
  mmc2 = &sdio;
 };

 chosen: chosen {
  bootargs = "earlycon=uart8250,mmio32,0xfeb50000 console=ttyFIQ0 irqchip.gicv3_pseudo_nmi=0 root=PARTUUID=614e0000-0000 rw rootwait rcupdate.rcu_expedited=1 rcu_nocbs=all";
 };

 cspmu: cspmu@fd10c000 {
  compatible = "rockchip,cspmu";
  reg = <0x0 0xfd10c000 0x0 0x1000>,
        <0x0 0xfd10d000 0x0 0x1000>,
        <0x0 0xfd10e000 0x0 0x1000>,
        <0x0 0xfd10f000 0x0 0x1000>,
        <0x0 0xfd12c000 0x0 0x1000>,
        <0x0 0xfd12d000 0x0 0x1000>,
        <0x0 0xfd12e000 0x0 0x1000>,
        <0x0 0xfd12f000 0x0 0x1000>;
 };

 debug: debug@fd104000 {
  compatible = "rockchip,debug";
  reg = <0x0 0xfd104000 0x0 0x1000>,
        <0x0 0xfd105000 0x0 0x1000>,
        <0x0 0xfd106000 0x0 0x1000>,
        <0x0 0xfd107000 0x0 0x1000>,
        <0x0 0xfd124000 0x0 0x1000>,
        <0x0 0xfd125000 0x0 0x1000>,
        <0x0 0xfd126000 0x0 0x1000>,
        <0x0 0xfd127000 0x0 0x1000>;
 };

 fiq_debugger: fiq-debugger {
  compatible = "rockchip,fiq-debugger";
  rockchip,serial-id = <2>;
  rockchip,wake-irq = <0>;

  rockchip,irq-mode-enable = <1>;
  rockchip,baudrate = <1500000>;
  interrupts = <0 423 8>;
  pinctrl-names = "default";
  pinctrl-0 = <&uart2m0_xfer>;
  status = "okay";
 };

 firmware {
  optee: optee {
   compatible = "linaro,optee-tz";
   method = "smc";

  };
 };

 minidump: minidump {
  compatible = "rockchip,minidump";
  smem-region = <&minidump_smem>;
  minidump-region = <&minidump_mem>;
  status = "disabled";
 };

 reserved-memory {
  #address-cells = <2>;
  #size-cells = <2>;
  ranges;

  cma {
   compatible = "shared-dma-pool";
   reusable;
   size = <0x0 (8 * 0x100000)>;
   linux,cma-default;
  };

  drm_logo: drm-logo@00000000 {
   compatible = "rockchip,drm-logo";
   reg = <0x0 0x0 0x0 0x0>;
  };

  drm_cubic_lut: drm-cubic-lut@00000000 {
   compatible = "rockchip,drm-cubic-lut";
   reg = <0x0 0x0 0x0 0x0>;
  };

  ramoops: ramoops@110000 {
   compatible = "ramoops";

   reg = <0x0 0x110000 0x0 0xe0000>;
   boot-log-size = <0x8000>;
   boot-log-count = <0x1>;
   console-size = <0x80000>;
   pmsg-size = <0x30000>;
   ftrace-size = <0x00000>;
   record-size = <0x14000>;
  };

  minidump_smem: minidump-smem@1f0000 {
   reg = <0x0 0x1f0000 0x0 0x100>;
   no-map;
   status = "disabled";
  };

  minidump_mem: minidump-mem@c000000 {
   reg = <0x0 0x0c000000 0x0 0x2000000>;
   no-map;
   status = "disabled";
  };

 };
};

&display_subsystem {
 memory-region = <&drm_logo>;
 memory-region-names = "drm-logo";
};

&dfi {
 status = "okay";
};

&dmc {
 status = "okay";
 center-supply = <&vdd_ddr_s0>;
 mem-supply = <&vdd_log_s0>;
};

&rng {
 status = "okay";
};
# 16 "arch/arm64/boot/dts/rockchip/rk3588/rp-rk3588-board.dtsi" 2

/ {
    model = "Rockchip RK3588 EVB4 LP4 V10 Board";
    compatible = "rockchip,rk3588-evb4-lp4-v10", "rockchip,rk3588";
};

&rkcif {
  status = "okay";
};

&rkcif_mmu {
  status = "okay";
};

&wdt {
  status = "okay";
};

&dsi0 {
    status = "disabled";
    /delete-node/ panel@0;
    ports {
        /delete-node/ port@1;
    };
};

&dsi1 {
    status = "disabled";
    /delete-node/ panel@0;
    ports {
        /delete-node/ port@1;
    };
};

&i2c0 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&i2c0m2_xfer>;

    vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
        compatible = "rockchip,rk8602";
        reg = <0x42>;
        vin-supply = <&vcc5v0_sys>;
        vsel-gpios = <&gpio0 3 0>;
        regulator-compatible = "rk860x-reg";
        regulator-name = "vdd_cpu_big0_s0";
        regulator-min-microvolt = <550000>;
        regulator-max-microvolt = <1050000>;
        regulator-ramp-delay = <2300>;
        rockchip,suspend-voltage-selector = <1>;
        regulator-boot-on;
        regulator-always-on;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };

    vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
        compatible = "rockchip,rk8603";
        reg = <0x43>;
        vin-supply = <&vcc5v0_sys>;
        vsel-gpios = <&gpio0 30 0>;
        regulator-compatible = "rk860x-reg";
        regulator-name = "vdd_cpu_big1_s0";
        regulator-min-microvolt = <550000>;
        regulator-max-microvolt = <1050000>;
        regulator-ramp-delay = <2300>;
        rockchip,suspend-voltage-selector = <1>;
        regulator-boot-on;
        regulator-always-on;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
};

&i2c1 {
    status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&i2c1m2_xfer>;

    vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
        compatible = "rockchip,rk8602";
        reg = <0x42>;
        vin-supply = <&vcc5v0_sys>;
        vsel-gpios = <&gpio0 17 0>;
        regulator-compatible = "rk860x-reg";
        regulator-name = "vdd_npu_s0";
        regulator-min-microvolt = <550000>;
        regulator-max-microvolt = <950000>;
        regulator-ramp-delay = <2300>;
        rockchip,suspend-voltage-selector = <1>;
        regulator-boot-on;
        regulator-always-on;
        regulator-state-mem {
            regulator-off-in-suspend;
        };
    };
};


&fiq_debugger {
    compatible = "rockchip,fiq-debugger";
    rockchip,serial-id = <2>;
    rockchip,wake-irq = <0>;

    rockchip,irq-mode-enable = <1>;
    rockchip,baudrate = <115200>;
    interrupts = <0 423 8>;
    pinctrl-names = "default";
    pinctrl-0 = <&uart2m0_xfer>;
    status = "okay";
};


&sdmmc {
 max-frequency = <200000000>;
 no-sdio;
 no-mmc;
 bus-width = <4>;
 cap-mmc-highspeed;
 cap-sd-highspeed;
 disable-wp;
 sd-uhs-sdr104;
 vmmc-supply = <&vcc_3v3_s0>;
 vqmmc-supply = <&vccio_sd_s0>;
 pinctrl-names = "default";
 pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
 status = "okay";
};


/delete-node/ &backlight;
# 4 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2




# 1 "arch/arm64/boot/dts/rockchip/rk3588/rpdzkj_config.dtsi" 1

/ {
    rpdzkj:rpdzkj_config {
        compatible = "rp_config";

        lcd_device0 = "DSI-1";
        lcd_rotate0 = "0";

        lcd_device1 = "HDMI-1";
        lcd_rotate1 = "0";

        lcd_device2 = "HDMI-2";
        lcd_rotate2 = "0";

        lcd_device3 = "DP-1";
        lcd_rotate3 = "0";

        status = "okay";
    };
};
# 9 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2


# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-typec-rk3588.dtsi" 1

/ {
        vbus5v0_typec: vbus5v0-typec {
                compatible = "regulator-fixed";
                regulator-name = "vbus5v0_typec";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                enable-active-high;
                gpio = <&gpio1 2 0>;
                vin-supply = <&vcc5v0_usb>;
                pinctrl-names = "default";
                pinctrl-0 = <&typec5v_pwren>;
        };
};



&i2c4 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&i2c4m1_xfer>;

    usbc0: fusb302@22 {
        compatible = "fcs,fusb302";
        reg = <0x22>;
        interrupt-parent = <&gpio0>;
        interrupts = <27 8>;
        pinctrl-names = "default";
        pinctrl-0 = <&usbc0_int>;
        vbus-supply = <&vbus5v0_typec>;
        status = "okay";

        ports {
            #address-cells = <1>;
            #size-cells = <0>;

            port@0 {
                reg = <0>;
                usbc0_role_sw: endpoint@0 {
                    remote-endpoint = <&dwc3_0_role_switch>;
                };
            };
        };

        usb_con: connector {
            compatible = "usb-c-connector";
            label = "USB-C";
            data-role = "dual";
            power-role = "dual";
            try-power-role = "sink";
            op-sink-microwatt = <1000000>;
            sink-pdos =
                <(((0) << 30) | ((1 << 26)) | ((((5000) / 50) & 0x3ff) << 10) | ((((1000) / 10) & 0x3ff) << 0))>;
            source-pdos =
                <(((0) << 30) | ((1 << 26)) | ((((5000) / 50) & 0x3ff) << 10) | ((((3000) / 10) & 0x3ff) << 0))>;

            altmodes {
                #address-cells = <1>;
                #size-cells = <0>;

                altmode@0 {
                    reg = <0>;
                    svid = <0xff01>;
                    vdo = <0xffffffff>;
                };
            };

            ports {
                #address-cells = <1>;
                #size-cells = <0>;

                port@0 {
                    reg = <0>;
                    usbc0_orien_sw: endpoint {
                        remote-endpoint = <&usbdp_phy0_orientation_switch>;
                    };
                };

                port@1 {
                    reg = <1>;
                    dp_altmode_mux: endpoint {
                        remote-endpoint = <&usbdp_phy0_dp_altmode_mux>;
                    };
                };
            };
        };
    };
};


&usbdp_phy0 {
    orientation-switch;
    svid = <0xff01>;
    sbu1-dc-gpios = <&gpio3 28 0>;
    sbu2-dc-gpios = <&gpio3 29 0>;

    port {
        #address-cells = <1>;
        #size-cells = <0>;
        usbdp_phy0_orientation_switch: endpoint@0 {
            reg = <0>;
            remote-endpoint = <&usbc0_orien_sw>;
        };

        usbdp_phy0_dp_altmode_mux: endpoint@1 {
            reg = <1>;
            remote-endpoint = <&dp_altmode_mux>;
        };
    };
};


&usbdrd_dwc3_0 {
    dr_mode = "otg";
    usb-role-switch;
    port {
        #address-cells = <1>;
        #size-cells = <0>;
        dwc3_0_role_switch: endpoint@0 {
            reg = <0>;
            remote-endpoint = <&usbc0_role_sw>;
        };
    };
};

&pinctrl {
        usb-typec {
                usbc0_int: usbc0-int {
                        rockchip,pins = <0 27 0 &pcfg_pull_up>;
                };

                typec5v_pwren: typec5v-pwren {
                        rockchip,pins = <1 2 0 &pcfg_pull_none>;
                };

       };
};
# 12 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-usb-host.dtsi" 1

&u2phy2 {
    status = "okay";
};

&u2phy3 {
    status = "okay";
};





&u2phy2_host {
    status = "okay";
};

&u2phy3_host {
    status = "okay";
};

&usb_host0_ehci {
    status = "okay";
};

&usb_host0_ohci {
    status = "okay";
};

&usb_host1_ehci {
    status = "okay";
};

&usb_host1_ohci {
    status = "okay";
};




&usbhost3_0 {
    status = "disabled";
};

&usbhost_dwc3_0 {
    status = "disabled";
};
# 13 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2



# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-eth-gmac1.dtsi" 1

&mdio1 {
    rgmii_phy1: phy@1 {
        compatible = "ethernet-phy-ieee802.3-c22";
        reg = <0x1>;
        clocks = <&cru 262>;
    };
};

&gmac1 {

    phy-mode = "rgmii-rxid";
    clock_in_out = "input";

    snps,reset-gpio = <&gpio3 15 1>;
    snps,reset-active-low;

    snps,reset-delays-us = <0 20000 100000>;

    pinctrl-names = "default";
    pinctrl-0 = <&gmac1_miim
             &gmac1_tx_bus2
             &gmac1_rx_bus2
             &gmac1_rgmii_clk
             &gmac1_rgmii_bus
            &gmac1_clkinout
            &eth1_pins>;

    tx_delay = <0x44>;


    phy-handle = <&rgmii_phy1>;
    status = "okay";
};
# 17 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 30 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-hdmirx.dtsi" 1

/ {

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;


        cma {
            compatible = "shared-dma-pool";
            reusable;
            reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>;
            linux,cma-default;
        };
    };

  hdmiin-sound {
    compatible = "simple-audio-card";
    simple-audio-card,format = "i2s";
    simple-audio-card,name = "rockchip,hdmiin";
    simple-audio-card,bitclock-master = <&dailink0_master>;
    simple-audio-card,frame-master = <&dailink0_master>;
    status = "okay";
    simple-audio-card,cpu {
      sound-dai = <&i2s7_8ch>;
    };
    dailink0_master: simple-audio-card,codec {
       sound-dai = <&hdmiin_dc>;
   };
  };

  hdmiin_dc: hdmiin-dc {
     compatible = "rockchip,dummy-codec";
     #sound-dai-cells = <0>;
 };

};

&i2s7_8ch {
  status = "okay";
};


&hdmirx_ctrler {
    status = "okay";


    hpd-trigger-level = <1>;
    hdmirx-det-gpios = <&gpio1 29 1>;
    pinctrl-0 = <&hdmim1_rx_cec &hdmim2_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda>;
    pinctrl-names = "default";
};
# 31 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 65 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 1
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi0.dtsi" 1
&hdmi0 {
        status = "okay";
};

&hdmi0_in_vp0 {
        status = "okay";
};

&hdmi0_sound {
        status = "okay";
};

&i2s5_8ch {
        status = "okay";
};

&hdptxphy_hdmi0 {
        status = "okay";
};

&route_hdmi0 {
    status = "okay";
    connect = <&vp0_out_hdmi0>;
};
# 2 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-hdmi1.dtsi" 1
&hdmi1 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim2_tx1_scl &hdmim2_tx1_sda>;
};

&hdmi1_in_vp1 {
    status = "okay";
};

&hdmi1_sound {
    status = "okay";
};

&i2s6_8ch {
        status = "okay";
};


&hdptxphy_hdmi1 {
    status = "okay";
};


&route_hdmi1 {
        status = "okay";
        connect = <&vp1_out_hdmi1>;
};
# 3 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2
# 1 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-typec-dp0.dtsi" 1
&dp0 {
    status = "okay";
};

&dp0_in_vp2 {
    status = "okay";
};

&dp0_sound{
        status = "okay";
};

&spdif_tx2 {
        status = "okay";
};
# 4 "arch/arm64/boot/dts/rockchip/rk3588/rp-lcd-multi-hdmi0-hdmi1-dp0.dtsi" 2
# 66 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts" 2
# 89 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
/ {
    model = "dr4-rk3588";

    reserved-memory {
        #address-cells = <2>;
        #size-cells = <2>;
        ranges;
        dma_trans: dma-trans@3c000000 {
            reg = <0x0 0x3c000000 0x0 0x04000000>;
        };
    };

    vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
        compatible = "regulator-fixed";
        regulator-name = "vcc_1v1_nldo_s3";
        regulator-always-on;
        regulator-boot-on;
        regulator-min-microvolt = <1100000>;
        regulator-max-microvolt = <1100000>;
        vin-supply = <&vcc5v0_sys>;
    };

 fan_gpio_control {
            compatible = "fan_gpio_control";
            gpio-pin = <&gpio4 7 0>;
            thermal-zone = "soc-thermal";
            threshold-temp = <60000>;
            running-time = <10000>;
            status = "disabled";
        };

        rp_power{
                status = "okay";
                compatible = "rp_power";
                rp_not_deep_sleep = <1>;
# 136 "arch/arm64/boot/dts/rockchip/rk3588/dr4-rk3588.dts"
                led {
                        gpio_num = <&gpio4 6 0>;
                        gpio_function = <3>;
                };

                usb-host-power {
                        gpio_num = <&gpio2 17 0>;
                        gpio_function = <4>;
                };

                usb-hub-reset {
                        gpio_num = <&gpio3 10 0>;
                        gpio_function = <4>;
                };
    };

        rp_gpio{
                status = "disabled";
                compatible = "rp_gpio";

                gpio3c7 {
                        gpio_num = <&gpio3 23 0>;
                        gpio_function = <0>;
                };
        };
};


&uart3 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&uart3m2_xfer>;
};

&uart6 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&uart6m2_xfer>;
};

&uart4 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&uart4m2_xfer>;
};

&uart7 {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&uart7m2_xfer>;
};



&can0 {
    assigned-clocks = <&cru 112>;
    assigned-clock-rates = <200000000>;
    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&can0m0_pins>;
};

&can1 {
    assigned-clocks = <&cru 114>;
    assigned-clock-rates = <200000000>;
    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&can1m1_pins>;
};

&i2c4 {
    status = "disabled";
    pinctrl-names = "default";
    pinctrl-0 = <&i2c4m1_xfer>;

    hym8563: hym8563@51 {
        compatible = "haoyu,hym8563";
        reg = <0x51>;
        #clock-cells = <0>;
        clock-frequency = <32768>;
        clock-output-names = "hym8563";





    };

};


&sdmmc {
    status = "okay";
};

&fiq_debugger {
    rockchip,baudrate = <115200>;
};

&display_subsystem {
clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>;
clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll";
};

&hdptxphy_hdmi_clk0 {
            status = "okay";
};

&hdptxphy_hdmi_clk1 {
            status = "okay";
};
