/*
 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
 *
 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 */

/ {
	chosen: chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff130000 kpti=0 coherent_pool=1m";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <2>;
		rockchip,signal-irq = <159>;
		rockchip,wake-irq = <0>;
		/* If enable uart uses irq instead of fiq */
		rockchip,irq-mode-enable = <0>;
		rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>;
		status = "okay";
	};

	firmware {
		firmware_android: android {};

		optee: optee {
			compatible = "linaro,optee-tz";
			method = "smc";
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		drm_logo: drm-logo@00000000 {
			compatible = "rockchip,drm-logo";
			reg = <0x0 0x0 0x0 0x0>;
		};

		ramoops: ramoops@110000 {
			compatible = "ramoops";
			reg = <0x0 0x110000 0x0 0xf0000>;
			record-size = <0x20000>;
			console-size = <0x80000>;
			ftrace-size = <0x00000>;
			pmsg-size = <0x50000>;
		};

		secure_memory: secure-memory@20000000 {
			compatible = "rockchip,secure-memory";
			reg = <0x0 0x20000000 0x0 0x0>;
		};

		/* global autoconfigured region for contiguous allocations */
		linux,cma {
			compatible = "shared-dma-pool";
			reusable;
			size = <0x0 0x2000000>;
			linux,cma-default;
		};
	};
};

&display_subsystem {
	logo-memory-region = <&drm_logo>;
	status = "okay";
	secure-memory-region = <&secure_memory>;
	route {
		route_hdmi: route-hdmi {
			status = "okay";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "fullscreen";
			charge_logo,mode = "fullscreen";
			connect = <&vop_out_hdmi>;
		};
		route_tve: route-tve {
			status = "okay";
			logo,uboot = "logo.bmp";
			logo,kernel = "logo_kernel.bmp";
			logo,mode = "fullscreen";
			charge_logo,mode = "fullscreen";
			connect = <&vop_out_tve>;
		};
	};
};

&rng {
	status = "okay";
};
