// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 */

/ {
	rockchip_amp: rockchip-amp {
		compatible = "rockchip,rk3568-amp";
		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>,
			 <&cru PCLK_TIMER>, <&cru CLK_TIMER4>, <&cru CLK_TIMER5>,
			 <&cru ACLK_MCU>;

		pinctrl-names = "default";
		pinctrl-0 = <&uart4m1_xfer>;
		status = "okay";

		amp_cpus: amp-cpus {
			amp-cpu3 {
				id = <0x0 0x300>;
				entry = <0x0 0x2800000>;
				boot-on = <0>;
				mode = <0>;
			};
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* remote amp core address */
		amp_shmem_reserved: amp-shmem@7800000 {
			reg = <0x0 0x7800000 0x0 0x400000>;
			no-map;
		};

		rpmsg_reserved: rpmsg@7c00000 {
			reg = <0x0 0x7c00000 0x0 0x400000>;
			no-map;
		};

		rpmsg_dma_reserved: rpmsg-dma@8000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x8000000 0x0 0x100000>;
			no-map;
		};

		/* mcu address */
		mcu_reserved: mcu@8200000 {
			reg = <0x0 0x8200000 0x0 0x100000>;
			no-map;
		};
	};

	rpmsg: rpmsg@7c00000 {
		compatible = "rockchip,rpmsg";
		mbox-names = "rpmsg-rx", "rpmsg-tx";
		mboxes = <&mailbox 0 &mailbox 3>;
		rockchip,vdev-nums = <1>;
		rockchip,link-id = <0x03>;
		reg = <0x0 0x7c00000 0x0 0x20000>;
		memory-region = <&rpmsg_dma_reserved>;

		status = "okay";
	};
};

&mailbox {
	rockchip,txpoll-period-ms = <1>;
	status = "okay";
};

