// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
 *
 */

/dts-v1/;
#include "rk3399-box.dtsi"

/ {
	model = "Rockchip RK3399 Board rev1 (BOX)";
	compatible = "rockchip-box-rev1","rockchip,rk3399-box";
};

&pinctrl {
	sdio0 {
		sdio0_bus1: sdio0-bus1 {
			rockchip,pins =
				<2 RK_PC4 1 &pcfg_pull_up_20ma>;
		};

		sdio0_bus4: sdio0-bus4 {
			rockchip,pins =
				<2 RK_PC4 1 &pcfg_pull_up_20ma>,
				<2 RK_PC5 1 &pcfg_pull_up_20ma>,
				<2 RK_PC6 1 &pcfg_pull_up_20ma>,
				<2 RK_PC7 1 &pcfg_pull_up_20ma>;
		};

		sdio0_cmd: sdio0-cmd {
			rockchip,pins =
				<2 RK_PD0 1 &pcfg_pull_up_20ma>;
		};

		sdio0_clk: sdio0-clk {
			rockchip,pins =
				<2 RK_PD1 1 &pcfg_pull_none_20ma>;
		};
	};

	sdmmc {
		sdmmc_bus1: sdmmc-bus1 {
			rockchip,pins =
				<4 RK_PB0 1 &pcfg_pull_up_8ma>;
		};

		sdmmc_bus4: sdmmc-bus4 {
			rockchip,pins =
				<4 RK_PB0 1 &pcfg_pull_up_8ma>,
				<4 RK_PB1 1 &pcfg_pull_up_8ma>,
				<4 RK_PB2 1 &pcfg_pull_up_8ma>,
				<4 RK_PB3 1 &pcfg_pull_up_8ma>;
		};

		sdmmc_clk: sdmmc-clk {
			rockchip,pins =
				<4 RK_PB4 1 &pcfg_pull_none_18ma>;
		};

		sdmmc_cmd: sdmmc-cmd {
			rockchip,pins =
				<4 RK_PB5 1 &pcfg_pull_up_8ma>;
		};
	};

	fusb30x {
		fusb0_int: fusb0-int {
			rockchip,pins =
				<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&i2c4 {
	status = "okay";
	fusb0: fusb30x@22 {
		compatible = "fairchild,fusb302";
		reg = <0x22>;
		pinctrl-names = "default";
		pinctrl-0 = <&fusb0_int>;
		vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
		int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
		status = "okay";
	};
};

&cdn_dp {
	status = "okay";
	extcon = <&fusb0>;
};

&hdmi_in_vopl {
	status = "disabled";
};

&dp_in_vopb {
	status = "disabled";
};
