// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
 *
 */

#include <dt-bindings/display/media-bus-format.h>
#include "rk3562-evb2-ddr4-v10.dtsi"
#include "rk3562-android.dtsi"
#include "rk3562-rk809.dtsi"

/ {
	model = "Rockchip RK3562 EVB2 DDR4 V10 Board + RK EVB BT1120 TO HDMI V10 Ext Board";
	compatible = "rockchip,rk3562-evb2-ddr4-v10-sii9022-bt1120-to-hdmi", "rockchip,rk3562";
};

&dsi {
	status = "disabled";
};

&dsi_in_vp0 {
	status = "disabled";
};

/*
 * The pins of gamc0 and bt1120 are multiplexed
 */
&gmac0 {
	status = "disabled";
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-0 = <&i2c1m1_xfer>;
	status = "okay";

	sii9022: sii9022@39 {
		compatible = "sil,sii9022";
		reg = <0x39>;
		pinctrl-names = "default";
		pinctrl-0 = <&sii902x_hdmi_int>;
		interrupt-parent = <&gpio4>;
		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
		reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
		enable-gpio = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
		/*
		 * MEDIA_BUS_FMT_YUYV8_1X16 for bt1120
		 * MEDIA_BUS_FMT_UYVY8_2X8  for bt656
		 */
		bus-format = <MEDIA_BUS_FMT_YUYV8_1X16>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				sii9022_in_rgb: endpoint {
					remote-endpoint = <&rgb_out_sii9022>;
				};
			};
		};
	};
};

&pinctrl {
	sii902x {
		sii902x_hdmi_int: sii902x-hdmi-int {
			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&rgb {
	status = "okay";
	pinctrl-names = "default";
	/*
	 * <&bt1120_pins> for bt1120
	 * <&bt656_pins>  for bt656
	 */
	pinctrl-0 = <&bt1120_pins>;

	ports {
		port@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgb_out_sii9022: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&sii9022_in_rgb>;
			};
		};
	};
};

&rgb_in_vp0 {
	status = "okay";
};

&video_phy {
	status = "disabled";
};
