99 lines
4.0 KiB
C
99 lines
4.0 KiB
C
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#include "VM_Sram.h"
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#include "delay.h"
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u8 Sram_Buf[50000] __attribute__((at(0X68000000)));//<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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SRAM_HandleTypeDef SRAM_Handler; //SRAM<41><4D><EFBFBD><EFBFBD>
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//SRAM<41><4D>ʼ<EFBFBD><CABC>
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void SRAM_Init(void)
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{
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GPIO_InitTypeDef GPIO_Initure;
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FSMC_NORSRAM_TimingTypeDef FSMC_ReadWriteTim;
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__HAL_RCC_FSMC_CLK_ENABLE(); //ʹ<><CAB9>FSMCʱ<43><CAB1>
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__HAL_RCC_GPIOD_CLK_ENABLE(); //ʹ<><CAB9>GPIODʱ<44><CAB1>
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__HAL_RCC_GPIOE_CLK_ENABLE(); //ʹ<><CAB9>GPIOEʱ<45><CAB1>
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__HAL_RCC_GPIOF_CLK_ENABLE(); //ʹ<><CAB9>GPIOFʱ<46><CAB1>
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__HAL_RCC_GPIOG_CLK_ENABLE(); //ʹ<><CAB9>GPIOGʱ<47><CAB1>
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//PD0,1,4,5,8~15
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GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_8|\
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GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|\
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GPIO_PIN_14|GPIO_PIN_15;
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GPIO_Initure.Mode=GPIO_MODE_AF_PP; //<2F><><EFBFBD>츴<EFBFBD><ECB8B4>
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GPIO_Initure.Pull=GPIO_PULLUP; //<2F><><EFBFBD><EFBFBD>
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GPIO_Initure.Speed=GPIO_SPEED_HIGH; //<2F><><EFBFBD><EFBFBD>
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GPIO_Initure.Alternate=GPIO_AF12_FSMC; //<2F><><EFBFBD><EFBFBD>ΪFSMC
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HAL_GPIO_Init(GPIOD,&GPIO_Initure);
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//PE0,1,7~15
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GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|\
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GPIO_PIN_10| GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|\
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GPIO_PIN_15;
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HAL_GPIO_Init(GPIOE,&GPIO_Initure);
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//PF0~5,12~15
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GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|\
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GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15;
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HAL_GPIO_Init(GPIOF,&GPIO_Initure);
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//PG0~5,10
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GPIO_Initure.Pin=GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3|GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10;
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HAL_GPIO_Init(GPIOG,&GPIO_Initure);
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SRAM_Handler.Instance=FSMC_NORSRAM_DEVICE;
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SRAM_Handler.Extended=FSMC_NORSRAM_EXTENDED_DEVICE;
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SRAM_Handler.Init.NSBank=FSMC_NORSRAM_BANK3; //ʹ<><CAB9>NE3
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SRAM_Handler.Init.DataAddressMux=FSMC_DATA_ADDRESS_MUX_DISABLE; //<2F><>ַ/<2F><><EFBFBD><EFBFBD><EFBFBD>߲<EFBFBD><DFB2><EFBFBD><EFBFBD><EFBFBD>
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SRAM_Handler.Init.MemoryType=FSMC_MEMORY_TYPE_SRAM; //SRAM
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SRAM_Handler.Init.MemoryDataWidth=FSMC_NORSRAM_MEM_BUS_WIDTH_16; //16λ<36><CEBB><EFBFBD>ݿ<EFBFBD><DDBF><EFBFBD>
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SRAM_Handler.Init.BurstAccessMode=FSMC_BURST_ACCESS_MODE_DISABLE; //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9>ͻ<EFBFBD><CDBB><EFBFBD><EFBFBD><EFBFBD><EFBFBD>,<2C><><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ͻ<EFBFBD><CDBB><EFBFBD>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD>Ч,<2C>˴<EFBFBD>δ<EFBFBD>õ<EFBFBD>
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SRAM_Handler.Init.WaitSignalPolarity=FSMC_WAIT_SIGNAL_POLARITY_LOW; //<2F>ȴ<EFBFBD><C8B4>źŵļ<C5B5><C4BC><EFBFBD>,<2C><><EFBFBD><EFBFBD>ͻ<EFBFBD><CDBB>ģʽ<C4A3><CABD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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SRAM_Handler.Init.WaitSignalActive=FSMC_WAIT_TIMING_BEFORE_WS; //<2F>洢<EFBFBD><E6B4A2><EFBFBD><EFBFBD><EFBFBD>ڵȴ<DAB5><C8B4><EFBFBD><EFBFBD><EFBFBD>֮ǰ<D6AE><C7B0>һ<EFBFBD><D2BB>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ڻ<EFBFBD><DABB>ǵȴ<C7B5><C8B4><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ڼ<EFBFBD>ʹ<EFBFBD><CAB9>NWAIT
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SRAM_Handler.Init.WriteOperation=FSMC_WRITE_OPERATION_ENABLE; //<2F>洢<EFBFBD><E6B4A2>дʹ<D0B4><CAB9>
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SRAM_Handler.Init.WaitSignal=FSMC_WAIT_SIGNAL_DISABLE; //<2F>ȴ<EFBFBD>ʹ<EFBFBD><CAB9>λ,<2C>˴<EFBFBD>δ<EFBFBD>õ<EFBFBD>
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SRAM_Handler.Init.ExtendedMode=FSMC_EXTENDED_MODE_DISABLE; //<2F><>дʹ<D0B4><CAB9><EFBFBD><EFBFBD>ͬ<EFBFBD><CDAC>ʱ<EFBFBD><CAB1>
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SRAM_Handler.Init.AsynchronousWait=FSMC_ASYNCHRONOUS_WAIT_DISABLE; //<2F>Ƿ<EFBFBD>ʹ<EFBFBD><CAB9>ͬ<EFBFBD><CDAC><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ģʽ<C4A3>µĵȴ<C4B5><C8B4>ź<EFBFBD>,<2C>˴<EFBFBD>δ<EFBFBD>õ<EFBFBD>
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SRAM_Handler.Init.WriteBurst=FSMC_WRITE_BURST_DISABLE; //<2F><>ֹͻ<D6B9><CDBB>д
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SRAM_Handler.Init.ContinuousClock=FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC;
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//FMC<4D><43>ʱ<EFBFBD><CAB1><EFBFBD><EFBFBD><EFBFBD>ƼĴ<C6BC><C4B4><EFBFBD>
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FSMC_ReadWriteTim.AddressSetupTime=0x00; //<2F><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ʱ<EFBFBD>䣨ADDSET<45><54>Ϊ1<CEAA><31>HCLK 1/168M=6ns*16=96ns
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FSMC_ReadWriteTim.AddressHoldTime=0x00; //<2F><>ַ<EFBFBD><D6B7><EFBFBD><EFBFBD>ʱ<EFBFBD>䣨ADDHLD<4C><44>ģʽAδ<41>õ<EFBFBD>
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FSMC_ReadWriteTim.DataSetupTime=0x03; //<2F><><EFBFBD>ݱ<EFBFBD><DDB1><EFBFBD>ʱ<EFBFBD><CAB1>Ϊ8<CEAA><38>HCLK =6*1=6ns
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FSMC_ReadWriteTim.BusTurnAroundDuration=0X00;
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FSMC_ReadWriteTim.AccessMode=FSMC_ACCESS_MODE_A;//ģʽA
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HAL_SRAM_Init(&SRAM_Handler,&FSMC_ReadWriteTim,&FSMC_ReadWriteTim);
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}
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//<2F><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ(WriteAddr+Bank1_SRAM3_ADDR)<29><>ʼ,<2C><><EFBFBD><EFBFBD>д<EFBFBD><D0B4>n<EFBFBD><6E><EFBFBD>ֽ<EFBFBD>.
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//pBuffer:<3A>ֽ<EFBFBD>ָ<EFBFBD><D6B8>
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//WriteAddr:Ҫд<D2AA><D0B4><EFBFBD>ĵ<EFBFBD>ַ
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//n:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
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void FSMC_SRAM_WriteBuffer(u8 *pBuffer,u32 WriteAddr,u32 n)
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{
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for(;n!=0;n--)
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{
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*(vu8*)(Bank1_SRAM3_ADDR+WriteAddr)=*pBuffer;
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WriteAddr++;
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pBuffer++;
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}
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}
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//<2F><>ָ<EFBFBD><D6B8><EFBFBD><EFBFBD>ַ((WriteAddr+Bank1_SRAM3_ADDR))<29><>ʼ,<2C><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>n<EFBFBD><6E><EFBFBD>ֽ<EFBFBD>.
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//pBuffer:<3A>ֽ<EFBFBD>ָ<EFBFBD><D6B8>
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//ReadAddr:Ҫ<><D2AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ʼ<EFBFBD><CABC>ַ
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//n:Ҫд<D2AA><D0B4><EFBFBD><EFBFBD><EFBFBD>ֽ<EFBFBD><D6BD><EFBFBD>
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void FSMC_SRAM_ReadBuffer(u8 *pBuffer,u32 ReadAddr,u32 n)
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{
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for(;n!=0;n--)
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{
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*pBuffer++=*(vu8*)(Bank1_SRAM3_ADDR+ReadAddr);
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ReadAddr++;
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}
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}
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